Analog Devices AD9216 Service Manual

10-Bit, 65/80/105 MSPS

FEATURES

Integrated dual 10-bit ADC Single 3 V supply operation SNR = 57.6 dBc (to Nyquist, AD9216-105) SFDR = 74 dBc (to Nyquist, AD9216-105) Low power: 150 mW/ch at 105 MSPS Differential input with 300 MHz 3 dB bandwidth Exceptional crosstalk immunity < -80 dB Offset binary or twos complement data format Clock duty cycle stabilizer

APPLICATIONS

Ultrasound equipment IF sampling in communications receivers

3G, radio point-to-point, LMDS, MMDS Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes

GENERAL DESCRIPTION

The AD9216 is a dual, 3 V, 10-bit, 105 MSPS analog-to-digital converter (ADC). It features dual high performance sampleand-hold amplifiers (SHAs) and an integrated voltage reference. The AD9216 uses a multistage differential pipelined architecture with output error correction logic to provide 10-bit accuracy and guarantee no missing codes over the full operating temperature range at up to 105 MSPS data rates. The wide bandwidth, differential SHA allows for a variety of user selectable input ranges and offsets, including single-ended applications. The AD9216 is suitable for various applications, including multiplexed systems that switch full-scale voltage levels in successive channels and for sampling inputs at frequencies well beyond the Nyquist rate.

Dual A/D Converter

AD9216

FUNCTIONAL BLOCK DIAGRAM

AVDD AGND

VIN+_A

VIN–_A

REFT_A

REFB_A

VREF

SENSE

AGND

REFT_B

REFB_B

VIN+_B

VIN–_B

SHA

0.5V

SHA

AD9216

ADC

DRVDD

Figure 1.

10

OUTPUT

BUFFERS

CLOCK

DUTY CYCLE

STABILIZER

CONTROL

10

OUTPUT

BUFFERS

DRGND

Fabricated on an advanced CMOS process, the AD9216 is available in a space saving, Pb-free, 64-lead LFCSP (9 mm × 9 mm) and is specified over the industrial temperature range (−40°C to +85°C).

PRODUCT HIGHLIGHTS

1. Pin compatible with AD9238, dual 12-bit 20 MSPS/40 MSPS/

65 MSPS ADC and AD9248, dual 14-bit 20 MSPS/40 MSPS/ 65 MSPS ADC.

2. 105 MSPS capability allows for demanding, high frequency

applications.

MUX/

MODE

MUX/

10

D9_A–D0_A OEB_A

MUX_SELECT CLK_A CLK_B DCS

SHARED_REF PWDN_A PWDN_B DFS

D9_B–D0_B OEB_B

04775-001

Dual single-ended clock inputs are used to control all internal conversion cycles. A duty cycle stabilizer is available on the AD9216 and can compensate for wide variations in the clock duty cycle, allowing the converters to maintain excellent performance. The digital output data is presented in either straight binary or twos complement format.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

3. Low power consumption: AD9216–105: 105 MSPS = 300 mW.

4. The patented SHA input maintains excellent performance for

input frequencies up to 200 MHz and can be configured for single-ended or differential operation.

5. Typical channel crosstalk of < −80 dB at f

up to 70 MHz.

IN

6. The clock duty cycle stabilizer maintains performance over a

wide range of clock duty cycles.

www.analog.com

AD9216

TABLE OF CONTENTS

DC Specifications ............................................................................. 3

Output Coding............................................................................ 23

AC Specifications.............................................................................. 4

Logic Specifications.......................................................................... 5

Switching Specifications .................................................................. 6

Timing Diagram ............................................................................... 7

Absolute Maximum Ratings............................................................ 8

Explanation of Test Levels........................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Te r mi n ol o g y .................................................................................... 11

Typical Performance Characteristics ........................................... 13

Equivalent Circuits......................................................................... 19

Theory of Operation ...................................................................... 20

Analog Input ............................................................................... 20

Clock Input and Considerations .............................................. 22

Power Dissipation and Standby Mode..................................... 22

Timing ......................................................................................... 23

Data Format................................................................................ 23

Voltage Reference....................................................................... 24

Dual ADC LFCSP PCB.................................................................. 26

Power Connector ........................................................................ 26

Analog Inputs ............................................................................. 26

Optional Operational Amplifier .............................................. 26

Clock ............................................................................................ 26

Volt a ge R e fer e nc e ....................................................................... 26

Data Outputs............................................................................... 26

LFCSP Evaluation Board Bill of Materials (BOM) ................ 27

LFCSP PCB Schematics............................................................. 28

LFCSP PCB Layers..................................................................... 31

Thermal Considerations............................................................ 37

Outline Dimensions ....................................................................... 38

Digital Outputs ........................................................................... 22

REVISION HISTORY

6/05—Rev. 0 to Rev. A

Added 65 and 80 Speed Grades ........................................ Universal

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Changes to Table 3............................................................................ 5

Changes to Table 4............................................................................ 6

Changes to Table 7............................................................................ 9

Added Figure 8................................................................................ 13

Added Figure 11, Figure 13, and Figure 14 ................................. 14

Changes to Figure 36...................................................................... 18

Changes to Table 12........................................................................ 27

Changes to Figure 51...................................................................... 28

Changes to Figure 52...................................................................... 29

Changes to Figure 53...................................................................... 30

Changes to Figure 54...................................................................... 31

Changes to Figure 55...................................................................... 32

Changes to Figure 56...................................................................... 33

Changes to Figure 57...................................................................... 34

Changes to Figure 58...................................................................... 35

Changes to Figure 59...................................................................... 36

Changes to Ordering Guide.......................................................... 38

Ordering Guide .......................................................................... 38

10/04—Revision 0: Initial Version

Rev. A | Page 2 of 40

AD9216

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 1.

Parameter RESOLUTION Full VI 10 10 10 Bits ACCURACY

No Missing Codes Full VI Guaranteed Guaranteed Guaranteed Offset Error Full VI -1.9 ±0.3 +1.9 -1.9 ±0.3 +1.9 −2.2 ±0.3 +2.2 % FSR Gain Error Differential Nonlinearity (DNL) 25°C I -0.9 ±0.3 +0.9 -0.9 ±0.4 +0.9 −1.0 ±0.5 +1.0 LSB

Integral Nonlinearity (INL)2 Full IV -1.4 ±0.5 +1.4 -1.6 ±0.5 +1.6 −2.5 ±1.0 +2.5 LSB 25°C I -1.0 ±0.5 +1.0 -1.1 ±0.5 +1.1 −1.5 ±1.0 +1.5 LSB TEMPERATURE DRIFT

Offset Error Full V ±10 ±10 ±10 µV/°C

Gain Error1 Full V ±75 ±75 ±75 ppm/°C

Reference Voltage Full V ±15 ±15 ±15 ppm/°C INTERNAL VOLTAGE REFERENCE

Output Voltage Error Full VI ±2 ±35 ±2 ±35 ±2 ±35 mV

Load Regulation @ 1.0 mA 25°C V 1.0 1.0 1.0 mV INPUT REFERRED NOISE

Input Span = 2.0 V 25°C V 0.5 0.5 0.5 LSB ANALOG INPUT

Input Span, VREF = 1.0 V Full IV 2 2 2 V p-p

Input Capacitance REFERENCE INPUT RESISTANCE 25°C V 7 7 7 kΩ POWER SUPPLIES

Supply Voltages

Supply Current

PSRR 25°C V ±0.1 ±0.1 ±0.1 % FSR POWER CONSUMPTION

P

AVDD

P

DRVDD

Standby Power MATCHING CHARACTERISTICS

Offset Matching Error

Gain Matching Error (Shared Reference

Mode)

Gain Matching Error (Nonshared

Reference Mode)

1

Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).

2

Measured with low frequency ramp at maximum clock rate.

3

Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure for the equivalent analog input structure. 37

4

Measured with low frequency analog input at maximum clock rate with approximately 5 pF loading on each output bit.

5

Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).

6

Both shared reference mode and nonshared reference mode.

, DCS enabled, unless otherwise noted.

MAX

Temp Test AD9216BCPZ-65 AD9216BCPZ-80 AD9216BCPZ-105

1

2

3

25°C VI -1.6 ±0.4 +1.6 -1.6 ±0.4 +1.6 −1.6 ±0.4 +1.6 % FSR Full IV -1.0 ±0.3 +1.0 -1.0 ±0.4 +1.0 −1.0 ±0.5 +1.0 LSB

25°C V 2 2 2 pF

Level Min Typ Max Min Typ Max Min Typ Max Unit

rms

AVDD Full IV 2.7 3.0 3.3 2.7 3.0 3.3 2.7 3.0 3.3 V DRVDD Full IV 2.25 2.5 3.3 2.25 2.5 3.3 2.25 2.5 3.3 V

4

IAVDD

Full VI 72 80 78 85 100 110 mA

IDRVDD4 Full VI 15 18 24 mA

4

25°C I 216 240 234 255 300 330 mW

4

25°C V 38 45 60 mW

5

6

25°C V 3.0 3.0 3.0 mW

25°C I -2.6 ±0.2 +2.6 -2.6 ±0.2 +2.6 −3.5 ±0.3 +3.5 % FSR 25°C I -0.4 ±0.1 +0.4 -0.4 ±0.1 +0.4 −0.6 ±0.1 +0.6 % FSR

25°C I -1.6 ±0.1 +1.6 -1.6 ±0.1 +1.6 −1.6 ±0.3 +1.6 % FSR

Rev. A | Page 3 of 40

AD9216

AC SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 2.

Parameter Temp Test

SIGNAL-TO-NOISE RATIO (SNR)

f

INPUT

f

INPUT

25°C I 57.2 58.4 56.4 58.5 56.4 57.6 dB f

INPUT

f

INPUT

SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)

f

INPUT

f

INPUT

25°C I 57.0 58.3 56.2 58.0 56.1 57.4 dB f

INPUT

f

INPUT

EFFECTIVE NUMBER OF BITS (ENOB)

f

INPUT

f

INPUT

25°C I 9.2 9.4 9.0 9.3 9.1 9.3 Bits f

INPUT

f

INPUT

WORST HARMONIC (SECOND OR THIRD)

f

INPUT

f

INPUT

25°C I −79.5 -67.8 −77.0 -67.2 −74.0 −66.5 dBc f

INPUT

f

INPUT

WORST OTHER (EXCLUDING SECOND OR THIRD)

f

INPUT

f

INPUT

25°C I −80.5 -68.7 −78.0 -67.8 −75.0 −67.5 dBc f

INPUT

f

INPUT

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f

INPUT

f

INPUT

25°C I 67.8 79.5 67.2 77.0 66.5 74.0 dBc f

INPUT

f

INPUT

TWO-TONE SFDR (AIN = −7 dBFS)

f

IN1

f

IN1

ANALOG BANDWIDTH 25°C V 300 300 300 MHz CROSSTALK 25°C V −80.0 −80.0 −80.0 dB

1

Nyquist = approximately 32 MHz, 40MHz, 50MHz for the −65, −80, and −105 grades respectively

, DCS enabled, unless otherwise noted.

MAX

AD9216BCPZ-65 AD9216BCPZ-80 AD9216BCPZ-105 Min Typ Max Min Typ Max Min Typ Max Unit

Level

= 2.4 MHz 25°C V 58.6 58.5 58.0 dB = Nyquist

1

Full IV 56.6 58.4 55.9 58.1 54.8 57.6 dB

= 69 MHz 25°C V 58.0 58.0 57.4 dB = 100 MHz 25°C V 57.5 57.5 57.3 dB

= 2.4 MHz 25°C V 58.5 58.2 57.8 dB = Nyquist1 Full IV 56.4 58.3 55.4 58.0 53.4 57.4 dB

= 69 MHz 25°C V 57.5 57.5 56.8 dB = 100 MHz 25°C V 57.0 57.0 56.7 dB

= 2.4 MHz 25°C V 9.4 9.4 9.3 Bits = Nyquist1 Full IV 9.1 9.4 8.9 9.3 8.6 9.3 Bits

= 69 MHz 25°C V 9.3 9.3 9.2 Bits = 100 MHz 25°C V 9.3 9.3 9.2 Bits

= 2.4 MHz Full IV −82.0 −81.0 −76.0 dBc = Nyquist1 Full IV −79.5 -65.1 −77.0 -64.1 −74.0 −60.0 dBc

= 69 MHz 25°C V −79.0 −76.5 −74.0 dBc = 100 MHz 25°C V −78.5 −76.0 −74.0 dBc

= 2.4 MHz Full IV −82.5 −81.5 −76.5 dBc = Nyquist1 Full IV −80.5 -65.8 −78.0 -64.5 −75.0 −62.0 dBc

= 69 MHz 25°C V −80.0 −77.5 −75.0 dBc = 100 MHz 25°C V −79.5 −77.0 −75.0 dBc

= 2.4 MHz Full IV 82.0 81.0 76.0 dBc = Nyquist1 Full IV 65.1 79.5 64.1 77.0 60.0 74.0 dBc

= 69 MHz 25°C V 79.0 76.5 74.0 dBc = 100 MHz 25°C V 78.5 76.0 74.0 dBc

= 69.1 MHz, f = 100.1 MHz, f

= 70.1 MHz 25°C V 71.0 70.0 70.0 dBc

IN2

= 101.1 MHz 25°C V 70.0 69.0 69.0 dBc

IN2

Rev. A | Page 4 of 40

AD9216

LOGIC SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 3.

Parameter Temp Test

LOGIC INPUTS

High Level Input

Voltage

Low Level Input

Voltage

High Level Input

Current

Low Level Input

Current

Input Capacitance Full IV 2 2 2 pF LOGIC OUTPUTS

DRVDD = 2.5 V

1

Output voltage levels measured with 5 pF load on each output.

, DCS enabled, unless otherwise noted.

MAX

Full IV 2.0 2.0 2.0 V

Full IV 0.8 0.8 0.8 V

Full IV −10 +10 −10 +10 −10 +10 µA

1

High Level Output

Full IV 2.45 2.45 2.45 V

Voltage Low Level Output

Full IV 0.05 0.05 0.05 V

Voltage

AD9216BCPZ-65 AD9216BCPZ-80 AD9216BCPZ-105

Min Typ Max Min Typ Max Min Typ Max Unit

Level

Rev. A | Page 5 of 40

AD9216

SWITCHING SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,

to T

T

MIN

Table 4.

Parameter Temp Test Level Min Typ Max Min Typ Max Min Typ Max Unit SWITCHING PERFORMANCE

Maximum Conversion Rate Full VI 65 80 105 MSPS Minimum Conversion Rate Full IV 10 10 10 MSPS

OUTPUT PARAMETERS

Output Propagation Delay2 (tPD) 25°C I 4.5 6.4 4.5 6.4 4.5 6.4 nS Valid Time3 (tV) 25°C I 2.0 2.0 2.0 Output Rise Time (10% to 90%) 25°C V 1.0 1.0 1.0 nS Output Fall Time (10% to 90%) 25°C V 1.0 1.0 1.0 nS Output Enable Time Output Disable Time4 Full IV 1 1 1 Cycle Pipeline Delay (Latency) Full IV 6 6 6 Cycle

APERTURE

Aperture Delay (tA) 25°C V 1.5 1.5 1.5 nS Aperture Uncertainty (tJ) 25°C V 0.5 0.5 0.5 pS Wake-Up Time

OUT-OF-RANGE RECOVERY TIME 25°C V 1 1 1 Cycle

1

C

LOAD

2

Output delay is measured from clock 50% transition to data 50% transition.

3

Valid time is approximately equal to the minimum output propagation delay.

4

Output enable time is OEB_A, OEB_B falling to respective channel outputs coming out of high impedance. Output disable time is OEB_A, OEB_B rising to respective

channel outputs going into high impedance.

5

Wake-up time is dependent on value of decoupling capacitors; typical values shown for 0.1 µF and 10 µF capacitors on REFT and REFB.

, DCS enabled, unless otherwise noted.

MAX

AD9216BCPZ-65 AD9216BCPZ-80 AD9216BCPZ-105

CLK Period Full VI 15.4 12.5 9.5 nS CLK Pulse Width High Full VI 4.6 4.4 3.8 nS CLK Pulse Width Low Full VI 4.6 4.4 3.8 nS

1

4

5

equals 5 pF maximum for all output switching parameters.

Full IV 1 1 1 Cycle

rms

25°C V 7 7 7 ms

Rev. A | Page 6 of 40

AD9216

TIMING DIAGRAM

N+1

ANALOG

INPUT

CLK

N–1

N

t

A

N+2

N+3

N+4

N+5

N+8

N+7

N+6

DATA

OUT

N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1

t

PD

04775-002

Figure 2.

Rev. A | Page 7 of 40

AD9216

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter To Rating

ELECTRICAL AVDD AGND

DRVDD DRGND

AGND DRGND

AVDD DRVDD

Digital Outputs DRGND

CLK_A, CLK_B, DCS, DFS, MUX_SELECT, OEB_A, OEB_B, SHARED_REF, PDWN_A, PDWN_B

VIN−_A, VIN+_A, VIN−_B, VIN+_B

REFT_A, REFB_A,VREF, REFT_B, REFB_B, SENSE

ENVIRONMENTAL

Operating Temperature

Junction Temperature 150°C Lead Temperature (10 sec) 300°C Storage Temperature

1

Typical thermal impedances (64-lead LFCSP); θ

measurements were taken on a 4-layer board (with thermal via array) in still air, in accordance with EIA/JESD51-7.

1

AGND

= 26.4°C/W. These

JA

−0.3 V to +3.9 V

−0.3 V to +0.3 V

−0.3 V to +3.9 V

−0.3 V to DRVDD +

0.3 V

−0.3 V to AVDD +

0.3 V

−0.3 V to AVDD +

0.3 V

−0.3 V to AVDD +

0.3 V

−40°C to +85°C

−65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

EXPLANATION OF TEST LEVELS

Table 6.

Test Level Description

I 100% production tested. II

III Sample tested only. IV

V Parameter is a typical value only. VI

100% production tested at 25°C and sample tested at specified temperatures.

Parameter is guaranteed by design and characterization testing.

100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 8 of 40

AD9216

A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVDD

CLK_A

SHARED_REF

MUX_SELECT

PDWN_A

OEB_A

DNC

D9_A (MSB)

D8_A

D7_A

D6_A

DRGND

DRVDD

D5_A

D4_A

646362616059585756555453525150

D3_A 49

AGND

1

VIN+_A

2

VIN–_A

3

AGND

4

AVDD

5

REFT_A

6

REFB_

7 8

VREF

9

SENSE

10

REFB_B

11

REFT_B

12

AVDD

13

AGND

14

VIN–_B

15

VIN+_B

16

AGND

DNC = DO NOT CONNECT

PIN 1 INDICATOR

AD9216

TOP VIEW

(Not to Scale)

171819202122232425262728293031

DFS

DCS

DNC

D0_B (LSB)

DRVDD

DRGND

D1_B

AVDD

CLK_B

OEB_B

PDWN_B

D2_B

32

D3_B

48

D2_A

47

D1_A

46

D0_A (LSB)

45

DNC

44

DNC

43

DNC

42

DNC

41

DRVDD

40

DRGND

39

DNC

38

D9_B (MSB)

37

D8_B

36

D7_B

35

D6_B

34

D5_B

33

D4_B

04775-003

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1, 4, 13, 16 AGND

1

Analog Ground. 2 VIN+_A Analog Input Pin (+) for Channel A. 3 VIN−_A Analog Input Pin (−) for Channel A. 5, 12, 17, 64 AVDD Analog Power Supply. 6 REFT_A Differential Reference (+) for Channel A. 7 REFB_A Differential Reference (−) for Channel A. 8 VREF Voltage Reference Input/Output. 9 SENSE Reference Mode Selection. 10 REFB_B Differential Reference (−) for Channel B. 11 REFT_B Differential Reference (+) for Channel B. 14 VIN−_B Analog Input Pin (−) for Channel B. 15 VIN+_B Analog Input Pin (+) for Channel B. 18 CLK_B Clock Input Pin for Channel B. 19 DCS Duty Cycle Stabilizer (DCS) Mode Pin (Active High). 20 DFS Data Output Format Select Pin. Low for offset binary; high for twos complement. 21 PDWN_B Power-Down Function Selection for Channel B.

Logic 0 enables Channel B. Logic 1 powers down Channel B. (Outputs static, not High-Z.)

22 OEB_B Output Enable for Channel B.

Logic 0 enables Data Bus B. Logic 1 sets outputs to High-Z.

23 to 26, 39,

DNC Do Not Connect Pins. Should be left floating.

42 to 45, 58 27, 30 to 38

D0_B (LSB) to

Channel B Data Output Bits.

D9_B (MSB) 28, 40, 53 DRGND Digital Output Ground. 29, 41, 52 DRVDD

Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 µF capacitor. Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF.

Rev. A | Page 9 of 40

AD9216

Pin No. Mnemonic Description

46 to 51, 54 to 57

D0_A (LSB) to D9_A (MSB)

59 OEB_A Output Enable for Channel A.

60 PDWN_A Power-Down Function Selection for Channel A.

61 MUX_SELECT Data Multiplexed Mode. (See Data Format section for how to enable.) 62 SHARED_REF Shared Reference Control Bit. Low for independent reference mode; high for shared reference mode. 63 CLK_A Clock Input Pin for Channel A.

1

It is recommended that all ground pins (AGND and DRGND) be tied to a common ground plane.

Channel A Data Output Bits.

Logic 0 enables Data Bus A. Logic 1 sets outputs to High-Z.

Logic 0 enables Channel A. Logic 1 powers down Channel A. (Outputs static, not High-Z.)

Rev. A | Page 10 of 40

AD9216

TERMINOLOGY

Analog Bandwidth

The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.

Aperture Delay

The delay between the 50% point of the rising edge of the encode command and the instant the analog input is sampled.

Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay.

Clock Pulse Width/Duty Cycle

Pulse-width high is the minimum amount of time that the clock pulse should be left in a Logic 1 state to achieve rated performance; pulse-width low is the minimum time clock pulse should be left in a low state. At a given clock rate, these specifications define an acceptable clock duty cycle.

Crosstalk

Coupling onto one channel being driven by a low level (−40 dBFS) signal when the adjacent interfering channel is driven by a full-scale signal.

Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance

The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180° and by taking the peak measurement again. The difference is then computed between both peak measurements.

Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step.

Effective Number of Bits (ENOB)

The ENOB is calculated from the measured SINAD based on the equation (assuming full-scale input)

SINAD

ENOB

=

MEASURED

6.02

dB1.76−

Full-Scale Input Power

Expressed in dBm and computed using the following equation.

2

⎛

V

⎜

Power

=

SCALEFULL

⎜

log10

⎜ ⎜ ⎜

⎝

SCALEFULL

Z

INPUT

0.001

rms

⎞ ⎟

⎟ ⎟ ⎟ ⎟

⎠

Gain Error

The difference between the measured and ideal full-scale input voltage range of the ADC.

Harmonic Distortion, Second

The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc.

Harmonic Distortion, Third

The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc.

Integral Nonlinearity

The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between a 50% crossing of the CLK rising edge and the time when all output data bits are within valid logic levels.

Rev. A | Page 11 of 40

AD9216

Noise (for Any Range within the ADC)

This value includes both thermal and quantization noise.

noise

ZV

⎛

××=

10.0010

⎜

⎜ ⎝

−−

10

⎞

dBFSdBcdBm

⎟

⎟ ⎠

SignalSNRFS

where:

Z is the input impedance.

FS is the full scale of the device for the frequency in question.

SNR is the value for the particular input level.

Signal

is the signal level within the ADC reported in dB below

full scale.

Power Supply Rejection Ratio

The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit.

Signal-to-Noise and Distortion (SINAD)

The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc.

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product, in dBc.

Two-Tone SFDR

The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It also may be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (that is, always relates back to converter full scale).

Worst Other Spur

The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic), reported in dBc.

Transi ent Res p onse T i m e

The time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.

Signal-to-Noise Ratio (without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first seven harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. It also may be reported in dBc (that is, degrades as signal level is lowered) or dBFS (that is, always related back to converter full scale).

Rev. A | Page 12 of 40

AD9216

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 3.0 V, DRVDD = 2.5 V, T = 25°C, AIN differential drive, internal reference, DCS on, unless otherwise noted.

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

Figure 4. FFT: f

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

SNR = 57.8dB SINAD = 57.8dB H2 = –92.7dBc H3 = –80.3dBc SFDR = 78.2dBc

20 30010 4050

FREQUENCY (MHz)

= 105 MSPS, AIN = 10.3 MHz at −0.5 dBFS (−105 Grade)

S

SNR = 56.9dB SINAD = 56.8dB H2 = –78.5dBc H3 = –80dBc SFDR = 78.3dBc

04775-018

0

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBFS)

–70

–80

–90

–100

27 28 29

Figure 7. FFT: f

= 105 MSPS, AIN =70 MHz, 76 MHz (−105 Grade)

S

70MHz ON CHANNEL A ACTIVE

76MHz CROSSTALK FROM CHANNEL B

30 31 32 33 34 35

(76)

FREQUENCY (MHz)

(A Port FFT while Both A and B Ports Are Driven at −0.5 dBFS)

0

–20

–40

76MHz CROSSTALK

–60

FROM CHANNEL B

–80

AMPLITUDE (dBFS)

70MHz ON CHANNEL A ACTIVE

SNR = 57.6dB SINAD = 57.4dB H2 = –84.1dBc H3 = –77.2dBc SFDR = 74dBc

(70)

04775-021

36

–100

–120

Figure 5. FFT: f

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

Figure 6. FFT: f

20 30010 4050

FREQUENCY (MHz)

= 105 MSPS, AIN = 70 MHz at −0.5 dBFS (−105 Grade)

S

0

20 30010 4050

FREQUENCY (MHz)

= 105 MSPS, AIN = 100 MHz at −0.5 dBFS (−105 Grade)

S

SNR = 56.8dB SINAD = 56.7dB H2 = –74dBc H3 = –84.3dBc SFDR = 74dBc

04775-019

04775-020

–100

–120

0

5 101520253035

Figure 8. FFT: f

S

FREQUENCY (MHz)

= 80 MSPS, AIN =70 MHz, 76 MHz (−80 Grade)

(A Port FFT while Both A and B Ports Are Driven at −0.5 dBFS)

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0

5 1015202530

Figure 9. FFT: f

70MHz ON CHANNEL A ACTIVE

76MHz CROSSTALK FROM CHANNEL B

FREQUENCY (MHz)

= 65 MSPS, AIN =70 MHz, 76 MHz (−65 Grade)

S

SNR = 57.5dB SINAD = 57.3dB H2 = –85.9dBc H3 = –74.4dBc SFDR = 72.4dBc

(A Port FFT while Both A and B Ports Are Driven at −0.5 dBFS)

04775-048

40

04775-049

Rev. A | Page 13 of 40

AD9216

100

90

H2

80

dB

70

60

50

0 20 40 60 80 100 120

SNR

SINAD

CLOCK FREQUENCY (MHz)

Figure 10. SNR, SINAD, H2, H3, SFDR vs. Sample Clock Frequency

= 70 MHz at −0.5 dBFS (−105 Grade)

A

IN

100

90

80

dB

70

60

H2

SNR

SFDR

H3

SFDR

04775-022

100

H2

90

80

dB

70

60

50

0

SFDR

50 100 150 200 250 300

ANALOG INPUT FREQUENCY (MHz)

H3

SNR

SINAD

Figure 13. Analog Input Frequency Sweep, A

f

= 80 MSPS (−80 Grade)

S

100

H2

90

H3

80

dB

70

SFDR

SNR

60

= −0.5 dBFS,

IN

04775-051

50

010

20 30 40 50 60 70 80 90 100

SINAD

CLOCK FREQUENCY (MHz)

Figure 11. SNR, SINAD, H2, H3, SFDR vs. Sample Clock Frequency,

= 70 MHz at −0.5 dBFS (−65/80 Grade)

A

IN

100

90

H2

80

dB

70

SFDR

60

50

0 50 100 150 200 250 300

ANALOG INPUT FREQUENCY (MHz)

H3

SNR

SINAD

Figure 12. Analog Input Frequency Sweep, AIN = −0.5 dBFS,

= 105 MSPS (−105 Grade)

f

S

04775-050

04775-023

50

50 100 150 200 250 300

0

Figure 14. Analog Input Frequency Sweep, A

90

80

70

60

50

dB

40

65dB REF. LINE

30

20

10

0 –60–50 –30–20–10 0

SINAD

ANALOG INPUT FREQUENCY (MHz)

f

= 65 MSPS (−65 Grade)

S

SFDR dBFS

SFDR dBc

SNR dB

–40

INPUT LEVEL (dBFS)

= −0.5 dBFS,

IN

Figure 15. SFDR vs. Analog Input Level,

= 70 MHz, fS = 105 MSPS (−105 Grade)

A

IN

04775-052

04775-053

Rev. A | Page 14 of 40

AD9216

90

80

70

60

50

dB

40

30

20

10

0

–60 –50 –40 –30 –20 –10 0

SFDR dBFS

SFDR dBc

65dB REF. LINE

SNR dB

INPUT LEVEL (dBFS)

Figure 16. SFDR vs. Analog Input Level,

= 70 MHz, fS = 80 MSPS (−80 Grade)

A

IN

90

80

SFDR dBFS

70

60

50

dB

40

30

20

10

0

–60 –50 –40 –30 –20 –10 0

SFDR dBc

SNR dB

65dB REF. LINE

INPUT LEVEL (dBFS)

Figure 17. SFDR vs. Analog Input Level,

= 70 MHz, fS = 65 MSPS (−65 Grade )

A

IN

0

–10

–20

–30

–40

–50

AMPLITUDE (dBFS)

–60

–70

–80

–90

–100

IMD = –69.9dBc

20 30010 4050

INPUT FREQUENCY (MHz)

Figure 18. Two-Tone IMD Performance

F1, F2 = 69.1 MHz, 70.1 MHz at −7 dBFS, 105 MSPS (−105 Grade)

04775-063

04775-054

04775-025

90

80

70

60

50

dB

40

30

20

10

0

–60 –50 –40 –30 –20 –10 0

TWO-TONE SFDR dBFS

TWO-TONE SFDR dBc

TWO-TONE ANALOG INPUT LEVEL (dBFS)

Figure 19. Two-Tone IMD Performance vs. Input Drive Level

(69.1 MHz and 70.1 MHz; f

90

80

70

60

50

dB

40

30

20

10

0

–60 –50 –40 –30 –20 –10 0

–70

= 105 MSPS (−105 Grade); F1, F2 Levels Equal)

S

SFDR dBFS

SFDR dBc

TWO-TONE ANALOG INPUT LEVEL (dBFS)

Figure 20. Two-Tone IMD Performance vs. Input Drive Level

(69.1 MHz and 70.1 MHz; f

90

80

70

60

50

dB

40

30

20

10

SFDR dBFS

0

–60 –50 –40 –30 –20 –10 0

–70

= 80 MSPS (−80 Grade); F1, F2 Levels Equal)

S

SFDR dBc

75dB REF. LINE

TWO-TONE ANALOG INPUT LEVEL (dBFS)

Figure 21. Two-Tone IMD Performance vs. Input Drive Level

(69.1 MHz and 70.1 MHz; f

= 65 MSPS (−65 Grade); F1, F2 Levels Equal)

S

70dB REF LINE

04775-026

75dB REF. LINE

04775-055

04775-056

Rev. A | Page 15 of 40

AD9216

100

90

80

70

TWO-TONE SFDR dBFS

60

50

dB

40

30

20

10

0

–60 –50 –40 –30 –20 –10 0

Figure 22. Two-Tone IMD Performance vs. Input Drive Level

(100.1 MHz and 101.1 MHz; f

100

90

80

70

60

50

40

CURRENT (mA)

30

20

10

0

10 20 40 60 80 90 100

80

TWO-TONE SFDR dBc

70dB REF LINE

TWO-TONE ANALOG INPUT LEVEL (dBFS)

= 105 MSPS (−105 Grade); F1, F2 Levels Equal)

S

AVDD CURRENT (–105 GRADE)

AVDD CURRENT (–65/80 GRADE)

DRVDD CURRENT (ALL GRADES)

30 50 70

SAMPLE CLOCK RATE (MSPS)

, I

Figure 23. I

C

LOAD

AVDD

= 5 pF, AIN = 70 MHz @ −0.5 dBFS

vs. Sample Clock Frequency,

DRVDD

04775-027

04775-028

80

75

70

65

60

dB

55

50

45

40

0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.95 1.05 1.15 1.25

SFDR

SNR

VREF (V)

04775-030

Figure 25. SNR, SFDR vs. External VREF (Full Scale = 2 × VREF)

= 70.3 MHz at −0.5 dBFS, 105 MSPS (−105 Grade)

A

IN

1.0

0.8

0.6

0.4

0.2

EXTERNAL REFERENCE MODE

0

–0.2

–0.4

GAIN ERROR (% Full Scale)

–0.6

–0.8

–1.0

–40–20020406080

INTERNAL REFERENCE MODE

TEMPERATURE (°C)

04775-031

Figure 26. Typical Gain Error Variation vs. Temperature, (−105 Grade)

= 70 MHz at 0.5 dBFS, 105 MSPS (Normalized to 25°C)

A

IN

80

70

60

SNR DCS ON

50

dB

40

30

20

25 30 35 40 45 50 55 60 65 70 75

SNR DCS OFF

POSITIVE DUTY CYCLE (%)

SFDR DCS ON

SFDR DCS OFF

Figure 24. SNR, SFDR vs. Positive Duty Cycle DCS Enabled, Disabled;

= 70 MHz at −0.5 dBFS, 105 MSPS (−105 Grade)

A

IN

04775-029

Rev. A | Page 16 of 40

75

70

dB

65

60

55

–40–20020406080

SFDR

SNR

SINAD

TEMPERATURE (°C)

Figure 27. SNR, SINAD, SFDR vs. Temperature, (−105 Grade)

= 70 MHz at −0.5 dBFS, 105 MSPS, Internal Reference Mode

A

IN

04775-032

AD9216

80

75

SFDR

70

dB

65

dB

65

SFDR

60

55

–40–20020406080

SNR

SINAD

TEMPERATURE (°C)

Figure 28. SNR, SINAD, SFDR vs. Temperature, (−105 Grade)

= 70 MHz at −0.5 dBFS, 105 MSPS , External Reference Mode

A

IN

80

75

70

dB

65

60

55

–20 0 20 40 60 80

–40

SFDR

SNR

SINAD

TEMPERATURE (°C)

Figure 29. SNR, SINAD, SFDR vs. Temperature, (-80 Grade)

= 70 MHz at −0.5 dBFS, 80 MSPS, Internal Reference Mode

A

IN

85

SFDR

80

75

04775-033

04775-057

60

55

2.7

2.8 2.9 3.0 3.1 3.2 3.3 AVDD (V)

Figure 31. SNR, SINAD, SFDR vs. AVDD, A

(−105 Grade)

80

75

70

dB

65

60

55

2.7

SFDR

SINAD

2.8 2.9 3.0 3.1 3.2 3.3 AVDD (V)

Figure 32. SNR, SINAD, SFDR vs. AVDD, A

(−80 Grade)

85

80

SFDR

75

SNR

SINAD

= 70 MHz at −0.5 dBFS, 105 MSPS

IN

SNR

= 70 MHz at −0.5 dBFS, 80 MSPS

IN

04775-059

04775-062

70

dB

65

60

55

–20 0 20 40 60 80

–40

TEMPERATURE (°C)

SINAD

Figure 30. SNR, SINAD, SFDR vs. Temperature, (-65 Grade)

A

= 70 MHz at −0.5 dBFS, 65 MSPS,, Internal Reference Mode

IN

SNR

04775-058

Rev. A | Page 17 of 40

70

dB

65

60

55

2.8 2.9 3.0 3.1 3.2 3.3

2.7

SINAD

AVDD (V)

Figure 33. SNR, SINAD, SFDR vs. AVDD, A

(−65 Grade)

SNR

= 70 MHz at −0.5 dBFS, 65MSPS

IN

04775-060

AD9216

2.0

5.2

1.5

1.0

0.5

0

LSB

–0.5

–1.0

–1.5

–2.0

0 200 400 600 800 1000

CODE

Figure 34. Typical DNL Plot, A

= 10.3 MHz at −0.5 dBFS, 105 MSPS

IN

(−105 Grade)

2.0

1.5

1.0

0.5

0

LSB

–0.5

04775-035

5.0

4.8

4.6

(ns)

PD

T

4.4

4.2

4.0 –40–200 20406080

TEMPERATURE (°C)

04775-061

Figure 36. Typical Propagation Delay vs. Temperature ( All Speed Grades)

–1.0

–1.5

–2.0

0 200 400 600 800 1000

Figure 35. Typical INL Plot, A

CODE

= 10.3 MHz at −0.5 dBFS, 105 MSPS

IN

(−105 Grade)

04775-036

Rev. A | Page 18 of 40

AD9216

EQUIVALENT CIRCUITS

AVDD

VIN+_A, VIN–_A, VIN+_B, VIN–_B

CLK_A, CLK_B

DCS, DFS,

MUX_SELECT,

SHARED_REF

Figure 37. Equivalent Analog Input

AVDD

Figure 38. Equivalent Clock, Digital Inputs Circuit

04775-004

04775-005

PDWN

30kΩ

04775-006

Figure 39. Power-Down Input

DRVDD

04775-007

Figure 40. Digital Outputs

Rev. A | Page 19 of 40

AD9216

THEORY OF OPERATION

The AD9216 consists of two high performance ADCs that are based on the AD9215 converter core. The dual ADC paths are independent, except for a shared internal band gap reference source, VREF. Each of the ADC paths consists of a proprietary front end SHA followed by a pipelined, switched-capacitor ADC. The pipelined ADC is divided into three sections, consisting of a sample-and-hold amplifier, followed by seven 1.5-bit stages, and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined through the digital correction logic block into a final 10-bit result. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the respective clock.

Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC and a residual multiplier to drive the next stage of the pipeline. The residual multiplier uses the flash ADC output to control a switched capacitor digital-to-analog converter (DAC) of the same resolution. The DAC output is subtracted from the stage’s input signal and the residual is amplified (multiplied) to drive the next pipeline stage. The residual multiplier stage is also called a multiplying DAC (MDAC). One bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC.

The input stage contains a differential SHA that can be configured as ac- or dc-coupled in differential or single-ended modes. The output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing.

ANALOG INPUT

The analog input to the AD9216 is a differential switchedcapacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA input accepts inputs over a wide common-mode range. An input common-mode voltage of midsupply is recommended to maintain optimal performance.

This passive network creates a low-pass filter at the ADC’s input; therefore, the precise values are dependant on the application. In IF under-sampling applications, any shunt capacitors should be removed. In combination with the driving source impedance, they would limit the input bandwidth. For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched, so the common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC.

H

VIN+

VIN

T

C

PAR

T

–

C

PAR

Figure 41. Switched-Capacitor Input

0.5pF

T

H

04775-008

An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common-mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as:

REFT = 1/2 (AV D D + VREF)

REFB = 1/2 (AV D D − VREF)

Span = 2 × (REFT − REFB) = 2 × VREF

It can be seen from the equations above that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage.

The SHA may be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as

The SHA input is a differential switched-capacitor circuit. In Figure 41, the clock signal alternatively switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. Also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents.

Rev. A | Page 20 of 40

VCM

= VREF/2

MIN

= (AV D D + VREF)/2

MAX

The minimum common-mode input level allows the AD9216 to accommodate ground-referenced inputs. Although optimum performance is achieved with a differential input, a single-ended source may be driven into VIN+ or VIN−. In this configuration, one input accepts the signal, while the opposite input should be set to midscale by connecting it to an appropriate reference.

AD9216

2

For example, a 2 V p-p signal may be applied to VIN+, while a 1 V reference is applied to VIN−. The AD9216 then accepts an input signal varying between 2 V and 0 V. In the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies.

85

80

75

70

65

dB

60

55

50

45

40

0.25 0.75 1.25 1.75 2.25 2.75 ANALOG INPUT COMMON-MODE VOLTAGE (V)

2V p-p SFDR

2V p-p SNR

04775-009

Figure 42. Input Common-Mode Voltage Sensitivity

Differential Input Configurations

As previously detailed, optimum performance is achieved while driving the AD9216 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set to AVDD/2, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.

At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the AD9216. This is especially true in IF under-sampling applications where frequencies in the 70 MHz to 200 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration, as shown in Figure 43.

AVDD

VIN_A

AD9216

VIN_B

AGND

V p-p

49.9Ω

50Ω

10pF

50Ω

10pF

1kΩ

For dc-coupled applications, the AD8138, AD8139, or AD8351 can serve as a convenient ADC driver, depending on requirements. Figure 44 shows an example with the AD8138. The AD9216 PCB has an optional AD8139 on board, as shown in Figure 53. Note the AD8351 typically yields better performance for frequencies greater than 30 MHz to 40 MHz.

49.9Ω

1kΩ

0.1µF

Figure 44. Driving the ADC with the AD8138

SENSE = GROUND

VIN+

FULL

SCALE/2

AVDD/2 AVDD/2

VIN–

DIGITAL OUT = ALL ONES DIGITAL OUT = ALL ZEROES

Figure 45. Analog Input Full Scale (Full Scale = 2 V)

499Ω

523Ω

499Ω

AD8138

499Ω

33Ω

20pF

AVDD

VIN+

AD9216

VIN–

AGND

04775-011

04775-012

Single-Ended Input Configuration

A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, there is a degradation in SFDR and distortion performance due to the large input common-mode swing. However, if the source impedances on each input are matched, there should be little effect on SNR performance.

0.1µF

1kΩ

04775-010

Figure 43. Differential Transformer Coupling

The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion.

Rev. A | Page 21 of 40

AD9216

CLOCK INPUT AND CONSIDERATIONS

Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics.

The AD9216 provides separate clock inputs for each channel. The optimum performance is achieved with the clocks operated at the same frequency and phase. Clocking the channels asynchronously may degrade performance significantly. In some applications, it is desirable to skew the clock timing of adjacent channels. The AD9216’s separate clock inputs allow for clock timing skew (typically ±1 ns) between the channels without significant performance degradation.

POWER DISSIPATION AND STANDBY MODE

The power dissipated by the AD9216 is proportional to its sampling rates. The digital (DRVDD) power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The digital drive current can be calculated by

I

= V

DRVDD

where

N is the number of bits changing, and C

load on the digital pins that changed.

The analog circuitry is optimally biased, so each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates that increases with clock frequency.

DRVDD

× C

LOAD

× f

CLOCK

× N

is the average

LOAD

The AD9216 contains two clock duty cycle stabilizers, one for each converter, that retime the nonsampling edge, providing an internal clock with a nominal 50% duty cycle. Faster input clock rates, where it becomes difficult to maintain 50% duty cycles, can benefit from using DCS, as a wide range of input clock duty cycles can be accommodated. Maintaining a 50% duty cycle clock is particularly important in high speed applications, when proper track-and-hold times for the converter are required to maintain high performance. The DCS can be enabled by tying the DCS pin high.

The duty cycle stabilizer uses a delay-locked loop to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 2 µs to 3 µs to allow the DLL to acquire and settle to the new rate.

High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (f

) due only to aperture jitter (tJ) can be

INPUT

calculated by

SNR degradation = 2 × log 10[1/2 × p × f

In the equation, the rms aperture jitter,

t

, represents the root-

J

INPUT

× tJ]

sum square of all jitter sources, which includes the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter.

For optimal performance, especially in cases where aperture jitter may affect the dynamic range of the AD9216, it is important to minimize input clock jitter. The clock input circuitry should use stable references; for example, use analog power and ground planes to generate the valid high and low digital levels for the AD9216 clock input. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.

Either channel of the AD9216 can be placed into standby mode independently by asserting the PWDN_A or PDWN_B pins. Time to go into or come out of standby mode is 5 cycles maximum when only one channel is being powered down. When both channels are powered down, VREF goes to ground, resulting in a wake-up time of ~7 ms dependent on decoupling capacitor values.

It is recommended that the input clock(s) and analog input(s) remain static during either independent or total standby, which results in a typical power consumption of 3 mW for the ADC. If the clock inputs remain active while in total standby mode, typical power dissipation of 10 mW results.

The minimum standby power is achieved when both channels are placed into full power-down mode (PDWN_A = PDWN_B = HI). Under this condition, the internal references are powered down. When either or both of the channel paths are enabled after a power-down, the wake-up time is directly related to the recharging of the REFT and REFB decoupling capacitors and to the duration of the power-down.

A single channel can be powered down for moderate power savings. The powered-down channel shuts down internal circuits, but both the reference buffers and shared reference remain powered on. Because the buffer and voltage reference remain powered on, the wake-up time is reduced to several clock cycles.

DIGITAL OUTPUTS

The AD9216 output drivers can interface directly with 3 V logic families. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches because large drive currents tend to cause current glitches on the supplies that may affect converter performance.

The data format can be selected for either offset binary or twos complement. This is discussed in the Data Format section.

Rev. A | Page 22 of 40

AD9216

OUTPUT CODING

Table 8.

Code (VIN+) − (VIN−) Offset Binary Twos Complement

1023 > +0.998 V 11 1111 1111 01 1111 1111 1023 +0.998 V 11 1111 1111 01 1111 1111 1022 +0.996 V 11 1111 1110 01 1111 1110

• • • •

• • • • 513 +0.002 V 10 0000 0001 00 0000 0001 512 +0.0 V 10 0000 0000 00 0000 0000 511 −0.002 V 01 1111 1111 11 1111 1111

• • • •

• • • • 1 −0.998 V 00 0000 0001 10 0000 0001 0 −1.000 V 00 0000 0000 10 0000 0000 0 < −1.000 V 00 0000 0000 10 0000 0000

TIMING

The AD9216 provides latched data outputs with a pipeline delay of six clock cycles. Data outputs are available one propagation delay (t Figure 2 for a detailed timing diagram.

The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9216. These transients can detract from the converter’s dynamic performance. The lowest conversion rate of the AD9216 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance may degrade.

) after the rising edge of the clock signal. Refer to

PD

DATA FORMAT

The AD9216 data output format can be configured for either twos complement or offset binary. This is controlled by the data format select pin (DFS). Connecting DFS to AGND produces offset binary output data. Conversely, connecting DFS to AVDD formats the output data as twos complement.

The output data from the dual ADCs can be multiplexed onto a single, 10-bit output bus. The multiplexing is accomplished by toggling the MUX_SELECT bit, which directs channel data to the same or opposite channel data port. When MUX_SELECT is logic high, the Channel A data is directed to the Channel A output bus, and the Channel B data is directed to the Channel B output bus. When MUX_SELECT is logic low, the channel data is reversed; that is, the Channel A data is directed to the Channel B output bus, and the Channel B data is directed to the Channel A output bus. By toggling the MUX_SELECT bit, multiplexed data is available on either of the output data ports.

If the ADCs are run with synchronized timing, this same clock can be applied to the MUX_SELECT pin. Any skew between CLK_A, CLK_B, and MUX_SELECT can degrade ac performance. It is recommended to keep the clock skew < 100 pHs. After the MUX_SELECT rising edge, either data port has the data for its respective channel; after the falling edge, the alternate channel’s data is placed on the bus. Typically, the other unused bus is disabled by setting the appropriate OEB high to reduce power consumption and noise. Figure 46 shows an example of multiplex mode. When multiplexing data, the data rate is two times the sample rate. Note that both channels must remain active in this mode and that each channel’s powerdown pin must remain low.

A

–1

B

–1

0

B

0

B

–7

Figure 46. Example of Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT

A

1

B

1

A

B

–6

A

2

B

2

A

B–5A–4B–4A

–5

A

3

B

3

A

4

B

4

B

–3

A

5

B

5

A

B

–2

A–1B

A

6

B

6

A0B0A1B

–1

7

B

7

A

B

1

8

ANALOG INPUT ADC A

ANALOG INPUT ADC B

CLK_A = CLK_B = MUX_SELECT

D0_A –D11_A

04775-013

Rev. A | Page 23 of 40

AD9216

VOLTAGE REFERENCE

A stable and accurate 0.5 V voltage reference is built into the AD9216. The input range can be adjusted by varying the reference voltage applied to the AD9216, using either the internal reference with different external resistor configurations or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly.

Internal Reference Connection

A comparator within the AD9216 detects the potential at the SENSE pin and configures the reference into three possible states, which are summarized in Table 9. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 47), setting VREF to 1 V. If a resistor divider is connected, as shown in Figure 48, the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as

VREF = 0.5 × (1 + R2/R1)

Table 9. Reference Configuration Summary

Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p)

External Reference AVDD N/A 2 × External Reference Programmable Reference 0.2 V to VREF 0.5 × (1 + R2/R1) 2 × VREF (see Figure 48) Internal Fixed Reference AGND to 0.2 V 1.0 2.0

Note: The optimum performance is obtained with VREF =

1.0 V; performance degrades as VREF (and full scale) reduces (see Figure 25). In all reference configurations, REFT and REFB drive the ADC core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.

VIN+ VIN–

ADC

CORE

VREF

10µF

0.1µF

SENSE

Figure 47. Internal Reference Configuration (One Channel Shown)

SELECT

LOGIC

0.5V

AD9216

REFT

REFB

0.1µF

10µF

04775-014

Rev. A | Page 24 of 40

AD9216

External Reference Operation

The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve the thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may be necessary to reduce gain matching errors to an acceptable level. A high precision external reference may also be selected to provide lower gain and offset temperature drift. Figure 49 shows the typical drift characteristics of the internal reference.

When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 kΩ load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 V. If the internal reference of the AD9216 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 50 depicts how the internal reference voltage is affected by loading.

VIN+ VIN–

CORE

V

REF

10µF

SENSE

R2

R1

SELECT

LOGIC

0.5V

AD9216

Figure 48. Programmable Reference Configuration (one channel shown)

ADC

REFT

REFB

0.1µF

10µF

0.6

0.5

0.4

0.3 VREF = 1.0V

VREF ERROR (%)

0.2

0.1

0

–40–200 20406080

0.05

0

–0.05

–0.10

VREF ERROR (%)

–0.15

–0.20

–0.25

0 0.5 1.0 1.5 2.0 2.5 3.0

TEMPERATURE (°C)

Figure 49. Typical VREF Drift

VREF = 1.0V

I

(mA)

LOAD

04775-016

04775-017

Figure 50. VREF Accuracy vs. Load

Shared Reference Mode

The shared reference mode allows the user to connect the references from the dual ADCs together externally for superior gain and offset matching performance. If the ADCs are to function independently, the reference decoupling can be treated independently and can provide superior isolation

04775-015

between the dual channels. To enable shared reference mode, the SHARED_REF pin must be tied high, and the external differential references must be externally shorted. (REFT_A must be externally shorted to REFT_B, and REFB_A must be shorted to REFB_B.)

Rev. A | Page 25 of 40

AD9216

DUAL ADC LFCSP PCB

The PCB requires a low jitter clock source, analog sources, and power supplies. The PCB interfaces directly with ADI’s standard dual-channel data capture board (HSC-ADC-EVALDC), which together with ADI’s ADC Analyzer™ software allows for quick ADC evaluation.

POWER CONNECTOR

Power is supplied to the board via three detachable 4-lead power strips.

Table 10. Power Connector

Terminal Comments

VCC1 3.0 V Analog supply for ADC VDD1 2.5 V Output supply for ADC VDL1 2.5 V Buffer supply VCLK 3.0 V Supply for XOR Gates +5 V Optional op amp supply

−5 V Optional op amp supply

1

VCC, VDD, and VDL are the minimum required power connections.

ANALOG INPUTS

The evaluation board accepts a 2 V p-p analog input signal centered at ground at two SMB connectors, Input A and Input B. These signals are terminated at their respective primary side transformer. T1 and T2 are wideband RF transformers that provide the single-ended-to-differential conversion, allowing the ADC to be driven differentially, minimizing even-order harmonics. The analog signals can be low-pass filtered at the secondary transformer to reduce high frequency aliasing.

OPTIONAL OPERATIONAL AMPLIFIER

The PCB has been designed to accommodate an optional AD8139 op amp that can serve as a convenient solution for dc-coupled applications. To use the AD8139 op amp, remove C14, R4, R5, C13, R37, and R36, and place R22, R23, R30, and R24.

CLOCK

The single-clock input is at J5; the input clock is buffered and drives both channel input clocks from Pin 3 at U8 through R79, R40, and R85. Jumper E11 to E19 allows for inverting the input clock. U8 also provides CLKA and CLKB outputs, which are buffered by U6 and U5, which drive the DRA and DRB signals (these are the data-ready clocks going off card). DRA and DRB can also be inverted at their respective jumpers.

Table 11. Jumpers

Terminal Comments

OEB A Output Enable for A Side PWDN A Power-Down A MUX Mux Input SHARED REF Shared Reference Input DRA Invert DRA LATA Invert A Latch Clock ENC A Invert Encode A OEB B Output Enable for B Side PWDN B Power-Down B DFS Data Format Select SHARED REF Shared Reference Input DRB Invert DRB LATB Invert B Latch Clock ENC B Invert Encode B

VOLTAGE REFERENCE

The ADC SENSE pin is brought out to E41, and the internal reference mode is selected by placing a jumper from E41 to ground (E27). External reference mode is selected by placing a jumper from E41 to E25 and E30 to E2. R56 and R45 allow for programmable reference mode selection.

DATA OUTPUTS

The ADC outputs are buffered on the PCB at U2, U4. The ADC outputs have the recommended series resistors in line to limit switching transient effects on ADC performance.

Rev. A | Page 26 of 40

AD9216

LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM)

Table 12. Dual CSP PCB Rev. B

No. Quan. Reference Designator Device Package Value

1 2 C1, C3 Capacitors 0201 20 pF 2 7 C2, C5, C7, C9, C10, C22, C36 Capacitors 0805 10 µF 3 44

C4, C6, C8, C11 to C15, C20, C21, C24 to C27, C29 to

Capacitors 0402 0.1 µF, (C59, C61 NP

C35, C39 to C66 4 7 C16 to C19, C37, C38,C67 Capacitors TAJD 10 µF 5 2 C23, C28 Capacitors 0201 0.1 µF 6 40

E1 to E7, E9 to E22, E24 to E27, E29 to E31, E33 to

Jumpers

E38, E40 to E43, E49, E61 7 6 J1 to J6 SMA 8 3 P1, P4, P11 Power Connector Posts Z5.531.3425.0 Wieland 9 3 P1, P4, P11 Detachable Connectors 25.602.5453.0 Wieland 10 1 P3, P8 (implemented as one 80 pin connector) Connector TSW-140-08-

Samtec

L-D-RA 11 4 R1, R2, R32, R34 Resistors 0402 36 Ω (All NP1) 12 6 R3, R7, R11, R14, R51, R61 Resistors 0402 50 Ω, (R11, R51 NP1) 13 4 R6, R8, R33, R42 Resistors 0402 100 Ω, (All NP1) 14 4 R4, R5, R36, R37 Resistors 0402 33 Ω 15 10 R9, R12, R20, R35, R40, R43, R50, R53, R84, R85 Resistors 0402

Zero Ω (R9, R12, R35,

R43, R50, R84 NP 16 6 R15, R16, R18, R26, R29, R31 Resistors 0402 499 Ω (R16, R29 NP1) 17 2 R17, R25 Resistors 0402 525 Ω 18 34

R19, R21, R27, R28, R39, R41, R44, R46 to R49, R52, R54, R55, R57 to R60, R62 to R73, R75, R77, R78, R81

Resistors 0402

1 kΩ (R64, R78, R81, R82,

R83 NP

1

)

to R83

19 4 R22 to R24, R30 Resistors 0402

40 Ω (R22, R23, R24, R30

1

)

NP 20 2 R45, R56 Resistors 0402 10 kΩ (R45, R56 NP1) 21 7 R10, R13, R38, R74, R76, R79, R80 Resistor 0402 22 Ω 22 8 RZ1, RZ2, RZ3, RZ4, RZ5, RZ6, RZ9, RZ10 Resistor Pack CTS

47 Ω

742C163470J

24 2 T1, T2 Transformers T1-1WT Minicircuits

1

)

1

)

25 1 U1 AD9216/AD9238/AD9248 LFCSP-64

26 2 U2, U4 Transparent Latch/Buffer TSSOP-48 SN74LVCH16373ADGGR 27 2 U3, U7 Inverter SC-70

SN74LVC1G04DCKT

(U3, U7 NP

1

) 28 3 U5, U6, U8 XOR SO-14 SN74VCX86 29 2 U11, U12 Amp SO-8/EP AD8139

30 14 P2, P5 to P7, P9, P10, P12 to P18, P21 Solder Bridge

1

Not Populated.

Rev. A | Page 27 of 40

AD9216

LFCSP PCB SCHEMATICS

Ω

ENCA

R33

NP_100

R42

NP_100

VD

VCLK

C25

0.1µF

Ω

R43

VCLK

C58

0.1µF

C36

DUT CLOCK SELECTABLE

TO BE DIRECT OR BUFFERED

VD

10µF

SN74LVC1G04

C56

R64

NP_0

Ω

22

4

5

VCC

NCAGND

123

J6

F

µ

0.1

MUX

E9

E7

Ω

NP_1k

P1

P4

P11

Y

R61

VD

R65

R74

U7

Ω

50

1kΩ

VD

412 3

4123 4123

E10

E17

VD

14

VCC

74LCX86

1A

1234567

P12 P10

VCLK

R39

Ω

R63

1k

E6

E5

+5V –5VVCLKVDLVDD

VD

E15

Ω

E14

E13 E12

R46

1k

DRA

Ω

R10

22

124Y113B103A9

4B134A

1B1Y2A2B2Y

E4

P14

VD

1kΩ

C40

0.1µF

TIEA

J3

CLOCK A

C8

0.1µF

VDD

Ω

E20

R62

1k

E18

ENCA

Ω

R66

1k

C45

C44

C43

C39

VD

+

C67

EXT_VREF VCLK

C19

C18

VDD VDL

C17

+ + + ++

VD

C16

+5V

C38

+

–5V

C37

VDL

VD

VDD

P5

P7

P6

P21 VCLK

VD

E38

Ω

E37

E34 E16

R48

1k

DRB

R12

Ω

R13

22

41Y31B21A1

2A

1011121314

E36VD

R49

1kΩ

E35

R54

1kΩ

R51

J2

CLOCK B



R70

F

SENSE

µ

C30

0.1

R45

Ω

E41

NP_10k

E25

VD

E27

NP_50Ω

R69

R68

F

µ

0.1

Ω

NP_10k

E30

Ω

R55

1k

74VCX86

F

µ

C41

0.1

VD

E31

Ω

1k

Ω

1k

Ω

1k

R67

VREF

C2

E2

VD

E33

E26

VD

E29

E21

VD

E40

E22

VD

Ω

1k

E24

F

µ

10

F

E1

µ

C66

0.1

EXT_VREF

04775-038

ENCB

NP_100ΩR8

R50

VCLK

R38

4

Y

VCC

A

GND

NC

2

3

32

D7_B

31

D6_B

30

D5_B

29

DRVDD

28

DRGND

27

D4_B

26

D3_B

25

D2_B

24

D1_B

23

D0_B

22

OEB_B

21

PDWN_B

20

DFS

19

DCS

18

CLK_B

17

AVDD3

F

µ

C63

0.1

Ω

R32

NP_36

T1

J1

Ω

NP_100

CLKLATB

VCLK

P9 P2

R52

D7B D6B

D5B

D4B D3B D2B D1B D0B

ENCB VD

U5

1kΩ

F

µ

0.1

7

8

P13

TIEB

Ω

NP_0

62B5

2Y

GND 3Y3A3B4Y4A4BVCC

9

C42

0.1µF

C6

VDD

Ω

NP_0

Ω

22

U3

C11

AMPOUTB

Ω

R36

33

R56

F

µ

0.1

Ω

50

VREF AND SENSE CIRCUIT

C13

R7

Ω

R47

1k

R6

Ω

NP_0

8

R9

CLKLATA

BUFFERED

TO BE DIRECT OR

DUT CLOCK SELECTABLE

VD

3Y

C57

D13B

D12B

D11B

37

36

D13_B

D12_B

D11_B

14-BIT PINOUT SHOWN

FOR 14-BIT: LSB = PIN 42, PIN 23

FOR 12-BIT: LSB = PIN 44, PIN 25

FOR 10-BIT: LSB = PIN 46, PIN 27

AGND214VIN_BB15VIN_B16AGND3

AVDD2

13

12

VD

C28

0.1µF

10µF

0.1µF

AMPOUTBB

REFBB

P18

P17

CTAPB

Ω

R60

1k

F

Ω

µ

1k

C10

10

D10B

35

D10_B

6

1

C12

C22

0.1µF

10µF

5

SN74LVC1G04

1

D9B

D8B

34

33

D9_B

D8_B

C3

20pF

Ω

R37

33

Ω

R34

NP_36

5

4

2

3

CTAPB

AMPINB

F

µ

0.1 AIN B

U6

GND

R44

1kΩ

E3

R41

1kΩ

R11

NP_50Ω

D8A

D11A D13A

1µF

.

0 1µF

.

0 1µF

.

0

0.1µF

10µF

D6_A D6A48D5_A D5A47D4_A D4A46D3_A D3A45D2_A D2A44D1_A D1A43D0_A D0A

D7_A D7A

49

D8_A

50

D9_A D9A

51 52 53 54 55 56 57 58 59 60 61 62 63 64

65

AGND2VIN_A3VIN_AB4AGND1

1

AMPOUTA

Ω

R4

33

Ω

R1

NP_36

F

µ

C14

0.1

Ω

R3

50

DRVDD2

DRGND2 D10_A D10A D11_A D12_A D12A D13_A

OTR_A OTRA OEB_A

SH_REF

CLK_A

AVDD5

EPAD

C1

20pF

J4

PWDN_A

C62

R2

MUX_SEL

0.1µF

Ω

NP_36

T2

AVDD16REFT_A

5

VD

REFT_A

C23

0.1µF C55

C5

C24

0.1µF

Ω

R5

33

CTAPA

6

5

1

2

CTAPA

AMPINA

C31

AIN A

J2, J3, OPTIONAL CLOCK PATHING

C4

42

7

REFB_A

C26

4

3

F

µ

0.1

F

µ

0.1

REFB_A

0.1µF

10µF

0.1µF

AMPOUTAB

C9

41

8

R58

DRVDD1

VREF

SEE

PADS TO SHORT

F

µ

10

VDD

40

DRGND1

U1

SENSE

9

SENSE

BELOW

C29

0.1µF

REFTA

P15

REFERENCES TOGETHER

Ω

1k

R57

38

39

OTR_B OTRB

NOTE

REFB_B11REFT_B

10

REFB_B

REFT_B

C54

C7

C27

REFTB

REFBA

P16

VD

E42

E43

Ω

R59

1k

Figure 51. PCB Schematic (1 of 3)

Rev. A | Page 28 of 40

AD9216

D13Q

D12Q

D11Q

DRA

GND

D13P

D12P

D11P

D10P

D10Q

D9Q

D8Q

D7Q

D6Q

GND

D9P

D8P

D7P

D6P

D5P

D0P

D4P

D3P

D2P

D1P

DORP

DRB

D5Q

D0Q

D4Q

DORQ

D3Q

D2Q

D1Q

DORP

D13P

D12P

16151413121110

47Ω

RZ5

47Ω

RZ3

R3R1R2

RSO16ISO

22

23

24

2Q7

2Q8

OE2

D = INPUT

Q = OUTPUT

LE2

2D7

2D8

27

26

25

CLKLATA

16151413121110

R3R1R2

RSO16ISO

GND GND

39

37

39

P3

40

D9P

D8P

D11P

R4

D7P

D10P

9

R8

R7

R6

R5

876

54312

3234363840

47Ω

RZ6

RSO16ISO

212325272931333537

D6P

16151413121110

11131517192123252729313335

1113151719

D5P

D4P

D3P

D2P

R5

R4

R3R1R2

54312

13579

HEADER40

246

8

101214161820222426283032343638

246

8

1012141618202224262830

D13Q

D10Q

D9Q

D12Q

D11Q

D1P

D0P

9

R8

R7

R6

876

DORQ

16151413121110

47Ω

RZ10

RSO16ISO

R3R1R2 312

R6

R5

R4

5

4

37

39

37

39

P8

242628303234363840

40

D6Q

D3Q

D4Q

D8Q

D7Q

9

R8

R7

876

D5Q

16151413121110

47Ω

RZ9

R3R1R2

RSO16ISO

R5

R4

54312

11131517192123252729313335

10121416182022

D0Q

D1Q

D2Q

9

R8

R7

R6

8

7

6

13579

HEADER40

246

8

246

8

101214161820222426283032343638



C50

0.1µF

C51

0.1µF

VDL

6

8

9

11

12

10

7

1Q3

1Q4

1Q5

1Q6

1Q7

VCC

GND

VCC

1D3

1D4

1D5

1D6

1D7

GND

43

41

40

38

37

39

42

VDL

16151413121110

R4

R3R1R2

RSO16ISO

5

44

R5 54312

4

GND

45

R6

6

3

1Q2

1D2

46

2

1

1Q1

OE1

1D1

LE1

47

48

CLKLATB

9

R8

R7

8

7

U4

SN74LVCH16373A

R78

NP_1kΩ

R81

NP_1kΩ

C52

0.1µF

C53

0.1µF

C46

0.1µF

C47

0.1µF

C48

0.1µF

C49

0.1µF

VDL

23

26

2Q7

2D7

R3R1R2 312

VDL

13

14

16

17

19

20

22

21

2Q6

2D6

GND GND

29

27

28

R5

R4

5

4

2Q5

2D5

30

15

18

2Q1

2Q2

2Q3

2Q4

VCC

2D4

31

VDL

R6

1Q8

GND

1D8

2D1

2D2

2D3

36

35

33

32

34

9

47Ω

R8

R7

876

RZ2

VDL

13

14

16

17

19

20

21

2Q6

2D6

29

28

R5

R4

54312

2Q5

2D5

15

18

2Q3

1Q8

2Q1

2Q2

2Q4

VCC

GND

VCC

2D4

30

31

VDL

R7

R6

1D8

2D1

2D2

2D3

GND

36

35

33

32

34

9

47Ω

R8 876

RZ4

VDL

6

8

9

11

12

10

7

1Q4

1Q5

1Q6

1Q7

VCC

GND

VCC

1D4

1D5

1D6

1D7

GND

39

42

43

41

40

38

37

VDL

16151413121110

R4

R3R1R2

RSO16ISO

5

1Q3

1D3

44

R5 54312

4

GND

45

R6 6

3

1Q2

1D2

46

1

2

1Q1

OE1

LE1

1D1

48

47

CLKLATA

9

R7

R8

8

7

U2

SN74LVCH16373A

R82

NP_1kΩ

R83

NP_1kΩ

47Ω

RZ1

RSO16ISO

24

2Q8

OE2

D = INPUT

Q = OUTPUT

LE2

2D8

25

CLKLATB

16151413121110

D13A

OTRA

D12A

D11A

D10A

D8A

D9A

D7A

D6A

D2A

D3A

D4A

D5A

D0A

D1A

OTRB

D13B

D12B

D11B

D10B

D9B

D8B

D7B

D5B

D6B

D4B

D0B

D3B

D2B

D1B

04775-039

Figure 52. PCB Schematic (2 of 3)

Rev. A | Page 29 of 40

AD9216

MUXMUX1

R35

R84

NP_0Ω

SINGLE CLOCK CIRCUIT

TO TIE CLOCKS TOGETHER

E49

E61

R40

R85

5

2A

2B

U8

4Y

3B

10

CLKB

R72

1kΩ

C64

J5

CLOCK A/B

0Ω

4

11

R76

1µF

7

GND

3Y

8

R80

CLKA

R77

ENCA

ENCB

6

2Y

3A

9

22Ω

1kΩ

VCLK

SCLK MUX1

1Y

4A

22Ω

R53

E19 VD

E11

SCLK

R79

3

12

22Ω

R71

R14

0Ω

1B

4B

TIEBCLKB

2

13

1kΩ

50Ω

R20

R75

1

1A

VCC

14

VCLK

R73

TIEACLKA

0Ω

1kΩ

74VCX86

C65

0.1µF

1kΩ

R19

1kΩ

VD

R16

NP_499Ω

AMPINA

OP AMP INPUT OFF PIN ONE OF TRANSFORMER

R17

525Ω

SINGLE CLOCK PATH

R26

R28

1kΩ

VD

R25

525Ω

R29

NP_499Ω

AMPINB

C15

499Ω

C59

C21

R21

9

NP_0.1µF

C20

R27

9

1kΩ

1

8

R15

R31

0.1µF

–IN

EPAD

+IN

C33

499Ω

C60

0.1µF

1kΩ

1

–IN

EPAD

+IN

8

C34

499Ω

R18

2

VOCM

NC

7

0.1µF

NP_0.1µF

2

VOCM

NC

7

0.1µF

499Ω

C32

0.1µF

+5V

R22

NP_40Ω

4

36

V+

+OUT

U11

AMPOUTA

AD8139

V–

–OUT

5

–5V

C35

0.1µF

+5V

4

36

V+

+OUT

U12

R23

R30

NP_40Ω

AMPOUTAB

NP_40Ω

AD8139

V–

–OUT

5

–5V

R24

NP_40Ω

AMPOUTB AMPOUTBB

Figure 53. PCB Schematic (3 of 3)

Rev. A | Page 30 of 40

C61

04775-040

NP_0.1µF

AD9216

LFCSP PCB LAYERS

04775–041

Figure 54. PCB Top-Side Silkscreen

Rev. A | Page 31 of 40

AD9216

04775–042

Figure 55. PCB Top-Side Copper Routing

Rev. A | Page 32 of 40

AD9216

Figure 56. PCB Ground Layer

Rev. A | Page 33 of 40

04775–043

AD9216

04775–044

Figure 57. PCB Split Power Plane

Rev. A | Page 34 of 40

AD9216

04775–045

Figure 58. PCB Bottom-Side Copper Routing

Rev. A | Page 35 of 40

AD9216

Figure 59. PCB Bottom-Side Silkscreen

Rev. A | Page 36 of 40

04775–046

AD9216

THERMAL CONSIDERATIONS

The AD9216 LFCSP package has an integrated heat slug that improves the thermal and electrical properties of the package when locally attached to a ground plane at the PCB. A thermal (filled) via array to a ground plane beneath the part provides a path for heat to escape the package, lowering junction temperature. Improved electrical performance also results from the reduction in package parasitics due to proximity of the ground plane. Recommended array is 0.3 mm vias on 1.2 mm pitch. θ configuration. Soldering the slug to the PCB is a requirement for this package.

= 26.4°C/W with this recommended

JA

Figure 60. Thermal Via Array

04775-047

Rev. A | Page 37 of 40

AD9216

OUTLINE DIMENSIONS

BSC SQ

PIN 1 INDICATOR

9.00

TOP

VIEW

8.75

BSC SQ

0.60 MAX

49

48

0.60 MAX

EXPOSED PAD

(BOTTOM VIEW)

0.30

0.25

0.18

64

1

PIN 1 INDICATOR

*

4.85

4.70 SQ

4.55

1.00

0.85

0.80

12° MAX

SEATING PLANE

0.45

0.40

0.35

0.80 MAX

0.65 TYP

0.50 BSC

*

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD EXCEPT FOR EXPOSED PAD DIMENSION

0.05 MAX

0.02 NOM

0.20 REF

33

32

7.50 REF

16

17

Figure 61. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 × 9 mm Body, Very Thin Quad (CP-64-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9216BCPZ-65 AD9216BCPZRL7-651 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP-VQ) CP-64-1 AD9216BCPZ-801 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP-VQ) CP-64-1 AD9216BCPZRL7-801 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP-VQ) CP-64-1 AD9216BCPZ-1051 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP-VQ) CP-64-1 AD9216BCPZRL7-1051 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP-VQ) CP-64-1 AD9216-80PCB AD9216-105PCB Evaluation Board with AD9216BCPZ-105

1

Z = Pb-free part.

2

Supports AD9216-65 and AD9216-80 Evaluation.

1

2

−40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP-VQ) CP-64-1

Evaluation Board with AD9216BCPZ-80

Rev. A | Page 38 of 40

AD9216

NOTES

Rev. A | Page 39 of 40

AD9216

NOTES

D04775–0–6/05(A)

Rev. A | Page 40 of 40

Analog Devices AD9216 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

LOGIC SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING DIAGRAM

ABSOLUTE MAXIMUM RATINGS

EXPLANATION OF TEST LEVELS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS

EQUIVALENT CIRCUITS

THEORY OF OPERATION

ANALOG INPUT

Differential Input Configurations

Single-Ended Input Configuration

CLOCK INPUT AND CONSIDERATIONS

POWER DISSIPATION AND STANDBY MODE

DIGITAL OUTPUTS

OUTPUT CODING

TIMING

DATA FORMAT

VOLTAGE REFERENCE

Internal Reference Connection

External Reference Operation

Shared Reference Mode

DUAL ADC LFCSP PCB

POWER CONNECTOR

ANALOG INPUTS

OPTIONAL OPERATIONAL AMPLIFIER

CLOCK

VOLTAGE REFERENCE

DATA OUTPUTS

LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM)

LFCSP PCB SCHEMATICS

LFCSP PCB LAYERS

THERMAL CONSIDERATIONS

OUTLINE DIMENSIONS

ORDERING GUIDE