10-Bit, 65/80/105 MSPS,
FEATURES
Single 3 V supply operation (2.7 V to 3.3 V)
SNR = 58 dBc (to Nyquist)
SFDR = 77 dBc (to Nyquist)
Low power ADC core: 96 mW at 65 MSPS, 104 mW
@ 80 MSPS, 120 mW at 105 MSPS
Differential input with 300 MHz bandwidth
On-chip reference and sample-and-hold amplifier
DNL = ±0.25 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
VIN+
VIN–
REFT
REFB
VREF
SENSE
3 V A/D Converter
FUNCTIONAL BLOCK DIAGRAM
DRVDD
10
MODE
SELECT
REF
SELECT
AVDD
SHA
AD9215
AGND
PIPELINE
ADC CORE
CORRECTION LOGIC
OUTPUT BUFFERS
CLOCK
DUTY CYCLE
STABLIZER
0.5V
CLK PDWN MODE
Figure 1.
AD9215
OR
D9 (MSB)
D0
DGND
02874-A-001
PRODUCT DESCRIPTION
The AD9215 is a family of monolithic, single 3 V supply, 10-bit,
65/80/105 MSPS analog-to-digital converters (ADC). This family
features a high performance sample-and-hold amplifier (SHA)
and voltage reference. The AD9215 uses a multistage differential
pipelined architecture with output error correction logic to provide 10-bit accuracy at 105 MSPS data rates and to guarantee no
missing codes over the full operating temperature range.
The wide bandwidth, truly differential sample-and-hold amplifier (SHA) allows for a variety of user-selectable input ranges
and offsets including single-ended applications. It is suitable for
multiplexed systems that switch full-scale voltage levels in
successive channels and for sampling single-channel inputs at
frequencies well beyond the Nyquist rate. Combined with
power and cost savings over previously available ADCs, the
AD9215 is suitable for applications in communications, imaging, and medical ultrasound.
A single-ended clock input is used to control all internal conversion
cycles. A duty cycle stabilizer compensates for wide variations in the
clock duty cycle while maintaining excellent performance. The digital
output data is presented in straight binary or twos complement formats. An out-of-range signal indicates an overflow condition, which
can be used with the MSB to determine low or high overflow.
Fabricated on an advanced CMOS process, the AD9215 is available in both a 28-lead surface-mount plastic package and a
32-lead chip scale package and is specified over the industrial
temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. The AD9215 operates from a single 3 V power supply and
features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families.
2. Operating at 105 MSPS, the AD9215 core ADC consumes
a low 120 mW; at 80 MSPS, the power dissipation is 104
mW; and at 65 MSPS, the power dissipation is 96 mW.
3. The patented SHA input maintains excellent performance
for input frequencies up to 200 MHz and can be configured for single-ended or differential operation.
4. The AD9215 is part of several pin compatible 10-, 12-, and
14-bit low power ADCs. This allows a simplified upgrade
from 10 bits to 12 bits for systems up to 80 MSPS.
5. The clock duty cycle stabilizer maintains converter per-
formance over a wide range of clock pulse widths.
6. The out of range (OR) output bit indicates when the signal
is beyond the selected input range.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
AD9215
TABLE OF CONTENTS
Specifications..................................................................................... 3
REVISION HISTORY
Absolute Maximum Ratings............................................................ 6
Explanation of Test Levels........................................................... 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Equivalent Circuits....................................................................... 8
Definitions of Specifications ....................................................... 8
Typical Performance Characteristics ........................................... 10
Applying the AD9215 Theory of Operation............................... 14
Clock Input and Considerations ..............................................15
Evaluation Board ........................................................................ 18
Outline Dimensions ....................................................................... 33
Ordering Guide........................................................................... 34
2/04—Data Sheet Changed from a REV. 0 to a REV. A
Renumbered Figures and Tables ..............................UNIVERSAL
Changes to Product Title................................................................ 1
Changes to Features ........................................................................ 1
Changes to Product Description................................................... 1
Changes to Product Highlights .....................................................1
Changes to Specifications............................................................... 2
Changes to Figure 2......................................................................... 4
Changes to Figures 9 to 11 ........................................................... 10
Added Figure 14 ............................................................................10
Added Figures 16 and 18.............................................................. 11
Changes to Figures 21 to 24 and 25 to 26................................... 12
Deleted Figure 25........................................................................... 12
Changes to Figures 28 and 29...................................................... 13
Changes to Figure 31.....................................................................14
Changes t0 Figure 35..................................................................... 16
Changes to Figures 50 through 58...............................................26
Added Table 11 .............................................................................. 31
Updated Outline Dimensions...................................................... 32
Changes to Ordering Guide......................................................... 33
5/03—Revision 0: Initial Version
Rev. A | Page 2 of 36
AD9215
SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, unless otherwise
noted.
Table 1. DC Specifications
AD9215BRU-65/
AD9215BCP-65
Parameter
Temp
Test
Level Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full VI 10 10 10 Bits
ACCURACY
No Missing Codes Full VI Guaranteed Guaranteed Guaranteed
Offset Error1 Full VI ±0.3 ±2.0 ±0.3 ±2.0 ±0.3 ±2.0 % FSR
Gain Error1 Full VI 0 +1.5 +4.0 +1.5 +4.0 +1.5 +4.0 % FSR
Differential Nonlinearity (DNL)2 Full VI −1.0 ±0.5 +1.0 −1.0 ±0.5 +1.0 −1.0 ±0.6 +1.2 LSB
Integral Nonlinearity (INL)2 Full VI ±0.5 ±1.2 ±0.5 ±1.2 ±0.65 ±1.2 LSB
TEMPERATURE DRIFT
Offset Error1 Full V +15 +15 +15 ppm/°C
Gain Error
1
Full V +30 +30 +30 ppm/°C
Reference Voltage (1 V Mode) Full V ±230 ±230 ±230 ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode) Full VI ±2 ±35 ±2 ±35 ±2 ±35 mV
Load Regulation @ 1.0 mA Full V 0.2 0.2 0.2 mV
Output Voltage Error (0.5 V Mode) Full V ± 1 ±1 ±1 mV
Load Regulation @ 0.5 mA Full V 0.2 0.2 0.2 mV
INPUT REFERRED NOISE
VREF = 0.5 V 25°C V 0.8 0.8 0.8 LSB rms
VREF = 1.0 V 25°C V 0.4 0.4 0.4 LSB rms
ANALOG INPUT
Input Span, VREF = 0.5 V Full IV 1 1 1 V p-p
Input Span, VREF = 1.0 V Full IV 2 2 2 V p-p
Input Capacitance3 Full V 2 2 2 pF
REFERENCE INPUT RESISTANCE Full V 7 7 7 kΩ
POWER SUPPLIES
Supply Voltage
AVDD Full IV 2.7 3.0 3.3 2.7 3.0 3.3 2.7 3.0 3.3 V
DRVDD Full IV 2.25 2.5 3.6 2.25 2.5 3.6 2.25 2.5 3.6 V
Supply Current
2
I
Full VI 32 35 34.5 39 40 44 mA
AVDD
2
I
25°C V 7.0 8.6 11.3 mA
DRVDD
PSRR Full V ± 0.1 ± 0.1 ± 0.1 % FSR
POWER CONSUMPTION
Sine Wave Input2
2
I
Full VI 96 104 120 mW
AVDD
2
I
25°C V 18 20 25 mW
DRVDD
Standby Power4 25°C V 1.0 1.0 1.0 mW
AD9215BRU-80/
AD9215BCP-80
AD9215BRU-105/
AD9215BCP-105
1
With a 1.0 V internal reference.
2
Measured at fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to for the equivalent analog input structure. Figure 5
4
Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).
Rev. A | Page 3 of 36
AD9215
AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference,
AIN = −0.5 dBFS, MODE = AVDD/3 (duty cycle stabilizer [DCS] enabled), unless otherwise noted.
Table 2. AC Specifications
AD9215BRU-65/
AD9215BCP-65
Parameter
Temp
Test
Level
Min Typ Max Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz Full VI 56.0 58.5 56.0 58.5 57.5 dB
25°C I 57.0 59.0 57.0 59.0 56.6 58.5 dB
fIN = Nyquist
1
Full VI 56.0 58.0 56.0 58.0 57.5 dB
25°C I 56.5 58.5 56.5 58.5 56.4 58.0 dB
fIN = 70 MHz 25°C V 58.0 57.8 dB
fIN = 100 MHz 25°C V 57.5 57.7 dB
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.4 MHz Full VI 55.8 58.5 55.7 58.5 57.6 dB
25°C I 56.5 59.0 56.8 58.5 56.5 58.2 dB
fIN = Nyquist1 Full VI 55.8 58.0 55.5 58.0 57.3 dB
25°C I 56.3 58.5 56.3 58.5 56.1 57.8 dB
fIN = 70 MHz 25°C V 56.0 57.7 dB
fIN = 100 MHz 25°C V 55.5 57.4 dB
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz Full VI 9.1 9.5 9.0 9.5 9.3 Bits
25°C I 9.2 9.6 9.3 9.5 9.2 9.5 Bits
fIN = Nyquist1 Full VI 9.1 9.4 9.0 9.4 9.4 Bits
25°C I 9.1 9.5 9.0 9.5 9.1 9.4 Bits
fIN = 70 MHz 25°C V 9.1 9.4 Bits
fIN = 100 MHz 25°C V 9.0 9.3 Bits
WORST HARMONIC (Second or Third)
fIN = 2.4 MHz Full VI −78 −64 −78 −64 −78 dBc
25°C I −80 −65 −80 −65 −84 −70 dBc
fIN = Nyquist1 Full VI −77 −64 −76 −63 −74 dBc
25°C I −78 −65 −78 −65 −75 −61 dBc
fIN = 70 MHz 25°C V −70 −75 dBc
fIN = 100 MHz 25°C V −70 −74 dBc
WORST OTHER (Excluding Second or Third)
fIN = 2.4 MHz Full VI −77 −67 −77 −66 −73 dBc
25°C I −78 −68 −77 −68 −75 −66 dBc
fIN = Nyquist1 Full VI −77 −67 −77 −66 −71 dBc
25°C I −78 −68 −77 −68 −75 −63 dBc
fIN = 70 MHz 25°C V −80 -75 dBc
fIN = 100 MHz 25°C V −80 −75 dBc
TWO-TONE SFDR (AIN = –7 dBFS)
f
= 70.3 MHz, f
IN1
f
= 100.3 MHz, f
IN1
= 71.3 MHz 25°C V 75 75 dBc
IN2
= 101.3 MHz 25°C V 74 74 dBc
IN2
ANALOG BANDWIDTH 25°C V 300 300 300 MHz
AD9215BRU-80/
AD9215BCP-80
AD9215BRU-105/
AD9215BCP-105
1
Tested at fIN = 35 MHz for AD9215-65; fIN = 39 MHz for AD9215-80; and fIN = 50 MHz for AD9215-105.
Rev. A | Page 4 of 36
AD9215
Table 3. Digital Specifications
AD9215BRU-65/
AD9215BCP-65
Parameter
Temp
Test
Level Min Typ Max Min Typ Max Min Typ Max Unit
LOGIC INPUTS (CLK, PDWN)
High Level Input Voltage Full IV 2.0 2.0 2.0 V
Low Level Input Voltage Full IV 0.8 0.8 0.8 V
High Level Input Current Full IV −650 +10 −650 +10 −650 +10 µA
Low Level Input Current Full IV −70 +10 −70 +10 −70 +10 µA
Input Capacitance Full V 2 2 2 pF
LOGIC OUTPUTS1
DRVDD = 2.5 V
High Level Output Voltage Full IV 2.45 2.45 2.45 V
Low Level Output Voltage Full IV 0.05 0.05 0.05 V
1
Output voltage levels measured with a 5 pF load on each output.
Table 4. Switching Specifications
AD9215BRU-65/
AD9215BCP-65
Parameter
Temp
Test
Level Min Typ Max Min Typ Max Min Typ Max
CLOCK INPUT PARAMETERS
Maximum Conversion Rate Full VI 65 80 105 MSPS
Minimum Conversion Rate Full V 5 5 5 MSPS
CLOCK Period Full V 15.4 12.5 9.5 ns
DATA OUTPUT PARAMETERS
Output Delay1 (tOD) Full VI 2.5 4.8 6.5 2.5 4.8 6.5 2.5 4.8 6.5 ns
Pipeline Delay (Latency) Full V 5 5 5 Cycles
Aperture Delay 25°C V 2.4 2.4 2.4 ns
Aperture Uncertainty (Jitter) 25°C V 0.5 0.5 0.5 ps rms
Wake-Up Time2 25°C V 7 7 7 ms
OUT-OF-RANGE RECOVERY TIME 25°C V 1 1 1 Cycles
N+1
ANALOG
INPUT
N–1
N
t
N+2
A
N+3
AD9215BRU-80/
AD9215BCP-80
AD9215BRU-80/
AD9215BCP-80
N+4
N+5
N+6
AD9215BRU-105/
AD9215BCP-105
AD9215BRU-105/
N+8
N+7
AD9215BCP-105
Unit
CLK
DATA
OUT
N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 N+2
t
PD
Figure 2. Timing Diagram
02874-A-002
1
Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
2
Wake-up time is dependent on the value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
Rev. A | Page 5 of 36
AD9215
ABSOLUTE MAXIMUM RATINGS
Table 5.
Mnemonic
ELECTRICAL
AVDD AGND −0.3 +3.9 V
DRVDD DRGND −0.3 +3.9 V
AGND DRGND −0.3 +0.3 V
AVDD DRVDD −3.9 +3.9 V
Digital Outputs DRGND −0.3 DRVDD + 0.3 V
CLK, MODE AGND −0.3 AVDD + 0.3 V
VIN+, VIN− AGND −0.3 AVDD + 0.3 V
VREF AGND −0.3 AVDD + 0.3 V
SENSE AGND −0.3 AVDD + 0.3 V
REFB, REFT AGND −0.3 AVDD + 0.3 V
PDWN AGND −0.3 AVDD + 0.3 V
ENVIRONMENTAL
Operating Temperature
Junction Temperature
Lead Temperature (10 sec)
Storage Temperature
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances 28-lead TSSOP: θJA = 67.7°C/W, 32-lead LFCSP:
= 32.7°C/W; heat sink soldered down to ground plane.
θ
JA
With
Respect to Min Max
2
−40 +85 °C
150 °C
300 °C
−65 +150 °C
1
Unit
EXPLANATION OF TEST LEVELS
Tes t Le v el
I 100% production tested.
II 100% production tested at 25°C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range;
100% production tested at temperature extremes for military devices.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 36
AD9215
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
OR
1
MODE
2
SENSE
3
4
VREF
5
REFB
6
REFT
AVDD
AGND
VIN+
VIN–
AGND
AVDD
PDWN
AD9215
TOP VIEW
7
(Not to Scale)
8
9
10
11
12
13
CLK
14
DNC = DO NOT CONNECT
Figure 3. TSSOP (RU-28)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D9 (MSB)
D8
D7
D6
DRVDD
DRGND
D5
D4
D3
D2
D1
D0 (LSB)
DNC
DNC
32 AVDD
31 AGND
30 VIN–
29 VIN+
28 AGND
27 AVDD
26 REFT
25 REFB
DNC 1
CLK 2
DNC 3
PDWN 4
DNC 5
DNC 6
DNC 7
DNC 8
02874-A-003
DNC = DO NOT CONNECT
(Not to Scale)
D1 10
(LSB) D0 9
AD9215
TOP VIEW
D2 11
D3 12
D4 13
D5 14
DRVDD 16
DRGND 15
Figure 4. LFCSP (CP-32)
Table 6. Pin Function Descriptions
TSSOP Pin No. LFCSP Pin No. Mnemonic Description
1 21 OR Out-of-Range Indicator.
2 22 MODE Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection.
3 23 SENSE Reference Mode Selection.
4 24 VREF Voltage Reference Input/Output.
5 25 REFB Differential Reference (Negative).
6 26 REFT Differential Reference (Positive).
7, 12 27, 32 AVDD Analog Power Supply.
8, 11 28, 31 AGND Analog Ground.
9 29 VIN+ Analog Input Pin (+).
10 30 VIN− Analog Input Pin (−).
13 2 CLK Clock Input Pin.
14 4 PDWN Power-Down Function Selection (Active High).
15 to 16 1, 3, 5 to 8 DNC Do not connect, recommend floating this pin.
17 to 22,
25 to 28
9 to 14,
17 to 20
D0 (LSB) to
D9 (MSB)
Data Output Bits.
23 15 DRGND Digital Output Ground.
24 16 DRVDD
Digital Output Driver Supply. Must be decoupled to DRGND with a
minimum 0.1 µF capacitor. Recommended decoupling is 0.1 µF in parallel with 10 µF.
24 VREF
23 SENSE
22 MODE
21 OR
20 D9 (MSB)
19 D8
18 D7
17 D6
02874-A-004
Rev. A | Page 7 of 36
AD9215
EQUIVALENT CIRCUITS
AVDD
MODE
02874-A-005
Figure 5. Equivalent Analog Input Circuit
AVDD
MODE
20kΩ
02874-A-006
Figure 6. Equivalent MODE Input Circuit
DRVDD
D9–D0,
OR
02874-A-007
Figure 7. Equivalent Digital Output Circuit
AVDD
2.6kΩ
CLK
2.6kΩ
02874-A-008
Figure 8. Equivalent Digital Input Circuit
DEFINITIONS OF SPECIFICATIONS
Aperture Delay
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
Aperture Jitter
Aperture jitter is the variation in aperture delay for successive
samples and can be manifested as frequency-dependent noise
on the input to the ADC.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse
should be left in the low state. At a given clock rate, these speci-
fications define an acceptable clock duty cycle.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 10-bit resolution indicate that all 1024
codes, respectively, must be present over all operating ranges.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, it is possible to obtain a
measure of performance expressed as N, the effective number of
bits
N = (SINAD – 1.76)/6.02
Thus, the effective number of bits for a device for sine wave
inputs at a given input frequency can be calculated directly
from its measured SINAD.
Gain Error
The first code transition should occur at an analog value 1/2
LSB above negative full scale. The last transition should occur at
an analog value 1 1/2 LSB below the positive full scale. Gain
error is the deviation of the actual difference between the first
and last code transitions and the ideal difference between the
first and last code transitions.
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as negative full scale occurs 1/2 LSB before the
first code transition. Positive full scale is defined as a level 1 1/2
LSB beyond the last code transition. The deviation is measured
from the middle of each particular code to the true straight line.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Offset Error
The major carry transition should occur for an analog value 1/2
LSB below VIN+ = VIN−. Zero error is defined as the deviation
of the actual transition from that point.
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.
Output Propagation Delay
The delay between the clock logic threshold and the time when
Rev. A | Page 8 of 36
AD9215
all bits are within valid logic levels.
Power Supply Rejection
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
Signal-to-Noise and Distortion (SINAD) Ratio
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for SINAD is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
Temperature Drift
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at
or T
T
MIN
MAX
.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. It may be reported in dBc
(i.e., degrades as signal levels are lowered) or in dBFS (always
related back to converter full scale).
Rev. A | Page 9 of 36
AD9215
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.0 V, DRVDD = 2.5 V with DCS enabled, TA = 25°C, 2 V differential input, AIN = −0.5 dBFS, VREF = 1.0 V, unless
otherwise noted.
80
75
70
2V p-p SFDR (dBc)
1V p-p SFDR (dBc)
AIN = –0.5dBFS
–20
–40
0
AIN = –0.5dBFS
SNR = 58.0
ENOB = 9.4 BITS
SFDR = 75.5dB
–60
–80
AMPLITUDE (dBFS)
–100
–120
0 52.5045.9439.3832.8126.2519.6913.136.56
FREQUENCY (MHz)
Figure 9. Single-Tone 32k FFT with f
0
AIN = –0.5dBFS
SNR = 57.8
ENOB = 9.4 BITS
SFDR = 75.0dB
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–100
–120
–20
–40
–60
–80
0 52.5045.9439.3832.8126.2519.6913.136.56
Figure 10. Single-Tone 32k FFT with f
0
AIN = –0.5dBFS
–20
–40
SNR = 57.7
ENOB = 9.3 BITS
SFDR = 75dB
= 10.3 MHZ, f
IN
= 70.3 MHz, f
IN
SAMPLE
SAMPLE
= 105 MSPS
= 105 MSPS
65
dB
60
55
02874-A-062
50
5 1525354555657585
Figure 12. AD9215-80 SNR/SFDR vs. f
80
75
70
65
dB
60
55
02874-A-063
50
5 152535455565
Figure 13. AD9215-65 SNR/SFDR vs. f
85
80
75
2V p-p SNR (dB)
1V p-p SFDR (dBc)
2V p-p SNR (dB)
1V p-p SNR (dB)
ENCODE (MSPS)
2V p-p SFDR (dBc)
ENCODE (MSPS)
2V p-p SFDR
1V p-p SNR (dB)
, fIN = 10.3 MHz
SAMPLE
AIN = –0.5dBFS
, fIN = 10.3 MHz
SAMPLE
02874-A-012
02874-A-013
–60
–80
AMPLITUDE (dBFS)
–100
–120
0 52.5045.9439.3832.8126.2519.6913.136.56
FREQUENCY (MHz)
Figure 11. Single-Tone 32k FFT with f
= 100.3 MHz, f
IN
= 105 MSPS
SAMPLE
02874-A-065
Rev. A | Page 10 of 36
70
dB
65
60
55
0 10080604020
f
SAMPLE
Figure 14. AD9215-105 SNR/SFDR vs. f
2V p-p SNR
(MSPS)
, fIN = 10.3 MHz
SAMPLE
02874-A-066
AD9215
80
80
70
60
80dB REFERENCE LINE
50
40
dB
30
20
10
0
–50 –40–45 –35 –25–30 –10–15–20 –5 0
2V p-p SFDR (dBc)
ANALOG INPUT LEVEL
1V p-p SFDR (dBc)
2V p-p SNR (dB)
1V p-p SNR (dB)
Figure 15. AD9215-80 SNR/SFDR vs.
Analog Input Drive Level, f
80
70
60
50
40
dB
30
20
10
0
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
–70dBFS
REFERENCE LINE
2V p-p
SNR
ANALOG INPUT LEVEL (–dBFS)
= 80 MSPS, fIN = 39.1 MHz
SAMPLE
2 SFDR dBc
1V p-p SFDR (dBc)
1V p-p SNR
Figure 16. AD9215-105 SNR/SFDR vs.
Analog Input Drive Level, f
80
70
60
80dB REFERENCE LINE
50
= 105 MSPS, fIN = 50.3 MHz
SAMPLE
1V p-p SFDR (dBc)
2V p-p SNR (dB)
75
SFDR
70
65
dB
60
55
02874-A-014
50
0 50 100 150 200 250 300
SNR
FREQUENCY (MHz)
02874-A-072
Figure 18. AD9215-105 SNR/SFDR vs.
, AIN = −0.5 dBFS, f
f
IN
85
80
75
70
dB
65
60
55
02874-A-067
50
2V p-p SFDR (dBc)
2V p-p SNR (dB)
0 10050 150 250200 300
f
IN
SAMPLE
(MHz)
= 105 MSPS
02874-A-016
Figure 19. AD9215-80 SNR/SFDR vs.
fIN, AIN = −0.5 dBFS, f
80
75
2V p-p SFDR (dBc)
70
SAMPLE
= 80 MSPS
40
dB
30
20
10
0
–50 –40–45 –35 –25–30 –10–15–20 –5 0
2V p-p SFDR (dBc)
ANALOG INPUT LEVEL
1V p-p SNR (dB)
Figure 17. AD9215-65 SNR/SFDR vs.
Analog Input Drive Level, f
= 65 MSPS, fIN = 30.3 MHz
SAMPLE
02874-A-015
Rev. A | Page 11 of 36
65
dB
60
55
50
0 10050 150 250200 300
2V p-p SNR (dB)
ANALOG INPUT (MHz)
Figure 20. AD9215-65 SNR/SFDR vs.
, AIN = −0.5 dBFS, f
f
IN
SAMPLE
= 65 MSPS
02874-A-017
AD9215
0
–20
–40
, A
= –7dBFS
A
IN1
IN2
SFDR = 74dBc
80
70
60
50
SFDR
–60
dB
–80
–100
–120
0 52.50039.37526.25013.125
Figure 21. Two-Tone 32k FFT with f
and f
0
–20
–40
–60
dB
–80
–100
–120
0 52.50039.37526.25013.125
Figure 22. Two-Tone 32k FFT with f
and f
80
70
60
50
40
dB
30
20
10
0
–65 –55 –45 –35 –25 –15 –5
Figure 23. AD9215-105 Two-Tone SFDR vs. A
f
= 70.1 MHz, and f
IN1
FREQUENCY (MHz)
= 71.1 MHz, f
IN2
, A
= –7dBFS
A
IN1
IN2
SFDR = 74dBc
FREQUENCY (MHz)
= 101.3 MHz, f
IN2
SFDR
AIN1, AIN2 (dBFS)
IN2
= 70.1 MHz,
IN1
= 105 MSPS
SAMPLE
= 100.3 MHz,
IN1
= 105 MSPS
SAMPLE
80dBFS REFERENCE LINE
= 71.1 MHz, f
= 105 MSPS
SAMPLE
IN
40
dB
30
20
10
02874-A-060
0
–60 –5–10–15–20–25–30–35–40–45–50–55
Figure 24. AD9215-80 Two-Tone SFDR vs. A
80
75
70
65
SNR DCS ON
60
55
dB
50
45
40
35
02874-A-061
30
20 30 40 50 60 70 80
80dBFS REFERENCE LINE
AIN (dBFS)
101.3 MHz, f
CLOCK DUTY CYCLE HIGH (%)
SAMPLE
IN
= 105 MSPS
SNR DCS OFF
, f
= 100.3 MHz, and f
IN1
SFDR DCS ON
SFDR DCS OFF
02874-A-073
=
IN2
02874-A-069
Figure 25. SINAD, SFDR vs.
Clock Duty Cycle, f
80
2V p-p SFDR (dBc)
75
70
65
dBc
60
55
02874-A-068
50
–40–200 20406080
,
Figure 26. SINAD, SFDR vs. Temperature,
f
SAMPLE
= 105 MSPS, fIN = 50.3 MH
SAMPLE
1V p-p SFDR (dBc)
2V p-p SINAD
1V p-p SINAD
TEMPERATURE (°C)
= 105 MSPS, fIN = 50 MHz
02874-A-070
Rev. A | Page 12 of 36
AD9215
40
0.6
30
20
10
0
–10
GAIN ERROR (ppm/°C)
–20
–30
–40
–40 –20 0 20 6040 80
TEMPERATURE (°C)
Figure 27. Gain vs. Temperature External 1 V Reference
0.5
0.4
0.3
0.2
0.1
0
DNL (LSB)
–0.1
–0.2
–0.3
–0.4
–0.5
CODE
Figure 28. AD9215-105 Typical DNL, f
= 105 MSPS, fIN = 2.3 MHz
SAMPLE
0.4
0.2
0
INL (LSB)
–0.2
–0.4
02874-A-025
–0.6
CODE
Figure 29. AD9215-105 Typical INL, f
= 105 MSPS, fIN = 2.3 MHz
SAMPLE
02874-A-074
10248967686405123842561280
02874-A-064
10248967686405123842561280
Rev. A | Page 13 of 36
AD9215
APPLYING THE AD9215 THEORY OF OPERATION
The AD9215 architecture consists of a front-end SHA followed
by a pipelined switched capacitor ADC. Each stage provides
sufficient overlap to correct for flash errors in the preceding
stages. The quantized outputs from each stage are combined
into a final 10-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new
input sample, while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.
The input stage contains a differential SHA that can be configured as ac-coupled or dc-coupled in differential or single-ended
modes. Each stage of the pipeline, excluding the last, consists of
a low resolution flash ADC connected to a switched capacitor
DAC and interstage residue amplifier (MDAC). The residue
amplifier magnifies the difference between the reconstructed
DAC output and the flash input for the next stage in the pipeline. Redundancy is used in each one of the stages to facilitate
digital correction of flash errors.
The output-staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the
output buffers go into a high impedance state.
Analog Input and Reference Overview
The analog input to the AD9215 is a differential switched
capacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA input
can support a wide common-mode range and maintain excellent performance, as shown in Figure 31. An input commonmode voltage of midsupply minimizes signal-dependent errors
and provides optimum performance.
H
VIN+
VIN–
T
C
PAR
T
C
PAR
Figure 30. Switched-Capacitor SHA Input
0.5pF
0.5pF
The clock signal alternatively switches the SHA between sample
mode and hold mode (see Figure 30). When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
T
T
02874-A-028
H
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC’s input; therefore, the precise values are dependent upon the application. In IF undersampling applications, any shunt capacitors
should be removed. In combination with the driving source
impedance, they would limit the input bandwidth.
The analog inputs of the AD9215 are not internally dc biased.
In ac-coupled applications, the user must provide this bias externally. V
= AV D D /2 is recommended for optimum per-
CM
formance, but the device functions over a wider range with reasonable performance (see Figure 31).
85
80
75
70
65
dB
60
55
50
45
40
0.25 0.75 1.25 1.75 2.25 2.75
ANALOG INPUT COMMON-MODE VOLTAGE (V)
Figure 31. AD9215-105 SNR, SFDR vs. Common-Mode Voltage
2V p-p SFDR
2V p-p SNR
02874-A-071
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as
REFT = 1/2 (AV D D + VREF)
REFB = 1/2 (AV D D − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the VREF
voltage.
The internal voltage reference can be pin-strapped to fixed values of 0.5 V or 1.0 V or adjusted within the same range as discussed in the Internal Reference Connection section. Maximum
Rev. A | Page 14 of 36
AD9215
2
SNR performance is achieved with the AD9215 set to the largest
input span of 2 V p-p. The relative SNR degradation is 3 dB
when changing from 2 V p-p mode to 1 V p-p mode.
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels
are defined as
VCM
VCM
= VREF/2
MIN
= (AV D D + VREF)/2
MAX
The minimum common-mode input level allows the AD9215 to
accommodate ground-referenced inputs.
Although optimum performance is achieved with a differential
input, a single-ended source may be driven into VIN+ or VIN−.
In this configuration, one input accepts the signal, while the
opposite input should be set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal may be
applied to VIN+ while a 1 V reference is applied to VIN−. The
AD9215 then accepts a signal varying between 2 V and 0 V. In
the single-ended configuration, distortion performance may
degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies.
Differential Input Configurations
As previously detailed, optimum performance is achieved while
driving the AD9215 in a differential input configuration. For
baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AV D D /2, and the driver can be configured in a Sallen Key filter
topology to provide band limiting of the input signal.
1kΩ
0.1µF
1V p-p
1kΩ
49.9Ω
523Ω
499Ω
V
CM
499Ω
AD8138
499Ω
R
C
R
C
AVDD
VIN+
AD9215
VIN–
AGND
02874-A-030
Figure 32. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9215. This is especially true in IF
undersampling applications where frequencies in the 70 MHz to
200 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration. The value of the shunt capacitor is dependant on the input
frequency and source impedance and should be reduced or removed. An example of this is shown in Figure 33.
R
Vp-p
1kΩ
1kΩ
49.9Ω
AVDD
0.1µF
C
R
C
Figure 33. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is a degradation in SFDR and distortion performance due to the large
input common-mode swing. However, if the source impedances
on each input are kept matched, there should be little effect on
SNR performance. Figure 34 details a typical single-ended input
configuration.
10µF
1kΩ
R
0.1µF
2V p-p
1kΩ
1kΩ
AVDD
10µF 0.1µF
1kΩ
C49.9Ω
R
C
Figure 34. Single-Ended Input Configuration
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required
on the clock duty cycle to maintain dynamic performance characteristics. The AD9215 contains a clock duty cycle stabilizer
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9215. As shown in Figure 25, noise and distortion performance are nearly flat over a 50% range of duty cycle. For best
ac performance, enabling the duty cycle stabilizer is recommended for all applications.
The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 100 clock cycles to allow
the DLL to acquire and lock to the new rate.
AVDD
VIN+
AD9215
VIN–
AGND
AVDD
VIN+
AD9215
VIN–
AGND
02874-A-031
02874-A-032
Rev. A | Page 15 of 36
AD9215
Table 7. Reference Configuration Summary
Selected Mode
Externally Supplied Reference AVDD N/A N/A 2 × External Reference
Internal 0.5 V Reference VREF Voltage Follower (G = 1) 0.5 1.0
Programmed Variable
Reference
Internally Programmed 1 V
Reference
Table 8. Digital Output Coding
Code VIN+ − VIN− Input Span =
2 V p-p (V)
1023 1.000 0.500 11 1111 1111 01 1111 1111
512 0 0 10 0000 0000 00 0000 0000
511 −0.00195 −0.000978 01 1111 1111 11 1111 1111
0 −1.00 −0.5000 00 0000 0000 10 0000 0000
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (f
) due only to aperture jitter (tA) can be
INPUT
calculated with the following equation
SNR Degradation = 20 × log
In the equation, the rms aperture jitter, t
sum square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9215. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.
Power Dissipation and Standby Mode
As shown in Figure 35, the power dissipated by the AD9215 is
proportional to its sample rate. The digital power dissipation
does not vary substantially between the three speed grades
because it is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current can be calculated as
External SENSE
Connection
Internal Op Amp
Configuration
Resulting VREF
(V)
Resulting Differential Span
(V p-p)
External Divider Noninverting (1 < G < 2) 0.5 × (1 + R2/R1) 2 × VREF
AGND to 0.2 V Internal Divider 1.0 2.0
VIN+ − VIN− Input Span =
1 V p-p (V)
Digital Output Offset Binary
(D9••••••D0)
Digital Output Twos
Complement (D9••••••D0)
ber of output bits switching, which are determined by the encode
rate and the characteristics of the analog input signal.
Digital power consumption can be minimized by reducing the
capacitive load presented to the output drivers. The data in
[2 × π × f
10
A
INPUT
, represents the root-
× tA]
Figure 35 was taken with a 5 pF load on each output driver.
40
(mA)
AVDD
I
35
30
25
20
15
AD9215-65/80 I
I
DRVDD
Figure 35. Supply Current vs. f
AD9215-105 I
AVDD
f
SAMPLE
AVDD
(MSPS)
for fIN = 10.3 MHz
SAMPLE
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increases linearly with the clock
frequency.
1055 152535455565758595
15
13
11
9
7
DRVDD
I
5
3
1
02874-A-075
–1
I
DRVDD
= V
DRVDD
× C
LOAD
× f
CLOCK
× N
where N is the number of output bits, 10 in the case of the
AD9215. This maximum current is for the condition of every
output bit switching on every clock cycle, which can only occur
for a full-scale square wave at the Nyquist frequency, f
CLOCK
/2. In
practice, the DRVDD current is established by the average num-
Rev. A | Page 16 of 36
By asserting the PDWN pin high, the AD9215 is placed in
standby mode. In this state, the ADC typically dissipates 1 mW
if the CLK and analog inputs are static. During standby, the
output drivers are placed in a high impedance state. Reasserting
the PDWN pin low returns the AD9215 into its normal operational mode.
AD9215
In standby mode, low power dissipation is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode and then must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode, and shorter standby
cycles result in proportionally shorter wake-up times. With the
recommended 0.1 µF and 10 µF decoupling capacitors on REFT
and REFB, it takes approximately one second to fully discharge
the reference buffer decoupling capacitors and 7 ms to restore
full operation.
Digital Outputs
The AD9215 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
Timing
The AD9215 provides latched data outputs with a pipeline delay
of five clock cycles. Data outputs are available one propagation
delay (t
) after the rising edge of the clock signal. Refer to
OD
Figure 2 for a detailed timing diagram.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9215;
these transients can detract from the converter’s dynamic performance.
The lowest typical conversion rate of the AD9215 is 5 MSPS. At
clock rates below 5 MSPS, dynamic performance may degrade.
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9215. The input range can be adjusted by varying the reference voltage applied to the AD9215, using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly.
Internal Reference Connection
A comparator within the AD9215 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in Table 1 If SENSE is grounded,
the reference amplifier switch is connected to the internal resistor divider (see Figure 36), setting VREF to 1 V. Connecting the
SENSE pin to the VREF pin switches the amplifier output to the
SENSE pin, configuring the internal op amp circuit as a voltage
follower and providing a 0.5 V reference output. If an external
resistor divider is connected as shown in Figure 37, the switch is
again set to the SENSE pin. This puts the reference amplifier in a
noninverting mode with the VREF output defined as
VREF 15.0
VIN+
VIN–
VREF
10µF+0.1µF
SENSE
Figure 36. Internal Reference Configuration
In all reference configurations, REFT and REFB drive the ADC
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
10µF+0.1µF
R2
SENSE
R1
Figure 37. Programmable Reference Configuration
If the internal reference of the AD9215 is used to drive multiple
converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 38 depicts how the internal reference voltage is affected by loading.
VIN+
VIN–
VREF
R2
⎞
⎛
+×=
⎟
⎜
R1
⎠
⎝
REFT
0.1µF
0.1µF 10µF
REFB
0.1µF
02874-A-034
REFT
0.1µF
0.1µF 10µF
REFB
0.1µF
0.5V
02874-A-035
7kΩ
7kΩ
SELECT
LOGIC
AD9215
SELECT
LOGIC
AD9215
ADC
CORE
CORE
0.5V
ADC
Rev. A | Page 17 of 36
AD9215
0.05
0
–0.05
–0.10
VREF ERROR (%)
–0.15
–0.20
–0.25
0 0.5 1.0 1.5 2.0 2.5 3.0
Figure 38. VREF Accuracy vs. Load
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may be necessary to reduce gain
matching errors to an acceptable level. A high precision external
reference may also be selected to provide lower gain and offset
temperature drift. Figure 39 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes.
0.6
0.5
0.4
0.3
VREF ERROR (%)
0.2
0.1
0
–40 –20 0 20 40 60 80
Figure 39. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
VREF = 0.5V
VREF = 1.0V
I
LOAD
VREF = 0.5V
TEMPERATURE (°C)
(mA)
VREF = 1.0V
02874-A-036
02874-A-037
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1 V.
Operational Mode Selection
As discussed earlier, the AD9215 can output data in either offset
binary or twos complement format. There is also a provision for
enabling or disabling the clock duty cycle stabilizer (DCS). The
MODE pin is a multilevel input that controls the data format
and DCS state. For best ac performance, enabling the duty cycle
stabilizer is recommended for all applications. The input
threshold values and corresponding mode selections are outlined in Table 9.
As detailed in Table 9, the data format can be selected for either
offset binary or twos complement.
Table 9. Mode Selection
MODE Voltage Data Format Duty Cycle Stabilizer
AVDD Twos Complement Disabled
2/3 AVDD Twos Complement Enabled
1/3 AVDD Offset Binary Enabled
AGND (Default) Offset Binary Disabled
The MODE pin is internally pulled down to AGND by a 20 kΩ
resistor.
EVALUATION BOARD
The AD9215 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially
through an AD8351 driver, a transformer, or single-ended.
Separate power pins are provided to isolate the DUT from the
support circuitry. Each input configuration can be selected by
proper connection of various jumpers (refer to the schematics).
Figure 40 shows the typical bench characterization setup used
to evaluate the ac performance of the AD9215. It is critical that
signal sources with very low phase noise (<1 ps rms jitter) be
used to realize the ultimate performance of the converter.
Proper filtering of the input signal, to remove harmonics and
lower the integrated noise at the input, is also necessary to
achieve the specified noise performance.
Complete schematics and layout plots follow that demonstrate
the proper routing and grounding techniques that should be
applied at the system level.
REFIN
10MHz
REFOUT
R AND S SMG, 2V p-p
SIGNAL SYNTHESIZER
R AND S SMG, 2V p-p
SIGNAL SYNTHESIZER
2.5V
–+ –+–+–+
AVDD DRVDDGND GND V
AD9215
EVALUATION BOARD
BAND-PASS
FILTER
3.0V
XFMR
INPUT
CLK
Figure 40. Evaluation Board Connections
Rev. A | Page 18 of 36
2.5V 5.0V
VAMP
DL
P12
DATA
CAPTURE
AND
PROCESSING
02874-A-038
AD9215
X
X
X
X
X
1
2
Ω
0
2
2
2
P
R
P4
GND
C11
C29
3
R
1
1
1
O
D
D
D
3
4
5
6
1
1
1
1
4
3
2
1
)
B
S
M
(
17
18
19
20
21
22
23
24
0.1µF
10µF
C7
0.1µF
GND
6
6
E
E
L
L
O
O
H
H
T
T
2
1
M
M
H
H
D
N
G
1
P6
AVDD
EXTREF
1V MAX E1
3
H
1234 56
5
R
C13
AVDD
Ω
k
1
2
2
C
GND
6
6
E
E
L
L
O
O
H
H
T
T
4
M
H
M
P2
5.0V
VAMP
2.5V
VDL
GND
2.5V
DRVDD
GND
3.0V
AVDD
P5
MODE
2
2
P1
F
µ
0
1
GND
GND
0.10µF
P11
E
P8
P9
P7 A B C D
R1
10kΩ
3
P3
Ω
7
k
1
R
P10
R9
C12
T
I
B
E
G
N
A
R
R
E
V
O
C8
0.1µF
GND
4
Ω
6
k
1
R
C9
0.10µF
0.1µF
GND
10kΩ
GND
X
X
X
0
7
9
8
1
D
D
D
D
9
0
1
2
1
1
1
8
6
5
7
D6
D7
D8
D9
OR
MODE
SENSE
VREF
REFB
25262728303132
GND
2
4
Ω
0
R
6
C
X
X
X
X
X
6
4
5
D
D
D
3
4
5
6
1
1
1
1
1
4
3
2
)
B
D
D
D
V
N
R
G
D
4
5
6
1
1
1
5
D
D
D
D
N
V
G
R
D
D
S
L
(
0
1
2
3
1
1
1
1
2
4
3
1
D
D
D
D
U4
AD9215
D
D
T
F
D
V
E
R
A
D
D
V
A
D
N
G
6
Ω
2
k
1
R
6
Ω
3
k
1
R
D
D
V
A
N
I
P
M
A
F
µ
1
.
0
D
+
–
N
N
N
N
G
G
I
I
A
A
V
V
29
–
+
D
D
N
N
I
I
N
N
V
V
G
G
1
2
C
Ω
4
3
3
R
2
1
Ω
0
R
OUT
X
T1
X
X
3
1
0
2
D
D
D
D
9
0
1
2
1
1
1
Ω
0
2
2
1
P
R
8
6
5
7
9
0
D
D
D
V
A
D
D
V
A
D
N
G
T
C
E
L
E
S
F
6
p
2
0
C
1
0
Ω
1
6
3
R
6
1
ADT1–1WT
XFRIN1
0
0
1
1
L
1
J
9
1
C
D
N
G
5
4
E
CT
2
34
5
NC
F
µ
5
1
1
.
0
C
P
M
A
8
DNC
DNC
7
DNC
6
DNC
5
PDWN
4
DNC
3
CLK
2
DNC
1
D
R
N
E
G
T
3
L
I
1
L
R
O
F
p
0
1
2
X
X
R
D
N
G
F
µ
6
1
1
.
0
C
C
E
S
I
R
P
D
N
G
2
F
C
R
O
F
F
5
µ
1
C
.
0
1
Ω
B
1
6
3
R
OUT
X
D
N
G
OPTIONAL XFRT2FT C1–1–13
D
N
G
)
T
L
U
A
F
E
R
D
E
(
:
D
I
E
R
V
C
E
I
P
N
D
E
M
E
R
U
G
E
J
A
F
E
T
E
L
L
R
B
O
V
A
V
1
R
L
L
E
A
A
D
N
L
N
R
O
R
E
S
E
T
T
X
N
I
N
E
I
P
:
:
E
A
B
S
O
O
N
T
T
E
E
E
S
Ω
8
k
1
R
K
L
C
T
C
E
L
E
S
5
Ω
1
3
3
R
3
Ω
0
R
B
N
I
P
M
A
B
T
OUT
OUT
C
X
X
4
2
5
1
3
D
N
I
N
R
G
F
X
F
N
F
E
O
O
:
C
R
S
S
N
E
E
C
R
N
E
E
F
E
R
E
R
F
V
E
5
.
R
0
L
L
A
A
N
N
R
R
E
E
T
T
X
N
E
I
:
:
C
D
O
O
T
T
E
E
D
N
G
P13
P14
D
D
V
A
F
µ
0
8
1
1
.
0
C
R18
C
E
S
I
R
P
F
E
N
F
C
C
P
O
O
D
D
/
/
M
S
S
T
T
U
C
C
N
N
J
E
E
D
D
/
/
E
M
M
Y
Y
L
E
E
R
R
B
L
L
A
A
A
P
P
N
N
R
I
I
M
M
E
B
B
O
O
D
T
T
C
C
L
E
E
S
S
O
S
S
O
O
S
F
F
F
F
W
W
N
I
T
O
T
O
P
:
:
:
:
1
3
2
4
E
D
O
O
O
O
T
T
T
O
T
5
5
5
M
5
D
N
G
5
Ω
2
k
1
R
3
Ω
1
k
1
R
D
D
V
A
R SINGLE ENDED
D
N
G
25Ω
R3, R17, R18
ONLY ONE SHOULD BE
ON BOARD AT A TIME
02874-A-039
Figure 41. LFCSP Evaluation Board Schematic, Analog Inputs and DUT
Rev. A | Page 19 of 36
AD9215
GND
135791113151719212325272931333537
P12
13579
HEADER 40
246
246
GNDDRGND
111315171921232527293133353739
8
101214161820222426283032343638
8
101214161820222426283032343638
MSB
DRY
39
40
40
AMPIN
AMPINB
GND
GND
GND
GND
C24
10µF
C45
0.1µF
R14
25Ω
VAMP
R39
1kΩ
R38
1kΩ
C44
0.1µF
10 VOCM
8 OPHI
9 VPOS
C27
0.1µF
R16
0Ω
7 OPLO
C17
0.1µF
R17
0Ω
GND
6 COMM
DRY
GND
GND
DRVDD
GND
24232221201918171615141312111098765432
CC
GND
GND
GND
2Q6
2D6
D12X
2Q5
2D5
D11X
V
2Q4
2Q3
2Q2
GND
CC
2D4
V
2D3
2D2
GND
D8X
D9X
GND
D10X
DRVDD
2Q7
2OE
2QB
U1
74LVTH162374
2CLK
2DB
2D7
2526272829303132333435363738394041424344454647
DRX
CLKAT/DAC
D13X
MSB
2Q1
2D1
D7X
1Q8
1D8
D6X
1Q7
1D7
D5X
GND
GND
GND
GND
1Q6
1D6
D4X
1Q5
1D5
D3X
DRVDD
CC
V
CC
V
DRVDD
Figure 42. LFCSP Evaluation Board, Digital Path
1Q4
1D4
D2X
1Q3
1D3
D1X
GND
GND
GND
GND
1Q2
1D2
D0X
LSB
1Q1
1D1
GND
1
OUT
1OE
1CLK 1
IN
48
CLKLAT/DAC
VAMP
GND
POWER DOWN
USE R40 OR R41
U3
AD8351
INHI 3
INLO 4
RGP1 2
PWDN 1
R40
10kΩ
GNDVAMP
R41
10kΩ
C28
0.1µF
AMP IN
AMP
R34
1.2kΩ
RPG2 5
R33
25Ω
C35
0.10µF
Ω
R35
25
GND
R19
GND
50Ω
02874-A-040
Rev. A | Page 20 of 36
AD9215
C40
0.001µF
C46
C37
0.1µF
10µF
VDL
DRVDD
C48
C41
C14
C33
C47
C1
C39
C38
C36
C34
C31
C30
C20
10µF
GND
C49
0.001µF
0.001µF
0.1µF
0.1µF
0.001µF
0.001µF
0.1µF
0.1µF
0.1µF
0.001µF
C2
22µF
GND
0.1µF
0.001µF
0.1µF
VAMP
LATCH BYPASSING
GND
DR
Rx
DNP
R37
25Ω
CLKLAT/DAC
SCHEMATIC SHOWS TWO-GATE DELAY SETUP.
FOR ONE DELAY REMOVE R22 AND R37
ATTACH Rx (Rx = 0Ω)
0Ω
R23
GND
ENCX
367
8
11
GND
1Y
2Y
3Y
74VCX86
A
B
2
1
245
R32
A
B
3
2
9
1kΩ
VDL
CLK
ENC
E51
E50
A
1
1
VDL
14
B
3
10
GND
PWR
4Y
A
4
12
R22
0Ω
U5
B
4
13
R20
1kΩ
E52 E53
VDL
GND
R21
1kΩ
VDL
E31 E35
GND
E43 E44
R24
1kΩ
GND
VDL
AVDD
DRVDD AVDD
VDL
C32
C25
C4
0.001µF
10µF
C3
C10
10µF
10µF
22µF
ANALOG BYPASSING DIGITAL BYPASSING
GND
GND
DUT BYPASSING
R27
ENCX
0Ω
ENC
R28
0Ω
CLOCK TIMING ADJUSTMENTS
FOR A BUFFERED ENCODE USE R28
FOR A DIRECT ENCODE USE R27
VDL
R31
1kΩ
C43
0.1µF
ENCODE
J2
R30
R29
1kΩ
GND
50Ω
GND
GND
02874-A-041
Figure 43. LFCSP Evaluation Board Schematic, Clock Input
Rev. A | Page 21 of 36
AD9215
Figure 44. LFCSP Evaluation Board Layout, Primary Side
02874-A-042
Figure 45. LFCSP Evaluation Board Layout, Secondary Side
02874-A-043
Rev. A | Page 22 of 36
AD9215
Figure 46. LFCSP Evaluation Board Layout, Ground Plane
02874-A-044
Figure 47. LFCSP Evaluation Board Layout, Power Plane
02874-A-045
Rev. A | Page 23 of 36
AD9215
Figure 48. LFCSP Evaluation Board Layout, Primary Silkscreen
02874-A-046
Figure 49. LFCSP Evaluation Board Layout, Secondary Silkscreen
02874-A-047
Rev. A | Page 24 of 36
AD9215
Table 10. LFCSP Evaluation Board Bill of Materials (BOM)
Item Qty Omit
18
1
Reference Designator
C1, C5, C7, C8, C9, C11,
C12, C13, C15, C16, C31, C33,
C34, C36, C37, C41, C43, C47
8
C6, C18, C27, C17,
C28, C35, C45, C44
8
C2, C3, C4, C10,
C20, C22, C25, C29
2 C46, C24,
3 8
C14, C30, C32, C38,
C39 C40, C48, C49
1 C19 Chip Capacitor 0603 10 pF 4
2 C21, C23
5 1 C26 Chip Capacitor 0603 10 pF
9
6
E31, E35, E43, E44,
E50, E51, E52, E53
2 E1, E45
7 2 J1, J2 SMA Connector/50 Ω SMA
8 1 L1 Inductor 0603 10 nH
9 1 P2 Terminal Block TB6
10 1 P12
5 R3, R12, R23, R18, RX Chip Resistor 0603 0 Ω 11
6 R37, R22, R42, R16, R17, R27
12 2 R4, R15 Chip Resistor 0603 33 Ω
13 14
R5, R6, R7, R8, R13, R20, R21, R24,
R25, R26, R30, R31, R32, R36
14 2 R10, R11 Chip Resistor 0603 36 Ω
1 R29 Chip Resistor 0603 50 Ω 15
1 R19
16 2 RP1, RR2 Resistor Pack R_742 220 Ω
17 1 T1 ADT1-1WT AWT1-T1 Mini-Circuits
18 1 U1
19 1 U4 AD9215BCP ADC (DUT) CSP-32 Analog Devices, Inc.
20 1 U5 74VCX86M SOIC-14 Fairchild
21 1 PCB AD9XXBCP/PCB PCB Analog Devices, Inc.
22 1 U3 AD8351 Op Amp MSOP-8 Analog Devices, Inc.
23 1 T2 MACOM Transformer ETC1-1-13 1-1 TX MACOM/ETC1-1-13
24 5 R9, R1, R2, R38, R39 Chip Resistor 0603 Select
25 3 R18, R14, R35 Chip Resistor 0603 25 Ω
26 2 R40, R41 Chip Resistor 0603 10 kΩ
27 1 R34 Chip Resistor 1.2 kΩ
28 1 R33 Chip Resistor 110 Ω
1
These items are included in the PCB design but are omitted at assembly.
Device
Package Value
Recommended Vendor/
Part Number
Chip Capacitor 0603 0.1 µF 1
Tantalum Capacitor TAJD 10 µF 2
Chip Capacitor 0603
0.001
µF
Header EHOLE Jumper Blocks
Coilcraft/0603CS10NXGBU
Wieland/25.602.2653.0
z5-530-0625-0
Header Dual 20-Pin RT
HEADER40 Digi-Key S2131-20-ND
Angle
Chip Resistor 0603 1 Ω
Digi-Key
CTS/742C163220JTR
74LVTH162374 CMOS
TSSOP-48
Register
Rev. A | Page 25 of 36
AD9215
DRVDD
MODE SELECT CONFIGURATION
E:2C/DCS OFF
F:2C/DCS ON
G:OB/DCS ON
H:OB/DCS OFF
P2
1324
1324
E29 E28
E26E25
E27
E24
VDL
GND
VCLK
GND
GND
VCLKAVDD
VDL
VAMP
DRVDD
AVDD
5.0V
3.0V
3.0V
2.5V
3.0V
C15
02874-A-048
ORX
D9X
13
14
15
16
RP2 220Ω
2345678
1
(MSB)
OR1
OVERRANGE BIT
GND
0.1µF
D5X
D6X
D7X
D8X
9
10
12
11
25
26
27
28
D6
D7
D8
D9
MODE
OR
SENSE
VREF
2
1
4
DRVDD
23
24
DRVDD
REFB
563
D4X
16
RP1 220Ω
2345678
1
GND
20
21
22
D4
D5
DRGND
AGND
AVDD
REFT
897
GND
AVDD
AINAMP
D3X
15
D3
VIN+
D2X
D1X
13
14
18
19
D1
D2
VIN–
AGND
101112 17
GND
AIN
D0X
12
AVDD D0
AVDD
11
16
13
NCX
DNC
CLK
NC2X
10
15
DNC
PWDN
14
9
(LSB)
U1
PARTS = 1
DEVICE = AD9215
CLK
R11
GND
1kΩ
E11
E9
AVDD
E7
E
E6
MODE SELECT
AVDD
C52
10µF
+
C30
VREF
REFERENCE CONFIGURATION
A: EXTERNAL VOLTAGE DIVIDER REFERENCE
B: INTERNAL 1V REFERENCE
C: EXTERNAL REFERENCE
D: INTERNAL 0.5V REFERENCE 1V MAX
0.1µF
R8
1kΩ
GND
GND
GND AVDD
R4
10kΩ
OPTIONAL
E5
F
E1
E21E20
CDBA
E18
E22
E16E17
R15
C18
0.1µF
Figure 50. TSSOPP Evaluation Board Schematic, Analog Inputs and DUT
E2
E3
R10
1kΩ
SENSE
E23
E19
GND
10kΩ
GND
E8
G
H
E4
R9
1kΩ
GND
C17
0.1µF
+
C29
10µF
C16
C13
0.1µF
0.1µF
GND
SINGLE-ENDED INPUT OPERATION
1. PLACE R7( 50Ω), R5( 0Ω) AND R46 (25Ω)
2. PLACE C23 (0.1µF), C9 (0.1µF)
3. REMOVE C33, C1, R34, R6, C32
GND
GND
R45
1kΩ
R44
1kΩ
AVDD
R5
0Ω
AMPIN
C9
0.1µF
DIFFERENTIAL
R6
0Ω
INPUT
R19
C8
33Ω
10pF
R33
C7
36Ω
L1
C32
J1
GND
C11
R16
0.001µF
SEC
PRI
10nH
0.1µF
0.1µF
XX
GND
COM
GND
C5
10pF
R21
33Ω
GND
C6
0.1µF
R32
36Ω
E45 E12
2
6
T1
1534
GND
OPTIONAL
R7
50Ω
GND
GND
GND
R29
R24
AVDD
0Ω
R34
1kΩ
1kΩ
AVDD
ANALOG INPUT OPTIONS
1. R6, R34 FOR DIFFERENTIAL OPERATION
2. C1, C33 FOR OP AMP OPERATION
C23
0.1µF
AMPIN
3. R7, R46, R5, C9, C23 FOR SINGLE-ENDED OPERATION
GND
R25
25Ω
COMMON MODE
PLEASE JUMPER E45 TO E32 DC VOLTAGE ADJUST
OR JUMPER E45 TO E12 CAPACITOR TO GROUND
C12
0.1µF
C14
0.1µF
R3
5kΩ
R1
10Ω
E32
OPTIONAL
GND
GNDGND
Rev. A | Page 26 of 36
AD9215
GND
P1
P3
P5
P7
P9
P11
P13
P15
P17
P19
P21
P23
P25
P27
P2
P4
P6
P8
P10
P12
P14
P16
P18
P20
P22
P24
P26
P28
P30 P29
P32 P31
P34 P33
GND
GND
C47
10µF
VAMP
E14
E30
OUT OF RANGE BIT
STRAP THIS AT ASSEMBLY
E13
9
10
11
RP4
14
15
16
220Ω
2345678
1
10
12
13
11
C41
9
GND
C42
0.1µF
+
GND
GND
0.1µF
R48
1kΩ
R49
1kΩ
VAMP
VAMPGND
AMPIN
C33
0.1µF
R17
C43
0.001µF
0Ω
R28
VPOS
VOCM
RGP1
PWUP
R47
10kΩ
R22
10kΩ
R50
0Ω
25Ω
8910
321
7
OPHI
INHI
4
C1
0.1µF
R27
6
OPLO
INLO
5
AMPIN
0Ω
COMM
RGP2
R31
GND
R30
U6
1.2kΩ
DEVICE = AD8351
100Ω
R51
25Ω
16
RP3
220Ω
1
P35
U2
P38 P37
P40 P39
P36
DRX
GND
GND
MSB
12
13
14
15
2345678
02874-A-049
U4
74LVT574
DEVICE = 74LVT574A
GND
VDL
20
19181716151413
Y3
Y2
Y1
Y0
VCC
X3
X2
X1
X0
OE
2345678
1
D7X
D8X
D9X
ORX
MSB
C44
VDL
CLKLAT/DAC
GND
1110
12
Y7
Y6
Y5
Y4
X4
D6X
CP
GND
X7
X6
X5
9
D5X
D4X
GND
GND
U3
20
74LVT574
1
DEVICE = 74LVT574A
VDL
VCC
OE
GND
19
2
GND
Y0
X0
GND
18
GND
17
Y1
X1
GND
11
12
13
14
15
16
Y7
Y6
Y5
Y4
Y3
Y2
X4
X3
X2
6
543
D3X
D2X
D1X
LSB
CP
GND
X7
X6
X5
9
8
7
10
D0X
NCX
GND
NC2X
R20
150Ω
CLKLAT/DAC
GND
C31
10pF
R23
100Ω
0.1µF
AMP
C45
0.1µF
GND
R36
25Ω
Figure 51. TSSOP Evaluation Board, Digital Path
Rev. A | Page 27 of 36
AD9215
DRX
0Ω
R52
J4
OPTIONAL
R43
1kΩ
R2
1kΩ
R26
1kΩ
R39
1kΩ
DRX
C28
GND
VCLK
GND
VCLK
GND
VCLK
GND
VCLK
0.1µF
R14
AVDD
AVDD
DRVDD
VDL
VCLK
DRVDD
1B1Y2A
234
R42
1kΩ
C40
ENCODE
R25
7
DRX
CLKLAT/DAC
0Ω
R18
GND
GND
11
14
2B2Y3A
3B3Y4A
569
10812
R41
0.1µF
R40
J3
VCLK
1kΩ
50Ω
0Ω
PWR
0Ω
4Y
4B
13
GND
GND
GND
R38
EXTERNAL DATA READY
E51E50
E52 E53
E44E43
E36E35
C19
0.001µF
SCHEMATIC SHOWS 1-GATE DELAY SETUP
FOR TWO-GATE DELAY REMOVE RESISTOR R52
GND
C21
0.1µF
DUT DRVDD BYPASSING
ENCX
C46
0.1µF
C39
0.001µF
C51
0.1µF
C36
0.1µF
C49
0.001µF
C35
0.001µF
C34
0.1µF
C48
0.1µF
AVDD BYPASSING GND
C50
10µF
+
C3
22µF
+
GNDGND
C4
10µF
+
C10
22µF
+
C2
22µF
+
C20
10µF
+
VCLK
C38
0.001µF
C37
0.001µF
C26
0.1µF
C24
0.1µF
C25
10µF
+
C27
10µF
+
DUT BYPASSING
VDL
GND
GND
CLK
U5 BYPASSING
R37
U3/U4 BYPASSING
ENCODE FROM XOR
ADD RESISTORS R38 AND R18
U5
74VCX86
1A
1
ENCX
FOR A DIRECT ENCODE USE R35
0Ω
R35
ENC
ENC
AVDD
0Ω
FOR A BUFFERED ENCODE USE R37
02874-A-050
50Ω
GNDGND
Figure 52. TSSOP Evaluation Board Schematic, Clock Input
Rev. A | Page 28 of 36
AD9215
Figure 53. TSSOP Evaluation Board Layout, Primary Side
Figure 54. TSSOP Evaluation Board Layout, Secondary Side
02874-A-051
02874-A-053
Figure 55. TSSOP Evaluation Board Layout, Ground Plane
02874-A-052
02874-A-054
Figure 56. TSSOP Evaluation Board Layout, Power Plane
Rev. A | Page 29 of 36
AD9215
02874-A-055
Figure 57. TSSOP Evaluation Board Layout, Primary Silkscreen Figure 58. TSSOP Evaluation Board Layout, Secondary Silkscreen
02874-A-056
Rev. A | Page 30 of 36
AD9215
Table 11. TSSOP Evaluation Board Bill of Materials (BOM)
Item Qty. Omit Reference Designator
11
1
C47
C2 to C4, C10, C20,
C25, C27, C29,
C47, C50, C52
Device
Tantalum Capacitor TAJD 10 µF
Package Value
Recommended
Vendor/Part No.
2 C5,C8 2
1 C31
3 15
4 3 C12, C14, C23, C28 Chip Capacitor 0603 Select
5 8
6 6
7 1 C43 BCAP0402 0402 0.001 µF
8 1 C11 BCAP0603 0603 Select
11
9
2 R48, R49
4 R6, R25, R34, R37 10
8
C6, C9, C13,
C15 to C18, C21, C24,
C26, C30, C32, C34, C36,
C40, C46, C48, C51
C7, C19, C35, C19,
C37 to C39, C49
C1,C33, C41 to C42,
C44 to C5
R2, R8 to R11, R24,
R26, R29, R39, R41 to R45
R5, R35, R17 to R18,
R27 to R28, R38, R52
Chip Capacitor 0603 10 pF
Chip Capacitor 0603 0.1 µF
Chip Capacitor 0603 0.001 µF
BCAP0402 0402 0.1 µF
BRES603 0603A 1 kΩ
BRES603 0603A 0 Ω
2 R7, R40 11
1 R14
12 2 R19, R21 BRES603 0603A 33 Ω
13 2 R32, R33 RES0603 0603A 36 Ω
14 1 R16 BRES603 0603 Select
15 2 R4, R15, BRES603 0603 10 kΩ
16 4 R20, R22 to R23, R47 BRES603 0603A Select
17 2 R48, R49 BRES603 0603 1 kΩ
18 4 R36, R46, R50 to R51 BRES603 0603 25 Ω
19 1 R31 BRES603 0603 100 Ω
20 1 R30 BRES603 0603 1.2 kΩ
21 1 R3 BRES603 0603 5 kΩ
22 1 R1 Potentiometer RJ24FW 10 kΩ
23 4 RP1 to RP4 Resister Pack 220• 742C163221
BRES603 0603A 50 Ω
Rev. A | Page 31 of 36
AD9215
Item Qty. Omit Reference Designator
Device
Package Value
Recommended
Vendor/Part No.
24 1 L1 Chip Inductor 0603 10 nH
25 1 T1 1:1 RF Transformer CD542
26 1 U1 ADC 28TSSOP
27 1 U2 Right Angle 40-Pin Header
28 2 U3, U4 Octal D-Type Flip-Flop Fairchild 74LVT57MSA
29 1 U5 Quad XOR Gate SO14 Fairchild 74VCX86M
30 1 U6 High Speed Amplifier SOMB10
2 J1, J3 31
1 J4
32 2 P1, P2 Power Connector PTMICRO4
33 26
E1/E5, E2/E3, E4/E8,
E9/E11, E6/E7, E16/E17,
E19/E22, E18/E23, E21/20,
E35/E51, E36/E50, E43/E53,
E44/E52
SMB Connecter SMBP
Headers/Jumper Blocks
Coilcraft/0603CS10NXGBU
Mini-Circuits
AWT1-1T
Analog Devices, Inc.
AD9215
Samtec
TSW-120-08-T-D-RA
Analog Devices, Inc.
AD8351ARM
Weiland
Z5.531.3425.0 Posts
25.602.5453.0 Top
TSW-120-07-G-S
SMT-100-BK-G
34 12
E24/E27, E25/E26, E28/E29,
E13/E14/E30, E12/E32/E45
Wirehole
Rev. A | Page 32 of 36
AD9215
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
PIN 1
0.15
0.05
COPLANARITY
0.10
0.65
BSC
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153AE
1.20 MAX
SEATING
PLANE
15
4.50
4.40
4.30
0.20
0.09
6.40 BSC
8°
0°
0.75
0.60
0.45
141
Figure 59. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
1.00
0.85
0.80
12° MAX
SEATING
PLANE
5.00
BSC SQ
PIN 1
INDICATOR
TOP
VIEW
0.80 MAX
0.65 TYP
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
NOTE:
IT IS RECOMMENDED THAT THE EXPOSED PADDLE BE SOLDERED
TO THE GROUND PLANE FOR THE LFCSP PACKAGE. THERE IS AN
INCREASED RELIABILITY OF THE SOLDER JOINTS, AND THE MAXIMUM
THERMAL CAPABILITY OF THE PACKAGE IS ACHIEVED WITH THE
EXPOSED PADDLE SOLDERED TO THE CUSTOMER BOARD.
4.75
BSC SQ
0.20 REF
0.05 MAX
0.02 NOM
0.60 MAX
0.50
BSC
0.50
0.40
0.30
COPLANARITY
0.08
Figure 60. 32-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-32)
Dimensions shown in millimeters
0.60 MAX
25
24
17
16
BOTTOM
VIEW
32
9
1
8
3.50 REF
PIN 1
INDICATOR
3.25
3.10 SQ
2.95
0.25 MIN
Rev. A | Page 33 of 36
AD9215
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9215BRU-65 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9215BRU-80 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9215BRU-105 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9215BRURL7-65 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9215BRURL7-80 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9215BRURL7-105 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD9215BRU-65EB AD9215BRU-65 Evaluation Board (TSSOP) RU-28
AD9215BRU-80EB AD9215BRU-80 Evaluation Board (TSSOP) RU-28
AD9215BRU-105EB AD9215BRU-105 Evaluation Board (TSSOP) RU-28
AD9215BCP-65 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32
AD9215BCP-80 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32
AD9215BCP-105 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32
AD9215BCPZ-651 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32
AD9215BCPZ-801 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32
AD9215BCPZ-1051 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32
AD9215BCP-65EB AD9215BCP-65 Evaluation Board (LFCSP) CP-32
AD9215BCP-80EB AD9215BCP-80 Evaluation Board (LFCSP) CP-32
AD9215BCP-105EB AD9215BCP-105 Evaluation Board (LFCSP) CP-32
1
Z = Pb-free part.
Rev. A | Page 34 of 36
AD9215
NOTES
Rev. A | Page 35 of 36
AD9215
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
C02874-0-2/04(A)
Rev. A | Page 36 of 36
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