Analog Devices AD9212 Service Manual

Octal, 10-Bit, 40/65 MSPS

A

V

FEATURES

Eight ADCs integrated into 1 package
100 mW ADC power per channel at 65 MSPS
SNR = 60.8 dB (to Nyquist)
Excellent linearity

DNL = ±0.3 LSB (typical)

INL = ±0.4 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power reduced signal option, IEEE 1596.3 similar
Data and frame clock outputs
325 MHz, full power analog bandwidth
2 V p-p input voltage range

1.8 V supply operation
Serial port control

Full-chip and individual-channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

APPLICATIONS

Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam forming systems
Quadrature radio receivers
Diversity radio receivers
Tap e dr ive s
Optical networking
Test equipment

GENERAL DESCRIPTION

The AD9212 is an octal, 10-bit, 40/65 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 65 MSPS and
is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.

The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock (DCO)
for capturing data on the output and a frame clock (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

Serial LVDS 1.8 V A/D Converter

AD9212

FUNCTIONAL BLOCK DIAGRAM

AGND

PDWN

0.5V

CSB

ADC

ADC

ADC

ADC

ADC

ADC

ADC

ADC

SERI AL P ORT

INTERFA CE

SDIO/

ODM

Figure 1.

SCLK/

DTP

12

SERIAL

LVDS

12

SERIAL

LVDS

12

SERIAL

LVDS

12

SERIAL

LVDS

12

SERIAL

LVDS

12

SERIAL

LVDS

12

SERIAL

LVDS

12

SERIAL

LVDS

DATA RATE

MULTI PLI ER

CLK+

DRGND

CLK–

DD DRVDD

AD9212

VIN+A

VIN–A

VIN+B

VIN–B

VIN+C

VIN–C

VIN+D

VIN–D

VIN+E

VIN–E

VIN+F

VIN–F

VIN+G

VIN–G

VIN+H

VIN–H

VREF

SENSE

REFT

REFB

REF

SELECT

RBIAS

The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user­defined test patterns entered via the serial port interface (SPI®).

The AD9212 is available in a Pb-free, 64-lead LFCSP package. It is
specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Small Footprint. Eight ADCs are contained in a small, space-

saving package; low power of 100 mW/channel at 65 MSPS.

2. Ease of Use. A data clock output (DCO) operates up to

300 MHz and supports double data rate operation (DDR).

3. User Flexibility. Serial port interface (SPI) control offers a wide

range of flexible features to meet specific system requirements.

4. Pin-Compatible Family. This includes the AD9222 (12-bit),

and AD9252 (14-bit).

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

D+A
D–A

D+B
D–B

D+C
D–C

D+D
D–D

D+E
D–E

D+F
D–F

D+G
D–G

D+H
D–H

FCO+

FCO–

DCO+
DCO–

05968-001

AD9212

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Diagrams.............................................................................. 7

Absolute Maximum Ratings............................................................ 9

Thermal Impedance..................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Equivalent Circuits......................................................................... 12

Typical Performance Characteristics ........................................... 14

Theory of Operation ...................................................................... 19

Analog Input Considerations ................................................... 19

Clock Input Considerations...................................................... 22

Serial Port Interface (SPI).............................................................. 30

Hardware Interface..................................................................... 30

Memory Map .................................................................................. 32

Reading the Memory Map Table.............................................. 32

Reserved Locations .................................................................... 32

Default Values............................................................................. 32

Logic Levels................................................................................. 32

Evaluation Board ............................................................................ 36

Power Supplies ............................................................................ 36

Input Signals................................................................................ 36

Output Signals ............................................................................ 36

Default Operation and Jumper Selection Settings................. 37

Alternative Analog Input Drive Configuration...................... 38

Outline Dimensions ....................................................................... 55

Ordering Guide .......................................................................... 55

REVISION HISTORY

10/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 56

AD9212

SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 1.

AD9212-40 AD9212-65
Parameter

RESOLUTION 10 10 Bits
ACCURACY

No Missing Codes Full Guaranteed Guaranteed
Offset Error Full ±1.5 ±8 ±1.5 ±8 mV
Offset Matching Full ±3 ±8 ±3 ±8 mV
Gain Error Full ±0.4 ±1.2 ±3.2 ±4.3 % FS
Gain Matching Full ±0.3 ±0.7 ±0.4 ±0.9 % FS
Differential Nonlinearity (DNL) Full ±0.1 ±0.4 ±0.3 ±0.65 LSB
Integral Nonlinearity (INL) Full ±0.15 ±0.5 ±0.4 ±1 LSB

TEMPERATURE DRIFT

Offset Error Full ±2 ±2 ppm/°C
Gain Error Full ±17 ±17 ppm/°C
Reference Voltage (1 V Mode) Full ±21 ±21 ppm/°C

REFERENCE

Output Voltage Error (VREF = 1 V) Full ±2 ±30 ±2 ±30 mV
Load Regulation @ 1.0 mA (VREF = 1 V) Full 3 3 mV
Input Resistance Full 6 6 kΩ

ANALOG INPUTS

Differential Input Voltage Range (VREF = 1 V) Full 2 2 V p-p
Common-Mode Voltage Full AVDD/2 AVDD/2 V
Differential Input Capacitance Full 7 7 pF
Analog Bandwidth, Full Power Full 325 325 MHz

POWER SUPPLY

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
IAVDD Full 252 260 390 405 mA
IDRVDD Full 49.5 53 54 58 mA
Total Power Dissipation (Including Output Drivers) Full 542 560 800 833 mW
Power-Down Dissipation Full 3 11 3 11 mW

Standby Dissipation
CROSSTALK Full −90 −90 dB
CROSSTALK (Overrange Condition)

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

Can be controlled via SPI.

3

Overrange condition is specific with 6 dB of the full-scale input range.

1

2

3

Temperature Min Typ Max Min Typ Max Unit

Full 83 95 mW

Full −90 −90 dB

Rev. 0 | Page 3 of 56

AD9212

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 2.

AD9212-40 AD9212-65
Parameter

SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz Full 61.2 60.8 dB
f
f
f
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz Full 61.2 60.7 dB
f
f
f
EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz Full 9.87 9.81 Bits
f
f
f
SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz Full 87 81 dBc
f
f
f
f
WORST HARMONIC (Second or Third) fIN = 2.4 MHz Full −87 −81 dBc
f
f
f
f
WORST OTHER (Excluding Second or Third) fIN = 2.4 MHz Full −90 −86 dBc
f
f
f
TWO-TONE INTERMODULATION DISTORTION (IMD)—

AIN1 AND AIN2 = −7.0 dBFS

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

1

Temperature Min Typ Max Min Typ Max Unit

= 19.7 MHz Full 60.2 61.2 60.8 dB

IN

= 35 MHz Full 61.2 58.5 60.8 dB

IN

= 70 MHz Full 61.0 60.7 dB

IN

= 19.7 MHz Full 60.0 61.0 60.6 dB

IN

= 35 MHz Full 61.0 57.0 60.5 dB

IN

= 70 MHz Full 60.8 60.4 dB

IN

= 19.7 MHz Full 9.71 9.87 9.81 Bits

IN

= 35 MHz Full 9.87 9.43 9.81 Bits

IN

= 70 MHz Full 9.84 9.79 Bits

IN

= 19.7 MHz Full 72 85 79 dBc

IN

= 35 MHz Full 79 62 77 dBc

IN

= 35 MHz 25°C 69 77 dBc

IN

= 70 MHz Full 74 72 dBc

IN

= 19.7 MHz Full −85 −72 −79 dBc

IN

= 35 MHz Full −79 −77 −62 dBc

IN

= 35 MHz 25°C −77 −69 dBc

IN

= 70 MHz Full −74 −72 dBc

IN

= 19.7 MHz Full −85 −72 −86 dBc

IN

= 35 MHz Full −85 −85 −70 dBc

IN

= 70 MHz Full −85 −85 dBc

IN

f

= 15 MHz,

IN1

= 16 MHz

f

IN2

= 70 MHz,

f

IN1

= 71 MHz

f

IN2

25°C 80.0 77.0 dBc

25°C 77.0 77.0 dBc

Rev. 0 | Page 4 of 56

AD9212

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 3.

AD9212-40 AD9212-65
Parameter

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL

Differential Input Voltage

Input Common-Mode Voltage Full 1.2 1.2 V

Input Resistance (Differential) 25°C 20 20 kΩ

Input Capacitance 25°C 1.5 1.5 pF
LOGIC INPUTS (PDWN, SCLK/DTP)

Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V

Logic 0 Voltage Full 0 0.3 0.3 V

Input Resistance 25°C 30 30 kΩ

Input Capacitance 25°C 0.5 0.5 pF
LOGIC INPUT (CSB)

Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V

Logic 0 Voltage Full 0 0.3 0.3 V

Input Resistance 25°C 70 70 kΩ

Input Capacitance 25°C 0.5 0.5 pF
LOGIC INPUT (SDIO/ODM)

Logic 1 Voltage Full 1.2 DRVDD + 0.3 1.2 DRVDD + 0.3 V

Logic 0 Voltage Full 0 0.3 0 0.3 V

Input Resistance 25°C 30 30 kΩ

Input Capacitance 25°C 2 2 pF
LOGIC OUTPUT (SDIO/ODM)

Logic 1 Voltage (IOH = 50 μA) Full 1.79 1.79 V

Logic 0 Voltage (IOL = 50 μA) Full 0.05 0.05 V
DIGITAL OUTPUTS (D+, D−), (ANSI-644)

Logic Compliance LVDS LVDS

Differential Output Voltage (VOD) Full 247 454 247 454 mV

Output Offset Voltage (VOS) Full 1.125 1.375 1.125 1.375 V

Output Coding (Default) Offset binary Offset binary
DIGITAL OUTPUTS (D+, D−),

(Low Power, Reduced Signal Option)

Logic Compliance LVDS LVDS

Differential Output Voltage (VOD) Full 150 250 150 250 mV

Output Offset Voltage (VOS) Full 1.10 1.30 1.10 1.30 V

Output Coding (Default) Offset binary Offset binary

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

This is specified for LVDS and LVPECL only.

1

2

Temperature Min Typ Max Min Typ Max Unit

Full 250 250 mV p-p

Rev. 0 | Page 5 of 56

AD9212

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 4.

AD9212-40 AD9212-65

Parameter

CLOCK

OUTPUT PARAMETERS

APERTURE

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

Can be adjusted via the SPI interface.

3

Measurements were made using a part soldered to FR4 material.

4

t

SAMPLE

1

2

Temp

Min Typ Max Min Typ Max Unit

Maximum Clock Rate Full 40 65 MSPS
Minimum Clock Rate Full 10 10 MSPS
Clock Pulse Width High (tEH) Full 12.5 7.7 ns
Clock Pulse Width Low (tEL) Full 12.5 7.7 ns

2, 3

Propagation Delay (tPD) Full 1.5 2.3 3.1 1.5 2.3 3.1 ns
Rise Time (tR) (20% to 80%) Full 300 300 ps
Fall Time (tF) (20% to 80%) Full 300 300 ps
FCO Propagation Delay (t
DCO Propagation Delay (t

DCO to Data Delay (t

DCO to FCO Delay (t
Data to Data Skew

− t

(t

DATA-MAX

DATA-MIN

) Full 1.5 2.3 3.1 1.5 2.3 3.1 ns

FCO

)4Full t

CPD

DATA

FRAME

)4

)4

Full (t

Full (t

/20) − 300 (t

SAMPLE

/20) − 300 (t

SAMPLE

FCO

(t

+

SAMPLE

SAMPLE

SAMPLE

t

/20)
/20) (t

/20) (t

/20) + 300 (t

SAMPLE

/20) + 300 (t

SAMPLE

/20) − 300 (t

SAMPLE

/20) − 300 (t

SAMPLE

FCO

(t

SAMPLE

SAMPLE

SAMPLE

+

/20)
/20) (t

/20) (t

ns

/20) + 300 ps

SAMPLE

/20) + 300 ps

SAMPLE

Full ±50 ±200 ±50 ±200 ps

)
Wake-Up Time (Standby) 25°C 600 600 ns
Wake-Up Time (Power-Down) 25°C 375 375 μs
Pipeline Latency Full 8 8 CLK

cycles

Aperture Delay (tA) 25°C 750 750 ps
Aperture Uncertainty (Jitter) 25°C <1 <1 ps rms
Out-of-Range Recovery Time 25°C 1 1 CLK

cycles

/20 is based on the number of bits divided by 2 because the delays are based on half duty cycles.

Rev. 0 | Page 6 of 56

AD9212

TIMING DIAGRAMS

N–1

AIN

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

D–

D+

t

A

N

t

t

FCO

PD

t

EH

t

CPD

t

FRAME

MSB

D8

N – 8

N – 8D7N – 8

D6

N – 8

t

D5

N – 8

EL

t

DATA

D4

N – 8

D3

N – 8

D2

N – 8

D1

N – 8

D0

N – 8

MSB
N – 7

D8

N – 7D7N – 7

D6

N – 7

D5

N – 7

05968-003

Figure 2. 10-Bit Data Serial Stream (Default)

AIN

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

N-1

t

A

N

t

EH

t

CPD

t

FCO

t

D–

D+

PD

t

FRAME

MSB

D10

N – 8

N – 8D9(N – 8)D8N – 8D7N – 8D6N – 8D5N – 8D4N – 8D3N – 8D2N – 8D1N – 8D0N – 8

t

EL

t

DATA

D10

MSB

N – 7

N – 7

05968-002

Figure 3.12-Bit Data Serial Stream

Rev. 0 | Page 7 of 56

AD9212

N–1

AIN

t

A

N

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

t

EH

t

CPD

t

FCO

t

PD

D–

D+

t

FRAME

LSB

N – 8D0N – 8D1N – 8D2N – 8D3N – 8D4N – 8D5N – 8D6N – 8D7N – 8D8N – 8

t

EL

t

DATA

LSB

N – 7D0N – 7

D1

N – 7

D2

N – 7

05968-004

Figure 4. 10-Bit Data Serial Stream, LSB First

Rev. 0 | Page 8 of 56

AD9212

ABSOLUTE MAXIMUM RATINGS

Table 5.

With

Parameter

ELECTRICAL

AVDD AGND −0.3 V to +2.0 V
DRVDD DRGND −0.3 V to +2.0 V
AGND DRGND −0.3 V to +0.3 V
AVDD DRVDD −2.0 V to +2.0 V
Digital Outputs

(D+, D−, DCO+,

DCO−, FCO+, FCO−)
CLK+, CLK− AGND −0.3 V to +3.9 V
VIN+, VIN− AGND −0.3 V to +2.0 V
SDIO/ODM AGND −0.3 V to +2.0 V
PDWN, SCLK/DTP, CSB AGND −0.3 V to +3.9 V
REFT, REFB, RBIAS AGND −0.3 V to +2.0 V
VREF, SENSE AGND −0.3 V to +2.0 V

ENVIRONMENTAL

Operating Temperature

Range (Ambient)
Maximum Junction

Temperature
Lead Temperature

(Soldering, 10 sec)
Storage Temperature

Range (Ambient)

Respect To

DRGND −0.3 V to +2.0 V

−40°C to +85°C

150°C

300°C

−65°C to +150°C

Rating

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL IMPEDANCE

Table 6.

Air Flow
Velocity (m/s)

0.0 17.7°C/W

1.0 15.5°C/W 8.7°C/W 0.6°C/W

2.5 13.9°C/W

1

θ

for a 4-layer PCB with solid ground plane (simulated). Exposed pad

JA

soldered to PCB.

1

θ

JA

θ

JB

θ

JC

ESD CAUTION

Rev. 0 | Page 9 of 56

AD9212

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VIN+F

VIN–F

AVD D

VIN–E

VIN+E

AVD D

REFT

REFB

VREF

SENSE

RBIAS

VIN+D

VIN–D

AVD D

VIN–C

VIN+C

49

48

AVD D

47

VIN+B

46

VIN–B

45

AVD D

44

VIN–A

43

VIN+A

42

AVD D

41

PDWN

40

CSB

39

SDIO/ODM

38

SCLK/DTP

37

AVD D

36

DRGND

35

DRVDD

34

D+A

33

D–A

AVD D
VIN+G
VIN–G

AVD D
VIN–H
VIN+H

AVD D

AVD D

CLK–

CLK+

AVD D

AVD D

DRGND

DRVDD

D–H
D+H

646362616059585756555453525150

PIN 1
INDICATOR

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

EXPOSED PADDLE, PIN 0
(BOTTO M OF PACKAGE)

AD9212

TOP VIEW

(Not to Scale)

171819202122232425262728293031

D–F

D+F

D–E

D–G

D+E

D+G

D–D

FCO–

FCO+

DCO–

DCO+

32

D–C

D–B

D+D

D+C

D+B

Figure 5. 64-Lead LFCSP Top View

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

0 AGND Analog Ground (Exposed Paddle)
1, 4, 7, 8, 11,

AVDD 1.8 V Analog Supply
12, 37, 42, 45,
48, 51, 59, 62

13, 36 DRGND Digital Output Driver Ground
14, 35 DRVDD 1.8 V Digital Output Driver Supply
2 VIN+G ADC G Analog Input—True
3 VIN−G ADC G Analog Input—Complement
5 VIN−H ADC H Analog Input—Complement
6 VIN+H ADC H Analog Input—True
9 CLK− Input Clock—Complement
10 CLK+ Input Clock—True
15 D−H ADC H Digital Output—Complement
16 D+H ADC H True Digital Output—True
17 D−G ADC G Digital Output—Complement
18 D+G ADC G True Digital Output—True
19 D−F ADC F Digital Output—Complement
20 D+F ADC F True Digital Output—True
21 D−E ADC E Digital Output—Complement
22 D+E ADC E True Digital Output—True
23 DCO− Data Clock Digital Output—Complement
24 DCO+ Data Clock Digital Output—True
25 FCO− Frame Clock Digital Output—Complement
26 FCO+ Frame Clock Digital Output—True
27 D−D ADC D Digital Output—Complement
28 D+D ADC D True Digital Output—True
29 D−C ADC C Digital Output—Complement
30 D+C ADC C True Digital Output—True
31 D−B ADC B Digital Output—Complement
32 D+B ADC B True Digital Output—True

05968-005

Rev. 0 | Page 10 of 56

AD9212

Pin No. Mnemonic Description

33 D−A ADC A Digital Output—Complement
34 D+A ADC A True Digital Output—True
38 SCLK/DTP Serial Clock/Digital Test Pattern
39 SDIO/ODM Serial Data Input-Output/Output Driver Mode
40 CSB Chip Select Bar
41 PDWN Power Down
43 VIN+A ADC A Analog Input—True
44 VIN−A ADC A Analog Input—Complement
46 VIN−B ADC B Analog Input—Complement
47 VIN+B ADC B Analog Input—True
49 VIN+C ADC C Analog Input—True
50 VIN−C ADC C Analog Input—Complement
52 VIN−D ADC D Analog Input—Complement
53 VIN+D ADC D Analog Input—True
54 RBIAS External Resistor to Set the Internal ADC Core Bias Current
55 SENSE Reference Mode Selection
56 VREF Voltage Reference Input/Output
57 REFB Differential Reference (Negative)
58 REFT Differential Reference (Positive)
60 VIN+E ADC E Analog Input—True
61 VIN−E ADC E Analog Input—Complement
63 VIN−F ADC F Analog Input—Complement
64 VIN+F ADC F Analog Input—True

Rev. 0 | Page 11 of 56

AD9212

S

EQUIVALENT CIRCUITS

DRVDD

VIN

Figure 6. Equivalent Analog Input Circuit

CLK

CLK

10

10k

1.25V

10k

10

V

D– D+

V

05968-006

DRGND

V

V

5968-009

Figure 9. Equivalent Digital Output Circuit

SCLK/DTP OR PDWN

1k

30k

Figure 7. Equivalent Clock Input Circuit

DIO/ODM

350

30k

Figure 8. Equivalent SDIO/ODM Input Circuit

05968-007

05968-010

Figure 10. Equivalent SCLK/DTP or PDWN Input Circuit

RBIAS

05968-008

100

05968-011

Figure 11. Equivalent RBIAS Circuit

Rev. 0 | Page 12 of 56

AD9212

A

V

DD

70k

CSB

Figure 12. Equivalent CSB Input Circuit

1k

VREF

6k

05968-012

5968-014

Figure 14. Equivalent VREF Circuit

SENSE

1k

05968-013

Figure 13. Equivalent SENSE Circuit

Rev. 0 | Page 13 of 56

AD9212

TYPICAL PERFORMANCE CHARACTERISTICS

0

AIN = –0.5dBFS
SNR = 60.41dB
ENOB = 9.7
SFDR = 76.11dBc

–20

–20

0

AIN = –0.5dBFS
SNR = 60.08dB
ENOB = 9.61
SFDR = 71.68dBc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 5 10 15 20 25 30

Figure 15. Single-Tone 32k FFT with f

0

AIN = –0.5dBF S
SNR = 61.17dB
ENOB = 9.85
SFDR = 81.27dBc

–20

–40

–60

–80

AMPLI TUDE (d BFS)

–100

FREQUENCY (MHz)

IN

= 2.3 MHz, AD9212-40

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

0 5 10 15 20 25 30

05968-037

Figure 18. Single-Tone 32k FFT with f

0

–20

–40

–60

–80

AMPLI TUDE (d BFS)

–100

FREQUENCY (MHz)

IN

= 35 MHz, AD9212-65

AIN = –0.5dBFS
SNR = 60.25dB
ENOB = 9.66
SFDR = 72.45dBc

05968-040

–120

0

2 6 10 14 184 8 12 16 20

Figure 16. Single-Tone 32k FFT with f

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 5 10 15 20 25 30

Figure 17. Single-Tone 32k FFT with f

FREQUENCY (MHz)

= 19.7 MHz, AD9212-40

IN

FREQUENCY (MHz)

IN

AIN = –0.5dBF S
SNR = 60.48dB
ENOB = 9.72
SFDR = 76.84d Bc

= 2.3 MHz, AD9212-65

05968-038

05968-039

Rev. 0 | Page 14 of 56

–120

0 5 10 15 20 25 30

Figure 19. Single-Tone 32k FFT with f

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 5 10 15 20 25 30

Figure 20. Single-Tone 32k FFT with f

FREQUENCY (MHz)

IN

FREQUENCY (MHz)

= 120 MHz, AD9212-65

IN

= 70 MHz, AD9212-65

AIN = –0.5dBFS
SNR = 60.08dB
ENOB = 9.61
SFDR = 71.68dBc

05968-041

05968-042

AD9212

90

85

80

75

70

65

SNR/SF DR (dB)

60

55

50

10 40

Figure 21. SNR/SFDR vs. f

90

85

80

75

70

65

SNR/SFDR (dB)

60

55

50

10 40

Figure 22. SNR/SFDR vs. f

SFDR

SNR

ENCODE (MSPS)

, fIN = 10.3 MHz, AD9212-40

SAMPLE

SFDR

SNR

ENCODE (MSPS)

, fIN = 19.7 MHz, AD9212-40

SAMPLE

3530252015

05968-043

3530252015

05968-044

90

85

80

75

70

65

SNR/SFDR (dB)

60

55

50

10

Figure 24. SNR/SFDR vs. f

100

90

80

70

60

50

40

SNR/SFDR (dB)

30

20

10

0

–60 –50 –40 –30 –20 –10 0

Figure 25. SNR/SFDR vs. Analog Input Level, f

SFDR

SNR

ENCODE (MSPS)

, fIN = 35 MHz, AD9212-65

SAMPLE

SFDR

70dB REFERENCE

SNR

ANALOG INP UT LEVEL (dBFS)

= 10.3 MHz, AD9212-40

IN

6050403020

5968-046

05968-047

90

85

80

75

70

65

SNR/SFDR (dB)

60

55

50

10

Figure 23. SNR/SFDR vs. f

SFDR

SNR

ENCODE (MSPS)

, fIN = 10.3 MHz, AD9212-65

SAMPLE

100

90

80

70

60

50

40

SNR/SFDR (dB)

30

20

10

0

6050403020

05968-045

–60 –50 –40 –30 –20 –10 0

Figure 26. SNR/SFDR vs. Analog Input Level, f

SFDR

70dB REF ERENCE

SNR

ANALOG INPUT LEVEL (dBFS)

= 35 MHz, AD9212-40

IN

05968-048

Rev. 0 | Page 15 of 56

AD9212

100

90

80

70

60

50

40

SNR/SFDR (dB)

30

20

10

0

–60 –50 –40 –30 –20 –10 0

Figure 27. SNR/SFDR vs. Analog Input Level, f

SFDR

70dB REFERENCE

SNR

ANALOG INPUT LEVEL (dBFS)

= 10.3 MHz, AD9212-65

IN

05968-049

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0

24681012 14 16 18 20

FREQUENCY (MHz )

Figure 30. Two-Tone 32k FFT with f

AD9212-40

AIN1 AND AIN2 = –7dBFS
SFDR = 76.7d B
IMD2 = 83.38d Bc
IMD3 = 77.21d Bc

= 70 MHz and f

IN1

= 71 MHz,

IN2

05968-052

100

90

80

70

60

50

40

SNR/SFDR (dB)

30

20

10

0

–60 –50 –40 –30 –20 –10 0

Figure 28. SNR/SFDR vs. Analog Input Level, f

0

AIN1 AND AIN2 = –7dBFS
SFDR = 84.8dB
IMD2 = 83.66dBc
IMD3 = 84.6dBc

–20

–40

SFDR

70dB REFERENCE

SNR

ANALOG INPUT LEVEL (dBFS)

= 35 MHz, AD9212-65

IN

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

05968-050

0 5 10 15 20 25 30

FREQUENCY (MHz)

Figure 31. Two-Tone 32k FFT with f

= 16 MHz, AD9212-65

f

IN2

0

–20

–40

AIN1 AND AIN2 = –7dBFS
SFDR = 77.4dB
IMD2 = 77.92dBc
IMD3 = 76.9dBc

= 15 MHz and

IN1

AIN1 AND AIN2 = –7dBFS
SFDR = 72.5dB
IMD2 = 77.14dBc
IMD3 = 72.55dBc

5968-053

–60

–80

AMPLITUDE (dBFS)

–100

–120

0

24681012 14 16 18 20

FREQUENCY (MHz )

Figure 29. Two-Tone 32k FFT with f

AD9212-40

= 15 MHz and f

IN1

= 16 MHz,

IN2

5968-051

Rev. 0 | Page 16 of 56

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 5 10 15 20 25 30

Figure 32. Two-Tone 32k FFT with f

FREQUENCY (MHz )

= 71 MHz, AD9212- 65

f

IN2

= 70 MHz and

IN1

5968-054

AD9212

–

80

75

SFDR

70

65

SNR/SFDR (dB)

60

55

50

1 10 100 1 000

Figure 33. SNR/SFDR vs. f

SNR

ANALOG INPUT FREQUENCY ( MHz)

, AD9212-65

IN

05968-055

0.5

0.4

0.3

0.2

0.1

0

INL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0

Figure 36. INL, f

CODE

= 2.3 MHz, AD9212-65

IN

1000200 400 600 800

05968-058

90

85

80

75

70

65

SINAD/SFDR (d B)

60

55

50

–40 –20 0 20 40 60 80

TEMPERATURE (°C)

Figure 34. SINAD/SFDR vs. Temperature, f

90

85

80

75

70

65

SINAD/SFDR (d B)

60

55

50

–40 –20 0 20 40 60 80

SFDR

SINAD

TEMPERATURE (°C)

SFDR

SINAD

= 10.3 MHz, AD9212-40

IN

Figure 35. SINAD/SFDR vs. Temperature, fIN = 10.3 MHz, AD9212-65

0.5

0.4

0.3

0.2

0.1

0

DNL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

05968-056

05968-057

0

CODE

Figure 37. DNL, f

30

–35

–40

–45

–50

CMRR (dB)

–55

–60

–65

–70

0 5 10 15 20 25 30 35 40

= 2.3 MHz, AD9212-65

IN

FREQUENCY (MHz)

1000200 400 600 800

05968-060

05968-061

Figure 38. CMRR vs. Frequency, AD9212-65

Rev. 0 | Page 17 of 56