Analog Devices AD9212 Service Manual

Octal, 10-Bit, 40/65 MSPS

A

V

FEATURES

Eight ADCs integrated into 1 package 100 mW ADC power per channel at 65 MSPS SNR = 60.8 dB (to Nyquist) Excellent linearity

DNL = ±0.3 LSB (typical)

INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) Low power reduced signal option, IEEE 1596.3 similar Data and frame clock outputs 325 MHz, full power analog bandwidth 2 V p-p input voltage range

1.8 V supply operation Serial port control

Full-chip and individual-channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

APPLICATIONS

Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam forming systems Quadrature radio receivers Diversity radio receivers Tap e dr ive s Optical networking Test equipment

GENERAL DESCRIPTION

The AD9212 is an octal, 10-bit, 40/65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.

The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Serial LVDS 1.8 V A/D Converter

AD9212

FUNCTIONAL BLOCK DIAGRAM

AGND

PDWN

0.5V

CSB

ADC

SERI AL P ORT

INTERFA CE

SDIO/

ODM

Figure 1.

SCLK/

DTP

12

SERIAL

LVDS

12

SERIAL

LVDS

12

SERIAL

LVDS

12

SERIAL

LVDS

12

SERIAL

LVDS

12

SERIAL

LVDS

12

SERIAL

LVDS

12

SERIAL

LVDS

DATA RATE

MULTI PLI ER

CLK+

DRGND

CLK–

DD DRVDD

AD9212

VIN+A

VIN–A

VIN+B

VIN–B

VIN+C

VIN–C

VIN+D

VIN–D

VIN+E

VIN–E

VIN+F

VIN–F

VIN+G

VIN–G

VIN+H

VIN–H

VREF

SENSE

REFT

REFB

REF

SELECT

RBIAS

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom userdefined test patterns entered via the serial port interface (SPI®).

The AD9212 is available in a Pb-free, 64-lead LFCSP package. It is specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Small Footprint. Eight ADCs are contained in a small, space-

saving package; low power of 100 mW/channel at 65 MSPS.

2. Ease of Use. A data clock output (DCO) operates up to

300 MHz and supports double data rate operation (DDR).

3. User Flexibility. Serial port interface (SPI) control offers a wide

range of flexible features to meet specific system requirements.

4. Pin-Compatible Family. This includes the AD9222 (12-bit),

and AD9252 (14-bit).

D+A D–A

D+B D–B

D+C D–C

D+D D–D

D+E D–E

D+F D–F

D+G D–G

D+H D–H

FCO+

FCO–

DCO+ DCO–

05968-001

AD9212

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Diagrams.............................................................................. 7

Absolute Maximum Ratings............................................................ 9

Thermal Impedance..................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Equivalent Circuits......................................................................... 12

Typical Performance Characteristics ........................................... 14

Theory of Operation ...................................................................... 19

Analog Input Considerations ................................................... 19

Clock Input Considerations...................................................... 22

Serial Port Interface (SPI).............................................................. 30

Hardware Interface..................................................................... 30

Memory Map .................................................................................. 32

Reading the Memory Map Table.............................................. 32

Reserved Locations .................................................................... 32

Default Values............................................................................. 32

Logic Levels................................................................................. 32

Evaluation Board ............................................................................ 36

Power Supplies ............................................................................ 36

Input Signals................................................................................ 36

Output Signals ............................................................................ 36

Default Operation and Jumper Selection Settings................. 37

Alternative Analog Input Drive Configuration...................... 38

Outline Dimensions ....................................................................... 55

Ordering Guide .......................................................................... 55

REVISION HISTORY

10/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 56

AD9212

SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 1.

AD9212-40 AD9212-65 Parameter

RESOLUTION 10 10 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±1.5 ±8 ±1.5 ±8 mV Offset Matching Full ±3 ±8 ±3 ±8 mV Gain Error Full ±0.4 ±1.2 ±3.2 ±4.3 % FS Gain Matching Full ±0.3 ±0.7 ±0.4 ±0.9 % FS Differential Nonlinearity (DNL) Full ±0.1 ±0.4 ±0.3 ±0.65 LSB Integral Nonlinearity (INL) Full ±0.15 ±0.5 ±0.4 ±1 LSB

TEMPERATURE DRIFT

Offset Error Full ±2 ±2 ppm/°C Gain Error Full ±17 ±17 ppm/°C Reference Voltage (1 V Mode) Full ±21 ±21 ppm/°C

REFERENCE

Output Voltage Error (VREF = 1 V) Full ±2 ±30 ±2 ±30 mV Load Regulation @ 1.0 mA (VREF = 1 V) Full 3 3 mV Input Resistance Full 6 6 kΩ

ANALOG INPUTS

Differential Input Voltage Range (VREF = 1 V) Full 2 2 V p-p Common-Mode Voltage Full AVDD/2 AVDD/2 V Differential Input Capacitance Full 7 7 pF Analog Bandwidth, Full Power Full 325 325 MHz

POWER SUPPLY

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V IAVDD Full 252 260 390 405 mA IDRVDD Full 49.5 53 54 58 mA Total Power Dissipation (Including Output Drivers) Full 542 560 800 833 mW Power-Down Dissipation Full 3 11 3 11 mW

Standby Dissipation CROSSTALK Full −90 −90 dB CROSSTALK (Overrange Condition)

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

Can be controlled via SPI.

3

Overrange condition is specific with 6 dB of the full-scale input range.

1

2

3

Temperature Min Typ Max Min Typ Max Unit

Full 83 95 mW

Full −90 −90 dB

Rev. 0 | Page 3 of 56

AD9212

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 2.

AD9212-40 AD9212-65 Parameter

SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz Full 61.2 60.8 dB f f f SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz Full 61.2 60.7 dB f f f EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz Full 9.87 9.81 Bits f f f SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz Full 87 81 dBc f f f f WORST HARMONIC (Second or Third) fIN = 2.4 MHz Full −87 −81 dBc f f f f WORST OTHER (Excluding Second or Third) fIN = 2.4 MHz Full −90 −86 dBc f f f TWO-TONE INTERMODULATION DISTORTION (IMD)—

AIN1 AND AIN2 = −7.0 dBFS

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

1

Temperature Min Typ Max Min Typ Max Unit

= 19.7 MHz Full 60.2 61.2 60.8 dB

IN

= 35 MHz Full 61.2 58.5 60.8 dB

IN

= 70 MHz Full 61.0 60.7 dB

IN

= 19.7 MHz Full 60.0 61.0 60.6 dB

IN

= 35 MHz Full 61.0 57.0 60.5 dB

IN

= 70 MHz Full 60.8 60.4 dB

IN

= 19.7 MHz Full 9.71 9.87 9.81 Bits

IN

= 35 MHz Full 9.87 9.43 9.81 Bits

IN

= 70 MHz Full 9.84 9.79 Bits

IN

= 19.7 MHz Full 72 85 79 dBc

IN

= 35 MHz Full 79 62 77 dBc

IN

= 35 MHz 25°C 69 77 dBc

IN

= 70 MHz Full 74 72 dBc

IN

= 19.7 MHz Full −85 −72 −79 dBc

IN

= 35 MHz Full −79 −77 −62 dBc

IN

= 35 MHz 25°C −77 −69 dBc

IN

= 70 MHz Full −74 −72 dBc

IN

= 19.7 MHz Full −85 −72 −86 dBc

IN

= 35 MHz Full −85 −85 −70 dBc

IN

= 70 MHz Full −85 −85 dBc

IN

f

= 15 MHz,

IN1

= 16 MHz

f

IN2

= 70 MHz,

f

IN1

= 71 MHz

f

IN2

25°C 80.0 77.0 dBc

25°C 77.0 77.0 dBc

Rev. 0 | Page 4 of 56

AD9212

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 3.

AD9212-40 AD9212-65 Parameter

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL

Differential Input Voltage

Input Common-Mode Voltage Full 1.2 1.2 V

Input Resistance (Differential) 25°C 20 20 kΩ

Input Capacitance 25°C 1.5 1.5 pF LOGIC INPUTS (PDWN, SCLK/DTP)

Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V

Logic 0 Voltage Full 0 0.3 0.3 V

Input Resistance 25°C 30 30 kΩ

Input Capacitance 25°C 0.5 0.5 pF LOGIC INPUT (CSB)

Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V

Logic 0 Voltage Full 0 0.3 0.3 V

Input Resistance 25°C 70 70 kΩ

Input Capacitance 25°C 0.5 0.5 pF LOGIC INPUT (SDIO/ODM)

Logic 1 Voltage Full 1.2 DRVDD + 0.3 1.2 DRVDD + 0.3 V

Logic 0 Voltage Full 0 0.3 0 0.3 V

Input Resistance 25°C 30 30 kΩ

Input Capacitance 25°C 2 2 pF LOGIC OUTPUT (SDIO/ODM)

Logic 1 Voltage (IOH = 50 μA) Full 1.79 1.79 V

Logic 0 Voltage (IOL = 50 μA) Full 0.05 0.05 V DIGITAL OUTPUTS (D+, D−), (ANSI-644)

Logic Compliance LVDS LVDS

Differential Output Voltage (VOD) Full 247 454 247 454 mV

Output Offset Voltage (VOS) Full 1.125 1.375 1.125 1.375 V

Output Coding (Default) Offset binary Offset binary DIGITAL OUTPUTS (D+, D−),

(Low Power, Reduced Signal Option)

Logic Compliance LVDS LVDS

Differential Output Voltage (VOD) Full 150 250 150 250 mV

Output Offset Voltage (VOS) Full 1.10 1.30 1.10 1.30 V

Output Coding (Default) Offset binary Offset binary

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

This is specified for LVDS and LVPECL only.

1

2

Temperature Min Typ Max Min Typ Max Unit

Full 250 250 mV p-p

Rev. 0 | Page 5 of 56

AD9212

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 4.

AD9212-40 AD9212-65

Parameter

CLOCK

OUTPUT PARAMETERS

APERTURE

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

Can be adjusted via the SPI interface.

3

Measurements were made using a part soldered to FR4 material.

4

t

SAMPLE

1

2

Temp

Min Typ Max Min Typ Max Unit

Maximum Clock Rate Full 40 65 MSPS Minimum Clock Rate Full 10 10 MSPS Clock Pulse Width High (tEH) Full 12.5 7.7 ns Clock Pulse Width Low (tEL) Full 12.5 7.7 ns

2, 3

Propagation Delay (tPD) Full 1.5 2.3 3.1 1.5 2.3 3.1 ns Rise Time (tR) (20% to 80%) Full 300 300 ps Fall Time (tF) (20% to 80%) Full 300 300 ps FCO Propagation Delay (t DCO Propagation Delay (t

DCO to Data Delay (t

DCO to FCO Delay (t Data to Data Skew

− t

(t

DATA-MAX

DATA-MIN

) Full 1.5 2.3 3.1 1.5 2.3 3.1 ns

FCO

)4Full t

CPD

DATA

FRAME

)4

Full (t

/20) − 300 (t

SAMPLE

/20) − 300 (t

SAMPLE

FCO

(t

+

SAMPLE

t

/20) /20) (t

/20) (t

/20) + 300 (t

SAMPLE

/20) + 300 (t

SAMPLE

/20) − 300 (t

SAMPLE

/20) − 300 (t

SAMPLE

FCO

(t

SAMPLE

+

/20) /20) (t

/20) (t

ns

/20) + 300 ps

SAMPLE

/20) + 300 ps

SAMPLE

Full ±50 ±200 ±50 ±200 ps

) Wake-Up Time (Standby) 25°C 600 600 ns Wake-Up Time (Power-Down) 25°C 375 375 μs Pipeline Latency Full 8 8 CLK

cycles

Aperture Delay (tA) 25°C 750 750 ps Aperture Uncertainty (Jitter) 25°C <1 <1 ps rms Out-of-Range Recovery Time 25°C 1 1 CLK

cycles

/20 is based on the number of bits divided by 2 because the delays are based on half duty cycles.

Rev. 0 | Page 6 of 56

AD9212

TIMING DIAGRAMS

N–1

AIN

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

D–

D+

t

A

N

t

FCO

PD

t

EH

t

CPD

t

FRAME

MSB

D8

N – 8

N – 8D7N – 8

D6

N – 8

t

D5

N – 8

EL

t

DATA

D4

N – 8

D3

N – 8

D2

N – 8

D1

N – 8

D0

N – 8

MSB N – 7

D8

N – 7D7N – 7

D6

N – 7

D5

N – 7

05968-003

Figure 2. 10-Bit Data Serial Stream (Default)

AIN

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

N-1

t

A

N

t

EH

t

CPD

t

FCO

t

D–

D+

PD

t

FRAME

MSB

D10

N – 8

N – 8D9(N – 8)D8N – 8D7N – 8D6N – 8D5N – 8D4N – 8D3N – 8D2N – 8D1N – 8D0N – 8

t

EL

t

DATA

D10

MSB

N – 7

05968-002

Figure 3.12-Bit Data Serial Stream

Rev. 0 | Page 7 of 56

AD9212

N–1

AIN

t

A

N

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

t

EH

t

CPD

t

FCO

t

PD

D–

D+

t

FRAME

LSB

N – 8D0N – 8D1N – 8D2N – 8D3N – 8D4N – 8D5N – 8D6N – 8D7N – 8D8N – 8

t

EL

t

DATA

LSB

N – 7D0N – 7

D1

N – 7

D2

N – 7

05968-004

Figure 4. 10-Bit Data Serial Stream, LSB First

Rev. 0 | Page 8 of 56

AD9212

ABSOLUTE MAXIMUM RATINGS

Table 5.

With

Parameter

ELECTRICAL

AVDD AGND −0.3 V to +2.0 V DRVDD DRGND −0.3 V to +2.0 V AGND DRGND −0.3 V to +0.3 V AVDD DRVDD −2.0 V to +2.0 V Digital Outputs

(D+, D−, DCO+,

DCO−, FCO+, FCO−) CLK+, CLK− AGND −0.3 V to +3.9 V VIN+, VIN− AGND −0.3 V to +2.0 V SDIO/ODM AGND −0.3 V to +2.0 V PDWN, SCLK/DTP, CSB AGND −0.3 V to +3.9 V REFT, REFB, RBIAS AGND −0.3 V to +2.0 V VREF, SENSE AGND −0.3 V to +2.0 V

ENVIRONMENTAL

Operating Temperature

Range (Ambient) Maximum Junction

Temperature Lead Temperature

(Soldering, 10 sec) Storage Temperature

Range (Ambient)

Respect To

DRGND −0.3 V to +2.0 V

−40°C to +85°C

150°C

300°C

−65°C to +150°C

Rating

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL IMPEDANCE

Table 6.

Air Flow Velocity (m/s)

0.0 17.7°C/W

1.0 15.5°C/W 8.7°C/W 0.6°C/W

2.5 13.9°C/W

1

θ

for a 4-layer PCB with solid ground plane (simulated). Exposed pad

JA

soldered to PCB.

1

θ

JA

θ

JB

θ

JC

ESD CAUTION

Rev. 0 | Page 9 of 56

AD9212

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VIN+F

VIN–F

AVD D

VIN–E

VIN+E

AVD D

REFT

REFB

VREF

SENSE

RBIAS

VIN+D

VIN–D

AVD D

VIN–C

VIN+C

49

48

AVD D

47

VIN+B

46

VIN–B

45

AVD D

44

VIN–A

43

VIN+A

42

AVD D

41

PDWN

40

CSB

39

SDIO/ODM

38

SCLK/DTP

37

AVD D

36

DRGND

35

DRVDD

34

D+A

33

D–A

AVD D VIN+G VIN–G

AVD D VIN–H VIN+H

AVD D

CLK–

CLK+

AVD D

DRGND

DRVDD

D–H D+H

646362616059585756555453525150

PIN 1 INDICATOR

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

EXPOSED PADDLE, PIN 0 (BOTTO M OF PACKAGE)

AD9212

TOP VIEW

(Not to Scale)

171819202122232425262728293031

D–F

D+F

D–E

D–G

D+E

D+G

D–D

FCO–

FCO+

DCO–

DCO+

32

D–C

D–B

D+D

D+C

D+B

Figure 5. 64-Lead LFCSP Top View

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

0 AGND Analog Ground (Exposed Paddle) 1, 4, 7, 8, 11,

AVDD 1.8 V Analog Supply 12, 37, 42, 45, 48, 51, 59, 62

13, 36 DRGND Digital Output Driver Ground 14, 35 DRVDD 1.8 V Digital Output Driver Supply 2 VIN+G ADC G Analog Input—True 3 VIN−G ADC G Analog Input—Complement 5 VIN−H ADC H Analog Input—Complement 6 VIN+H ADC H Analog Input—True 9 CLK− Input Clock—Complement 10 CLK+ Input Clock—True 15 D−H ADC H Digital Output—Complement 16 D+H ADC H True Digital Output—True 17 D−G ADC G Digital Output—Complement 18 D+G ADC G True Digital Output—True 19 D−F ADC F Digital Output—Complement 20 D+F ADC F True Digital Output—True 21 D−E ADC E Digital Output—Complement 22 D+E ADC E True Digital Output—True 23 DCO− Data Clock Digital Output—Complement 24 DCO+ Data Clock Digital Output—True 25 FCO− Frame Clock Digital Output—Complement 26 FCO+ Frame Clock Digital Output—True 27 D−D ADC D Digital Output—Complement 28 D+D ADC D True Digital Output—True 29 D−C ADC C Digital Output—Complement 30 D+C ADC C True Digital Output—True 31 D−B ADC B Digital Output—Complement 32 D+B ADC B True Digital Output—True

05968-005

Rev. 0 | Page 10 of 56

AD9212

Pin No. Mnemonic Description

33 D−A ADC A Digital Output—Complement 34 D+A ADC A True Digital Output—True 38 SCLK/DTP Serial Clock/Digital Test Pattern 39 SDIO/ODM Serial Data Input-Output/Output Driver Mode 40 CSB Chip Select Bar 41 PDWN Power Down 43 VIN+A ADC A Analog Input—True 44 VIN−A ADC A Analog Input—Complement 46 VIN−B ADC B Analog Input—Complement 47 VIN+B ADC B Analog Input—True 49 VIN+C ADC C Analog Input—True 50 VIN−C ADC C Analog Input—Complement 52 VIN−D ADC D Analog Input—Complement 53 VIN+D ADC D Analog Input—True 54 RBIAS External Resistor to Set the Internal ADC Core Bias Current 55 SENSE Reference Mode Selection 56 VREF Voltage Reference Input/Output 57 REFB Differential Reference (Negative) 58 REFT Differential Reference (Positive) 60 VIN+E ADC E Analog Input—True 61 VIN−E ADC E Analog Input—Complement 63 VIN−F ADC F Analog Input—Complement 64 VIN+F ADC F Analog Input—True

Rev. 0 | Page 11 of 56

AD9212

S

EQUIVALENT CIRCUITS

DRVDD

VIN

Figure 6. Equivalent Analog Input Circuit

CLK

10

10k

1.25V

10k

10

V

D– D+

V

05968-006

DRGND

V

5968-009

Figure 9. Equivalent Digital Output Circuit

SCLK/DTP OR PDWN

1k

30k

Figure 7. Equivalent Clock Input Circuit

DIO/ODM

350

30k

Figure 8. Equivalent SDIO/ODM Input Circuit

05968-007

05968-010

Figure 10. Equivalent SCLK/DTP or PDWN Input Circuit

RBIAS

05968-008

100

05968-011

Figure 11. Equivalent RBIAS Circuit

Rev. 0 | Page 12 of 56

AD9212

A

V

DD

70k

CSB

Figure 12. Equivalent CSB Input Circuit

1k

VREF

6k

05968-012

5968-014

Figure 14. Equivalent VREF Circuit

SENSE

1k

05968-013

Figure 13. Equivalent SENSE Circuit

Rev. 0 | Page 13 of 56

AD9212

TYPICAL PERFORMANCE CHARACTERISTICS

0

AIN = –0.5dBFS SNR = 60.41dB ENOB = 9.7 SFDR = 76.11dBc

–20

0

AIN = –0.5dBFS SNR = 60.08dB ENOB = 9.61 SFDR = 71.68dBc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 5 10 15 20 25 30

Figure 15. Single-Tone 32k FFT with f

0

AIN = –0.5dBF S SNR = 61.17dB ENOB = 9.85 SFDR = 81.27dBc

–20

–40

–60

–80

AMPLI TUDE (d BFS)

–100

FREQUENCY (MHz)

IN

= 2.3 MHz, AD9212-40

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

0 5 10 15 20 25 30

05968-037

Figure 18. Single-Tone 32k FFT with f

0

–20

–40

–60

–80

AMPLI TUDE (d BFS)

–100

FREQUENCY (MHz)

IN

= 35 MHz, AD9212-65

AIN = –0.5dBFS SNR = 60.25dB ENOB = 9.66 SFDR = 72.45dBc

05968-040

–120

0

2 6 10 14 184 8 12 16 20

Figure 16. Single-Tone 32k FFT with f

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 5 10 15 20 25 30

Figure 17. Single-Tone 32k FFT with f

FREQUENCY (MHz)

= 19.7 MHz, AD9212-40

IN

FREQUENCY (MHz)

IN

AIN = –0.5dBF S SNR = 60.48dB ENOB = 9.72 SFDR = 76.84d Bc

= 2.3 MHz, AD9212-65

05968-038

05968-039

Rev. 0 | Page 14 of 56

–120

0 5 10 15 20 25 30

Figure 19. Single-Tone 32k FFT with f

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 5 10 15 20 25 30

Figure 20. Single-Tone 32k FFT with f

FREQUENCY (MHz)

IN

FREQUENCY (MHz)

= 120 MHz, AD9212-65

IN

= 70 MHz, AD9212-65

AIN = –0.5dBFS SNR = 60.08dB ENOB = 9.61 SFDR = 71.68dBc

05968-041

05968-042

AD9212

90

85

80

75

70

65

SNR/SF DR (dB)

60

55

50

10 40

Figure 21. SNR/SFDR vs. f

90

85

80

75

70

65

SNR/SFDR (dB)

60

55

50

10 40

Figure 22. SNR/SFDR vs. f

SFDR

SNR

ENCODE (MSPS)

, fIN = 10.3 MHz, AD9212-40

SAMPLE

SFDR

SNR

ENCODE (MSPS)

, fIN = 19.7 MHz, AD9212-40

SAMPLE

3530252015

05968-043

3530252015

05968-044

90

85

80

75

70

65

SNR/SFDR (dB)

60

55

50

10

Figure 24. SNR/SFDR vs. f

100

90

80

70

60

50

40

SNR/SFDR (dB)

30

20

10

0

–60 –50 –40 –30 –20 –10 0

Figure 25. SNR/SFDR vs. Analog Input Level, f

SFDR

SNR

ENCODE (MSPS)

, fIN = 35 MHz, AD9212-65

SAMPLE

SFDR

70dB REFERENCE

SNR

ANALOG INP UT LEVEL (dBFS)

= 10.3 MHz, AD9212-40

IN

6050403020

5968-046

05968-047

90

85

80

75

70

65

SNR/SFDR (dB)

60

55

50

10

Figure 23. SNR/SFDR vs. f

SFDR

SNR

ENCODE (MSPS)

, fIN = 10.3 MHz, AD9212-65

SAMPLE

100

90

80

70

60

50

40

SNR/SFDR (dB)

30

20

10

0

6050403020

05968-045

–60 –50 –40 –30 –20 –10 0

Figure 26. SNR/SFDR vs. Analog Input Level, f

SFDR

70dB REF ERENCE

SNR

ANALOG INPUT LEVEL (dBFS)

= 35 MHz, AD9212-40

IN

05968-048

Rev. 0 | Page 15 of 56

AD9212

100

90

80

70

60

50

40

SNR/SFDR (dB)

30

20

10

0

–60 –50 –40 –30 –20 –10 0

Figure 27. SNR/SFDR vs. Analog Input Level, f

SFDR

70dB REFERENCE

SNR

ANALOG INPUT LEVEL (dBFS)

= 10.3 MHz, AD9212-65

IN

05968-049

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0

24681012 14 16 18 20

FREQUENCY (MHz )

Figure 30. Two-Tone 32k FFT with f

AD9212-40

AIN1 AND AIN2 = –7dBFS SFDR = 76.7d B IMD2 = 83.38d Bc IMD3 = 77.21d Bc

= 70 MHz and f

IN1

= 71 MHz,

IN2

05968-052

100

90

80

70

60

50

40

SNR/SFDR (dB)

30

20

10

0

–60 –50 –40 –30 –20 –10 0

Figure 28. SNR/SFDR vs. Analog Input Level, f

0

AIN1 AND AIN2 = –7dBFS SFDR = 84.8dB IMD2 = 83.66dBc IMD3 = 84.6dBc

–20

–40

SFDR

70dB REFERENCE

SNR

ANALOG INPUT LEVEL (dBFS)

= 35 MHz, AD9212-65

IN

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

05968-050

0 5 10 15 20 25 30

FREQUENCY (MHz)

Figure 31. Two-Tone 32k FFT with f

= 16 MHz, AD9212-65

f

IN2

0

–20

–40

AIN1 AND AIN2 = –7dBFS SFDR = 77.4dB IMD2 = 77.92dBc IMD3 = 76.9dBc

= 15 MHz and

IN1

AIN1 AND AIN2 = –7dBFS SFDR = 72.5dB IMD2 = 77.14dBc IMD3 = 72.55dBc

5968-053

–60

–80

AMPLITUDE (dBFS)

–100

–120

0

24681012 14 16 18 20

FREQUENCY (MHz )

Figure 29. Two-Tone 32k FFT with f

AD9212-40

= 15 MHz and f

IN1

= 16 MHz,

IN2

5968-051

Rev. 0 | Page 16 of 56

–60

–80

AMPLITUDE (dBFS)

–100

–120

0 5 10 15 20 25 30

Figure 32. Two-Tone 32k FFT with f

FREQUENCY (MHz )

= 71 MHz, AD9212- 65

f

IN2

= 70 MHz and

IN1

5968-054

AD9212

–

80

75

SFDR

70

65

SNR/SFDR (dB)

60

55

50

1 10 100 1 000

Figure 33. SNR/SFDR vs. f

SNR

ANALOG INPUT FREQUENCY ( MHz)

, AD9212-65

IN

05968-055

0.5

0.4

0.3

0.2

0.1

0

INL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0

Figure 36. INL, f

CODE

= 2.3 MHz, AD9212-65

IN

1000200 400 600 800

05968-058

90

85

80

75

70

65

SINAD/SFDR (d B)

60

55

50

–40 –20 0 20 40 60 80

TEMPERATURE (°C)

Figure 34. SINAD/SFDR vs. Temperature, f

90

85

80

75

70

65

SINAD/SFDR (d B)

60

55

50

–40 –20 0 20 40 60 80

SFDR

SINAD

TEMPERATURE (°C)

SFDR

SINAD

= 10.3 MHz, AD9212-40

IN

Figure 35. SINAD/SFDR vs. Temperature, fIN = 10.3 MHz, AD9212-65

0.5

0.4

0.3

0.2

0.1

0

DNL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

05968-056

05968-057

0

CODE

Figure 37. DNL, f

30

–35

–40

–45

–50

CMRR (dB)

–55

–60

–65

–70

0 5 10 15 20 25 30 35 40

= 2.3 MHz, AD9212-65

IN

FREQUENCY (MHz)

1000200 400 600 800

05968-060

05968-061

Figure 38. CMRR vs. Frequency, AD9212-65

Rev. 0 | Page 17 of 56

AD9212

2.5

2.0

1.5

1.0

NUMBER OF HITS (Millions)

0.5

0

N – 3 N – 2 N – 1 N N +1 N + 2 N + 3

CODE

Figure 39. Input-Referred Noise Histogram, AD9212-65

0.096 LSB rms

05968-062

0

–1

–2

–3

–4

–5

–6

–7

AMPLITUDE ( dBFS)

–8

–9

–10

–11

0 50045040035030025020015010050

FREQUENCY (MHz)

–3dB BANDWIDTH = 325MHz

Figure 41. Full Power Bandwidth vs. Frequency, AD9212-65

05968-064

0

NPR = 51.13dB NOTCH = 18.0MHz NOTCH WIDT H = 3.0MHz

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0

5101520 25

FREQUENCY (MHz)

05968-063

Figure 40. Noise Power Ratio (NPR), AD9212- 65

Rev. 0 | Page 18 of 56

AD9212

V

THEORY OF OPERATION

The AD9212 architecture consists of a pipelined ADC that is divided into three sections: a 4-bit first stage followed by eight

1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a final 10- result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC.

The output staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The data is then serialized and aligned to the frame and output clock.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9212 is a differential switched-capacitor circuit designed for processing differential input signals. The input can support a wide common-mode range and maintain excellent performance. An input common-mode voltage of midsupply minimizes signal-dependent errors and provides optimum performance.

The clock signal alternately switches the input circuit between sample mode and hold mode (see Figure 42). When the input circuit is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. In addition, low-Q inductors or ferrite beads can be placed on each leg of the input to reduce the high differential capacitance seen at the analog inputs, thus realizing the maximum bandwidth of the ADC. Such use of low-Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit any unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article “Transformer-Coupled Front-End for Wideband A/D Converters” for more information on this subject. In general, the precise values depend on the application.

The analog inputs of the AD9212 are not internally dc-biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that V

= AV D D /2 is recom-

CM

mended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 45 and Figure 46.

H

C

PAR

IN+

VIN–

C

PAR

Figure 42. Switched-Capacitor Input Circuit

C

SAMPLE

SS

C

SAMPLE

H

5968-017

Rev. 0 | Page 19 of 56

AD9212

90

85

80

75

70

65

SNR/SF DR (dB)

60

55

50

0.3

SFDR (dBc)

SNR (dB)

0.6 0.9 1.2 1.5

ANALOG INPUT COMMON-MO DE VOLTAG E (V)

Figure 43. SNR/SFDR vs. Common-Mode Voltage,

f

= 2.3 MHz, AD9212-40

IN

90

85

80

75

70

SFDR (dBc)

85

80

75

70

65

SNR/SFDR (dB)

60

55

50

0.3

05968-065

SFDR

SNR

0.6 0.9 1.2 1.5

ANALOG INPUT COMMON-MO DE VOLTAG E (V)

05968-067

Figure 45. SNR/SFDR vs. Common-Mode Voltage,

f

= 2.3 MHz, AD9212-65

IN

90

85

80

75

70

SFDR

65

SNR/SFDR (dB)

60

55

50

0.3

SNR (dB)

0.6 0.9 1.2 1.5

ANALOG INPUT COMMON MODE VOLTAG E (V)

Figure 44. SNR/SFDR vs. Common-Mode Voltage,

= 19.7 MHz, AD9212-40

f

IN

5968-066

65

SNR/SF DR (dB)

60

55

50

0.3

0.6 0.9 1.2 1.5

ANALOG INPUT COMMON MODE VOLTAG E (V)

SNR

Figure 46. SNR/SFDR vs. Common-Mode Voltage,

= 35 MHz, AD9212-65

f

IN

05968-068

Rev. 0 | Page 20 of 56

AD9212

A

V

F

p

For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates the positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as

REFT = 1/2 (AVDD + VREF) REFB = 1/2 (AVDD − VREF) Span = 2 × (REFT − REFB) = 2 × VREF

It can be seen from these equations that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage.

Maximum SNR performance is always achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9212, the largest input span available is 2 V p-p.

Differential Input Configurations

There are several ways in which to drive the AD9212 either actively or passively. In either case, the optimum performance is achieved by driving the analog input differentially. One example is by using the AD8334 differential driver. It provides excellent performance and a flexible interface to the ADC (see Figure 50) for baseband applications. This configuration is common for medical ultrasound systems.

However, the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9212. For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. Two examples are shown in Figure 47 and Figure 48.

In any configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed.

DT1–1WT

2V p-p

1

C

DIFF

1:1 Z RATIO

49.9

AVD D

1k

0.1F

IS OPTIONAL.

C

R

1

C

DIFF

R

C

VIN+

VIN–

ADC

AD9212

AGND

05968-018

Figure 47. Differential Transformer-Coupled Configuration

for Baseband Applications

2V p-p

16nH

65

0.1F

1k

1:1 Z RATIO

AVD D

DT1–1WT

499

0.1F

16nH

33

2.2pF

33

1k

VIN+

ADC

AD9212

VIN–

Figure 48. Differential Transformer-Coupled Configuration for IF Applications

Single-Ended Input Configuration

A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input commonmode swing. If the application requires a single-ended input configuration, ensure that the source impedances on each input are well matched in order to achieve the best possible performance. A full-scale input of 2 V p-p can still be applied to the ADC’s VIN+ pin while the VIN− pin is terminated. Figure 49 details a typical single-ended input configuration.

DD

C

2V p-p

49.9

0.1µF

AVD D

1k

25

R

1

C

DIFF

R

C

VIN+

VIN–

ADC

AD9212

05968-019

1

C

IS OPTIONAL.

DIFF

05968-020

Figure 49. Single-Ended Input Configuration

0.1

0.1F

VIP

VIN

VGA

VOH

VOL

187

374

187

0.1F

1.0k

0.1F

0.1F10F

R

C

R

VIN+

AD9212

VIN–

ADC

VREF

05968-021

1V p-

0.1F

120nH

0.1F

22pF

LOP

18nF

INH

LMD

274

AD8334

LNA

LON

Figure 50. Differential Input Configuration Using the AD8334

Rev. 0 | Page 21 of 56

AD9212

A

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9212 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional bias.

Figure 51 shows one preferred method for clocking the AD9212. The low jitter clock source is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9212 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9212 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance.

MINI-CIRCUITS

ADT1–1WT, 1:1Z

CLOCK

INPUT

50

100

Figure 51. Transformer-Coupled Differential Clock

If a low jitter clock is available, another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 52. The AD9510/AD9511/AD9512/AD9513/AD9514/ AD9515 family of clock drivers offers excellent jitter performance.

CLOCK

INPU T

CLOCK

INPU T

50

1

50 RESISTORS ARE OPT IONAL .

CLOCK

INPU T

CLOCK

INPU T

50

1

50 RESISTORS ARE OPTI ONAL.

0.1µF

CLK

PECL DRIVER

0.1µF

50

CLK

1

Figure 52. Differential PECL Sample Clock

0.1µF

CLK

LVDS DRIVER

0.1µF

50

CLK

1

Figure 53. Differential LVDS Sample Clock

0.1µF0.1µF

XFMR

0.1µF

AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515

AD9510/AD9511/ AD9512/AD9513/ AD9514/AD95 15

SCHOTTKY

DIODES:

HSM2812

240240

0.1µF

100

0.1µF

100

0.1µF

CLK+

ADC

AD9212

CLK–

CLK+

ADC

AD9212

CLK–

CLK+

ADC

AD9212

CLK–

05968-022

05968-023

05968-024

In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be directly driven from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 F capacitor in parallel with a 39 kΩ resistor (see Figure 54). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages up to 3.3 V, making the selection of the drive logic voltage very flexible.

D9510/AD9511/ AD9512/AD9513/ AD9514/AD9515

CLK

CMOS DRIVER

CLK

0.1µF

OPTIONA L

100

39k

0.1µF

CLK+

ADC

AD9212

CLK–

50

0.1µF

1

0.1µF

CLOCK

INPU T

1

50 RESISTOR IS OPTIONAL.

Figure 54. Single-Ended 1.8 V CMOS Sample Clock

D9510/AD9511/ AD9512/AD9513/ AD9514/AD9515

CLK

CMOS DRIVER

CLK

OPTION AL

100

0.1µF

CLK+

ADC

AD9212

CLK–

50

0.1µF

1

0.1µF

CLOCK

INPU T

1

50 RESISTOR IS OPTIONAL.

Figure 55. Single-Ended 3.3 V CMOS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9212 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9212. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the Memory Map section for more details on using this feature.

The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate.

05968-025

05968-026

Rev. 0 | Page 22 of 56

AD9212

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (f

) due only to aperture jitter (tJ) can be calculated by

A

SNR degradation = 20 × log 10 [1/2 × π × f

× tJ]

A

In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 56).

The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9212. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.

Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs (visit

130

RMS CLO CK JITT ER REQ UIREME NT

120

110

100

90

80

SNR (dB)

70

10 BITS

60

8 BITS

50

40

30

1 10 100 1000

ANALOG INPUT FREQUENCY (MHz)

Figure 56. Ideal SNR vs. Input Frequency and Jitter

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

www.analog.com).

16 BITS

14 BITS

12 BITS

05968-015

Power Dissipation and Power-Down Mode

As shown in Figure 57 and Figure 58, the power dissipated by the AD9212 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers.

0.30

0.25

0.20

0.15

CURRENT (A)

0.10

0.05

0

10 15 20 25 30 35 40

Figure 57. Supply Current vs. f

0.40

0.35

0.30

0.25

0.20

CURRENT (A)

0.15

0.10

0.05

0

10 20 30 40 50 60

Figure 58. Supply Current vs. f

AVDD CURRENT

TOTAL POWER

DRVDD CURRENT

ENCODE (MHz)

AVDD CURRENT

TOTAL POWER

DRVDD CURRENT

ENCODE (MHz)

for fIN = 10.3 MHz, AD9212-40

SAMPLE

for fIN = 10.3 MHz, AD9212-65

SAMPLE

0.60

0.58

0.56

0.54

0.52

0.50

0.48

0.46

0.44

0.42

0.40

0.90

0.85

0.80

0.75

0.70

0.65

0.60

0.55

0.50

POWER (W)

05968-089

05968-090

Rev. 0 | Page 23 of 56

AD9212

By asserting the PDWN pin high, the AD9212 is placed in power-down mode. In this state, the ADC typically dissipates 11 mW. During power-down, the LVDS output drivers are placed in a high impedance state. The AD9212 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant.

In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode; shorter cycles result in proportionally shorter wake-up times. With the recommended 0.1 µF and 4.7 µF decoupling capacitors on REFT and REFB, it takes approximately 1 sec to fully discharge the reference buffer decoupling capacitors and 375 µs to restore full operation.

There are a number of other power-down options available when using the SPI port interface. The user can individually power down each channel or put the entire device into standby mode. This allows the user to keep the internal PLL powered when fast wake-up times (~600 ns) are required. See the Memory Map section for more details on using these features.

Digital Outputs and Timing

The AD9212 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option similar to the IEEE 1596.3 standard using the SDIO/ODM pin or via the SPI. This LVDS standard can further reduce the overall power dissipation of the device by approximately 36 mW. See the SDIO/ODM Pin section or Table 15 in the Memory Map section for more information. The LVDS driver current is derived on-chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver.

The AD9212 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a

100 Ω termination resistor placed as close to the receiver as possible. No far-end receiver termination and poor differential trace routing may result in timing errors. It is recommended that the trace length is no longer than 24 inches and that the differential output traces are kept close together and at equal lengths. An example of the FCO and data stream with proper trace length and position can be found in Figure 59.

CH1 500mV/DIV = FCO CH2 500mV/DIV = DCO CH3 500mV/DIV = DATA

Figure 59. LVDS Output Timing Example in ANSI Mode (Default)

05968-027

An example of the LVDS output using the ANSI standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on regular FR-4 material is shown in Figure 60. Figure 61 shows an example of when the trace lengths exceed 24 inches on regular FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. It is up to the user to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Additional SPI options allow the user to further increase the internal termination (increasing the current) of all eight outputs in order to drive longer trace lengths (see Figure 62). Even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the DRVDD supply increases when this option is used. Also notice in Figure 62 that the histogram has improved.

In cases that require increased driver strength to the DCO and FCO outputs because of load mismatch, Register 15 allows the user to increase the drive strength by 2×. To do this, set the appropriate bit in Register 5. Note that this feature cannot be used with Bit 4 and Bit 5 in Register 15. Bit 4 and Bit 5 will take precedence over this feature. See the Memory Map section for more details.

Rev. 0 | Page 24 of 56

AD9212

500

EYE: ALL BI TS ULS: 12071/12071

400

300

200

100

0

–100

–200

–300

EYE DIAGRAM VOLTAGE (mV)

–400

–500

–1.0ns–1.5n s –0.5ns 0ns 0.5ns 1.0n s 1.5ns

400

EYE: ALL BITS

300

200

100

0

–100

–200

EYE DIAGRA M VOLT AGE (mV)

–300

–400

–0.5ns 0ns 0. 5ns

–1.0ns 1.5ns–1.5ns 1.0ns

ULS: 12072/12072

90

80

70

60

50

40

30

20

TIE JIT TER HIST OGRAM (Hi ts)

10

0

–150ps –100ps –50ps 0ps 50ps 100ps 150ps

05968-030

Figure 60. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less

than 24 Inches on Standard FR-4

500

EYE: ALL BITS

400

300

200

100

0

–100

–200

–300

EYE DIAGRAM VOLTAG E (mV)

–400

–500

–1.0ns –0.5ns 0ns 0.5ns 1.5ns–1.5ns 1.0ns

100

90

80

70

60

50

40

30

TIE JITTER HISTO GRAM (Hits)

20

10

0

–200ps –100ps 100ps0ps 200ps

ULS: 12067/12067

5968-028

Figure 61. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths

Greater than 24 Inches on Standard FR-4

80

70

60

50

40

30

20

TIE JIT TER HIST OGRAM (Hi ts)

10

0

Figure 62. Data Eye for LVDS Outputs in ANSI Mode with 100 Ω Termination

–150ps –100ps –50ps 0ps 50ps 100ps 150ps

05968-029

on and Trace Lengths Greater than 24 Inches on Standard FR-4

The format of the output data is offset binary by default. An example of the output coding format can be found in Table 8. If it is desired to change the output data format to twos complement, see the Memory Map section.

Table 8. Digital Output Coding

(VIN+) − (VIN−), Input Span = 2 V p-p (V)

Code

1023 +1.00 11 1111 1111 512 0.00 10 0000 0000 511 −0.001953 01 1111 1111 0 −1.00 00 0000 0000

Digital Output Offset Binary (D9 ... D0)

Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 10 bits times the sample clock rate, with a maximum of 650 Mbps (10 bits × 65 MSPS = 650 Mbps). The lowest typical conversion rate is 10 MSPS. However, if lower sample rates are required for a specific application, the PLL can be set up for encode rates lower than 10 MSPS via the SPI. This allows encode rates as low as 5 MSPS. See the Memory Map section to enable this feature.

Rev. 0 | Page 25 of 56

AD9212

Two output clocks are provided to assist in capturing data from the AD9212. The DCO is used to clock the output data and is equal to five times the sampling clock (CLK) rate. Data is clocked out of the AD9212 and must be captured on the rising and falling edges of the DCO that supports double data rate

Table 9. Flex Output Test Modes

Output Test Mode Bit Sequence

Pattern Name Digital Output Word 1 Digital Output Word 2

0000 Off (default) N/A N/A N/A 0001 Midscale short

1000 0000 (8-bit) 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit)

0010 +Full-scale short

1111 1111 (8-bit) 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit)

0011 −Full-scale short

0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit)

0100 Checker board

1010 1010 (8-bit) 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit)

0101 PN sequence long

1

N/A N/A Yes 0110 PN sequence short1 N/A N/A Yes 0111 One/zero word toggle

1111 1111 (8-bit)

11 1111 1111 (10-bit)

1111 1111 1111 (12-bit)

11 1111 1111 1111 (14-bit) 1000 User input Register 0x19 to Register 0x1A Register 0x1B to Register 0x1C No 1001 One/zero bit toggle

1010 1010 (8-bit)

10 1010 1010 (10-bit)

1010 1010 1010 (12-bit)

10 1010 1010 1010 (14-bit) 1010 1× sync

0000 1111 (8-bit)

00 0001 1111 (10-bit)

0000 0011 1111 (12-bit)

00 0000 0111 1111 (14-bit) 1011 One bit high

1000 0000 (8-bit)

10 0000 0000 (10-bit)

1000 0000 0000 (12-bit)

10 0000 0000 0000 (14-bit) 1100 Mixed frequency

1010 0011 (8-bit)

10 0110 0011 (10-bit)

1010 0011 0011 (12-bit)

10 1000 0110 0111 (14-bit)

1

PN, or pseudorandom number, sequence is determined by the number of bits in the shift register. The long sequence is 23 bits and the short sequence is

9 bits. How the sequence is generated and utilized is described in the ITU O.150 standard. In general, the polynomial, X23 + X18 + 1 (long) and X9 + X5 + 1 (short), defines the pseudorandom sequence.

(DDR) capturing. The frame clock out (FCO) is used to signal the start of a new output byte and is equal to the sampling clock rate. See the timing diagram shown in Figure 2 for more information.

Subject to Data Format Select

Same Yes

0101 0101 (8-bit)

No 01 0101 0101 (10-bit) 0101 0101 0101 (12-bit) 01 0101 0101 0101 (14-bit)

0000 0000 (8-bit)

No 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit)

N/A No

Rev. 0 | Page 26 of 56

AD9212

When using the serial port interface (SPI), the DCO phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO timing, as shown in Figure 2, is 90° relative to the output data edge.

An 8-, 12-, and 14-bit serial stream can also be initiated from the SPI. This allows the user to implement and test compatibility to lower and higher resolution systems. When changing the resolution to a 12-bit serial stream, the data stream is lengthened. See Figure 3 for the 12-bit example. However, when using the 12-bit option, the data stream stuffs two 0s at the end of the normal 12-bit serial data.

When using the SPI, all of the data outputs can also be inverted from their nominal state. This is not to be confused with inverting the serial stream to an LSB-first mode. In default mode, as shown in Figure 2, the MSB is represented first in the data output serial stream. However, this can be inverted so that the LSB is represented first in the data output serial stream (see Figure 4).

There are 12 digital output test pattern options available that can be initiated through the SPI. This is a useful feature when validating receiver capture and timing. Refer to Table 9 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. It should be noted that some patterns may not adhere to the data format select option. In addition, customer user patterns can be assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode options can support 8- to 14-bit word lengths in order to verify data capture to the receiver.

Please consult the Memory Map section for information on how to change these additional digital output timing features through the serial port interface or SPI.

SDIO/ODM Pin

This pin is for applications that do not require SPI mode operation. The SDIO/ODM pin can enable a low power, reduced signal option similar to the IEEE 1596.3 reduced range link output standard if this pin and the CSB pin are tied to AVDD during device powerup. This option should only be used when the digital output trace lengths are less than 2 inches from the LVDS receiver. The FCO, DCO, and outputs function normally, but the LVDS signal swing of all channels is reduced from 350 mV p-p to 200 mV p-p. This output mode allows the user to further lower the power on the DRVDD supply. For applications where this pin is not used, it should be tied low. In this case, the device pin can be left open, and the 30 kΩ internal pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant. If applications require this pin to be driven from a 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to limit the current.

Table 10. Output Driver Mode Pin Settings

Resulting

Selected ODM ODM Voltage

Normal

Operation

ODM AVDD Low power,

10 kΩ to AGND ANSI-644

Output Standard

(default)

reduced signal option

Resulting FCO and DCO

ANSI-644 (default)

Low power, reduced signal option

SCLK/DTP Pin

This pin is for applications that do not require SPI mode operation. The serial clock/digital test pattern (SCLK/DTP) pin can enable a single digital test pattern if this pin and the CSB pin are held high during device power-up. When the DTP is tied to AVDD, all the ADC channel outputs shift out the following pattern: 10 0000 0000. The FCO and DCO outputs still work as usual while all channels shift out the repeatable test pattern. This pattern allows the user to perform timing alignment adjustments among the FCO, DCO, and output data. For normal operation, this pin should be tied to AGND through a 10 kΩ resistor. This pin is both 1.8 V and 3.3 V tolerant.

Table 11. Digital Test Pattern Pin Settings

Resulting

Selected DTP DTP Voltage

Normal

Operation

DTP AVDD 10 0000 0000 Normal operation

10 kΩ to AGND Normal

D+ and D−

operation

Resulting FCO and DCO

Normal operation

Additional and custom test patterns can also be observed when commanded from the SPI port. Consult the Memory Map section to choose from the different options available.

CSB Pin

The chip select bar (CSB) pin should be tied to AVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. This pin is both 1.8 V and 3.3 V tolerant.

RBIAS Pin

To set the internal core bias current of the ADC, place a resistor (nominally equal to 10.0 kΩ) to ground at the RBIAS pin. The resistor current is derived on-chip and sets the ADC’s AVDD current to a nominal 390 mA at 65 MSPS. Therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance. If SFDR performance is not as critical as power, simply adjust the ADC core current to achieve a lower power. Figure 63 and Figure 64 show the relationship between the dynamic range and power as the RBIAS resistance is changed. Nominally, a 10.0 kΩ value is used, as indicated by the dashed line.

Rev. 0 | Page 27 of 56

AD9212

90

80

SFDR

70

60

SNR/SFDR (dB)

50

SNR

0.8

0.7

0.6

0.5

0.4

IAVDD (A)

0.3

0.2

0.1

40

0

510 2015 25

RBIAS (k)

05968-069

Figure 63. SNR/SFDR vs. RBIAS, AD9212-40

0.8

0.7

0.6

0.5

0.4

IAVDD (A)

0.3

0.2

0.1

0

510 2015 25

RBIAS (k)

05968-070

Figure 64. IAVDD vs. RBIAS, AD9212-40

90

80

70

SFDR

0

510 2015 25

RBIAS (k)

05968-085

Figure 66. IAVDD vs. RBIAS, AD9212-65

Voltage Reference

A stable and accurate 0.5 V voltage reference is built into the AD9212. This is gained up by a factor of 2 internally, setting V

to 1.0 V, which results in a full-scale differential input span

REF

of 2 V p-p. The V

is set internally by default; however, the

REF

VREF pin can be driven externally with a 1.0 V reference to achieve more accuracy.

When applying the decoupling capacitors to the VREF, REFT, and REFB pins, use ceramic low ESR capacitors. These capacitors should be close to the ADC pins and on the same layer of the PCB as the AD9212. The recommended capacitor values and configurations for the AD9212 reference pin can be found in Figure 67.

Table 12. Reference Settings

Resulting Selected Mode

External

Reference

Internal,

2 V p-p FSR

SENSE Voltage

Resulting VREF (V)

AVDD N/A 2 × external

AGND to 0.2 V 1.0 2.0

Differential

Span (V p-p)

reference

60

SNR/SFDR (dB)

SNR

Internal Reference Operation

A comparator within the AD9212 detects the potential at the

50

SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal

40

0

510 2015 25

RBIAS (k)

05968-084

Figure 65. SNR/SFDR vs. RBIAS, AD9212-65

resistor divider (see Figure 67), setting VREF to 1 V.

The REFT and REFB pins establish their input span of the ADC core from the reference configuration. The analog input fullscale range of the ADC equals twice the voltage at the reference pin for either an internal or an external reference configuration.

If the reference of the AD9212 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 69 depicts how the internal reference voltage is affected by loading.

Rev. 0 | Page 28 of 56

AD9212

External Reference Operation

The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 70 shows the typical drift characteristics of the internal reference in 1 V mode.

When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. The external reference is loaded with an equivalent 6 kΩ load. An internal reference buffer generates the positive and negative full-scale references, REFT and REFB, for the ADC core. Therefore, the external reference must be limited to a nominal of 1.0 V.

5

1µF 0.1µ F

SENSE

VIN+

VIN–

V

REF

SELECT

LOGIC

ADC

CORE

0.5V

REFT

0.1µF

0.1µF 2.2µF

REFB

0.1µF

+

EXTERNAL

REFERENCE

1

1µF

1

OPTIONAL.

Figure 67. Internal Reference Configuration

VIN+

VIN–

V

REF

1

0.1µF

AVD D

SENSE

SELECT

LOGIC

Figure 68. External Reference Operation

ADC

CORE

0.5V

REFT

0.1µF

0.1µF 2.2µF

REFB

0.1µF

05968-031

+

5968-032

0

–5

–10

ERROR (%)

–15

REF

V

–20

–25

–30

01.00.5 2.01.5 3.02.5 3.5

0.02

0

–0.02

–0.04

–0.06

–0.08

ERROR (%)

–0.10

REF

V

–0.12

–0.14

–0.16

–0.18

–40

–20 0 20406080

CURRENT LOAD (mA)

Figure 69. V

Accuracy vs. Load

REF

TEMPERATURE (° C)

Figure 70. Typical V

REF

Drift

05968-087

05968-088

Rev. 0 | Page 29 of 56

AD9212

SERIAL PORT INTERFACE (SPI)

The AD9212 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This gives the user added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided down into fields, as documented in the Memory Map section. Detailed operational information can be found in the Analog Devices, Inc., user manual Interfacing to High Speed ADCs via SPI.

There are three pins that define the serial port interface, or SPI, to this particular ADC. They are the SCLK, SDIO, and CSB pins. The SCLK (serial clock) is used to synchronize the read and write data presented to the ADC. The SDIO (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB (chip select bar) is an active low control that enables or disables the read and write cycles (see Table 13).

Table 13. Serial Port Pins

Pin Function

SCLK

SDIO

CSB

Serial Clock. The serial shift clock in. SCLK is used to synchronize serial interface reads and writes.

Serial Data Input/Output. A dual-purpose pin. The typical role for this pin is an input or output, depending on the instruction sent and the relative position in the timing frame. Chip Select Bar (Active Low). This control gates the read and write cycles.

The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Fields W0 and W1. An example of the serial timing and its definitions can be found in Figure 72 and Table 14. In normal operation, CSB is used to signal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to process instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until the CSB is taken high to end the communication cycle. This allows complete memory transfers without having to provide additional instructions. Regardless of the mode, if CSB is taken high in the

middle of any byte transfer, the SPI state machine is reset and the device waits for a new instruction.

In addition to the operation modes, the SPI port can be configured to operate in different manners. For applications that do not require a control port, the CSB line can be tied and held high. This places the remainder of the SPI pins in their secondary mode as defined in the Serial Port Interface (SPI) section. CSB can also be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during power-up, caution must be exercised when using this mode to ensure that the serial port remains synchronized with the CSB line. When operating in 2-wire mode, it is recommended to use a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB line, streaming mode can be entered but not exited.

In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame.

Data can be sent in MSB- or LSB-first mode. MSB-first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the user manual Interfacing to High Speed ADCs via SPI.

HARDWARE INTERFACE

The pins described in Table 13 compose the physical interface between the user’s programming device and the serial port of the AD9212. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback.

This interface is flexible enough to be controlled by either serial PROMS or PIC mirocontrollers. This provides the user an alternative method, other than a full SPI controller, to program the ADC (see the AN-812 Application Note).

If the user chooses not to use the SPI interface, these pins serve a dual function and are associated with secondary functions when the CSB is strapped to AVDD during device power-up. See the Theory of Operation section for details on which pinstrappable functions are supported on the SPI pins.

If multiple SDIO pins share a common connection, care should be taken to ensure that proper V load as the AD9212, Figure 71 shows the number of SDIO pins that can be connected together and the resulting V

levels are met. Assuming the same

OH

level.

OH

Rev. 0 | Page 30 of 56

AD9212

CSB

SCLK

DON’T CARE

1.800

1.795

1.790

1.785

1.780

1.775

1.770

1.765

1.760

OH

1.755

V

1.750

1.745

1.740

1.735

1.730

1.725

1.720

1.715 0302010 40 50 60 70 80 90 100

NUMBER OF SDI O PINS CONNECTED TOGETHER

05968-059

Figure 71. SDIO Pin Loading

t

DS

t

S

t

DH

t

HI

t

CLK

t

LO

t

H

DON’T CARE

SDIO

R/W W1 W0 A12 A11 A10 A9 A8 A7

Figure 72. Serial Timing Details

Table 14. Serial Timing Definitions

Parameter Timing (minimum, ns) Description

t

DS

t

DH

t

CLK

t

S

t

H

t

HI

t

LO

t

EN_SDIO

5 Set-up time between the data and the rising edge of SCLK 2 Hold time between the data and the rising edge of SCLK 40 Period of the clock 5 Set-up time between CSB and SCLK 2 Hold time between CSB and SCLK 16 Minimum period that SCLK should be in a logic high state 16 Minimum period that SCLK should be in a logic low state 1

Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 72)

t

DIS_SDIO

5

Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 72)

D5 D4 D3 D2 D1 D0

DON’T C AREDON’T CARE

05968-033

Rev. 0 | Page 31 of 56

AD9212

MEMORY MAP

READING THE MEMORY MAP TABLE

Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: chip configuration register map (Address 0x00 to Address 0x02), device index and transfer register map (Address 0x05 and Address 0xFF), and program register map (Address 0x08 to Address 0x25).

The left-hand column of the memory map indicates the register address number in hexadecimal. The default value of this address is shown in hexadecimal in the right-hand column. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Hexadecimal Address 0x09, Clock, has a hexadecimal default value of 0x01. This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 6 at this address, the duty cycle stabilizer turns off. For more information on this and other functions, consult the user manual Interfacing to High Speed ADCs via SPI.

RESERVED LOCATIONS

Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up.

DEFAULT VALUES

Coming out of reset, critical registers are preloaded with default values. These values are indicated in Table 15, where an X refers to an undefined feature.

LOGIC LEVELS

An explanation of various registers follows: “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.”

Rev. 0 | Page 32 of 56

AD9212

Table 15. Memory Map Register

Default Addr. (Hex)

Chip Configuration Registers

00 chip_port_config 0 LSB first

01 chip_id 10-bit Chip ID Bits 7:0

02 chip_grade X Child ID 6:4

Device Index and Transfer Registers

04 device_index_2 X X X X Data

05 device_index_1 X X Clock

FF device_update X X X X X X X SW

ADC Functions

08 modes X X X X X Internal power-down mode

09 clock X X X X X X X Duty

0D test_io User test mode

Parameter Name

Bit 7 (MSB)

00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

1 = on 0 = off (default)

(identify device variants of Chip ID) 000 = 65 MSPS 001 = 40 MSPS

Soft reset 1 = on 0 = off (default)

Channel DCO 1 = on 0 = off (default)

Reset PN long gen 1 = on 0 = off (default)

1 1 Soft

(AD9212 = 0x08), (default)

Clock Channel FCO 1 = on 0 = off (default)

Reset PN short gen 1 = on 0 = off (default)

Bit 0 (LSB)

LSB first reset 1 = on 0 = off (default)

X X X X Read

Data

Channel H

1 = on (default) 0 = off

Data Channel D 1 = on (default) 0 = off

Output test mode—see Table 9 in the Digital Outputs and Timing section 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checker board output 0101 = PN 23 sequence 0110 = PN 9 0111 = one/zero word toggle 1000 = user input 1001 = one/zero bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode)

Channel G 1 = on (default) 0 = off

Data Channel C 1 = on (default) 0 = off

000 = chip run (default) 001 = full power-down 010 = standby 011 = reset

1 = on

0 = off

(default)

Data

Channel

F

1 = on

(default)

0 = off

Data

Channel

B

1 = on

(default)

0 = off

0 0x18 The nibbles

Data Channel E 1 = on (default) 0 = off

Data Channel A 1 = on (default) 0 = off

transfer 1 = on 0 = off (default)

cycle stabilizer 1 = on (default) 0 = off

Value (Hex)

Read only

only

0x0F Bits are set to

0x00 Synchronously

0x00 Determines

0x01 Turns the

0x00 When set, the

Default Notes/ Comments

should be mirrored so that LSB- or MSB-first mode registers correctly regardless of shift mode.

Default is unique chip ID, different for each device. This is a readonly register.

Child ID used to differentiate graded devices.

determine which on-chip device receives the next write command.

transfers data from the master shift register to the slave.

various generic modes of chip operation.

internal duty cycle stabilizer on and off.

test data is placed on the output pins in place of normal data.

Rev. 0 | Page 33 of 56

AD9212

Default Addr. (Hex)

14 output_mode X 0 = LVDS

15 output_adjust X X Output driver

16 output_phase X X X X 0011 = output clock phase adjust

19 user_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined

1A user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined

1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined

1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined

21 serial_control LSB first

22 serial_ch_stat X X X X X X Channel

Parameter Name

Bit 7 (MSB)

1 = on 0 = off (default)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

ANSI (default) 1 = LVDS low power, (IEEE

1596.3 similar)

X X X <10

X X X Output

X X X DCO and termination 00 = none (default) 01 = 200 Ω 10 = 100 Ω 11 = 100 Ω

(0000 through 1010)

(Default: 180° relative to DATA edge)

0000 = 0° relative to DATA edge

0001 = 60° relative to DATA edge

0010 = 120° relative to DATA edge

0011 = 180° relative to DATA edge

0100 = 240° relative to DATA edge

0101 = 300° relative to DATA edge

0110 = 360° relative to DATA edge

0111 = 420° relative to DATA edge

1000 = 480° relative to DATA edge

1001 = 540° relative to DATA edge

1010 = 600° relative to DATA edge

1011 to 1111 = 660° relative to DATA edge

MSPS,

low

encode

rate

mode

1 = on

0 = off

(default)

invert 1 = on 0 = off (default)

000 = 10 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits

00 = offset binary (default) 01 = twos complement

output reset 1 = on 0 = off (default)

Bit 0 (LSB)

FCO 2× drive strength 1 = on

0 = off (default)

Channel powerdown 1 = on 0 = off (default)

Value (Hex)

0x00 Configures the

0x00 Determines

0x03 On devices that

0x00 Serial stream

0x00 Used to power

Default Notes/ Comments

outputs and the format of the data.

LVDS or other output properties. Primarily functions to set the LVDS span and common-mode levels in place of an external resistor.

utilize global clock divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected.

pattern, 1 LSB.

pattern, 1 MSB.

pattern, 2 LSB.

pattern, 2 MSB.

control. Default causes MSB first and the native bit stream (global).

down individual sections of a converter (local).

Rev. 0 | Page 34 of 56

AD9212

Power and Ground Recommendations

When connecting power to the AD9212, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one supply is available, it should be routed to the AVDD first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD. The user can employ several different decoupling capacitors to cover both high and low frequencies. These should be located close to the point of entry at the PC board level and close to the parts with minimal trace length.

A single PC board ground plane should be sufficient when using the AD9212. With proper decoupling and smart partitioning of the PC board’s analog, digital, and clock sections, optimum performance is easily achieved.

Exposed Paddle Thermal Heat Slug Recommendations

It is required that the exposed paddle on the underside of the ADC is connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9212. An exposed continuous copper plane on the PCB should mate to the AD9212 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder filled or plugged.

To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the two during the reflow process. Using one continuous plane with no partitions only guarantees one tie point between the ADC and PCB. See Figure 73 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at

SILKSCREEN PARTITION

PIN 1 INDICATOR

www.analog.com.

05968-034

Figure 73. Typical PCB Layout

Rev. 0 | Page 35 of 56

AD9212

EVALUATION BOARD

The AD9212 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially through a transformer (default) or through the AD8334 driver. The ADC can also be driven in a single-ended fashion. Separate power pins are provided to isolate the DUT from the AD8334 drive circuitry. Each input configuration can be selected by proper connection of various jumpers (see Figure 76 to Figure 80). Figure 74 shows the typical bench characterization setup used to evaluate the ac performance of the AD9212. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance.

See Figure 76 to Figure 86 for the complete schematics and layout diagrams that demonstrate the routing and grounding techniques that should be applied at the system level.

POWER SUPPLIES

This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Simply connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack that connects to the PCB at P701. Once on the PC board, the 6 V supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board.

When operating the evaluation board in a nondefault condition, L701 to L704 can be removed to disconnect the switching power supply. This enables the user to bias each section of the board individually. Use P702 to connect a different supply for each section. At least one 1.8 V supply is needed with a 1 A current

WALL OUTLET 100V AC TO 240V AC 47Hz TO 63Hz

6V DC

SWITCHING

ROHDE & SCHWARZ,

SMHU,

2V p-p SIGNAL

SYNTHESIZ ER

ROHDE & SCHWARZ,

SMHU, 2V p-p SIGNAL SYNTHESIZER

POWER

SUPPLY

2A MAX

BAND-PASS

FILTER

XFMR INPUT

CLK

5.0V

–+

GND

1.8V

GND

AVDD_5V

EVALUATION BOARD

AVDD_DUT

AD9212

Figure 74. Evaluation Board Connection

–+–+

1.8V

GND

DRVDD_DUT

–+

capability for AVDD_DUT and DRVDD_DUT; however, it is recommended that separate supplies be used for both analog and digital. To operate the evaluation board using the VGA option, a separate 5.0 V analog supply is needed. The 5.0 V supply, or AVDD_5 V, should have a 1 A current capability. To operate the evaluation board using the SPI and alternate clock options, a separate 3.3 V analog supply is needed in addition to the other supplies. The 3.3 V supply, or AVDD_3.3 V, should have a 1 A current capability as well.

INPUT SIGNALS

When connecting the clock and analog source, use clean signal generators with low phase noise, such as Rohde & Schwarz SMHU or HP8644 signal generators or the equivalent. Use a 1 m, shielded, RG-58, 50 Ω coaxial cable for making connections to the evaluation board. Enter the desired frequency and amplitude from the ADC specifications tables. Typically, most Analog Devices evaluation boards can accept ~2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band, band-pass filter with 50 Ω terminations. Analog Devices uses TTE, Allen Avionics, and K&L types of band-pass filters. The filter should be connected directly to the evaluation board if possible.

OUTPUT SIGNALS

The default setup uses the HSC-ADC-FPGA high speed deserialization board to deserialize the digital output data and convert it to parallel CMOS. These two channels interface directly with the Analog Devices standard dual-channel FIFO data capture board (HSC-ADC-EVALB-DC). Two of the eight channels can then be evaluated at the same time. For more information on channel settings on these boards and their optional settings, visit www.analog.com/FIFO.

3.3V

GND

AVDD_3.3V

CHA TO CHH

10-BIT

SERIAL

LVD S

SPI SPISPI SPI

3.3V

–+

GND

HSC-ADC-FPG A

DESERIALIZATION

–+

3.3V_D

HIGH SPEED

BOARD

PARALLEL

1.5V

GND

2-CH

10-BIT

CMOS

1.5V_FPG A

HSC-ADC-EVALB-DC

3.3V

–+

GND

FIFO DATA

CAPTURE

BOARD

CONNECTION

VCC

USB

PC

RUNNING

ADC

ANALYZER

AND SPI

USER

SOFTWARE

5968-035

Rev. 0 | Page 36 of 56

AD9212

DEFAULT OPERATION AND JUMPER SELECTION SETTINGS

The following is a list of the default and optional settings or modes allowed on the AD9212 Rev. A evaluation board.

• POWER: Connect the switching power supply that is

supplied in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P701.

• AIN: The evaluation board is set up for a transformer-

coupled analog input with optimum 50 Ω impedance matching out to 150 MHz (see Figure 75). For more bandwidth response, the differential capacitor across the analog inputs can be changed or removed. The common mode of the analog inputs is developed from the center tap of the transformer or AVDD_DUT/2.

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

AMPLITUDE (dBFS)

–10

–11

–12

–13

–14

0 50 100 150 200 250 300 350 400 450 500

Figure 75. Evaluation Board Full Power Bandwidth

• VREF: VREF is set to 1.0 V by tying the SENSE pin to

ground, R317. This causes the ADC to operate in 2.0 V p-p full-scale range. A separate external reference option using the ADR510 or ADR520 is also included on the evaluation board. Simply populate R312 and R313 and remove C307. Proper use of the VREF options is noted in the Voltage Reference section.

• RBIAS: RBIAS has a default setting of 10 kΩ (R301) to

ground and is used to set the ADC core bias current. To further lower the core power (excluding the LVDS driver supply), simply change the resistor setting. However, performance of the ADC will degrade depending on the resistor chosen. See RBIAS section for more information.

• CLOCK: The default clock input circuitry is derived from a

simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T401) that adds a very low amount of jitter to the clock path. The clock input is

–3dB CUTOFF = 186MHz

FREQUENCY (MHz)

5968-086

50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs.

A differential LVPECL clock can also be used to clock the ADC input using the

AD9515 (U401). Simply populate R406 and R407 with 0 Ω resistors and remove R215 and R216 to disconnect the default clock path inputs. In addition, populate C205 and C206 with a 0.1 F capacitor and remove C409 and C410 to disconnect the default clock path outputs. The

AD9515 has many pin-strappable options that are set to a default working condition. Consult the AD9515 data sheet for more information about these and other options.

If using an oscillator, two oscillator footprint options are also available (OSC401) to check the ADC performance. J401 gives the user flexibility in using the enable pin, which is common on most oscillators.

• PDWN: To enable the power-down feature, simply short

J301 to the on position (AVDD) on the PDWN pin.

• SCLK/DTP: To enable a digital test pattern on the digital

outputs of the ADC, use J304. If J304 is tied to AVDD during device power-up, Test Pattern 10 0000 0000 will be enabled. See the SCLK/DTP Pin section for details.

• SDIO/ODM: To enable the low power, reduced signal option

similar to the IEEE 1595.3 reduced range link LVDS output standard, use J303. If J303 is tied to AVDD during device power-up, it enables the LVDS outputs in a low power, reduced signal option from the default ANSI standard. This option changes the signal swing from 350 mV p-p to 200 mV p-p, which reduces the power of the DRVDD supply. See the SDIO/ODM Pin section for more details.

• CSB: To enable the SPI information on the SDIO and

SCLK pins that is to be processed, simply tie J302 low in the always enable mode. To ignore the SDIO and SCLK information, tie J302 to AVDD.

• Non-SPI Mode: For users who wish to operate the DUT

without using SPI, simply remove Jumpers J302, J303, and J304. This disconnects the CSB, SCLK/DTP, and SDIO/OMD pins from the control bus, allowing the DUT to operate in its simplest mode. Each of these pins has internal termination and will float to its respective level.

• D+, D−: If an alternative data capture method to the setup

described in Figure 76 is used, optional receiver terminations, R318, R320 to R328, can be installed next to the high speed backplane connector.

Rev. 0 | Page 37 of 56

AD9212

ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION

The following is a brief description of the alternative analog input drive configuration using the AD8334 dual VGA. If this particular drive option is in use, some components may need to be populated, in which case all the necessary components are listed in Table 16. For more details on the AD8334 dual VGA, including how it works and its optional pin settings, consult the AD8334 data sheet.

To configure the analog input to drive the VGA instead of the default transformer option, the following components need to be removed and/or changed.

• Remove R102, R115, R128, R141, R202, R218, R234, R252,

T101, T102, T103, T104, T201, T202, T203, and T204 in the default analog input path.

• Populate R101, R114, R127, R140, R201, R217, R233, and

R251 with 0 Ω resistors in the analog input path.

• Populate R106, R107, R119, R120, R132, R133, R144, R145,

R206, R207, R223, R224, R239, R240, R257, and R258 with 10 kΩ resistors to provide an input common-mode level to the analog input.

• Populate R105, R113, R118, R124, R131, R137, R151, and

R160, R205, R213, R221, R222, R239, R240, R255, and R256 with 0 Ω resistors in the analog input path.

Currently, L505 to L520 and L605 to L620 are populated with 0 Ω resistors to allow signal connection. This area allows the user to design a filter if additional requirements are necessary.

Rev. 0 | Page 38 of 56

AD9212

VIN_D

VIN_C

DNP

R154

AVDD_DUT

R134

33Ω

10Ω

FB108

R132

DNP

CM3

5

6

R131

0Ω−DNP

T103

1234

CH_C

CM3

0.1µF

C115

R130

0Ω

DNP

P106

Ain

R127

0Ω−DNP

Connection

VGA Input

INH3

Channel C

DNP

R135

1kΩ

R158

AVDD_DUT

DNP

C119

2.2pF

C118

DNP

C117

R136

33Ω

10Ω

FB109

R163

499Ω

DNP

C120

DNP

R133

0.1µF

R137

CH_C

C116

10Ω

FB107

P105

Ain

C121

0Ω−DNP

CM3

1kΩ

1

R139

R138

1kΩ

0.1µF E103

AVDD_DUT

0Ω

R129

R128

64.9Ω

DNP

R155

AVDD_DUT

R151

0Ω−DNP

C122

VGA Input

Connection

R140

0Ω−DNP

INH4

Channel D

VIN_D

R148

1kΩ

DNP

R159

DNP

C126

2.2pF

C125

DNP

C124

499Ω

R164

R144

DNP

R145

CM4

5

34

2

CM4

DNP

P108

Ain

R141

64.9Ω

33Ω

R147

10Ω

FB112

DNP

C127

R160

0Ω−DNP

CM4

CH_D

1

E104

C123

0.1µF

AVDD_DUT

R143

0Ω

R142

R146

33Ω

Ω

FB111

10

6

T104

1

CH_D

0.1µF

10Ω

FB110

P107

Ain

05968-072

AVDD_DUT

DNP

0.1µF

C128

1kΩ

R150

R149

1kΩ

VIN_A

R109

1kΩ

DNP

R152

AVDD_DUT

R108

33Ω

10Ω

FB102

R106

DNP

CM1

5

6

R105

0Ω−DNP

T101

1

2

CH_A

CM1

0.1µF

C101

R104

0Ω

DNP

P102

Ain

VGA Input

Connection

R101

0Ω−DNP

INH1

Channel A

DNP

R156

AVDD_DUT

2.2pF

C104

DNP

C105

DNP

C103

R110

33Ω

10Ω

FB103

499Ω

R161

DNP

R107

4

R113

3

0.1µF

C102

FB101

P101

Ain

DNP

C106

0Ω−DNP

CM1

CH_A

1

E101

AVDD_DUT

10Ω

0Ω

R103

R102

64.9Ω

AVDD_DUT

0.1µF

C107

1kΩ

R112

R111

1kΩ

VGA Input

Connection

R153

INH2

VIN_B

DNP

R121

33Ω

10Ω

FB105

6

R118

0Ω−DNP

T102

1234

CH_B

0.1µF

C108

10Ω

FB104

R114

0Ω−DNP

P103

Channel B

Ain

Figure 76. Evaluation Board Schematic, DUT Analog Inputs

VIN_B

DNP

R123

1kΩ

R157

AVDD_DUT

DNP

C112

2.2pF

C111

DNP

C110

R122

33Ω

10Ω

FB106

R162

499Ω

R119

DNP

R120

CM2

5

R124

CM2

0.1µF

C109

R116

DNP

P104

Ain

R115

64.9Ω

DNP

C113

0.1µF

0Ω−DNP

CH_B

0Ω

R117

C114

CM2

0Ω

1kΩ

R126

1

R125

1KΩ

E102

AVDD_DUT

DNP: DO NOT POPULATE.

Rev. 0 | Page 39 of 56

AD9212

VIN_G

DNP

R248

AVDD_DUT

R242

33Ω

10Ω

FB208

R239

6

R237

T203

0Ω−DNP

1

25

CH_G

0.1µF

C215

R236

0Ω

DNP

P206

Ain

R233

0Ω−DNP

INH7

VGA Input

Connection

Channel G

R246

1kΩ

2.2pF

C218

DNP

C217

R241

499Ω

DNP

R240

CM7

R238

34

CH_G

CM7

10Ω

FB207

P205

Ain

DNP

R247

AVDD_DUT

DNP

C219

R245

33Ω

10Ω

FB209

DNP

C220

0.1µF

0Ω−DNP

C216

C221

CM7

1

R250

1kΩ

R249

1kΩ

0.1µF E203

AVDD_DUT

0Ω

R235

R234

64.9kΩ

Connection

VGA Input

VIN_H

R262

1kΩ

2.2pF

C225

DNP

C224

499Ω

R259

DNP

R258

CM8

R256

34

CH_H

CM8

C223

R254

P208

Ain

R252

64.9Ω

DNP

R263

DNP

C226

R261

33Ω

10Ω

FB212

DNP

C227

0Ω−DNP

CM8

1

E204

0.1µF

AVDD_DUT

0Ω

R253

DNP

R264

R260

33Ω

10Ω

FB211

R257

6

R255

T204

0Ω−DNP

1

25

CH_H

0.1µF

C222

10Ω

FB210

DNP

R251

0Ω−DNP

INH8

DNP

P207

Channel H

Ain

05968-073

AVDD_DUT

0.1µF

C228

R266

1kΩ

R265

1kΩ

VIN_E

R214

1kΩ

R215

2.2pF

C204

DNP

C203

R210

33Ω

FB203

499Ω

DNP

R207

R213

0Ω−DNP

34

CH_E

0.1µF

C202

10Ω

FB201

R203

R202

DNP

AVDD_DUT

DNP

C205

10Ω

DNP

C206

CM5

1

E201

0Ω

64.9Ω

AVDD_DUT

0.1µF

C207

R212

1kΩ

R211

1kΩ

AVDD_DUT

VGA Input

Connection

DNP

R216

AVDD_DUT

R209

33Ω

10Ω

FB202

R208

R206

DNP

CM5

6

R205

T201

0Ω−DNP

1

25

CH_E

CM5

0.1µF

C201

R204

0Ω

DNP

P202

Ain

VGA Input

Connection

R201

0Ω−DNP

INH5

VIN_F

DNP

R228

1kΩ

2.2pF

C211

DNP

C210

R227

33Ω

FB206

R225

499Ω

R223

DNP

R224

CM6

R222

0Ω−DNP

25

34

CH_F

CM6

0.1µF

C209

R220

0Ω

DNP

P204

Ain

64.9Ω

R218

R229

AVDD_DUT

DNP

C212

10Ω

DNP

C213

0.1µF

C214

CM6

0Ω

R219

1kΩ

R232

1

R231

1kΩ

E202

AVDD_DUT

DNP

R230

R226

33Ω

10Ω

FB205

6

R221

0Ω−DNP

T202

1

CH_F

0.1µF

C208

10Ω

FB204

R217

0Ω−DNP

INH6

P203

Channel F

P201

Channel E

Ain

Figure 77. Evaluation Board Schematic, DUT Analog Inputs (Continued)

Rev. 0 | Page 40 of 56

DNP: DO NOT POPULATE.

AD9212

Optional Output

Terminations

R318,R320−R328

DNP

R318

DCO

FCO

49

D9

D10

GNDCD9

GNDCD10

C10

C9

P301

39

59

DNP

R320

R321

R322

CHB

CHC

CHA

46

47

48

D6

D7

D8

GNDCD6

GNDCD7

GNDCD8

C6

C7

C8

37

38

56

57

58

36

DNP

R323

R324

R325

CHD

CHE

CHF

45

43

44

D5

D3

D4

GNDCD3

GNDCD4

GNDCD5

C3

C4

C5

33

34

53

54

55

35

DNP

R328

R326

R327

CHG

CHHCHH

18

19

415042

D1

D2

GNDCD1

GNDCD2

GNDAB10

C1

C2

314032

516052

B8

B9

B10

GNDAB7

GNDAB8

GNDAB9

A10

A8

A9

8

9

28

29

SCLK_CHA

SDI_CHA

CSB1_CHA

CSB2_CHA

SDO_CHA

112012

13

14

15

16

17

B7

GNDAB6

A7

7

27

B4

B5

B6

GNDAB3

GNDAB4

GNDAB5

A4

A5

A6

4

5

6

24

25

26

B1

B2

B3

GNDAB1

GNDAB2

A1

A2

A3

1102

3

213022

23

05968-074

Digital O utputs

CHF

DCO

CHA

FCO

CHB

AVDD_DUT

CHC

R302 DNP

CHD

CHE

CHG

SDI_CHB

SCLK_CHB

ALWAYS ENABLE SPI

ODM Enable

PDWN ENABLE

3

2

J302

J301

1

R304

100kΩ DNP

R303

CSB_DUT

DTP Enable

3

2

J303

J304

1

SDIO_ODM

R307 10kΩ

SCLK_DTP

R306 100kΩ

R305 100kΩ

CSB3_CHB

CSB4_CHB

SDO_CHB

NC

VSENSE_DUT

Vref Select

VREF_DUT

= External

= 0.5V

REF

V

DNP

R315

DNP

R314

= 1V

= 0.5V(1 + R219/R220)

REF

V

0Ω

R317

DNP

R31

AVDD_DUT

DNP

R312

DNP

R313

1µF

C307

0.1µF

1kΩ

VIN_B

AVDD_DUT

48

AVDD

49

VIN_C

AVDD_DUT

VIN_D

R301

VIN_D

10kΩ

VSENSE_DUT

VREF_DUT

C304

0.1µF AVDD_DUT

VIN_E

C303

Reference

4.7µF

Decoupling

VIN_E

AVDD_DUT

VIN_F

C301

0.1µF

VIN_F

C302

0.1µF

VIN+C

50

VIN−C

51

AVDD

52

VIN−D

53

VIN+D

54

RBIAS

55

SENSE

56

VREF

57

REFB

58

REFT

59

AVDD

60

VIN+E

61

VIN−E

62

AVDD

63

VIN−F

64

VIN+F

0

SLUG

AVDD

1

AVDD_DUT

VIN_B

47

45

46

AVDD

VIN−B

VIN+B

VIN+G

VIN−G

AVDD

4

2

3

VIN_G

AVDD_DUT

VIN_A

43

44

VIN−A

40

42

41

CSB

AVDD

VIN+A

PDWN

AD9212BCPZ-50

CLK−

VIN−H

5

VIN_H

AVDD

VIN+H

AVDD

7109118

6

AVDD_DUT

CLK

AVDD_DUT

VIN_H

AVDD_DUT

GND

38

39

37

AVDD

DRGND

SCLK/DTP

SDIO/ODM

U301

CLK+

CLK

AVDD

AVDD_DUT

DRGND

AVDD

12

13 36

GND

AVDD_DUT

CHA

DRVDD_DUT

33

34

D+A

D−A

DRVDD

14 35

32

D+B

D−B

D+C

D−C

D+D

D−D

FCO+

FCO−

DCO+

DCO−

D+E

D−E

D+F

D−F

D+G

D−G

D+H

D−H

16

15

CHH

CHB

31

CHB

30

CHC

29

CHC

28

CHD

27

CHD

26

FCO

25

FCO

24

DCO

23

DCO

22

CHE

21

CHE

20

CHF

19

CHF

18

CHG

17

CHG

AVDD_DUT

DNP

R311

Reference Circuitry

4.99kΩ

R309

VOUT

GND

1.0V

CW

10kΩ

R310

C305

0.1µF

ADR510ARTZ

OPTIONA L

EXT REF

TRIM/NC

U302

470kΩ

R308

DRVDD_DUT

R319

C306

Remove C214 when

using external Vref

DNP: DO NOT POPULATE.

Figure 78. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface

Rev. 0 | Page 41 of 56

AD9212

0Ω

DNP

R437

0Ω

R436

S6

AD9515 Pin−strap settings

AVDD_3.3V

0Ω

R4250ΩR427

0Ω

DNP

R424

R426

S1

S0

AVDD_3.3V

CLK

LVPECL OUTPUT

C405

0.1µF

C406

DNP

240Ω

R421

R422

100Ω

R420

240Ω

192322

OUT0

OUT1

OUT0B

33

GND_PAD

31

OPTIONAL CL OCK DRIVE CIRCUIT

AVDD_3.3V

GND

R406

CLK

R411

0Ω

DNP

AD9515BCPZ

CLKB

325

DNP

49.9Ω

SIGNAL=DNC;27,28

SIGNAL=AVDD_3.3V;4,17,20,21,24,26,29,30

SYNCB

R413

R412

0Ω

R407

1

VS

AVDD_3.3V

32

RSET

U401

R414

4.12kΩ

R410

10kΩ

R409

DNP

R408

0Ω

R441

R439

0Ω

DNP

R440

R438

S7

S8

AVDD_3.3V

0Ω

R431

R429

0Ω

DNP

R430

R428

S3

S2

AVDD_3.3V

DNP

R446

LVDS OUTPUT

0.1µF

C407

C408

0.1µF

DNP

CLK

R423

100Ω

18

25

S0

S0S1S2S3S4S5S6S7S8S9S10

OUT1B

16

S1

15

S2

14

S3

13

S4

12

S5

11

S6

10

S7

9

S8

8

S9

7

S10

6

VREF

1

E401

R417

10kΩ

DNP

0Ω

R445

R443

0Ω

DNP

R444

R442

S9

AVDD_3.3V

R433

R432

AVDD_3.3V

DNP

0.1µF

3

0Ω

T401

S10

AVDD_3.3V

0Ω

R435

0Ω

DNP

R434

S4

S5

AVDD_3.3V

CLK

CLIP SINE OUT (DE FAULT)

C409

C410

0.1µF

1

2

CR401

HSMS-2812-TR1G

0Ω

R418

6543

C411

0.1µF

2

1

814C414C

0.1µF0.1µF

C417

C416

0.1µF

514C214C

0.1µF

C413

0.1µF 0.1µF

AVDD_3.3V

0.1µF

05968-075

OPT_CL K

J401

DISABLE OSC401

ENABLE OSC401

3

1

2

R401

10kΩ

AVDD_3.3V

C401

0.1µF

R402

571

OE

OSC40 1

VCC

Optional Clock

Oscillator

10

12 3

14

AVDD_3.3V

Figure 79. Evaluation Board Schematic, Clock Circuitry

OPT_CL K

10kΩ

0.1µF

GND

GNDOU T

OUT

8

C402

CRYSTAL_3

49.9Ω

R404

R4030ΩDNP

P401

Enc

Input

Encode

Clock Circuit

0Ω

R416

R415

OPT_CLK

C403

0.1µF

R405

0Ω

DNP

P402

Enc

DNP: DO NOT POPULATE.

Rev. 0 | Page 42 of 56

AD9212

0

187Ω

R531

0.1µF

CH_ACH_B

DNP

R534

CH_B CH_A

DNP

R529

CH_CCH_D

DNP

R522

resistors or design your own filter.

Populate L505−L520 with 0Ω

CH_D CH_C

DNP

R517

AVDD_5V

Power Down Enable

(0−1V=Disable Power)

Rclamp Pin

10kΩ

DNP

R506

C508

0.1µF

C507

1000pF

0Ω

L520

C555

DNP

0Ω

L519

0Ω

L516

C551

DNP

0Ω

L515

0Ω

L512

C547

DNP

0Ω

L511

0Ω

L508

C543

DNP

0Ω

L507

C510

C509

10µF

0.1µF

AVDD_5V

R505 10kΩ

HILO Pin=H=+/− 75mV

HILO Pin=LO=+/− 50mV

0.018µF

0Ω

L518

C554

DNP

0Ω

L517

0Ω

L514

C550

DNP

0Ω

L513

0Ω

L510

C546

DNP

0Ω

L509

0Ω

L506

C542

DNP

0Ω

L505

R504 10kΩ

VG12

AVDD_5V

C505

0.1µF

R503 274Ω

C502

0.1µF C501

C553

374Ω

R533

DNP

R528

DNP

R521

DNP

R516

DNP

C512 10µF

C506

0.1µF

C503 22pF

L501 120nH

R532

C552

0.1µF R530

187Ω

0.1µF

C549

R526

187Ω

R527

374Ω

C548

0.1µF

R525

187Ω

R523

R524

AVDD_5V

187Ω

R519

0.1µF

C545

374Ω

R520

C544

0.1µF R518

187Ω

0.1µF

C541

R514

187Ω

374Ω

R515

C540

0.1µF

R513 187Ω

C511

0.1µF

48

49

VCM2

50

VCM1

51

EN34

52

EN12

53

CLMP12

54

GAIN12

55

VPS1

56

VIN1

57

VIP1

58

LOP1

59

LON1

60

COM1X

61

LMD1

62

INH1

63

COM1

64

COM2

U501

0.1µF

C504

COM12

INH2

L502 120nH

VOH1

LMD2

C515

0.018µF

VOL1

COM2X

0.1µF

C537

R507 274Ω

C514 22pF

10kΩ

AVDD_5V

MODE Pin

41424344454647

40

VOL2

VPS12

NC

VOH2

MODE

COM12

AD8334ACPZ -REEL

LON2

LOP2

VIP2

VIN2

VPS2

VPS3

987654321

AVDD_5V

C518

0.1µF

C538

AVDD_5V

Positive Gain Slope = 0−1.0V

Negitive Gain Slope = 2.25−5.0V

33343536373839

32

VOL3

VOH3

VPS34

COM34

VIN3

VIP3

LOP3

LON3

C523

0.1µF

C522

R508 274Ω

C521

0.018µF

NC

VOL4

VOH4

31

COM34

VCM3

30

VCM4

29

HILO

28

CLMP34

27

GAIN34

VPS4

VIN4

VIP4

LOP4

LON4

COM4X

LMD4

INH4

COM4

COM3

COM3X

LMD3

INH3

16151413121110

0.1µF

C524

L503

120nH

VG34

26

AVDD_5V

25

24

23

22

21

20

19

18

17

C520 22pF

0.1µF

C529

0.1µF

C528

L504 120nH

C536C 535C534C533

0.1µF0.1µF

10µF10µF

R511

R512

10kΩ

AVDD_5V

0.1µF

C530

HILO Pin=H=+/− 75mV

HILO Pin=LO=+/− 50mV

Rclamp Pin

10kΩ

DNP

R510

R509 274Ω

INH1

C527

0.018µF

0.1µF C525

C532

0.1µF

C531

1000pF

C526 22pF

5968-076

0.1µF C519

10kΩ

39kΩ

R535

R536

Variable Gain Circuit (0−1.0VDC)

AVDD_5V

DNP: DO NOT POPULATE.

INH2

2

EXT VG

JP502

1

GND

VG34

External Variable Gain Drive

CW

EXT VG

JP501

12

GND

VG12

External Variable Gain Drive

INH4

10kΩ

39kΩ

R501

R502

VariableGain Circuit (0−1.0VDC)

AVDD_5V

CW

VG12

0.1µF C513

INH3

Figure 80. Evaluation Board Schematic, Optional DUT Analog Input Drive

Rev. 0 | Page 43 of 56

AD9212

0.1µF

CH_E

DNP

R636

CH_F CH_E

DNP

R629

CH_F

CH_GCH_H

Populate L605−L620 with 0Ω

resistors or design your own filter.

DNP

R622

CH_H CH_G

DNP

R617

MODE Pin

Positive Gain Slope = 0−1.0V

Negative Gain Slope = 2.25−5.0V

AVDD_5V

Power Down Enable

(0−1V=Disable Power)

Rclamp Pin

10kΩ

DNP

R606

C608

0.1µF

C607

1000pF

0Ω

L620

C655

DNP

0Ω

L619

0Ω

L616

C651

DNP

0Ω

L615

0Ω

L612

C647

DNP

0Ω

L611

0Ω

L608

C643

DNP

0Ω

L607

C610

C609

10µF

0.1µF

AVDD_5V

R605

10kΩ

HILO Pin=H=+/− 75mV

HILO Pin=LO=+/− 50mV

0Ω

L618

C654

DNP

0Ω

L617

0Ω

L614

C650

DNP

0Ω

L613

0Ω

L610

C646

DNP

0Ω

L609

0Ω

L606

C642

DNP

0Ω

L605

R604

VG56

AVDD_5V

C605

0.1µF

C653

R631

187Ω

374Ω

R633

DNP

R628

DNP

R621

DNP

R616

DNP

C612 10µF

C606

0.1µF

R632

C652

0.1µF R630

187Ω

0.1µF

C649

R626

187Ω

R627

374Ω

0.1µF

C648

R625

187Ω

AVDD_5V

R619

187Ω

374Ω

R620

0.1µF

C645

0.1µF

C644

R618

187Ω

0.1µF

C641

R614

187Ω

374Ω

R615

0.1µF

C640

R613 187Ω

C611

0.1µF

VCM2

49

VCM1

50

10kΩ

EN34

51

EN12

52

CLMP12

53

GAIN12

54

VPS1

55

VIN1

56

VIP1

57

LOP1

58

LON1

59

COM1X

60

LMD1

61

INH1

62

COM1

63

COM2

64

U601

0.1µF

C604

AVDD_5V

48

VOL1

VOH1

VPS12

COM12

INH2

LMD2

COM2X

LON2

0.1µF

C616

10kΩ

R623

10kΩ

R624

AVDD_5V

C635

C630

R609 274Ω

C627

0.018µF

C636

0.1µF0.1µF

10µF

R611

R612

10kΩ

0.1µF

HILO Pin=H=+/− 75mV

HILO Pin=LO=+/− 50mV

Rclamp Pin

10kΩ

DNP

R610

C632

0.1µF

C631

1000pF

C626

22pF

C634C 633

10µF

41424344454647

40

VOL2

NC

VOH2

COM12

VOH3

MODE

COM34

AD8334ACPZ -REEL

LOP2

VIP2

VIN2

VPS2

VPS3

VIN3

VIP3

987654321

C623

AVDD_5V

C618

0.1µF

33343536373839

NC

VOL3

VOL4

VPS34

LOP3

LON3

COM3X

0.1µF

32

VOH4

COM34

VCM3

31

VCM4

30

HILO

29

CLMP34

28

GAIN34

27

VPS4

26

VIN4

25

VIP4

24

LOP4

23

LON4

22

COM4X

21

LMD4

20

INH4

19

COM4

18

COM3

17

LMD3

INH3

16151413121110

0.1µF

C624

VG78

AVDD_5V

C629

AVDD_5V

0.1µF

C628

L604

120nH

05968-077

EXT VG

JP601

12

GND

VG56

External Variable Gain Drive

0.1µF

0.018µF

C617

R607 274Ω

C615

C614 22pF

R603 274Ω

C602

0.018µF

C603

22pF

L601 120nH

0.1µF C601

INH8

39kΩ

R602

10kΩ

R601

CW

VG56

AVDD_5V

Variable Gain Circuit (0−1.0VDC)

L602 120nH

0.1µF C613

INH7

C622

R608 274Ω

C621

0.018µF

L603 120nH

INH6

Figure 81. Evaluation Board Schematic, Optional DUT Analog Input Drive (Continued)

Rev. 0 | Page 44 of 56

0.1µF C619

C620 22pF

GND

EXT VG

JP602

12

VG78

10kΩ

R634

CW

VG78

External Variable Gain Drive

INH5

0.1µF C625

39kΩ

R635

Variable Gain Circuit (0−1.0VDC)

AVDD_5V

DNP: DO NOT POPULATE.

AD9212

0

PWR_IN

CR702

GREEN

D702

SK33-TP

2

FER701

43

1

D701

F701

NANOSMDC110F-2

C704

1

Power Supply Input

6V, 2A max

P701

R716

261Ω

+3.3V

AVDD_3.3V

C710

0.1µF

C709

L703

10µH

S2A-TP

10µF

2

3

CON005

7.5V POWER

2.5MM JACK

3.3V_AVDD

1234567

P1P2P3P4P5P6P7

P702

DNP

Input

Optional Power

+5.0V

AVDD_5V

C706

10µF

5V_AVDD

C705

L701

10µH

DUT_AVDD

DUT_DRVDD

+1.8V

AVDD_DUT

0.1µF

10µF

8

P8

C708

10µF

C707

L702

10µH

Decoupling Capacitors

+1.8V

0.1µF

DRVDD_DUT

0.1µF

C712

10µF

C711

L704

10µH

0.1µF

C727

0.1µF

C726

0.1µF

C725

0.1µF

C724

0.1µF

C723

C753

0.1µF

C752

0.1µF

C751

0.1µF

C750

0.1µF

C749

0.1µF

AVDD_5V

0.1µF

C735

0.1µF

C734

0.1µF

C733

0.1µF

C732

0.1µF

C731

0.1µF

C730

C748

0.1µF

C747

0.1µF

C746

0.1µF

C745

0.1µF

C744

C743

0.1µF

C742

DRVDD_DUT

0.1µF

C741

0.1µF

C740

AVDD_3.3V

5968-078

SPI CIRCUITRY FROM FIFO

SDO_CHA

SDI_CHA

SCLK_CHA

CSB1_CHA

+5V = PROGRAMMING = AVDD_5V

AVDD_5V

1kΩ

R710

AVDD_3.3V

AVDD_DUT

1kΩ

R713

1kΩ

R712

SDIO_ODM

REMOVE WHEN USING OR PROGRAMMING PIC (U402)

R709

0Ω

R708

0Ω

R707

0ΩR706

0Ω−DNP

R705

R704

0Ω−DNP

R703

765

GP0

GP1

GP2

MCLR/GP3

GP4

GP5

VDD VSS

U701

3

2

J701

1

C701

AVDD_3.3V AVDD_ 5V

+3.3V = NORMAL OPERATION = AVD D_3.3V

0.1µF

PIC12F629-I/SNG

4

3

281

R701

4.7kΩ

261Ω

R702

OPTIONAL

4

3

S701

1

2

RESET/ REPROGRAM

NC7W207P6X_NL

CR701

GREEN

C702

0.1µF

5

6

Y1

Y2A2

VCC

GND

A1

U702

1234

R711

10kΩ

E701

1

J702

PICVCC

MCLR/GP3

2

1

GP1

4

3

GP0

6

5

ISPPIC PROGRAMMING HEADER

8

7

10

9

NC7WZ16P6X_NL

SCLK_DTP

654

Y1

A1

PICVCC

GP1

GP0

MCLR/GP3

AVDD_DUT

Y2A2

VCC

GND

321

AVDD_DUT

CSB_DUT

C703

0.1µF

U703

R715

10kΩ

R714

10kΩ

AVDD_DUT

3.3V_AVDD

L707

10µH

1µF

C720

4

2

OUT

GND

1

ADP3339ZAKC−3.3-RL

IN

U705

3

1µF

C719

PWR_IN

DUT_AVDD

10µH

L705

C715

1µF

234

OUT

GND

1

ADP3339ZAKC−1.8-RL

IN

U707

1µF

C714

PWR_IN

5V_AVDD

L708

10µH

1µF

C722

4

2

OUT

GND

1

ADP3339ZAKC−5-RL7

IN

U706

3

1µF

C721

PWR_IN

DUT_DRVDD

10µH

L706

C717

1µF

234

OUT

GND

1

ADP3339ZAKC−1.8-RL

IN

U704

1µF

C716

DNP: DO NOT POPULATE.

PWR_IN

Figure 82. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry

Rev. 0 | Page 45 of 56

AD9212

Figure 83. Evaluation Board Layout, Primary Side

05968-079

Rev. 0 | Page 46 of 56

AD9212

Figure 84. Evaluation Board Layout, Ground Plane

05968-045

Rev. 0 | Page 47 of 56

AD9212

Figure 85. Evaluation Board Layout, Power Plane

05968-046

Rev. 0 | Page 48 of 56

AD9212

Figure 86. Evaluation Board Layout, Secondary Side (Mirrored Image)

05968-082

Rev. 0 | Page 49 of 56

AD9212

Table 16. Evaluation Board Bill of Materials (BOM)

Qty per Board

Item

1 1 AD9212LFCSP_REVA PCB PCB PCB 2 118

3 8

4 8

5 1 C303 Capacitor 603

6 4

7 8

REFDES Device Package Value Manufacturer

C101, C102, C107, C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C202, C207, C208, C209, C214, C215, C216, C221, C222, C223, C228, C301, C302, C304, C305, C306, C401, C402, C403, C409, C410, C411, C412, C413, C414, C415, C416, C417, C418, C501, C504, C505, C506, C508, C509, C511, C513, C518, C519, C522, C523, C524, C525, C528, C529, C530, C532, C534, C536, C537, C538, C601, C604, C605, C606, C608, C609, C611, C613, C616, C617, C618, C619, C622, C623, C624, C625, C628, C629, C630, C632, C634, C636, C701, C702, C703, C706, C708, C710, C712, C723, C724, C725, C726, C727, C730, C731, C732, C733, C734, C735, C740, C741, C742, C743, C744, C745, C746, C747, C748, C749, C750, C751, C752, C753

C104, C111, C118, C125, C204, C211, C218, C225

C510, C512, C533, C535, C610, C612, C633, C635

C507, C531, C607, C631

C502, C515, C521, C527, C602, C615, C621, C627

Capacitor 402

Capacitor 805

Capacitor 402

1

Manufacturer Part Number

0.1 μF, ceramic, X5R, 10 V, 10% tol

2.2 pF, ceramic, COG,

0.25 pF tol, 50 V

10 μF, 6.3 V ±10% ceramic, X5R

4.7 μF, ceramic, X5R,

6.3 V, 10% tol 1000 pF, ceramic, X7R,

25 V, 10% tol

0.018 μF, ceramic, X7R, 16 V, 10% tol

Murata GRM155R71C104KA88D

Murata GRM1555C1H2R20CZ01D

Murata GRM219R60J106KE19D

Murata GRM188R60J475KE19D

Murata GRM155R71H102KA01D

AVX 0402YC183KAT2A

Rev. 0 | Page 50 of 56

AD9212

Qty per

Item

Board REFDES Device Package Value Manufacturer

8 8

9 1 C704 Capacitor 1206

10 9

11 16

12 4

13 1 CR401 Diode SOT-23

14 2 CR701, CR702 LED 603 Green, 4 V, 5 m candela Panasonic LNJ314G8TRA 15 1 D702 Diode

16 1 D701 Diode

17 1 F701 Fuse 1210

18 1 FER701 Choke coil 2020

19 24

20 4

21 6

23 1 J702 Connector 10-pin

24 8

25 8

C503, C514, C520, C526, C603, C614, C620, C626

C307, C714, C715, C716, C717, C719, C720, C721, C722

C540, C541, C544, C545, C548, C549, C552, C553, C640, C641, C644, C645, C648, C649, C652, C653

C705, C707, C709, C711

FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112, FB201, FB202, FB203, FB204, FB205, FB206, FB207, FB208, FB209, FB210, FB211, FB212

JP501, JP502, JP601, JP602

J301, J302, J303, J304, J401, J701

L701, L702, L703, L704, L705, L706, L707, L708

L501, L502, L503, L504, L601, L602, L603, L604

Capacitor 402

Capacitor 603

Capacitor 805

Capacitor 603

DO214AB

DO214AA

Ferrite bead 603

Connector 2-pin

Connector 3-pin

Ferrite bead 1210

Inductor 402

22 pF, ceramic, NPO, 5% tol, 50 V

10 μF, tantalum, 16 V, 20% tol

1 μF, ceramic, X5R,

6.3 V, 10% tol

0.1 μF, ceramic, X7R, 50 V, 10% tol

10 μF, ceramic, X5R,

6.3 V, 20% tol 30 V, 20 mA, dual

Schottky

3 A, 30 V, SMC

5 A, 50 V, SMC

6.0 V, 2.2 A trip-current resettable fuse

10 μH, 5 A, 50 V, 190 Ω @ 100 MHz

10 Ω, test frequency 100 MHz, 25% tol, 500 mA

100 mil header jumper, 2-pin

100 mil header jumper, 3-pin

100 mil header, male, 2 × 5 double row straight

10 μH, bead core 3.2 ×

2.5 × 1.6 SMD, 2 A

120 nH, test freq 100 MHz, 5% tol, 150 mA

Murata GRM1555C1H220JZ01D

Rohm TCA1C106M8R

Murata GRM188R61C105KA93D

Murata GRM21BR71H104KA01L

Murata GRM188R60J106ME47D

Agilent Technologies

Micro Commercial Co.

Tyco/Raychem NANOSMDC110F-2

Murata DLW5BSN191SQ2L

Murata BLM18BA100SN1D

Samtec TSW-102-07-G-S

Samtec TSW-103-07-G-S

Samtec TSW-105-08-G-D

Murata BLM31PG500SN1L

Murata LQG15HNR12J02D

Manufacturer Part Number

HSMS-2812-TR1G

SK33-TP

S2A-TP

Rev. 0 | Page 51 of 56

AD9212

Qty per

Item

Board REFDES Device Package Value Manufacturer

26 32

27 1 OSC401 Oscillator SMT

28 9

29 1 P301 Connector HEADER

30 1 P701 Connector

31 21

32 18

33 8

34 8

35 28

36 16

L505, L506, L507, L508, L509, L510, L511, L512, L513, L514, L515, L516, L517, L518, L519, L520, L605, L606, L607, L608, L609, L610, L611, L612, L613, L614, L615, L616, L617, L618, L619, L620

P101, P103, P105, P107, P201, P203, P205, P207, P401

R301, R307, R401, R402, R410, R413, R504, R505, R511, R512, R523, R524, R604, R605, R611, R612, R623, R624, R711, R714, R715

R103, R117, R129, R142, R203, R219, R235, R253, R317, R405, R415, R416, R417, R418, R706, R707, R708, R709

R102, R115, R128, R141, R202, R218, R234, R252

R104, R116, R130, R143, R204, R220, R236, R254

R109, R111, R112, R123, R125, R126, R135, R138, R139, R148, R149, R150, R211, R212, R214, R228, R231, R232, R246, R249, R250, R262, R265, R266, R319, R710, R712, R713

R108, R110, R121, R122, R134, R136, R146, R147, R209, R210, R226, R227, R242, R245, R260, R261

Resistor 805 0 Ω, 1/8 W, 5% tol

Clock oscillator,

65.00 MHz, 3.3 V, ±5% duty cycle

Connector SMA

0.1", PCMT

Resistor 402

Resistor 603

Resistor 402

Side-mount SMA for

0.063" board thickness

1469169-1, right angle 2-pair, 25 mm, header assembly

RAPC722, power supply connector

10 kΩ, 1/16 W, 5% tol

0 Ω, 1/16 W, 5% tol

64.9 Ω, 1/16 W, 1% tol

0 Ω, 1/10 W, 5% tol

1 kΩ, 1/16 W, 1% tol

33 Ω, 1/16 W, 5% tol

NIC Components Corp.

Valphey Fisher VFAC3H-L-65MHz

Johnson Components

Tyco 6469169-1

Switchcraft RAPC722X

NIC Components Corp.

Manufacturer Part Number

NRC04Z0TRF

142-0701-851

NRC04J103TRF

NRC04Z0TRF

NRC04F64R9TRF

NRC06Z0TRF

NRC04F1001TRF

NRC04J330TRF

Rev. 0 | Page 52 of 56

AD9212

Qty per

Item

Board REFDES Device Package Value Manufacturer

37 8

38 3 R303, R305, R306 Resistor 402

39 1 R414 Resistor 402

40 1 R404 Resistor 402

41 1 R309 Resistor 402

42 5

43 1 R308 Resistor 402

44 4

45 16

46 8

47 8

48 11

49 1 R701 Resistor 402

50 1 R702 Resistor 402

51 1 R716 Resistor 603

52 2 R420, R421 Resistor 402

53 2 R422, R423 Resistor 402

54 1 S701 Switch SMD

R161, R162, R163, R164, R208, R225, R241, R259

R310, R501, R535, R601, R634

R502, R536, R602, R635

R513, R514, R518, R519, R525, R526, R530, R531, R613, R614, R618, R619, R625, R626, R630, R631

R515, R520, R527, R532, R615, R620, R627, R632

R503, R507, R508, R509, R603, R607, R608, R609

R425, R427, R429, R431, R433, R435, R436, R439, R441, R443, R445

Resistor 402

Potentiometer 3-lead

Resistor 402

Resistor 201

499 Ω, 1/16 W, 1% tol

100 kΩ, 1/16 W, 1% tol

4.12 kΩ, 1/16W, 1% tol

49.9 Ω, 1/16 W,

0.5% tol

4.99 kΩ, 1/16 W, 5% tol

10 kΩ, Cermet trimmer potentiometer, 18 turn top adjust, 10%, 1/2 W

470 kΩ, 1/16 W, 5% tol

39 kΩ, 1/16 W, 5% tol

187 Ω, 1/16 W, 1% tol

374 Ω, 1/16 W, 1% tol

274 Ω, 1/16 W, 1% tol

0 Ω, 1/20 W, 5% tol

4.7 kΩ, 1/16 W, 1% tol

261 Ω, 1/16 W, 1% tol

240 Ω, 1/16 W, 5% tol

100 Ω, 1/16 W, 1% tol

LIGHT TOUCH, 100GE, 5 mm

NIC Components Corp.

Susumu RR0510R-49R9-D

NIC Components Corp.

COPAL ELECTRONICS

NIC Components Corp.

Panasonic EVQ-PLDA15

Manufacturer Part Number

NRC04F4990TRF

NRC04F1003TRF

NRC04F4121TRF

NRC04F4991TRF

CT94EW103

NRC04J474TRF

NRC04J393TRF

NRC04F1870TRF

NRC04F3740TRF

NRC04F2740TRF

NRC02Z0TRF

NRC04J472TRF

NRC04F2610TRF

NRC06F261OTRF

NRC04J241TRF

NRC04F1000TRF

Rev. 0 | Page 53 of 56

AD9212

Qty per

Item

Board REFDES Device Package Value Manufacturer

55 9

T101, T102, T103, T104, T201, T202, T203, T204, T401

56 2 U704, U707 IC SOT-223

Transformer CD542

ADT1-1WT+, 1:1 impedance ratio transformer

ADP33339AKC-1.8-RL,

Mini-Circuits ADT1-1WT+

Analog Devices ADP3339AKCZ-1.8-RL

1.5 A, 1.8 V LDO regulator

57 2 U501, U601 IC CP-64-3

AD8334ACPZ-REEL,

Analog Devices AD8334ACPZ-REEL ultralow noise precision dual VGA

58 1 U706 IC SOT-223 ADP33339AKC-5-RL7 Analog Devices ADP3339AKCZ-5-RL7 59 1 U705 IC SOT-223 ADP33339AKC-3.3-RL Analog Devices ADP3339AKCZ-3.3-RL 60 1 U301 IC CP-64-3

AD9212BCPZ-50, octal,

Analog Devices AD9212BCPZ-65 10-bit, 65 MSPS serial LVDS 1.8 V ADC

61 1 U302 IC SOT-23

ADR510ARTZ, 1.0 V,

Analog Devices ADR510ARTZ precision low noise shunt voltage reference

62 1 U401 IC

LFCSP CP-32-2

63 1 U702 IC

SC70, MAA06A

64 1 U703 IC

SC70, MAA06A

65 1 U701 IC 8-SOIC

AD9515BCPZ, 1.6 GHz clock distribution IC

NC7WZ07P6X_NL, UHS dual buffer

NC7WZ16P6X_NL, UHS dual buffer

Flash prog

Analog Devices AD9515BCPZ

Fairchild NC7WZ07P6X_NL

Fairchild NC7WZ16P6X_NL

Microchip PIC12F629-I/SNG mem 1kx14, RAM size 64 × 8, 20 MHz speed, PIC12F controller series

1

This BOM is RoHS compliant.

Manufacturer Part Number

Rev. 0 | Page 54 of 56

AD9212

OUTLINE DIMENSIONS

7.50 REF

0.30

0.25

0.18 PIN 1

16

1

INDICATOR

7.25

7.10 SQ

6.95

0.25 MIN

64

17

1.00

0.85

0.80

SEATING

PLANE

12° MAX

9.00

BSC SQ

PIN 1 INDICATOR

TOP

VIEW

0.80 MAX

0.65 TYP

0.50 BSC

8.75

BSC SQ

0.20 REF

0.60 MAX

0.50

0.40

0.30

0.05 MAX

0.02 NOM

49

48

33

32

0.60 MAX

EXPOSED PAD

(BOTTOM VIEW)

COMPLIANT TO JEDEC S TANDARDS MO-220- VMMD-4

063006-B

Figure 87. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Octal

(CP-64-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9212BCPZ-40 AD9212BCPZRL7-401 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel CP-64-3 AD9212BCPZ-651 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-3 AD9212BCPZRL7-651 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel CP-64-3 AD9212-65EBZ1 Evaluation Board

1

Z = Pb-free part.

1

−40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-3

Rev. 0 | Page 55 of 56

AD9212

NOTES

Rev. 0 | Page 56 of 56

Analog Devices AD9212 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

REVISION HISTORY

SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL IMPEDANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

EQUIVALENT CIRCUITS

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

ANALOG INPUT CONSIDERATIONS

Differential Input Configurations

Single-Ended Input Configuration

CLOCK INPUT CONSIDERATIONS

Clock Duty Cycle Considerations

Clock Jitter Considerations

Power Dissipation and Power-Down Mode

Digital Outputs and Timing

SDIO/ODM Pin

SCLK/DTP Pin

CSB Pin

RBIAS Pin

Voltage Reference

Internal Reference Operation

External Reference Operation

SERIAL PORT INTERFACE (SPI)

HARDWARE INTERFACE

MEMORY MAP

READING THE MEMORY MAP TABLE

RESERVED LOCATIONS

DEFAULT VALUES

LOGIC LEVELS

Power and Ground Recommendations

Exposed Paddle Thermal Heat Slug Recommendations

EVALUATION BOARD

POWER SUPPLIES

INPUT SIGNALS

OUTPUT SIGNALS

DEFAULT OPERATION AND JUMPER SELECTION SETTINGS

ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION

OUTLINE DIMENSIONS

ORDERING GUIDE