Analog Devices AD9203 Datasheet

10-Bit, 40 MSPS, 3 V, 74 mW

SHA GAIN

A/D D/A

SHA GAIN

A/D D/A

A/D

CORRECTION LOGIC

AD9203

OUTPUT BUFFERS

10

+
–

0.5V

BANDGAP

REFERENCE

CLK AVDD DRVDD

STBY

3 STATE

OTR

D9 (MSB)

D0 (LSB)

DRVSSDFSPWRCONAVSS

CLAMP

CLAMPIN

AINP
AINN

REFTF
REFBF

VREF

REFSENSE

a

FEATURES
CMOS 10-Bit 40 MSPS Sampling A/D Converter
Power Dissipation: 74 mW (3 V Supply, 40 MSPS)

17 mW (3 V Supply, 5 MSPS)
Operation Between 2.7 V and 3.6 V Supply
Differential Nonlinearity: ⴞ0.25 LSB
Power-Down (Standby) Mode, 0.65 mW
ENOB: 9.55 @ f
Out-of-Range Indicator
Adjustable On-Chip Voltage Reference
IF Undersampling up to f
Input Range: 1 V to 2 V p-p Differential or Single-Ended
Adjustable Power Consumption
Internal Clamp Circuit

APPLICATIONS
CCD Imaging
Video
Portable Instrumentation
IF and Baseband Communications
Cable Modems
Medical Ultrasound

PRODUCT DESCRIPTION

The AD9203 is a monolithic low power, single supply, 10-bit,
40 MSPS analog-to-digital converter, with an on-chip voltage
reference. The AD9203 uses a multistage differential pipeline
architecture and guarantees no missing codes over the full oper­ating temperature range. Its input range may be adjusted be­tween 1 V and 2 V p-p.

The AD9203 has an onboard programmable reference. An
external reference can also be chosen to suit the dc accuracy and
temperature drift requirements of an application.

An external resistor can be used to reduce power consumption
when operating at lower sampling rates. This yields power sav­ings for users who do not require the maximum sample rate.
This feature is especially useful at sample rates far below 40
MSPS. Excellent performance is still achieved at reduced power.
For example, 9.7 ENOB performance may be realized with only
17 mW of power, using a 5 MHz clock.

A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary or
twos complementary output format by using the DFS pin. An
out-of-range signal (OTR) indicates an overflow condition that
can be used with the most significant bit to determine over or
under range.

The AD9203 can operate with a supply range from 2.7 V to

3.6 V, attractive for low power operation in high speed por­table applications.

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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

= 20 MHz

IN

= 130 MHz

IN

A/D Converter

AD9203

FUNCTIONAL BLOCK DIAGRAM

The AD9203 is specified over industrial (–40°C to +85°C)

temperature ranges and is available in a 28-lead TSSOP
package.

PRODUCT HIGHLIGHTS
Low Power

The AD9203 consumes 74 mW on a 3 V supply operating at
40 MSPS. In standby mode, power is reduced to 0.65 mW.

High Performance

Maintains better than 9.55 ENOB at 40 MSPS input signal
from dc to Nyquist.

Very Small Package

The AD9203 is available in a 28-lead TSSOP.

Programmable Power

The AD9203 power can be further reduced by using an external
resistor at lower sample rates.

Built-In Clamp Function

Allows dc restoration of video signals.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

(AVDD = +3 V, DRVDD = +3 V, FS = 40 MSPS, input span from 0.5 V to 2.5 V, Internal 1 V

AD9203–SPECIFICATIONS

Reference, PWRCON = AVDD, 50% clock duty cycle, T

Parameter Symbol Min Typ Max Units Conditions

RESOLUTION 10 Bits

MAX CONVERSION RATE F

S

40 MSPS

PIPELINE DELAY 5.5 Clock Cycles

DC ACCURACY

Differential Nonlinearity DNL ±0.25 ±0.7 LSB
Integral Nonlinearity INL ±0.65 ±1.4 LSB

Offset Error E
Gain Error E

ZS

FS

±0.6 ±2.8 % FSR
±0.7 ±4.0 % FSR

ANALOG INPUT

Input Voltage Range AIN 1 2 V p-p
Input Capacitance C
Aperture Delay T
Aperture Uncertainty (Jitter) T

IN

AP

AJ

1.4 pF Switched, Single-Ended

2.0 ns

1.2 ps rms
Input Bandwidth (–3 dB) BW 390 MHz
Input Referred Noise 0.3 mV

INTERNAL REFERENCE

Output Voltage (0.5 V Mode) VREF 0.5 V REFSENSE = VREF
Output Voltage (1 V Mode) VREF 1 V REFSENSE = GND

Output Voltage Tolerance (1 V Mode) ±5 ±30 mV

Load Regulation 0.65 1.2 mV 1.0 mA Load

POWER SUPPLY

Operating Voltage AVDD 2.7 3.0 3.6 V

DRVDD 2.7 3.0 3.6 V
Analog Supply Current IAVDD 20.1 22.0 mA
Digital Supply Current IDRVDD 4.4 6.0 mA f

9.5 14.0 mA f

Power Consumption 74 84.0 mW f

88.8 108.0 mW f

Power-Down P

D

0.65 1.2 mW

IN

IN

IN

IN

Power Supply Rejection Ratio PSRR 0.04 ±0.25 % FS

DYNAMIC PERFORMANCE

(AIN = 0.5 dBFS)

Signal-to-Noise and Distortion SINAD Note 1

f = 4.8 MHz 59.7 dB
f = 20 MHz 57.2 59.3 dB

Effective Bits ENOB

f = 4.8 MHz 9.6 Bits Note 1
f = 20 MHz 9.2 9.55 Bits

Signal-to-Noise Ratio SNR

f = 4.8 MHz 60.0 dB
f = 20 MHz 57.5 59.5 dB

Total Harmonic Distortion THD

f = 4.8 MHz –76.0 dB Note 1
f = 20 MHz –74.0 –65.0 dB

Spurious Free Dynamic Range SFDR

f = 4.8 MHz 80 dB Note 1

f = 20 MHz 67.8 78 dB
Two-Tone Intermodulation Distortion IMD 68 dB f = 44.49 MHz and 45.52 MHz
Differential Phase DP 0.2 Degree NTSC 40 IRE Ramp
Differential Gain DG 0.3 %

DIGITAL INPUTS

High Input Voltage V
Low Input Voltage V

IH

IL

2.0 V

0.4 V
Clock Pulsewidth High 11.25 ns
Clock Pulsewidth Low 11.25 ns
Clock Period

2

25 ns

to T

MIN

unless otherwise noted.)

MAX

= 4.8 MHz, Output Bus Load = 10 pF
= 20 MHz, Output Bus Load = 20 pF
= 4.8 MHz, Output Bus Load = 10 pF
= 20 MHz, Output Bus Load = 20 pF

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Parameter Symbol Min Typ Max Units Conditions

DIGITAL OUTPUTS

High-Z Leakage I
Data Valid Delay t
Data Enable Delay t
Data High-Z Delay t

OZ

OD

DEN

DHZ

±5.0 µA Output = 0 to DRVDD

5nsC
6nsC
6nsC

= 20 pF

L

= 20 pF

L

= 20 pF

L

LOGIC OUTPUT (with DRVDD = 3 V)

High Level Output Voltage (I
High Level Output Voltage (I
Low Level Output Voltage (I
Low Level Output Voltage (I

NOTES

1

Differential Input (2 V p-p).

2

The AD9203 will convert at clock rates as low as 20 kHz.

Specifications subject to change without notice.

= 50 µA) V

OH

= 0.5 mA) V

OH

= 1.6 mA) V

OL

= 50 µA) V

OL

ANALOG

INPUT

N–1

OH

OH

OL

OL

+2.95 V
+2.80 V

+0.3 V
+0.05 V

N+1

N

N+2

N+3

N+4

N+5

N+6

AD9203

CLOCK

DATA

OUT

N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1

TOD = 3ns MIN

7ns MAX
(C

= 20pF)

LOAD

Figure 1. Timing Diagram

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–3–

AD9203

ABSOLUTE MAXIMUM RATINGS*

With
Respect

Parameter to Min Max Units

AVDD AVSS –0.3 +3.9 V
DRVDD DRVSS –0.3 +3.9 V
AVSS DRVSS –0.3 +0.3 V
AVDD DRVDD –3.9 +3.9 V
REFCOM AVSS –0.3 +0.3 V
CLK AVSS –0.3 AVDD + 0.3 V
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V
AINP AINN AVSS – 0.3 AVDD + 0.3 V
VREF AVSS –0.3 AVDD + 0.3 V
REFSENSE AVSS –0.3 AVDD + 0.3 V
REFTF, REFBF AVSS –0.3 AVDD + 0.3 V
STBY AVSS –0.3 AVDD + 0.3 V
CLAMP AVSS –0.3 AVDD + 0.3 V
CLAMPIN AVSS –0.3 AVDD + 0.3 V
PWRCON AVSS –0.3 AVDD + 0.3 V
DFS AVSS –0.3 AVDD + 0.3 V
3-STATE AVSS –0.3 AVDD + 0.3 V

Junction Temperature +150 °C
Storage Temperature –65 +150 °C

Lead Temperature

(10 sec) +300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

28-Lead TSSOP

= 97.9°C/W

θ

JA

= 14.0°C/W

θ

JC

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD9203ARU –40°C to +85°C 28-Lead Thin Shrink RU-28

Small Outline

AD9203-EB Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9203 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

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TOP VIEW

(Not to Scale)

AD9203

DFS

OTR

(MSB) D9

D8

D7

D6

D5

DRVSS
DRVDD

(LSB) D0

D1

D4

D3

D2

CLK

3-STATE

STBY

REFSENSE

CLAMP

CLAMPIN

PWRCON

AVDD
AVSS
AINN
AINP

REFTF

VREF

REFBF

1
2
3
4
5
6
7
8

9
10
11
12
13
14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

AD9203

PIN CONFIGURATION

PIN FUNCTION DESCRIPTIONS

Pin Name Description

1 DRVSS Digital Ground
2 DRVDD Digital Supply
3 D0 Bit 0, Least Significant Bit
4 D1 Bit 1
5 D2 Bit 2
6 D3 Bit 3
7 D4 Bit 4
8 D5 Bit 5
9 D6 Bit 6
10 D7 Bit 7
11 D8 Bit 8
12 D9 Bit 9, Most Significant Bit
13 OTR Out-of-Range Indicator
14 DFS Data Format Select. (HI: Twos Complement. LO: Straight Binary)
15 CLK Clock Input
16 3-STATE HI: High Impedance State Output. LO: Active Digital Output Drives
17 STBY HI: Power-Down Mode. LO: Normal Operation
18 REFSENSE Reference Select
19 CLAMP HI: Enable Clamp. LO: Open Clamp
20 CLAMPIN Clamp Signal Input
21 PWRCON Power Control Input
22 REFTF Top Reference Decoupling
23 VREF Reference In/Out
24 REFBF Bottom Reference Decoupling
25 AINP Noninverting Analog Input
26 AINN Inverting Analog Input
27 AVSS Analog Ground
28 AVDD Analog Supply

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AD9203

DEFINITIONS OF SPECIFICATIONS

INTEGRAL NONLINEARITY ERROR (INL)

Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as “negative full scale” occurs
1/2 LSB before the first code transition. “Positive full scale” is
defined as a level 1 1/2 LSB beyond the last code transition.
The deviation is measured from the middle of each particular
code to the true straight line.

DIFFERENTIAL NONLINEARITY ERROR (DNL, NO
MISSING CODES)

An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 10-bit resolution indicates that all 1024
codes respectively, must be present over all operating ranges.

SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIO

S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.

EFFECTIVE NUMBER OF BITS (ENOB)

For a sine wave, SINAD can be expressed in terms of the num­ber of bits. Using the following formula,

N = (SINAD – 1.76)/6.02

it is possible to get a measure of performance expressed as N,
the effective number of bits.

Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.

TOTAL HARMONIC DISTORTION (THD)

THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal and
is expressed as a percentage or in decibels.

SPURIOUS FREE DYNAMIC RANGE (SFDR)

The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.

OFFSET ERROR

First transition should occur for an analog value 1/2 LSB above
–full scale. Offset error is defined as the deviation of the actual
transition from that point.

GAIN ERROR

The first code transition should occur at an analog value
1/2 LSB above –full scale. The last transition should occur for
an analog value 1 1/2 LSB below the +full scale. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.

POWER SUPPLY REJECTION

The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value with
the supply at its maximum limit.

APERTURE JITTER

Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.

APERTURE DELAY

Aperture delay is a measure of the Sample-and-Hold Amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.

PIPELINE DELAY (LATENCY)

The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided on every rising edge.

SIGNAL-TO-NOISE RATIO (SNR)

SNR is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding harmonics and dc. The value for
SNR is expressed in decibels.

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