ANALOG DEVICES AD9125 Service Manual

Dual, 16-Bit, 1000 MSPS,

TxDAC+ Digital-to-Analog Converter

FEATURES

Flexible CMOS interface allows dual-word, word, or byte load Single-carrier W-CDMA ACLR = 80 dBc at 122.88 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, R Novel 2×/4×/8× interpolator/complex modulator allows

carrier placement anywhere in the DAC bandwidth Gain and phase adjustment for sideband suppression Multichip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter Low power: 900 mW at 500 MSPS, full operating conditions 72-lead, exposed paddle LFCSP

APPLICATIONS

Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, point-to-point Cable modem termination systems

= 25 Ω to 50 Ω

L

AD9125

GENERAL DESCRIPTION

The AD9125 is a dual, 16-bit, high dynamic range TxDAC+® digital-to-analog converter (DAC) that provides a sample rate of 1000 MSPS, permitting a multicarrier generation up to the Nyquist frequency. It includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface allows programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9125 comes in a 72-lead LFCSP.

PRODUCT HIGHLIGHTS

1. Ultralow noise and intermodulation distortion (IMD)

enable high quality synthesis of wideband signals from baseband to high intermediate frequencies.

2. A proprietary DAC output switching technique enhances

dynamic performance.

3. The current outputs are easily configured for various

single-ended or differential circuit topologies.

4. The flexible CMOS digital interface allows the standard

32-wire bus to be reduced to a 16-wire bus.

TYPICAL SIGNAL CHAIN

COMPLEX BAS EBAND

DC

2

DIGITAL

BASEBAND

PROCESSOR

NOTES

1. AQM = ANALOG QUADRATURE MODULATOR.

SIN

COS

2

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

COMPL E X I F

2/4

RF

f

IF

I DAC

ANTIALIASING

FILTER

Q DAC

Figure 1.

LO – f

IF

AQM

LO

PA

09016-001

AD9125

REVISION HISTORY

6/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 56

AD9125

FUNCTIONAL BLOCK DIAGRAM

D[31:0]

DCI

FRAME

f

/2

DATA

PRE

FIFO HB1 HB2 HB3

DATA

RECEIVER

MODE

PROGRAMMING

REGISTERS

MOD

SERIAL

INPUT/OUTPUT

PORT

SDO

NCO AND MOD

HB1_CLK

INTERNAL CL OCK TIMING AND CONT ROL LOGIC

CS

SDIO

IRQ

SCLK

10

HB2_CLK

HB3_CLK

INTP

FACTOR

PHASE

CORRECTION

POWER-ON

RESET

MULTICHIP

SYNCHRONIZATION

SYNC

Figure 2. AD9125 Functional Block Diagram

16

I OFFSET

Q OFFSET

16

INV

SINC

16

INVSINC_CLK

PLL CONTROL

DACCLK

PLL_LOCK

GAIN 110GAIN 2

10

DAC CLK_SEL

0

1

MULTIPLIER

(2× TO 16×)

DACCLK

CLOCK

1.2G DAC 1

16-BIT

1.2G DAC 1

16-BIT

REF AND

BIAS

AUX

CLK

RCVR

CLK

RCVR

IOUT1P

IOUT1N

IOUT2P

IOUT2N

REFIO FSADJ

DACCLKP DACCLKN

REFCLKP REFCLKN

09016-002

Rev. 0 | Page 3 of 56

AD9125

SPECIFICATIONS

DC SPECIFICATIONS

T

to T

MIN

Table 1.

Parameter Min Typ Max Unit

RESOLUTION 16 Bits ACCURACY

Differential Nonlinearity (DNL) ±2.1 LSB Integral Nonlinearity (INL) ±3.7 LSB

MAIN DAC OUTPUTS

Offset Error −0.001 0 +0.001 % FSR Gain Error (with Internal Reference) −3.6 ±2 +3.6 % FSR Full-Scale Output Current1 8.66 19.6 31.66 mA Output Compliance Range −1.0 +1.0 V Output Resistance 10 MΩ Gain DAC Monotonicity Guaranteed Settling Time to Within ±0.5 LSB 20 ns

MAIN DAC TEMPERATURE DRIFT

Offset 0.04 ppm/°C Gain 100 ppm/°C Reference Voltage 30 ppm/°C

REFERENCE

Internal Reference Voltage 1.2 V Output Resistance 5 kΩ

ANALOG SUPPLY VOLTAGES

AVDD33 3.13 3.3 3.47 V CVDD18 1.71 1.8 1.89 V

DIGITAL SUPPLY VOLTAGES

DVDD18 1.71 1.8 1.89 V IOVDD 1.71 1.8/3.3 3.47 V

POWER CONSUMPTION

2× Mode, f 2× Mode, f 8× Mode, f AVDD33 55 58 mA CVDD18 78 85 mA DVDD18 440 490 mA Power-Down Mode 1.5 2.7 mW Power Supply Rejection Ratio, AVDD33 −0.3 +0.3 % FSR/V

OPERATING RANGE −40 +25 +85 °C

1

Based on a 10 kΩ external resistor.

, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I

MAX

= 491.52 MSPS, IF = 10 MHz, PLL Off 834 mW

DAC

= 491.52 MSPS, IF = 10 MHz, PLL On 913 mW

DAC

= 800 MSPS, IF = 10 MHz, PLL Off 1114 1227 mW

DAC

= 20 mA, maximum sample rate, unless otherwise noted.

OUTFS

Rev. 0 | Page 4 of 56

AD9125

DIGITAL SPECIFICATIONS

T

to T

MIN

otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

CMOS DATA INPUTS

Input VIN Logic High 1.2 V

Input VIN Logic Low 0.6 V

Maximum Bus Speed 250 MHz

SERIAL PORT OUTPUT LOGIC LEVELS

Output V

IOVDD = 2.5 V 1.8 V

IOVDD = 3.3 V 2.0 V

Output V

IOVDD = 2.5 V 0.4 V

IOVDD = 3.3 V 0.4 V

SERIAL PORT INPUT LOGIC LEVELS

Input VIN Logic High IOVDD = 1.8 V 1.2 V

IOVDD = 2.5 V 1.6 V

IOVDD = 3.3 V 2.4 V

Input VIN Logic Low IOVDD = 1.8 V 0.6 V

IOVDD = 2.5 V 0.8 V

IOVDD = 3.3V 0.8 V

DACCLK INPUT (DACCLKP, DACCLKN)

Differential Peak-to-Peak Voltage 100 500 2000 mV

Common-Mode Voltage Self biased input, ac couple 1.25 V

Maximum Clock Rate 1000 MHz

REFCLK INPUT (REFCLKP, REFCLKN)

Differential Peak-to-Peak Voltage 100 500 2000 mV

Common-Mode Voltage 1.25 V

REFCLKx Frequency, PLL Mode 1 GHz ≤ f

REFCLKx Frequency, SYNC Mode See the Multichip Synchronization section for conditions 0 600 MHz

SERIAL PERIPHERAL INTERFACE

Maximum Clock Rate (SCLK) 40 MHz

Minimum Pulse Width High (t

Minimum Pulse Width Low (t

Setup Time, SDI to SCLK (tDS) 1.9 ns

Hold Time, SDI to SCLK (tDH) 0.2 ns

Data Valid, SDO to SCLK (tDV) 2.3 ns

Setup Time, CS to SCLK (t

, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I

MAX

Logic High IOVDD = 1.8 V 1.4 V

OUT

Logic Low IOVDD = 1.8 V 0.4

OUT

≤ 2.1 GHz 15.625 600 MHz

VCO

) 12.5 ns

PWH

) 12.5 ns

PWOL

) 1.4 ns

D

CS

= 20 mA, maximum sample rate, unless

OUTFS

LATENCY AND POWER-UP TIMING SPECIFICATIONS

Table 3.

Parameter Min Typ Max Unit

LATENCY (DACCLK Cycles)

1× Interpolation (with or Without Modulation) 64 Cycles

2× Interpolation (with or Without Modulation) 135 Cycles

4× Interpolation (with or Without Modulation) 292 Cycles

8× Interpolation (with or Without Modulation) 608 Cycles

Inverse Sinc 20 Cycles

Fine Modulation 8 Cycles

Power-Up Time 260 ms

Rev. 0 | Page 5 of 56

AD9125

AC SPECIFICATIONS

T

to T

MIN

Table 4.

Parameter Min Typ Max Unit

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f

DAC

f

DAC

f

DAC

f

DAC

TWO-TONE INTERMODULATION DISTORTION (IMD)

f

DAC

f

DAC

f

DAC

f

DAC

NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING

f

DAC

f

DAC

f

DAC

W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER

f

DAC

f

DAC

f

DAC

W-CDMA SECOND ACLR, SINGLE CARRIER

f

DAC

f

DAC

f

DAC

, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I

MAX

= 100 MSPS, f = 200 MSPS, f = 400 MSPS, f = 800 MSPS, f

= 200 MSPS, f = 400 MSPS, f = 400 MSPS, f = 800 MSPS, f

= 200 MSPS, f = 400 MSPS, f = 800 MSPS, f

= 491.52 MSPS, f = 491.52 MSPS, f = 983.04 MSPS, f

= 20 MHz 78 dBc

OUT

= 50 MHz 80 dBc

OUT

= 70 MHz 69 dBc

OUT

= 70 MHz 72 dBc

OUT

= 50 MHz 84 dBc

OUT

= 60 MHz 86 dBc

OUT

= 80 MHz 84 dBc

OUT

= 100 MHz 81 dBc

OUT

= 80 MHz −162 dBm/Hz

OUT

= 80 MHz −163 dBm/Hz

OUT

= 80 MHz −164 dBm/Hz

OUT

= 10 MHz 82 dBc

OUT

= 122.88 MHz 80 dBc

OUT

= 122.88 MHz 81 dBc

OUT

= 10 MHz 88 dBc

OUT

= 122.88 MHz 86 dBc

OUT

= 122.88 MHz 88 dBc

OUT

= 20 mA, maximum sample rate, unless otherwise noted.

OUTFS

Table 5. Interface Speeds

Mode Interpolation f

f

BUS

f

DATA

DAC

Byte Mode 1× 250 62.5 62.5 2× (HB1) 250 62.5 125 2× (HB2) 250 62.5 125 4× 250 62.5 250 8× 250 62.5 500 Word Mode 1× 250 125 125 2× (HB1) 250 125 250 2× (HB2) 250 125 250 4× 250 125 500 8× 250 125 1000 Dual-Word Mode 1× 250 250 250 2× (HB1) 250 250 500 2× (HB2) 250 250 500 4× 250 250 1000 8× 125 125 1000

Rev. 0 | Page 6 of 56

AD9125

ABSOLUTE MAXIMUM RATINGS

Table 6.

With

Parameter

AVDD33

IOVDD

DVDD18, CVDD18

AVS S

EPAD

CVSS

DVSS

FSADJ, REFIO,

IOUT1P/IOUT1N,

IOUT2P/IOUT2N

D[31:0], FRAME, DCI EPAD, DVSS −0.3 V to DVDD18 + 0.3 V DACCLKP/DACCLKN,

REFCLKP/REFCLKN

RESET, IRQ, CS, SCLK,

SDIO, SDO

Junction Temperature 125°C Storage Temperature

Range

Respect To Rating

AVSS, EPAD, CVSS, DVSS

EPAD, CVSS, DVSS

AVSS, CVSS, DVSS

AVSS, EPAD, DVSS

AVSS, EPAD, CVSS

AVSS −0.3 V to AVDD33 + 0.3 V

DVSS −0.3 V to CVDD18 + 0.3 V

EPAD, DVSS −0.3 V to IOVDD + 0.3 V

−65°C to +150°C

−0.3 V to +3.6 V

−0.3 V to +2.1 V

−0.3 V to +0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

The exposed paddle (EPAD) must be soldered to the ground plane for the 72-lead LFCSP. The EPAD performs as an electrical and thermal connection to the board.

Typical θ

, θJB, and θJC values are specified for a 4-layer board in

JA

still air. Airflow increases heat dissipation, effectively reducing θ

and θJB.

JA

Table 7. Thermal Resistance

Package θJA θJB θJC Unit Conditions

72-Lead LFCSP 20.7 10.9 1.1 °C/W EPAD soldered

ESD CAUTION

Rev. 0 | Page 7 of 56

AD9125

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CVDD18

REFCLKP

REFCLKN

AVDD33

IOUT1P

IOUT1N

AVDD33

AVSS

FSADJ

REFIO

AVSS

AVDD33

IOUT2N

IOUT2P

AVDD33

AVSS

NC

7271706968676665646362616059585756

55

CVDD18 DACCLKP DACCLKN

DVDD18

NOTES

1. NC = NO CONNECT.

2. EXPOSED PAD MUST BE CONNECTED TO AVSS.

CVSS

FRAME

NC IRQ D31 D30

NC

IOVDD

D29 D28 D27 D26

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17D25 18D24

PIN 1 INDICATOR

(Not to S cale)

192021222324252627282930313233

D23

D22

D21

D20

D19

D18

D17

AD9125

TOP VIEW

NC

DCI

D16

DVSS

DVDD18

D15

D14

D13

34

D12

35D11

36D10

54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37

RESET CS SCLK SDIO SDO DVDD18 D0 D1 D2 D3 DVSS DVDD18 D4 D5 D6 D7 D8 D9

09016-003

Figure 3. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

1 CVDD18 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. 2 DACCLKP DAC Clock Input, Positive. 3 DACCLKN DAC Clock Input, Negative. 4 CVSS Clock Supply Common. 5 FRAME Frame Input. 6 NC No Connect 7

IRQ

(INT)

Interrupt Request. Open Drain, Active Low Output. Connect external pull-up to IOVDD. 8 D31 Data Bit 31. 9 D30 Data Bit 30. 10 NC No Connect. 11 IOVDD

Supply for Serial Port Pin, RESET

Pin, and IRQ Pin. 1.8 V to 3.3 V can be applied to this pin. 12 DVDD18 1.8 V Digital Supply. Supplies power to digital core and digital data ports. 13 D29 Data Bit 29. 14 D28 Data Bit 28. 15 D27 Data Bit 27. 16 D26 Data Bit 26. 17 D25 Data Bit 25. 18 D24 Data Bit 24. 19 D23 Data Bit 23. 20 D22 Data Bit 22. 21 D21 Data Bit 21. 22 D20 Data Bit 20. 23 D19 Data Bit 19. 24 D18 Data Bit 18. 25 D17 Data Bit 17. 26 D16 Data Bit 16. 27 DCI Data Clock Input.

Rev. 0 | Page 8 of 56

AD9125

Pin No. Mnemonic Description

28 NC No Connect. 29 DVDD18 1.8 V Digital Supply. 30 DVSS Digital Common. 31 D15 Data Bit 15. 32 D14 Data Bit 14. 33 D13 Data Bit 13. 34 D12 Data Bit 12. 35 D11 Data Bit 11. 36 D10 Data Bit 10. 37 D9 Data Bit 9. 38 D8 Data Bit 8. 39 D7 Data Bit 7. 40 D6 Data Bit 6. 41 D5 Data Bit 5. 42 D4 Data Bit 4. 43 DVDD18 1.8 V Digital Supply. 44 DVSS Digital Supply Common. 45 D3 Data Bit 3. 46 D2 Data Bit 2. 47 D1 Data Bit 1. 48 D0 Data Bit 0. 49 DVDD18 1.8 V Digital Supply. 50 SDO Serial Port Data Output (CMOS levels with respect to IOVDD). 51 SDIO Serial Port Data Input/Output (CMOS levels with respect to IOVDD). 52 SCLK Serial Port Clock Input (CMOS levels with respect to IOVDD). 53

54 55 NC No Connect.

56 AVSS Analog Supply Common. 57 AVDD33 3.3 V Analog Supply. 58 IOUT2P Q DAC Positive Current Output. 59 IOUT2N Q DAC Negative Current Output. 60 AVDD33 3.3 V Analog Supply. 61 AVSS Analog Supply Common. 62 REFIO Voltage Reference. Nominally 1.2 V output. Should be decoupled to analog common. 63 FSADJ Full-Scale Current Output Adjust. Place a 10 kΩ resistor on the analog common. 64 AVSS Analog Common. 65 AVDD33 3.3 V Analog Supply. 66 IOUT1N I DAC Negative Current Output. 67 IOUT1P I DAC Positive Current Output. 68 AVDD33 3.3 V Analog Supply. 69 REFCLKN PLL Reference Clock Input, Negative. This pin has a secondary function as the SYNC input. 70 REFCLKP PLL Reference Clock Input, Positive. This pin has a secondary function as the SYNC input. 71 CVDD18 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. 72 CVDD18 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. EPAD

CS RESET

Serial Port Chip Select. Active Low (CMOS levels with respect to IOVDD). Reset. Active Low (CMOS levels with respect to IOVDD).

Exposed pad must be connected to AVSS. This provides an electrical, thermal, and mechanical connection to the PCB.

Rev. 0 | Page 9 of 56

AD9125

TYPICAL PERFORMANCE CHARACTERISTICS

0

f

= 125MSPS, S E COND HARMONIC

DATA

f

–10

–20

–30

–40

–50

–60

HARMONICS (dBc)

–70

–80

–90

–100

0 50 100 150 200 250 300

Figure 4. Harmonics vs. f

= 125MSPS, THIRD HARMONIC

DATA

f

= 250MSPS, S E COND HARMONIC

DATA

f

= 250MSPS, THIRD HARMONIC

DATA

f

(MHz)

OUT

over f

OUT

Digital Scale = 0 dBFS, f

, 2× Interpolation,

DATA

= 20 mA

SC

09016-101

–50

–55

–60

–65

–70

–75

HARMONICS (dBc)

–80

–85

–90

Figure 7. Second Harmonic vs. f

0dBFS –6dBFS –12dBFS –18dBFS

0 50 100150200250300

f

(MHz)

OUT

over Digital Scale, 2× Interpolation,

OUT

= 250 MSPS, fSC = 20 mA

f

DATA

09016-104

0

f

= 125MSPS, S E COND HARMONIC

DATA

f

–10

–20

–30

–40

–50

–60

HARMONICS (d Bc)

–70

–80

–90

–100

0 100 200 300 400 500 600

Figure 5. Harmonics vs. f

0

–10

–20

–30

–40

–50

–60

HARMONICS (dBc)

–70

–80

–90

–100

0 100 200 300 400 500 600

Figure 6. Harmonics vs. f

= 125MSPS, THIRD HARMONIC

DATA

f

= 250MSPS, S E COND HARMONIC

DATA

f

= 250MSPS, THIRD HARMONIC

DATA

f

(MHz)

OUT

over f

OUT

Digital Scale = 0 dBFS, f

f

= 125MSPS, S E COND HARMONIC

DATA

f

= 125MSPS, THIRD HARMONIC

DATA

f

(MHz)

OUT

over f

OUT

Digital Scale = 0 dBFS, f

, 4× Interpolation,

DATA

= 20 mA

SC

, 8× Interpolation,

DATA

= 20 mA

SC

–50

–55

–60

–65

–70

–75

–80

HARMONICS (d Bc)

–85

–90

–95

–100

09016-102

Figure 8. Third Harmonic vs. f

–50

–55

–60

–65

–70

–75

–80

HARMONICS (dBc)

–85

–90

–95

09016-103

0dBFS –6dBFS –12dBFS –18dBFS

0 50 100150200250300

f

(MHz)

OUT

over Digital Scale, 2× Interpolation,

OUT

= 250 MSPS, fSC = 20 mA

f

DATA

10mA, SECOND HARMONI C 20mA, SECOND HARMONI C 30mA, SECOND HARMONI C 10mA, THIRD HARMONIC 20mA, THIRD HARMONIC 30mA, THIRD HARMONIC

0 50 100150200250300

f

(MHz)

OUT

Figure 9. Harmonics vs. f

= 250 MSPS, Digital Scale = 0 dBFS

f

DATA

over fSC, 2× Interpolation,

OUT

09016-105

09016-106

Rev. 0 | Page 10 of 56

AD9125

–50

–55

–60

–65

–70

–75

–80

–85

HIGHEST DIGITAL S P UR ( dBc)

–90

–95

Figure 10. Highest Digital Spur vs. f

f

= 125MSPS

DATA

f

= 250MSPS

DATA

0 50 100 150 200 250 300

f

(MHz)

OUT

Digital Scale = 0 dBFS, f

OUT

over f

, 2× Interpolation,

DATA

= 20 mA

SC

2× INTERPO LATION, SINGLE-TONE SPECTRUM,

f

= 250MSPS,

DATA

f

= 101MHz

OUT

START 1.0 MHz #RES BW 10kHz

09016-107

VBW 10kHz STOP 500.0M Hz

SWEEP 6.017s (601 PTS)

09016-110

Figure 13. 2× Interpolation, Single-Tone Spectrum

–50

–55

–60

–65

–70

–75

–80

HIGHEST DIGITAL S P UR ( dBc)

–85

–90

Figure 11. Highest Digital Spur vs. f

–50

–55

–60

–65

–70

–75

–80

–85

HIGHEST DIGITAL S P UR ( dBc)

–90

–95

Figure 12. Highest Digital Spur vs. f

f

= 125MSPS

DATA

f

= 250MSPS

DATA

0 100 200 300 400 500 600

f

(MHz)

OUT

040035030025020015010050

Digital Scale = 0 dBFS, f

f

= 125MSPS

DATA

Digital Scale = 0 dBFS, f

f

OUT

(MHz)

OUT

over f

, 4× Interpolation,

DATA

= 20 mA

SC

, 8× Interpolation,

DATA

= 20 mA

SC

4× INTERPO LATION, SINGLE-TONE SPECTRUM,

f

= 125MSPS,

DATA

f

= 101MHz

OUT

START 1.0 MHz #RES BW 10kHz

09016-108

VBW 10kHz STOP 500.0M Hz

SWEEP 6.017s (601 PTS)

09016-111

Figure 14. 4× Interpolation, Single-Tone Spectrum

8× INTERPO LATION, SINGLE-TONE SPECTRUM,

f

= 125MSPS,

DATA

f

= 131MHz

OUT

START 1.0 MHz #RES BW 10kHz

09016-109

VBW 10kHz STOP 1.0G Hz

SWEEP 12.05s (601 PTS)

09016-112

Figure 15. 8× Interpolation, Single-Tone Spectrum

Rev. 0 | Page 11 of 56

AD9125

–50

–55

–60

f

DATA

f

DATA

= 125MSPS = 250MSPS

–50

–55

–60

0dBFS –6dBFS –12dBFS –18dBFS

–65

–70

IMD (dBc)

–75

–80

–85

–90

0 50 100 150 200 250 300

f

(MHz)

OUT

–50

–55

–60

–65

–70

IMD (dBc)

–75

–80

–85

Figure 16. IMD vs. f

Digital Scale = 0 dBFS, f

f

= 125MSPS

DATA

f

= 250MSPS

DATA

OUT

over f

, 2× Interpolation,

DATA

= 20 mA

SC

–65

–70

IMD (dBc)

–75

–80

–85

–90

0 50 100 150 200 250 300

f

(MHz)

09016-113

Figure 19. IMD vs. f

f

DATA

–50

–55

–60

–65

–70

IMD (dBc)

–75

–80

–85

20mA 30mA 10mA

OUT

over Digital Scale, 2× Interpolation,

OUT

= 250 MSPS, fSC = 20 mA

09016-116

–90

0 100 200 300 400 500 600

f

(MHz)

OUT

Figure 17. IMD vs. f

Digital Scale = 0 dBFS, f

–50

–55

–60

–65

–70

IMD (dBc)

–75

–80

–85

–90

f

= 125MSPS

DATA

0 100 200 300 400 500 600

Figure 18. IMD vs. f

Digital Scale = 0 dBFS, f

OUT

over f

f

OUT

over f

, 4× Interpolation,

DATA

= 20 mA

SC

(MHz)

, 8× Interpolation,

DATA

= 20 mA

SC

–90

0 50 100 150 200 250 300

f

(MHz)

09016-114

Figure 20. IMD vs. f

OUT

over fSC, 2× Interpolation, f

= 250 MSPS,

DATA

09016-117

Digital Scale = 0 dBFS

–40

–45

–50

–55

–60

–65

IMD (dBc)

–70

–75

–80

–85

–90

0 50 100 150 200 250 300

09016-115

PLL ON

PLL OFF

Figure 21. IMD vs. f

f

(MHz)

OUT

, PLL On vs. PLL Off

OUT

09016-118

Rev. 0 | Page 12 of 56

AD9125

–154

–156

–158

–160

–162

NSD (dBm/Hz)

–164

–166

–168

0600500400300200100

Figure 22. One-Tone NSD vs. f

Scale = 0 dBFS, f

2×,

f

DATA

4×,

f

DATA

8×,

f

DATA

f

(MHz)

OUT

over Interpolation Rate and f

OUT

= 20 mA, PLL Off

SC

= 250MSPS = 125MSPS = 125MSPS

DATA

09016-119

, Digital

–160

–161

–162

–163

NSD (dBm/Hz)

–164

–165

–166

Figure 25. Eight-Tone NSD vs. f

2×,

f

= 250MSPS

DATA

4×,

f

= 125MSPS

DATA

8×,

f

= 125MSPS

DATA

0 50 100 150 200 250 300 350 400 500450

f

(MHz)

OUT

over Interpolation Rate and f

OUT

Digital Scale = 0 dBFS, f

= 20 mA, PLL Off

SC

DATA

09016-122

,

–154

–156

–158

–160

–162

NSD (dBm/Hz)

–164

–166

–168

0dBFS –6dBFS –12dBFS –18dBFS

025020015010050

Figure 23. One-Tone NSD vs. f

4× Interpolation, f

–158

–159

–160

–161

–162

–163

NSD (dBm/Hz)

–164

–165

–166

–167

8×,

0600500400300200100

f

DATA

= 125MSPS

Figure 24. One-Tone NSD vs. f

Digital Scale = 0 dBFS, f

f

(MHz)

OUT

over Digital Scale, f

OUT

= 20 mA, PLL Off

SC

f

(MHz)

OUT

over Interpolation Rate and f

OUT

= 20 mA, PLL On

SC

DATA

= 200 MSPS,

,

DATA

–161.5

–162.0

–162.5

–163.0

–163.5

–164.0

–164.5

NSD (dBm/Hz)

–165.0

–165.5

–166.0

–166.5

09016-120

Figure 26. Eight-Tone NSD vs. f

–160

–161

–162

–163

–164

NSD (dBm/Hz)

–165

–166

–167

09016-121

Figure 27. Eight-Tone NSD vs. f

0dBFS –6dBFS –12dBFS –18dBFS

0 50 100 150 200 250

f

(MHz)

OUT

over Digital Scale, f

OUT

4× Interpolation, f

8×,

f

= 125MSPS

DATA

0 100 200 300 500400 600

Digital Scale = 0 dBFS, f

= 20 mA, PLL Off

SC

f

(MHz)

OUT

over Interpolation Rate and f

OUT

= 20 mA, PLL On

SC

= 200 MSPS,

DATA

09016-123

09016-124

,

Rev. 0 | Page 13 of 56

AD9125

ACLR (dBc)

–77

–78

–79

–80

–81

–82

–83

0dBFS –3dBFS –6dBFS

ACLR (dBc)

–50

–55

–60

–65

–70

–75

–80

–85

2×, PLL OFF 4×, PLL OFF 2×, PLL ON 4×, PLL ON

–84

0 50 100 150 200 250

f

(MHz)

OUT

Figure 28. One-Carrier W-CDMA ACLR vs. f

over Digital Cutback,

OUT

Adjacent Channel, PLL Off

–78

–80

–82

–84

ACLR (dBc)

–86

–88

–90

0dBFS –3dBFS –6dBFS

0 50 100 150 200 250

f

(MHz)

OUT

Figure 29. One-Carrier W-CDMA ACLR vs. f

OUT

Alternate Channel, PLL Off

–70

–75

0dBFS –3dBFS –6dBFS

over f

DAC

–90

0 100 200 300 400 500

f

(MHz)

09016-125

Figure 31. One-Carrier W-CDMA ACLR vs. f

OUT

over Interpolation Rate,

OUT

09016-128

Adjacent Channel, PLL On vs. PLL Off

–70

–72

–74

–76

–78

–80

–82

ACLR (dBc)

–84

–86

–88

–90

09016-126

,

Figure 32. One-Carrier W-CDMA ACLR vs. f

2×, PLL OFF 4×, PLL OFF 2×, PLL ON 4×, PLL ON

0 100 200 300 400 500

f

(MHz)

OUT

over Interpolation Rate,

OUT

09016-129

Alternate Channel, PLL On vs. PLL Off

–70

–75

2×, PLL OFF 4×, PLL OFF 2×, PLL ON 4×, PLL ON

–80

–85

ACLR (dBc)

–90

–95

0 50 100 150 200 250

f

(MHz)

OUT

Figure 30. One-Carrier W-CDMA ACLR vs. f

OUT

Second Alternate Channel, PLL Off

over f

DAC

09016-127

,

Rev. 0 | Page 14 of 56

–80

ACLR (dBc)

–85

–90

–95

0 100 200 300 400 500

f

(MHz)

OUT

Figure 33. One-Carrier W-CDMA ACLR vs. f

over Interpolation Rate,

OUT

Second Alternate Channel, PLL On vs. PLL Off

09016-130

AD9125

START 133.06M Hz #RES BW 30kHz

RMS RESULTS FREQ LOWER UPPER

CARRIER POWER 5.00MHz 3.840MHz –75.96 –85.96 –77.13 –87.13 –10.00dBm/ 10.00MHz 3.840MHz –85.33 –95.33 –85.24 –95.25

3.840MHz 15.00MHz 2.888MHz –95.81 –95.81 –85.43 –95.43

OFFSET REF BW dBc dBm dBc dBm

VBW 30kHz STOP 166.94MHz

SWEEP 143.6ms (601 PTS)

Figure 34. Four-Carrier W-CDMA ACLR Performance, IF ≈150 MHz

START 125.88MHz #RES BW 30kHz

TOTAL CARRIER POWER: –11.19dBm/15.3600MHz RRC FILTER: OFF FILTER ALPHA 0.22 REF CARRIER POWER: –16.89dBm/3.84000MHz

09016-131

1 –16.92dBm 5.000MHz 3.840MHz –65.88 –82.76 –67.52 –84.40 2 –16.89dBm 10.00MHz 3.840MHz –68.17 –85.05 –69.91 –86.79 3 –17.43dBm 15.00MHz 3.840MHz –70.42 –87.31 –71.40 –88.28 4 –17.64dBm

OFFSET FREQ INTEG BW dBc dBm dBc dBm

VBW 30kHz S TOP 174.42M Hz

SWEEP 206.9ms (601 PTS)

LOWER UPPER

09016-132

Figure 35. One-Carrier W-CDMA ACLR Performance, IF ≈150 MHz

Rev. 0 | Page 15 of 56

AD9125

TERMINOLOGY

Integral Nonlinearity (INL)

INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.

Offset Error

The deviation of the output current from the ideal of zero is called offset error. For IOUT1P, 0 mA output is expected when the inputs are all 0s. For IOUT1N, 0 mA output is expected when all inputs are set to 1.

Gain Error

The difference between the actual and ideal output span. The actual span is determined by the difference between the outputs when all inputs are set to 1 vs. when all inputs are set to 0.

Output Compliance Range

The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance.

Temp er at u re D ri ft

Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T

MIN

or T

MAX

. For offset and gain drift, the drift is reported in ppm of fullscale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius.

Power Supply Rejection (PSR)

The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages.

Settling Time

The time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition.

Spurious-Free Dynamic Range (SFDR)

The difference in decibels between the peak amplitude of the output signal and the peak spurious signal within the dc to the Nyquist frequency of the DAC. Typically, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths to the DAC output.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.

Interpolation Filter

If the digital inputs to the DAC are sampled at a multiple rate of f

(interpolation rate), a digital filter can be constructed that

DATA

has a sharp transition band near f appear around f

(output data rate) can be greatly suppressed.

DAC

/2. Images that typically

DATA

Adjacent Channel Leakage Ratio (ACLR)

The ratio in decibels relative to the carrier (dBc) between the measured power within a channel and that of its adjacent channel.

Complex Image Rejection

In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.

DATA

DCI

LATCH

INPUT

f

INTERFACE

DATA

FORMAT

32

WRITE

POINTER

16

2

FIFO

16

2

READ

POINTER

f

/

f

DATA

HB1

Figure 36. Defining Data Rates

Rev. 0 | Page 16 of 56

f

SIN NCO COS

CLOCK GENERATOR

AND DISTRIBUTOR

/

f

NCO

HB2

16

22

f

HB3

I DAC

16

Q DAC

DACCLK

f

DAC

09016-136

AD9125

THEORY OF OPERATION

The AD9125 combines many features that make it a very attractive DAC for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface to common quadrature modulators when designing single sideband transmitters. The speed and performance of the AD9125 allows wider bandwidths and more carriers to be synthesized than in previously available DACs. In addition, these devices include an innovative low power, 32-bit, complex NCO that greatly increases the ease of frequency placement.

The AD9125 offers features that allow simplified synchronization with incoming data and between multiple devices. Auxiliary DACs are also provided on chip for output dc offset compensation (for local oscillator [LO] compensation in single sideband [SSB] transmitters) and for gain matching (for image rejection optimization in SSB transmitters).

SERIAL PORT OPERATION

The serial port is a flexible, synchronous serial communication port, allowing easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI® and Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD9125. Single- or multiple-byte transfers are supported, as well as MSBfirst or LSB-first transfer formats. The serial interface ports can be configured as a single-pin I/O (SDIO) or two unidirectional pins for input/output (SDIO/SDO).

50

SDO

51

SDIO

SCLK

Figure 37. Serial Port Interface Pins

There are two phases of a communication cycle with the AD9125. Phase 1 is the instruction cycle (the writing of an instruction byte into the device), which is coincident with the first eight SCLK rising edges. The instruction byte provides the serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the device.

A logic high on the

CS

pin followed by a logic low resets the serial port timing to the initial state of the instruction cycle. From this state, the next eight rising SCLK edges represent the instruction bits of the current I/O operation.

CS

SPI

PORT

52

53

09016-010

The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the device and the system controller. Phase 2 of the communication cycle is a transfer of one or more data bytes. Registers change immediately upon writing to the last bit of each transfer byte, except for the frequency tuning word and NCO phase offsets, which only change when the frequency update bit (Register 0x36, Bit 0) is set.

DATA FORMAT

The instruction byte contains the information shown in Tab l e 9 .

Table 9. Serial Port Instruction Byte

I7 (MSB) I6 I5 I4 I3 I2 I1 I0 (LSB)

R/W

A6 A5 A4 A3 A2 A1 A0

R/W, Bit 7 of the instruction byte, determines whether a read or write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation, and Logic 0 indicates a write operation.

A6 to A0, Bit 6 to Bit 0 of the instruction byte, determine the register that is accessed during the data transfer portion of the communication cycle. For multibyte transfers, A6 is the starting byte address. The remaining register addresses are generated by the device based on the LSB_FIRST bit (Register 0x00, Bit 6).

SERIAL PORT PIN DESCRIPTIONS

Serial Clock (SCLK)

The serial clock pin synchronizes data to and from the device and runs the internal state machines. The maximum frequency of SCLK is 40 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK.

Chip Select (

An active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communication lines. The SDO and SDIO pins go to a high impedance state when this input is high. During the communication cycle, the

Serial Data I/O (SDIO)

Data is always written into the device on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Register 0x00, Bit 7. The default is

Logic 0, configuring the SDIO pin as unidirectional.

Serial Data Out (SDO)

Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the device operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state.

CS

)

CS

pin should stay low.

Rev. 0 | Page 17 of 56

ANALOG DEVICES AD9125 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TYPICAL SIGNAL CHAIN

TABLE OF CONTENTS

REVISION HISTORY

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

DC SPECIFICATIONS

DIGITAL SPECIFICATIONS

LATENCY AND POWER-UP TIMING SPECIFICATIONS

AC SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

THEORY OF OPERATION

SERIAL PORT OPERATION

DATA FORMAT

SERIAL PORT PIN DESCRIPTIONS