ANALOG DEVICES AD9116 Service Manual
Dual Low Power, 8-/10-/12-/14-Bit
FEATURES
Power dissipation @ 3.3 V, 20 mA output
191 mW @ 10 MSPS
232 mW @ 125 MSPS
Sleep mode: <3 mW @ 3.3 V
Supply voltage: 1.8 V to 3.3 V
SFDR to Nyquist
86 dBc @ 1 MHz output
85 dBc @ 10 MHz output
AD9117 NSD @ 1 MHz output, 125 MSPS, 20 mA: −162 dBc/Hz
Differential current outputs: 4 mA to 20 mA
2 on-chip auxiliary DACs
CMOS inputs with single-port operation
Output common mode: adjustable 0 V to 1.2 V
Small footprint 40-lead LFCSP RoHS-compliant package
APPLICATIONS
Wireless infrastructures
Picocell, femtocell base stations
Medical instrumentation
Ultrasound transducer excitation
Portable instrumentation
Signal generators, arbitrary waveform generators
TxDAC Digital-to-Analog Converters
AD9114/AD9115/AD9116/AD9117
GENERAL DESCRIPTION
The AD9114/AD9115/AD9116/AD9117 are pin-compatible
dual, 8-/10-/12-/14-bit, low power digital-to-analog converters
(DACs) that provide a sample rate of 125 MSPS. These TxDAC®
converters are optimized for the transmit signal path of communication systems. All the devices share the same interface, package,
and pinout, providing an upward or downward component
selection path based on performance, resolution, and cost.
The AD9114/AD9115/AD9116/AD9117 offer exceptional ac and
dc performance and support update rates up to 125 MSPS.
The flexible power supply operating range of 1.8 V to 3.3 V and
low power dissipation of the AD9114/AD9115/AD9116/AD9117
make them well suited for portable and low power applications.
PRODUCT HIGHLIGHTS
1. Low Power. DACs operate on a single 1.8 V to 3.3 V supply;
total power consumption reduces to 225 mW at 100 MSPS.
Sleep and power-down modes are provided for low power
idle periods.
2. CMOS Clock Input. High speed, single-ended CMOS clock
input supports a 125 MSPS conversion rate.
3. Easy Interfacing to Other Components. Adjustable output
common mode from 0 V to 1.2 V allows for easy interfacing
to other components that accept common-mode levels
greater than 0 V.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved.
AD9114/AD9115/AD9116/AD9117
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications ..................................................................................... 5
DC Specifications ......................................................................... 5
Digital Specifications ................................................................... 7
AC Specifications .......................................................................... 8
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 18
Terminolog y .................................................................................... 31
Theory of Operation ...................................................................... 32
Serial Peripheral Interface (SPI) ................................................... 33
General Operation of the Serial Interface ............................... 33
Instruction Byte .......................................................................... 33
Serial Interface Port Pin Descriptions ..................................... 33
MSB/LSB Transfers..................................................................... 34
Serial Port Operation ................................................................. 34
Pin Mode ..................................................................................... 34
SPI Register Map ............................................................................. 35
SPI Register Descriptions .............................................................. 36
Digital Interface Operation ........................................................... 40
Digital Data Latching and Retimer Section ............................ 41
Estimating the Overall DAC Pipeline Delay........................... 42
Reference Operation .................................................................. 43
Reference Control Amplifier .................................................... 43
DAC Transfer Function ............................................................. 43
Analog Output ............................................................................ 44
Self-Calibration ........................................................................... 44
Coarse Gain Adjustment ........................................................... 45
Using the Internal Termination Resistors ............................... 46
Applications Information .............................................................. 47
Output Configurations .............................................................. 47
Differential Coupling Using a Transformer ............................... 47
Single-Ended Buffered Output Using an Op Amp ................ 47
Differential Buffered Output Using an Op Amp .................. 48
Auxiliary DACs ........................................................................... 48
DAC-to-Modulator Interfacing ................................................ 49
Correcting for Nonideal Performance of Quadrature
Modulators on the IF-to-RF Conversion ................................ 49
I/Q Channel Gain Matching ..................................................... 49
LO Feedthrough Compensation .............................................. 50
Results of Gain and Offset Correction .................................... 50
Modifying the Evaluation Board to Use the ADL5370 On-Board
Quadrature Modulator ................................................................ 51
Evaluation Board Schematics and Artwork ................................ 52
Schematics ................................................................................... 52
Silkscreens ................................................................................... 60
Bill of Materials ............................................................................... 75
Outline Dimensions ....................................................................... 78
Ordering Guide .......................................................................... 78
Rev. A | Page 2 of 80
AD9114/AD9115/AD9116/AD9117
REVISION HISTORY
3/09—Rev. 0 to Rev. A
Changes to Product Title and General Description Section ....... 1
Changes to Figure 1 ........................................................................... 4
Changed I
= 2 mA to I
OUTFS
= 20 mA..................................... 5
xOUTFS
Changes to Table 1 ............................................................................ 6
Changed I
= 2 mA to I
OUTFS
= 20 mA..................................... 7
xOUTFS
Changes to Table 2 ............................................................................ 7
Changed DVDDIO = 1.8 V to DVDDIO = 3.3 V, Table 3 and
CVDD = 3.3 V to CVDD = 1.8 V, Table 4 ..................................... 8
Changes to Table 5 and Table 6 ....................................................... 9
Changes to Table 7 .......................................................................... 10
Changes to Table 8 .......................................................................... 12
Changes to Table 9 .......................................................................... 14
Changes to Table 10 ........................................................................ 16
Changes to Typical Performance Characteristics Section ......... 18
Changes to Theory of Operation Section and Figure 84 ........... 32
Added Figure 85 to Figure 88; Renumbered Sequentially ......... 34
Changes to Table 13 ........................................................................ 35
Changes to Table 14 ........................................................................ 36
Changes to Digital Interface Operation Section and Figure 89,
Figure 90, Figure 91, Figure 92, and Figure 93 ............................ 40
Changes to Figure 94, Digital Data Latching Section, and
Retimer Section ............................................................................... 41
Added Reference Operation Section, Reference Control
Amplifier Section, DAC Transfer Function Section, Figure 96,
and Table 17 ..................................................................................... 43
Added Analog Output Section ...................................................... 44
Changes to Auxiliary DACs Section ............................................. 48
Changes to DAC to Modulator Interfacing Section, Figure 107,
and Figure 108 ................................................................................. 49
Added Figure 111 to Figure 133 .................................................... 52
Added Table 18 ................................................................................ 75
8/08—Revision 0: Initial Version
Rev. A | Page 3 of 80
AD9114/AD9115/AD9116/AD9117
FUNCTIONAL BLOCK DIAGRAM
DB12
DB13 (MSB)
CS/PW RDN
SDIO/FORMAT
SCLK/CLKMD
RESET/PINMD
REFIO
FSADJQ/AUXQ
FSADJI/AUXI
CMLI
DB11
DB10
DB9
DB8
DVDDIO
DVSS
DVDD
DB7
DB6
DB5
1.8V
LDO
DB4
INTERLEAVED
INTERFACE
DB3
DB2
SPI
INTERFACE
1 INTO 2
DATA
DB1
(LSB) DB0
I
REF
100µA
DCLKIO
1V
QR
BAND
GAP
I DATA
Q DATA
SET
2kΩ
10kΩ
CLOCK
DIST
CVDD
CLKIN
CVSS
IR
SET
2kΩ
AUX1DAC
AUX2DAC
AD9117
60Ω TO
I DAC
Q DAC
60Ω TO
IR
260Ω
QR
260Ω
CM
CM
CMLQ
62.5Ω
62.5Ω
62.5Ω
62.5Ω
RLIN
IOUTN
IOUTP
RLIP
AVDD
AVSS
RLQP
QOUTP
QOUTN
RLQN
07466-001
Figure 1.
Rev. A | Page 4 of 80
AD9114/AD9115/AD9116/AD9117
SPECIFICATIONS
DC SPECIFICATIONS
T
to T
MIN
, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, I
MAX
Table 1.
AD9114 AD9115 AD9116 AD9117
Parameter
RESOLUTION 8 10 12 14 Bits
ACCURACY, AVDD = DVDDIO =
CVDD = 3.3 V
Differential Nonlinearity (DNL)
Precalibration ±0.02 ±0.06 ±0.4 ±1.4 LSB
Postcalibration ±0.02 ±0.04 ±0.2 ±0.6 LSB
Integral Nonlinearity (INL)
Precalibration ±0.03 ±0.19 ±0.68 ±1.2 LSB
Postcalibration ±0.03 ±0.07 ±0.42 ±0.6 LSB
ACCURACY, AVDD = DVDDIO =
CVDD = 1.8 V
Differential Nonlinearity (DNL)
Precalibration ±0.02 ±0.08 ±0.5 ±1.8 LSB
Postcalibration ±0.01 ±0.06 ±0.2 ±1.0 LSB
Integral Nonlinearity (INL)
Precalibration ±0.04 ±0.2 ±0.5 ±1.8 LSB
Postcalibration ±0.02 ±0.1 ±0.3 ±1.1 LSB
MAIN DAC OUTPUTS
Offset Error −1 +1 −1 +1 −1 +1 −1 +1 mV
Gain Error Internal Reference −2 +2 −2 +2 −2 +2 −2 +2 % of FSR
Full-Scale Output Current1
AVDD = 3.3 V 2 8 20 2 8 20 2 8 20 2 8 20 mA
AVDD = 1.8 V 2 8 2 8 2 8 2 8 mA
Output Common-Mode Level
(8 mA CMLx Pin)
Output Resistance 200 200 200 200 MΩ
Crosstalk, Q DAC to I DAC
(f
= 30 MHz)
OUT
Crosstalk, Q DAC to I DAC
(f
= 60 MHz)
OUT
MAIN DAC TEMPERATURE DRIFT
Offset 0 0 0 0 ppm/°C
Gain ±40 ±40 ±40 ±40 ppm/°C
Reference Voltage ±25 ±25 ±25 ±25 ppm/°C
AUXDAC OUTPUTS
Resolution 10 10 10 10 Bits
Full-Scale Output Current
(Current Sourcing Mode)
Voltage Output Mode
Output Compliance Range
(Sourcing 1 mA)
Output Compliance Range
(Sinking 1 mA)
Output Resistance in Current
Output Mode AV
to 1 V
SS
AUXDAC Monotonicity
Guaranteed
−0.5 0 +1.2 −0.5 0 +1.2 −0.5 0 +1.2 −0.5 0 +1.2 V
95 95 95 95 dB
76 76 76 76 dB
125 125 125 125 μA
VSS VDD −
VSS VDD −
0.25
VSS +
V
0.25
VSS +
DD
V
0.25
1 1 1 1 MΩ
10 10 10 10 Bits
= 20 mA, maximum sample rate, unless otherwise noted.
xOUTFS
VSS VDD −
0.25
VSS +
DD
0.25
V
VSS VDD −
0.25
VSS +
DD
0.25
0.25
V
DD
Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max
V
V
Rev. A | Page 5 of 80
AD9114/AD9115/AD9116/AD9117
AD9114 AD9115 AD9116 AD9117
Parameter
REFERENCE OUTPUT
Internal Reference Voltage 0.98 1.025 1.08 0.98 1.025 1.08 0.98 1.025 1.08 0.98 1.025 1.08 V
Output Resistance 10 10 10 10 kΩ
REFERENCE INPUT
Voltage Compliance
AVDD = 3.3 V 0.1 1.25 0.1 1.25 0.1 1.25 0.1 1.25 V
AVDD = 1.8 V 0.1 1.0 0.1 1.0 0.1 1.0 0.1 1.0 V
Input Resistance External
1 1 1 1 MΩ
Reference Mode
DAC MATCHING
Gain Matching −1 +1 −1 +1 −1 +1 −1 +1 % of FSR
ANALOG SUPPLY VOLTAGES
AVDD 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 V
CVDD 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 V
DIGITAL SUPPLY VOLTAGES
DVDD 1.7 1.9 1.7 1.9 1.7 1.9 1.7 1.9 V
DVDDIO 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 V
POWER CONSUMPTION, AVDD =
DVDDIO = CVDD = 3.3 V
f
= 125 MSPS, IF = 12.5 MHz 220 220 220 220 mW
DAC
I
55 55 55 55 mA
AVDD
I
+ I
DVDD
I
CVDD
10 10 10 10 mA
DVDDIO
3 3 3 3 mA
Power-Down Mode with Clock 8.5 8.5 8.5 8.5 mW
Power-Down Mode No Clock 3 3 3 3 mW
Power Supply Rejection Ratio −0.009 −0.009 −0.009 −0.009 % FSR/V
POWER CONSUMPTION, AVDD =
DVDDIO = CVDD = 1.8 V
f
= 125 MSPS, IF = 12.5 MHz 58 58 58 58 mW
DAC
I
24 24 24 24 mA
AVDD
I
DVDD + IDVDDIO
I
CVDD
8 8 8 8 mA
2 2 2 2 mA
Power-Down Mode with Clock 12 12 12 12 mW
Power-Down Mode No Clock 850 850 850 850 μW
Power Supply Rejection Ratio −0.007 −0.007 −0.007 −0.007 % FSR/V
OPERATING RANGE −40 +25 +85 −40 +25 +85 −40 +25 +85 −40 +25 +85 °C
1
Based on a 10 kΩ external resistor.
Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Rev. A | Page 6 of 80
AD9114/AD9115/AD9116/AD9117
DIGITAL SPECIFICATIONS
T
to T
MIN
, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, I
MAX
Table 2.
Parameter Min Typ Max Unit
DAC CLOCK INPUT (CLKIN)
VIH 2.1 3 V
VIL 0 0.9 V
Maximum Clock Rate 125 MSPS
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK) 25 MHz
Minimum Pulse Width High 20 ns
Minimum Pulse Width Low 20 ns
INPUT DATA
1.8 V Q Channel or DCLKIO Falling Edge
Setup 0.25 ns
Hold 1.2 ns
1.8 V I Channel or DCLKIO Rising Edge
Setup 0.13 ns
Hold 1.1 ns
3.3 V Q Channel or DCLKIO Falling Edge
Setup −0.2 ns
Hold 1.5 ns
3.3 V I Channel or DCLKIO Rising Edge
Setup −0.2 ns
Hold 1.6 ns
VIH 2.1 3 V
VIL 0 0.9 V
= 20 mA, maximum sample rate, unless otherwise noted.
xOUTFS
Rev. A | Page 7 of 80
AD9114/AD9115/AD9116/AD9117
AC SPECIFICATIONS
T
to T
MIN
, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, I
MAX
Table 3.
Parameter
SPURIOUS FREE DYNAMIC RANGE
(SFDR)
f
= 125 MSPS, f
DAC
f
= 125 MSPS, f
DAC
= 10 MHz 76 85 85 85 dBc
OUT
= 50 MHz 55 55 55 55 dBc
OUT
TWO TONE INTERMODULATION
DISTORTION (IMD)
f
= 125 MSPS, f
DAC
f
= 125 MSPS, f
DAC
= 10 MHz 81 81 81 82 dBc
OUT
= 50 MHz 60 60 60 61 dBc
OUT
NOISE SPECTRAL DENSITY (NSD),
EIGHT-TONE, 500 kHz TONE SPACING
f
= 125 MSPS, f
DAC
f
= 125 MSPS, f
DAC
= 10 MHz −132 −143 −153 −157 dBc/Hz
OUT
= 50 MHz −128 −138 −146 −149 dBc/Hz
OUT
W-CDMA ADJACENT CHANNEL LEAKAGE
RATIO (ACLR), SINGLE CARRIER
f
= 61.44 MSPS, f
DAC
f
= 122.88 MSPS, f
DAC
= 20 MHz −78 −78 −78 −78 dBc
OUT
= 30 MHz −80 −80 −80 −80 dBc
OUT
AD9114 AD9115 AD9116 AD9117
= 20 mA, maximum sample rate, unless otherwise noted.
xOUTFS
Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max
T
to T
MIN
, AVDD = 1.8 V, DVDD = 1.8 V, DVDDIO = 1.8 V, CVDD = 1.8 V, I
MAX
Table 4.
Parameter
SPURIOUS FREE DYNAMIC RANGE
(SFDR)
f
= 125 MSPS, f
DAC
f
= 125 MSPS, f
DAC
= 10 MHz 73 76 76 76 dBc
OUT
= 50 MHz 48 48 48 48 dBc
OUT
TWO TONE INTERMODULATION
DISTORTION (IMD)
f
= 125 MSPS, f
DAC
f
= 125 MSPS, f
DAC
= 10 MHz 76 76 76 76 dBc
OUT
= 50 MHz 50 50 50 50 dBc
OUT
NOISE SPECTRAL DENSITY (NSD),
EIGHT-TONE, 500 kHz TONE SPACING
f
= 125 MSPS, f
DAC
f
= 125 MSPS, f
DAC
= 10 MHz −125 −136 −146 −150 dBc/Hz
OUT
= 50 MHz −117 −127 −135 −138 dBc/Hz
OUT
W-CDMA ADJACENT CHANNEL LEAKAGE
RATIO (ACLR), SINGLE CARRIER
f
= 61.44 MSPS, f
DAC
f
= 122.88 MSPS, f
DAC
= 20 MHz −69 −69 −69 −69 dBc
OUT
= 30 MHz −72 −72 −72 −72 dBc
OUT
= 8 mA, maximum sample rate, unless otherwise noted.
xOUTFS
AD9114 AD9115 AD9116 AD9117
Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Rev. A | Page 8 of 80
AD9114/AD9115/AD9116/AD9117
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
AVDD, DVDDIO, CVDD to AVSS,
−0.3 V to +3.9 V
DVSS, CVSS
DVDD to DVSS −0.3 V to +2.1 V
AVSS to DVSS, CVSS −0.3 V to +0.3 V
DVSS to AVSS, CVSS −0.3 V to +0.3 V
CVSS to AVSS, DVSS −0.3 V to +0.3 V
REFIO, FSADJQ, FSADJI, CMLQ,
−0.3 V to AVDD + 0.3 V
CMLI to AVSS
QOUTP, QOUTN, IOUTP, IOUTN,
−1.0 V to AVDD + 0.3 V
RLQP, RLQN, RLIP, RLIN to AVSS
DBn1 (MSB) to D0 (LSB), CS, SCLK,
−0.3 V to DVDDIO + 0.3 V
SDIO, RESET to DVSS
CLKIN to CVSS −0.3 V to CVDD + 0.3 V
Junction Temperature 125°C
Storage Temperature Range −65°C to +150°C
1
n stands for 7 for the AD9114, 9 for the AD9115, 11 for the AD9116, and 13
for the AD9117.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 6.
Package Type θJA θ
40-Lead LFCSP (with No Airflow
29.8
Movement)
1
These calculations are intended to represent the thermal performance of the
indicated packages using a JEDEC multilayer test board. Do not assume the
same level of thermal performance in actual applications without a careful
inspection of the conditions in the application to determine that they are
similar to those assumed in these calculations.
1
1
θ
JB
Unit
JC
19.0 3.4 °C/W
ESD CAUTION
Rev. A | Page 9 of 80
AD9114/AD9115/AD9116/AD9117
Q
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
X
RDN
W
(MSB)
DIO/FORMAT
S
CS/P
DB7
DB6
37
38
39
40
PIN 1
1DB5
INDICATOR
2DB4
3DB3
4DB2
5DVDDIO
6DVSS
7DVDD
8DB1
9DB0 (LSB)
10NC
NOTES
1. NC = NO CO NNECT
2. THE EXPO SED PAD IS CONNECTED TO AVSS AND
MUST BE SOL DERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CO RNERS IS
CONNECTED TO THIS PAD.
AD9114
TOP VIEW
(Not to Scale)
11
12
13
14
C
NC
NC
NC
N
Figure 2. AD9114 Pin Configuration
CMLI
FSADJI/AUXI
REFIO
RESET/PINMD
SCLK/CLKMD
FSADJQ/AU
31
32
33
34
35
36
30
RLIN
29
IOUTN
28
IOUTP
27
RLIP
26
AVD D
25
AVS S
24
RLQP
23
QOUTP
22
QOUTN
21
RLQN
15
17
16
18
19
20
NC
CVSS
CVDD
CMLQ
CLKIN
DCLKIO
07466-005
Table 7. AD9114 Pin Function Descriptions
Pin No. Mnemonic Description
1 to 4 DB[5:2] Digital Inputs.
5 DVDDIO Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal).
6 DVSS Digital Common.
7 DVDD
Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD
with a 1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8 DB1 Digital Inputs
9 DB0 (LSB) Digital Input (LSB).
10 to
NC No Connect. These pins are not connected to the chip.
15
16 DCLKIO Data Input/Output Clock. Clock used to qualify input data.
17 CVDD Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
18 CLKIN LVCMOS Sampling Clock Input.
19 CVSS Sampling Clock Supply Voltage Common.
20 CMLQ
Q DAC Output Common-Mode Level. When the internal on-chip (QR
the on-chip QR
resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QR
CML
) is enabled, this pin is connected to
CML
disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor, see
the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
21 RLQN
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
24 RLQP
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
25 AVSS Analog Common.
26 AVDD Analog Supply Voltage Input (1.8 V to 3.3 V).
27 RLIP
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
CML
) is
Rev. A | Page 10 of 80
AD9114/AD9115/AD9116/AD9117
Pin No. Mnemonic Description
29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
30 RLIN
31 CMLI
32 FSADJQ/AUXQ
Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QR
33 FSADJI/AUXI
Auxiliary I DAC Output (AUXI). When the internal on-chip (IR
34 REFIO
35 RESET/PINMD
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
38
/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
CS
39 DB7 (MSB) Digital Input (MSB).
40 DB6 Digital Input.
EP (EPAD)
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
I DAC Output Common-Mode Level. When the internal on-chip (IR
on-chip IR
resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IR
CML
) is enabled, this pin is connected to the
CML
CML
) is
disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor, see
the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QR
) is disabled, this pin is the full-scale
SET
current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of Operation
section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.
) is enabled, this pin is the auxiliary Q DAC output.
SET
Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IR
) is disabled, this pin is the full-scale
SET
current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation
section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.
) is enabled, it is the auxiliary I DAC output.
SET
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
Pulse RESET high to reset the SPI registers to their default values.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer, see
the Retimer section.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down
to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement
input data format.
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for
the SPI port.
The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the
package corners is connected to this pad.
Rev. A | Page 11 of 80
AD9114/AD9115/AD9116/AD9117
Q
2
LKMD
ORMAT
RDN
CS/PW
DB9 (MSB)
DB8
38
39
40
PIN 1
1DB7
INDICATOR
2DB6
3DB5
4DB4
5DVDDIO
6DVSS
7DVDD
8DB3
9DB2
10DB1
NOTES
1. NC = NO CONNECT
. THE EXPO SED PAD IS CONNECT ED TO AVSS AND
MUST BE SOLDERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CO RNERS IS
CONNECTED TO THIS PAD.
AD9115
TOP VIEW
(Not to Scale)
11
12
13
NC
NC
DB0 (LSB)
Figure 3. AD9115 Pin Configuration
Q/AUX
MLI
C
FSADJI/AUXI
REFIO
RESET/PINMD
SCLK/C
SDIO/F
FSADJ
31
32
33
34
35
36
37
30 RLIN
29 IOUT N
28 IOUTP
27 RLIP
26 AVDD
25 AVSS
24 RLQP
23 QOUTP
22 QOUTN
21 RLQ N
15
17
16
18
19
14
NC
20
NC
VDD
CVSS
C
CMLQ
CLKIN
DCLKIO
07466-004
Table 8. AD9115 Pin Function Description
Pin No. Mnemonic Description
1 to 4 DB[7:4] Digital Inputs.
5 DVDDIO Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal).
6 DVSS Digital Common.
7 DVDD
Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD
with a 1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8 to 10 DB[3:1] Digital Inputs.
11 DB0 (LSB) Digital Input (LSB).
12 to 15 NC No Connect. These pins are not connected to the chip.
16 DCLKIO Data Input/Output Clock. Clock used to qualify input data.
17 CVDD Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
18 CLKIN LVCMOS Sampling Clock Input.
19 CVSS Sampling Clock Supply Voltage Common.
20 CMLQ
Q DAC Output Common-Mode Level. When the internal on-chip (QR
the on-chip QR
resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QR
CML
) is enabled, this pin is connected to
CML
disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor, see
the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
21 RLQN
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
24 RLQP
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
25 AVSS Analog Common.
26 AVDD Analog Supply Voltage Input (1.8 V to 3.3 V).
27 RLIP
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
30 RLIN
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
CML
) is
Rev. A | Page 12 of 80
AD9114/AD9115/AD9116/AD9117
Pin No. Mnemonic Description
31 CMLI
I DAC Output Common-Mode Level. When the internal on-chip (IR
on-chip IR
resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IR
CML
disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor,
see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
32 FSADJQ/AUXQ
Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QR
scale current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of
Operation section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QR
33 FSADJI/AUXI
Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IR
SET
current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation
section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on-chip (IR
34 REFIO
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
SET
reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).
35 RESET/PINMD
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
Pulse RESET high to reset the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retime, see
the Retimer section.
37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down
to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement
input data format.
38
/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
CS
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the
SPI port.
39 DB9 (MSB) Digital Input (MSB).
40 DB82 Digital Input.
EP (EPAD)
The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the
package corners is connected to this pad.
) is enabled, this pin is connected to the
CML
) is disabled, this pin is the full-
SET
CML
) is
) is enabled, this pin is the auxiliary Q DAC output.
) is disabled, this pin is the full-scale
SET
) is enabled, it is the auxiliary I DAC output.
Rev. A | Page 13 of 80
AD9114/AD9115/AD9116/AD9117
Q
2
NMD
LKMD
RDN
/C
CMLI
FSADJI/AUXI
REFIO
RESET/PI
SCLK
SDIO/FORMAT
CS/PW
DB11 (MSB)
DB10
38
39
40
PIN 1
1DB9
INDICATOR
2DB8
3DB7
4DB6
5DVDDIO
6DVSS
7DVDD
8DB5
9DB4
10DB3
NOTES
1. NC = NO CONNECT
. THE EXPOSED PAD IS CONNECTED TO AVSS AND
MUST BE SOL DERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CORNERS IS
CONNECTED TO THIS PAD.
AD9116
TOP VIEW
(Not to Scale)
11
12
13
DB2
DB1
DB0 (LSB)
Figure 4. AD9116 Pin Configuration
FSADJQ/AUX
31
32
33
34
35
36
37
30 RLI N
29 IOUTN
28 IOUTP
27 RLI P
26 AVDD
25 AVSS
24 RLQ P
23 QOUTP
22 QOUTN
21 RLQ N
15
17
16
18
19
14
NC
20
S
NC
CVS
CVDD
CMLQ
CLKIN
CLKIO
D
07466-003
Table 9. AD9116 Pin Function Descriptions
Pin No. Mnemonic Description
1 to 4 DB[9:6] Digital Inputs.
5 DVDDIO Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal).
6 DVSS Digital Common.
7 DVDD
Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD
with a 1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8 to 12 DB[5:1] Digital Inputs.
13 DB0 (LSB) Digital Input (LSB).
14, 15 NC No Connect. These pins are not connected to the chip.
16 DCLKIO Data Input/Output Clock. Clock used to qualify input data.
17 CVDD Sampling Clock Supply Voltage Input (1.8 V to 3.3 V ). CVDD must be ≥ DVDD.
18 CLKIN LVCMOS Sampling Clock Input.
19 CVSS Sampling Clock Supply Voltage Common.
20 CMLQ
Q DAC Output Common-Mode Level. When the internal on-chip (QR
the on-chip QR
resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QR
CML
) is enabled, this pin is connected to
CML
disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor,
see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
21 RLQN
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
24 RLQP
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
25 AVSS Analog Common.
26 AVDD Analog Supply Voltage Input (1.8 V to 3.3 V).
27 RLIP
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
30 RLIN
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
CML
) is
Rev. A | Page 14 of 80
AD9114/AD9115/AD9116/AD9117
Pin No. Mnemonic Description
31 CMLI
I DAC Output Common-Mode Level. When the internal on-chip (IR
on-chip IR
resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IR
CML
disabled, this pin is the common mode load for I DAC and must be connected to AVSS through a resistor, see
the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
32 FSADJQ/AUXQ
Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QR
scale current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of
Operation section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QR
33 FSADJI/AUXI
Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IR
SET
current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation
section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on-chip (IR
34 REFIO
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
SET
reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).
35 RESET/PINMD
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
Pulse RESET high to reset the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retime, see
the Retimer section.
37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low
(pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the
twos complement input data format.
38
/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
CS
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for
the SPI port.
39 DB11 (MSB) Digital Input (MSB).
40 DB10 Digital Input.
EP (EPAD)
The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the
package corners is connected to this pad.
) is enabled, this pin is connected to the
CML
) is disabled, this pin is the full-
SET
CML
) is
) is enabled, this pin is the auxiliary Q DAC output.
) is disabled, this pin is the full-scale
SET
) is enabled, it is the auxiliary I DAC output.
Rev. A | Page 15 of 80
AD9114/AD9115/AD9116/AD9117
Q
ORMAT
RDN
B13 (MSB)
B12
CS/PW
D
D
38
39
40
PIN 1
1DB11
INDICATOR
2DB10
3DB9
4DB8
5DVDDIO
6DVSS
7DVDD
8DB7
9DB6
10DB5
NOTES
1. THE EXPO SED PAD IS CONNECTED TO AVSS AND
MUST BE SOL DERED TO THE G ROUND PLANE.
EXPOSED METAL AT PACKAGE CO RNERS IS
CONNECTED TO THIS PAD.
AD9117
TOP VIEW
(Not to Scale)
11
12
13
DB4
DB3
DB2
Figure 5. AD9117 Pin Configuration
Table 10. AD9117 Pin Function Descriptions
Pin No. Mnemonic Description
1 to 4 DB[11:8] Digital Inputs.
5 DVDDIO Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal).
6 DVSS Digital Common.
7 DVDD
Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD
with a 1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8 to 14 DB[7:1] Digital Inputs.
15 DB0 (LSB) Digital Input (LSB).
16 DCLKIO Data Input/Output Clock. Clock used to qualify input data.
17 CVDD Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
18 CLKIN LVCMOS Sampling Clock Input.
19 CVSS Sampling Clock Supply Voltage Common.
20 CMLQ
Q DAC Output Common-Mode Level. When the internal on-chip (QR
the on-chip QR
resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QR
CML
disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor,
see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
21 RLQN
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
24 RLQP
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
25 AVSS Analog Common.
26 AVDD Analog Supply Voltage Input (1.8 V to 3.3 V).
27 RLIP
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
30 RLIN
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
Q/AUX
LK/CLKMD
MLI
C
FSADJI/AUXI
REFIO
RESET/PINMD
SC
SDIO/F
FSADJ
31
32
33
34
35
36
37
30 RLIN
29 IOUTN
28 IOUTP
27 RLIP
26 AVDD
25 AVSS
24 RLQP
23 QOUTP
22 QOUTN
21 RLQ N
15
17
16
18
19
14
DB1
20
VDD
CVSS
C
CMLQ
(LSB)
CLKIN
DCLKIO
DB0
07466-002
) is enabled, this pin is connected to
CML
CML
) is
Rev. A | Page 16 of 80
AD9114/AD9115/AD9116/AD9117
Pin No. Mnemonic Description
31 CMLI
I DAC Output Common-Mode Level. When the internal on-chip (IR
the on-chip IR
resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IR
CML
is disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor,
see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
32 FSADJQ/AUXQ
Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QR
scale current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of
Operation section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QR
33 FSADJI/AUXI
Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IR
SET
current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation
section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on-chip (IR
34 REFIO
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
SET
reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).
35 RESET/PINMD
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
Pulse RESET high to reset the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retime, see
the Retimer section.
37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low
(pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the
twos complement input data format.
38
/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
CS
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for
the SPI port.
39 DB13 (MSB) Digital Input (MSB).
40 DB12 Digital Input.
EP (EPAD)
The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the
package corners is connected to this pad.
) is enabled, this pin is connected to
CML
CML
) is disabled, this pin is the full-
SET
) is enabled, this pin is the auxiliary Q DAC output.
) is disabled, this pin is the full-scale
SET
) is enabled, it is the auxiliary I DAC output.
)
Rev. A | Page 17 of 80
AD9114/AD9115/AD9116/AD9117
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD, DVDD, DVDDIO, CVDD = 1.8 V, I
2.0
= 8 mA, maximum sample rate (125 MSPS), unless otherwise noted.
xOUTFS
2.0
1.5
1.0
0.5
0
–0.5
–1.0
PRECALIBRATI ON INL (LS B)
–1.5
–2.0
0 2048 4096 6144 8192 10,240 12,288 14, 336 16,384
CODE
Figure 6. AD9117 Precalibration INL at 1.8 V, 8 mA (DVDD = 1.8 V)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
PRECALIBRATIO N DNL (LSB)
–1.5
1.5
1.0
0.5
0
–0.5
–1.0
POSTCALIBRATION INL (LSB)
–1.5
–2.0
0 2048 4096 6144 8192 10,240 12,288 14,336 16,384
07466-006
CODE
07466-009
Figure 9. AD9117 Postcalibration INL at 1.8 V, 8 mA (DVDD = 1.8 V)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
POSTCALI BRATION DNL (L SB)
–1.5
–2.0
0 2048 4096 6144 8192 10,240 12,288 14, 336 16,384
CODE
Figure 7. AD9117 Precalibration DNL at 1.8 V, 8 mA (DVDD = 1.8 V)
1.5
1.0
0.5
0
–0.5
PRECALIBRATIO N INL (LSB)
–1.0
–1.5
0 2048 4096 6144 8192 10,240 12,288 14,336 16,384
CODE
07466-007
7466-008
–2.0
0 2048 4096 6144 8192 10,240 12,288 14,336 16,384
CODE
Figure 10. AD9117 Postcalibration DNL at 1.8 V, 8 mA (DVDD = 1.8 V)
1.5
1.0
0.5
0
–0.5
POSTCALI BRATION INL ( LSB)
–1.0
–1.5
0 2048 4096 6144 8192 10,240 12,288 14,336 16,384
CODE
Figure 8. AD9117 Precalibration INL at 3.3 V, 20 mA (DVDD = 1.8 V) Figure 11. AD9117 Postcalibration INL at 3.3 V, 20 mA (DVDD = 1.8 V)
Rev. A | Page 18 of 80
07466-010
7466-011
AD9114/AD9115/AD9116/AD9117
1.5
1.5
1.0
0.5
0
–0.5
PRECALIBRATI ON DNL (LSB)
–1.0
–1.5
0 2048 4096 6144 8192 10,240 12,288 14,336 16,384
CODE
Figure 12. AD9117 Precalibration DNL at 3.3 V, 20 mA
0.8
0.6
0.4
0.2
0
–0.2
–0.4
PRECALIBRATIO N INL (LSB)
–0.6
1.0
0.5
0
–0.5
POSTCALI BRATION DNL (L SB)
–1.0
–1.5
7466-012
0 2048 4096 6144 8192 10,240 12,288 14,336 16,384
CODE
7466-015
Figure 15. AD9117 Postcalibration DNL at 3.3 V, 20 mA
0.8
0.6
0.4
0.2
0
–0.2
–0.4
POSTCALI BRATION INL (LSB)
–0.6
–0.8
0 512 1024 1536 2048 2560 3072 3584 4096
CODE
Figure 13. AD9116 Precalibration INL at 1.8 V, 8 mA
0.6
0.4
0.2
0
–0.2
PRECALIBRATI ON DNL (LSB)
–0.4
–0.6
0 512 1024 1536 2048 2560 3072 3584 4096
CODE
Figure 14. AD9116 Precalibration DNL at 1.8 V, 8 mA
–0.8
7466-013
0 512 1024 1536 2048 2560 3072 3584 4096
CODE
7466-016
Figure 16. AD9116 Postcalibration INL at 1.8 V, 8 mA
0.6
0.4
0.2
0
–0.2
POSTCALI BRATION DNL (L SB)
–0.4
–0.6
7466-014
0 512 1024 1536 2048 2560 3072 3584 4096
CODE
7466-017
Figure 17. AD9116 Postcalibration DNL at 1.8 V, 8 mA
Rev. A | Page 19 of 80
AD9114/AD9115/AD9116/AD9117
0.8
0.8
0.6
0.4
0.2
0
–0.2
–0.4
PRECALIBRATIO N INL (LSB)
–0.6
–0.8
0 512 1024 1536 2048 2560 3072 3584 4096
CODE
Figure 18. AD9116 Precalibration INL at 3.3 V, 20 mA
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
PRECALIBRATIO N DNL (LSB)
–0.3
–0.4
–0.5
0 512 1024 1536 2048 2560 3072 3584 4096
CODE
Figure 19. AD9116 Precalibration DNL at 3.3 V, 20 mA
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
PRECALIBRATION INL (LSB)
–0.15
–0.20
–0.25
0 128 256 384 512 640 768 896 1024
CODE
Figure 20. AD9115 Precalibration INL at 1.8 V, 8 mA
0.6
0.4
0.2
0
–0.2
–0.4
POSTCALI BRATION INL (LSB)
–0.6
–0.8
7466-018
0 512 1024 1536 2048 2560 3072 3584 4096
CODE
7466-021
Figure 21. AD9116 Postcalibration INL at 3.3 V, 20 mA
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
POSTCALI BRATION DNL (L SB)
–0.4
–0.5
7466-019
0 512 1024 1536 2048 2560 3072 3584 4096
CODE
07466-022
Figure 22. AD9116 Postcalibration DNL at 3.3 V, 20 mA
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
POSTCALI BRATION INL (LSB)
–0.15
–0.20
–0.25
7466-020
0 128 256 384 512 640 768 896 1024
CODE
07466-023
Figure 23. AD9115 Postcalibration INL at 1.8 V, 8 mA
Rev. A | Page 20 of 80
AD9114/AD9115/AD9116/AD9117
0.08
0.08
0.06
0.04
0.02
0
–0.02
–0.04
PRECALIBRATI ON DNL (LSB)
–0.06
–0.08
0 128 256 384 512 640 768 896 1024
CODE
Figure 24. AD9115 Precalibration DNL at 1.8 V, 8 mA
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
PRECALIBRATION INL (LSB)
–0.15
–0.20
–0.25
0 128 256 384 512 640 768 896 1024
CODE
Figure 25. AD9115 Precalibration INL at 3.3 V, 20 mA
0.08
0.06
0.04
0.02
0
–0.02
–0.04
POSTCALI BRATION DNL (L SB)
–0.06
–0.08
0 128 256 384 512 640 768 896 1024
07466-024
CODE
07466-027
Figure 27. AD9115 Postcalibration DNL at 1.8 V, 8 mA
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
POSTCALI BRATION INL (LSB)
–0.15
–0.20
–0.25
7466-025
0 128 256 384 512 640 768 896 1024
CODE
7466-028
Figure 28. AD9115 Postcalibration INL at 3.3 V, 20 mA
0.08
0.06
0.04
0.02
0
–0.02
–0.04
PRECALIBRATI ON DNL (LSB)
–0.06
–0.08
0 128 256 384 512 640 768 896 1024
CODE
Figure 26. AD9115 Precalibration DNL at 3.3 V, 20 mA
07466-026
Rev. A | Page 21 of 80
0.06
0.04
0.02
0
–0.02
–0.04
POSTCALI BRATION DNL (L SB)
–0.06
–0.08
0 128 256 384 512 640 768 896 1024
CODE
Figure 29. AD9115 Postcalibration DNL at 3.3 V, 20 mA
07466-029
AD9114/AD9115/AD9116/AD9117
0.035
0.035
0.025
0.015
0.005
0
–0.005
–0.015
PRECALIBRATI ON INL (LSB)
–0.025
–0.035
0 32 64 96 128 160 192 224 256
CODE
Figure 30. AD9114 Precalibration INL at 1.8 V, 8 mA
0.025
0.020
0.015
0.010
0.005
0
–0.005
–0.010
PRECALIBRATIO N DNL (LSB)
–0.015
–0.020
–0.025
0 32 64 96 128 160 192 224 256
CODE
Figure 31. AD9114 Precalibration DNL at 1.8 V, 8 mA
0.03
0.025
0.015
0.005
0
–0.005
–0.015
POSTCALIBRATION INL (LSB)
–0.025
–0.035
0 32 64 96 128 160 192 224 256
07466-030
CODE
07466-033
Figure 33. AD9114 Postcalibration INL at 1.8 V, 8 mA
0.025
0.020
0.015
0.010
0.005
0
–0.005
–0.010
–0.015
POSTCALI BRATION DNL (L SB)
–0.020
–0.025
0 32 64 96 128 160 192 224 256
07466-031
CODE
07466-034
Figure 34. AD9114 Postcalibration DNL at 1.8 V, 8 mA
0.03
0.02
0.01
0
–0.01
PRECALIBRATIO N INL (LSB)
–0.02
–0.03
0 32 64 96 128 160 192 224 256
CODE
Figure 32. AD9114 Precalibration INL at 3.3 V, 20 mA
07466-032
Rev. A | Page 22 of 80
0.02
0.01
0
–0.01
POSTCALI BRATION INL (LSB)
–0.02
–0.03
0 32 64 96 128 160 192 224 256
CODE
Figure 35. AD9114 Postcalibration INL at 3.3 V, 20 mA
07466-035
AD9114/AD9115/AD9116/AD9117
–
–
–
–
0.025
0.020
0.015
0.010
0.005
0
–0.005
–0.010
PRECALIBRATIO N DNL (LSB)
–0.015
–0.020
–0.025
0 32 64 96 128 160 192 224 256
CODE
Figure 36. AD9114 Precalibration DNL at 3.3 V, 20 mA
124
–130
AD9114
–136
–142
NSD (dBc)
AD9115
–148
AD9116
–154
AD9117
–160
0 102030405
Figure 37. NSD at 8 mA vs. f
f
(MHz)
OUT
, 1.8 V
OUT
136
07466-036
0
07466-137
0.025
0.020
0.015
0.010
0.005
0
–0.005
–0.010
–0.015
POSTCALI BRATION DNL (LSB)
–0.020
–0.025
0326496128
160 192 224 256
CODE
Figure 39. AD9114 Postcalibration DNL at 3.3 V, 20 mA
124
–130
–136
–142
–148
NSD (dBc)
–154
–160
–166
0 1020305 15253540455055
Figure 40. NSD at 20 mA vs. f
AD9114
AD9115
AD9116
AD9117
f
OUT
(MHz)
OUT
, 3.3 V
136
07466-039
07466-200
–139
–142
–145
–148
–151
NSD (dBm/Hz)
–154
–157
–160
0 1020305 15253540455055
Figure 38. AD9117 NSD at Three Temperatures 8 mA vs. f
+25°C
+85°C
–40°C
f
OUT
(MHz)
OUT
, 1.8 V
07466-201
–139
–142
–145
–148
–151
NSD (dBm/Hz)
–154
–157
–160
0 1020305 15253540455055
+25°C
Figure 41. AD9117 NSD at Three Temperatures 8 mA vs. f
+85°C
f
OUT
–40°C
(MHz)
OUT
, 3.3 V
07466-202
Rev. A | Page 23 of 80
AD9114/AD9115/AD9116/AD9117
–
–
130
130
–136
–142
–148
NSD (dBc)
–154
–160
–166
0 5 10 15 20 25 30 35 40 45 50 55
f
OUT
1.8V, 4mA
1.8V, 8mA
(MHz)
Figure 42. AD9117 NSD at Two Output Currents vs. f
0
–10
–20
–30
–40
–50
(dBm)
–60
–70
–80
–90
–100
START 1MHz 1.5MHz/DIV STOP 16MHz
OUT
, 1.8 V
–136
–142
–148
NSD (dBc)
07466-142
3.3V, 4mA
3.3V, 8mA
–154
–160
3.3V, 20mA
–166
0 5 10 15 20 25 30 35 40 45 50 55
f
OUT
(MHz )
Figure 45. AD9117 NSD at Three Output Currents vs. f
OUT
07466-145
, 3.3 V
0
–10
–20
–30
–40
–50
(dBm)
–60
–70
–80
–90
–100
07466-090
START 1MHz 1.5MHz/DIV STOP 16MHz
07466-091
Figure 43. AD9117 Two Tone Spectrum at 1.8 V
90
AD9117
80
70
IMD (dBc)
60
50
5 10152025303540 4550
AD9116
AD9115
AD9114
f
(MHz)
OUT
Figure 44. All IMD 8 mA vs. f
OUT
, 1.8 V
7466-144
Rev. A | Page 24 of 80
Figure 46. AD9117 Two Tone Spectrum at 3.3 V
96
90
84
78
72
IMD (dBc)
66
60
54
5 101520253035404550
AD9117
AD9116
AD9115
AD9114
f
(MHz)
OUT
Figure 47. All IMD 20 mA vs. f
OUT
, 3.3 V
7466-147
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