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AD9114
Datasheet (ANALOG DEVICES)
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Datasheet AD9114 Datasheet (ANALOG DEVICES)

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TxDAC Digital-to-Analog Converters
AD9114/AD9115/AD9116/AD9117
Rev. B
rights of third parties that may result from its use. Specifications subject to change without notice. No
Trademarks and registered trademarks are the prop erty of their respective owner s.
Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved.
Data Sheet

FEATURES

Power dissipation @ 3.3 V, 20 mA output
191 mW @ 10 MSPS
232 mW @ 125 MSPS Sleep mode: <3 mW @ 3.3 V Supply voltage: 1.8 V to 3.3 V SFDR to Nyquist
86 dBc @ 1 MHz output
85 dBc @ 10 MHz output AD9117 NSD @ 1 MHz output, 125 MSPS, 20 mA: −162 dBc/Hz Differential current outputs: 4 mA to 20 mA 2 on-chip auxiliary DACs CMOS inputs with single-port operation Output common mode: adjustable 0 V to 1.2 V Small footprint 40-lead LFCSP RoHS-compliant package

APPLICATIONS

Wireless infrastructures
Picocell, femtocell base stations Medical instrumentation
Ultrasound transducer excitation Portable instrumentation
Signal generators, arbitrary waveform generators
Dual Low Power, 8-/10-/12-/14-Bit

GENERAL DESCRIPTION

The AD9114/AD9115/AD9116/AD9117 are pin-compatible dual, 8-/10-/12-/14-bit, low power digital-to-analog converters (DACs) that provide a sample rate of 125 MSPS. These TxDAC® converters are optimized for the transmit signal path of commu­nication systems. All the devices share the same interface, package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost.
The AD9114/AD9115/AD9116/AD9117 offer exceptional ac and dc performance and support update rates up to 125 MSPS.
The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9114/AD9115/AD9116/AD9117 make them well suited for portable and low power applications.

PRODUCT HIGHLIGHTS

1. Low Power. DACs operate on a single 1.8 V to 3.3 V supply;
total power consumption reduces to 225 mW at 100 MSPS. Sleep and power-down modes are provided for low power idle periods.
2. CMOS Clock Input. High speed, single-ended CMOS clock
input supports a 125 MSPS conversion rate.
3. Easy Interfacing to Other Components. Adjustable output
common mode from 0 V to 1.2 V allows for easy interfacing to other components that accept common-mode levels greater than 0 V.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com
AD9114/AD9115/AD9116/AD9117 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications ..................................................................................... 5
DC Specifications ......................................................................... 5
Digital Specifications ................................................................... 7
AC Specifications .......................................................................... 8
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 18
Terminology .................................................................................... 31
Theory of Operation ...................................................................... 32
Serial Peripheral Interface (SPI) ................................................... 33
General Operation of the Serial Interface ............................... 33
Instruction Byte .......................................................................... 33
Serial Interface Port Pin Descriptions ..................................... 33
MSB/LSB Transfers..................................................................... 34
Serial Port Operation ................................................................. 34
Pin Mode ..................................................................................... 34
SPI Register Map ............................................................................. 35
SPI Register Descriptions .............................................................. 36
Digital Interface Operation ........................................................... 40
Digital Data Latching and Retimer Section ............................ 41
Estimating the Overall DAC Pipeline Delay........................... 42
Reference Operation .................................................................. 43
Reference Control Amplifier .................................................... 43
DAC Transfer Function ............................................................. 43
Analog Output ............................................................................ 44
Self-Calibration ........................................................................... 44
Coarse Gain Adjustment ........................................................... 45
Using the Internal Termination Resistors ............................... 46
Applications Information .............................................................. 47
Output Configurations .............................................................. 47
Differential Coupling Using a Transformer ............................... 47
Single-Ended Buffered Output Using an Op Amp ................ 47
Differential Buffered Output Using an Op Amp .................. 48
Auxiliary DACs ........................................................................... 48
DAC-to-Modulator Interfacing ................................................ 49
Correcting for Nonideal Performance of Quadrature
Modulators on the IF-to-RF Conversion ................................ 49
I/Q Channel Gain Matching ..................................................... 49
LO Feedthrough Compensation .............................................. 50
Results of Gain and Offset Correction .................................... 50
Outline Dimensions ....................................................................... 51
Ordering Guide .......................................................................... 52
Rev. B | Page 2 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117

REVISION HISTORY

5/12—Rev. A to Rev. B
Changes to Table 1 ............................................................................ 5
Changes to Table 2 ............................................................................ 7
Changes to Table 3 and Table 4 ....................................................... 8
Changes to Theory of Operation Section .................................... 32
Changes to SCLK—Serial Clock Section ..................................... 33
Changes to Pin Mode Section ........................................................ 34
Changes to Table 14 ........................................................................ 37
Changes to Self-Calibration Section ............................................. 44
Deleted Modifying the Evaluation Board to Use the ADL5370
On-Board Quadrature Modulator Section ......................................... 51
Deleted Evaluation Board Schematics and Artwork Section and
Figure 111 to Figure 133, Renumbered Sequentially ................. 52
Updated Outline Dimensions ........................................................ 51
Changes to Ordering Guide ........................................................... 52
Deleted Bill of Materials Section and Table 18 ............................ 75
3/09—Rev. 0 to R e v. A
Changes to Product Title and General Description Section ....... 1
Changes to Figure 1 ........................................................................... 4
Changed I
= 2 mA to I
OUTFS
= 20 mA..................................... 5
xOUTFS
Changes to Table 1 ............................................................................ 6
Changed I
= 2 mA to I
OUTFS
= 20 mA..................................... 7
xOUTFS
Changes to Table 2 ............................................................................ 7
Changed DVDDIO = 1.8 V to DVDDIO = 3.3 V, Table 3 and
CVDD = 3.3 V to CVDD = 1.8 V, Table 4 ..................................... 8
Changes to Ta bl e 5 and Table 6 ....................................................... 9
Changes to Table 7 .......................................................................... 10
Changes to Table 8 .......................................................................... 12
Changes to Table 9 .......................................................................... 14
Changes to Table 10 ........................................................................ 16
Changes to Typical Performance Characteristics Section ......... 18
Changes to Theory of Operation Section and Figure 84 ........... 32
Added Figure 85 to Figure 88; Renumbered Sequentially ......... 34
Changes to Table 13 ........................................................................ 35
Changes to Table 14 ........................................................................ 36
Changes to Digital Interface Operation Section and Figure 89,
Figure 90, Figure 91, Figure 92, and Figure 93 ............................ 40
Changes to Figure 94, Digital Data Latching Section, and
Retimer Section ............................................................................... 41
Added Reference Operation Section, Reference Control Amplifier Section, DAC Transfer Function Section, Figure 96,
and Tabl e 17 ..................................................................................... 43
Added Analog Output Section ...................................................... 44
Changes to Auxiliary DACs Section ............................................. 48
Changes to DAC to Modulator Int
erfacing Section, Figure 107,
and Figure 108 ................................................................................. 49
Added Figure 111 to Figure 133 .................................................... 52
Added Table 18 ................................................................................ 75
8/08—Revision 0: Initial Version
Rev. B | Page 3 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
I DAC
Q DAC
AUX1DAC
AUX2DAC
BAND
GAP
CLOCK
DIST
10kΩ
QR
SET
2kΩ
IR
SET
2kΩ
I
REF
100µA
IR
CM
60Ω TO
260Ω
QR
CM
60Ω TO
260Ω
62.5Ω
62.5Ω
62.5Ω
62.5Ω
SPI
INTERFACE
1 INTO 2
INTERLEAVED
DATA
INTERFACE
I DATA
Q DATA
1.8V
LDO
1V
AD9117
RLIN
IOUTN IOUTP
RLIP AVDD AVSS RLQP
QOUTP QOUTN
RLQN
DB11
DB10
DB9
DB8
DV
DDIO
DVSS
DVDD
DB7
DB6
DB5
DB12
DB13 (MSB)
CS/PWRDN
SDIO/FORMAT
SCLK/CLKMD
RESET/PINMD
REFIO
FSADJQ/AUXQ
FSADJI/AUXI
CMLI
DB4
DB3
DB2
DB1
(LSB) DB0
DCLKIO
CVDD
CLKIN
CVSS
CMLQ
07466-001

FUNCTIONAL BLOCK DIAGRAM

Figure 1.
Rev. B | Page 4 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117

SPECIFICATIONS

DC SPECIFICATIONS

T
to T
MIN
, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, I
MAX
Table 1.
AD9114 AD9115 AD9116 AD9117
Parameter
RESOLUTION 8 10 12 14 Bits ACCURACY, AVDD = DVDDIO =
CVDD = 3.3 V Differential Nonlinearity (DNL)
Precalibration ±0.02 ±0.06 ±0.4 ±1.4 LSB Postcalibration ±0.02 ±0.04 ±0.2 ±0.6 LSB
Integral Nonlinearity (INL)
Precalibration ±0.03 ±0.19 ±0.68 ±1.2 LSB Postcalibration ±0.03 ±0.07 ±0.42 ±0.6 LSB
ACCURACY, AVDD = DVDDIO =CVDD =
1.8 V Differential Nonlinearity (DNL)
Precalibration ±0.02 ±0.08 ±0.5 ±1.8 LSB Postcalibration ±0.01 ±0.06 ±0.2 ±1.0 LSB
Integral Nonlinearity (INL)
Precalibration ±0.04 ±0.2 ±0.5 ±1.8 LSB Postcalibration ±0.02 ±0.1 ±0.3 ±1.1 LSB
MAIN DAC OUTPUTS
Offset Error −1 +1 −1 +1 −1 +1 −1 +1 mV Gain Error Internal Reference −2 +2 −2 +2 −2 +2 −2 +2 % of FSR Full-Scale Output Current1
AVDD = 3.3 V 2 8 20 2 8 20 2 8 20 2 8 20 mA AVDD = 1.8 V 2 8 2 8 2 8 2 8 mA
Output Common-Mode Level
(8 mA CMLx Pin)
Output Compliance Range
AVDD = 3.3 V, 8 mA Output
Common Mode Level = −0.5 −0.9 −0.1 −0.9 −0.1 −0.9 −0.1 −0.9 −0.1 V Common Mode Level = 0 −0.4 +0.4 −0.4 +0.4 −0.4 +0.4 −0.4 +0.4 V
Common Mode Level = +1.2 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 V Output Resistance 200 200 200 200 MΩ Crosstalk, Q DAC to I DAC
= 30 MHz)
(f
OUT
Crosstalk, Q DAC to I DAC
= 60 MHz)
(f
OUT
MAIN DAC TEMPERATURE DRIFT
Offset 0 0 0 0 ppm/°C Gain ±40 ±40 ±40 ±40 ppm/°C Reference Voltage ±25 ±25 ±25 ±25 ppm/°C
−0.5 0 +1.2 −0.5 0 +1.2 −0.5 0 +1.2 −0.5 0 +1.2 V
95 95 95 95 dB
76 76 76 76 dB
= 20 mA, maximum sample rate, unless otherwise noted.
xOUTFS
Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Rev. B | Page 5 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
Guaranteed
AD9114 AD9115 AD9116 AD9117
Parameter
AUXDAC OUTPUTS
Resolution 10 10 10 10 Bits Full-Scale Output Current
125 125 125 125 µA
(Current Sourcing Mode)
Voltage Output Mode
Output Compliance Range
(Sourcing 1 mA)
Output Compliance Range
(Sinking 1 mA)
Output Resistance in Current
Output Mode AV
to 1 V
SS
AUXDAC Monotonicity
VSS VDD −
VSS +
VDD VSS +
0.25
VSS VDD −
0.25
0.25
VSS VDD −
0.25
VDD VSS +
0.25
VSS VDD −
0.25
VDD VSS +
0.25
VDD V
1 1 1 1 MΩ
10 10 10 10 Bits
REFERENCE OUTPUT
Internal Reference Voltage 0.98 1.025 1.08 0.98 1.025 1.08 0.98 1.025 1.08 0.98 1.025 1.08 V Output Resistance 10 10 10 10 kΩ
REFERENCE INPUT
Voltage Compliance
AVDD = 3.3 V 0.1 1.25 0.1 1.25 0.1 1.25 0.1 1.25 V AVDD = 1.8 V 0.1 1.0 0.1 1.0 0.1 1.0 0.1 1.0 V
Input Resistance External
1 1 1 1 MΩ
Reference Mode
DAC MATCHING
Gain Matching −1 +1 −1 +1 −1 +1 −1 +1 % of FSR
ANALOG SUPPLY VOLTAGES
AVDD 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 V CVDD 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 V
DIGITAL SUPPLY VOLTAGES
DVDD 1.7 1.9 1.7 1.9 1.7 1.9 1.7 1.9 V DVDDIO 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 V
POWER CONSUMPTION, AVDD =
DVDDIO = CVDD = 3.3 V f
= 125 MSPS, IF = 12.5 MHz 220 220 220 220 mW
DAC
I
55 55 55 55 mA
AVDD
I
+ I
DVDD
I
CVDD
10 10 10 10 mA
DVDDIO
3 3 3 3 mA Power-Down Mode with Clock 8.5 8.5 8.5 8.5 mW Power-Down Mode No Clock 3 3 3 3 mW Power Supply Rejection Ratio −0.009 −0.009 −0.009 −0.009 % FSR/V
POWER CONSUMPTION, AVDD =
DVDDIO = CVDD = 1.8 V f
= 125 MSPS, IF = 12.5 MHz 58 58 58 58 mW
DAC
I
24 24 24 24 mA
AVDD
I
DVDD + IDVDDIO
I
CVDD
8 8 8 8 mA
2 2 2 2 mA Power-Down Mode with Clock 12 12 12 12 mW Power-Down Mode No Clock 850 850 850 850 µW Power Supply Rejection Ratio −0.007 −0.007 −0.007 −0.007 % FSR/V
OPERATING RANGE −40 +25 +85 −40 +25 +85 −40 +25 +85 −40 +25 +85 °C
1
Based on a 10 kΩ external resistor.
Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max
V
0.25
Rev. B | Page 6 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
Minimum SDIO and to SCLK Setup, tDS
10 ns
1.8 V I Channel or DCLKIO Rising Edge
3.3 V I Channel or DCLKIO Rising Edge

DIGITAL SPECIFICATIONS

T
to T
MIN
, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, I
MAX
Table 2.
Parameter Min Typ Max Unit
DAC CLOCK INPUT (CLKIN)
VIH 2.1 3 V VIL 0 0.9 V Maximum Clock Rate 125 MSPS
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK) 25 MHz Minimum Pulse Width High 20 ns Minimum Pulse Width Low 20 ns
Minimum SCLK to SDIO Hold, tDH 5 ns Maximum SCLK to Valid SDIO, tDV 20 ns Minimum SCLK to Invalid SDIO, t
5 ns
DNV
INPUT DATA
1.8 V Q Channel or DCLKIO Falling Edge Setup 0.25 ns Hold 1.2 ns
= 20 mA, maximum sample rate, unless otherwise noted.
xOUTFS
Setup 0.13 ns Hold 1.1 ns
3.3 V Q Channel or DCLKIO Falling Edge Setup −0.2 ns Hold 1.5 ns
Setup −0.2 ns Hold 1.6 ns
DVDDIO = 3.3 V
VIH 2.1 3 V VIL 0 0.9 V
DVDDIO = 1.8 V
VIH 1.2 1.8 V VIL 0 0.5 V
Rev. B | Page 7 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
W-CDMA ADJACENT CHANNEL LEAKAGE
AD9114
AD9115
AD9116
AD9117
f
= 125 MSPS, f
= 10 MHz
76
76
76
76 dBc

AC SPECIFICATIONS

T
to T
MIN
, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, I
MAX
Table 3.
AD9114 AD9115 AD9116 AD9117
Parameter
DYNAMIC PERFORMANCE
Output Settling Time (tST) to 0.1% 11.5 11.5 11.5 11.5 ns Output Rise Time (10% to 90%) 0.27 0.27 0.27 0.27 ns Output Fall Time (90% to 10%) 0.27 0.27 0.27 0.27 ns Output Noise (I
= 20mA) 1471 465 117 37 pA/√Hz
OUTFS
SPURIOUS FREE DYNAMIC RANGE (SFDR)
f
= 125 MSPS, f
DAC
f
= 125 MSPS, f
DAC
TWO TONE INTERMODULATION
= 10 MHz 76 85 85 85 dBc
OUT
= 50 MHz 55 55 55 55 dBc
OUT
DISTORTION (IMD)
f
= 125 MSPS, f
DAC
f
= 125 MSPS, f
DAC
NOISE SPECTRAL DENSITY (NSD),
= 10 MHz 81 81 81 82 dBc
OUT
= 50 MHz 60 60 60 61 dBc
OUT
EIGHT-TONE, 500 kHz TONE SPACING
f
= 125 MSPS, f
DAC
f
= 125 MSPS, f
DAC
f
= 125 MSPS, f
DAC
= 1 MHz −131 −141 −153 −163 dBc/Hz
OUT
= 10 MHz −132 −143 −153 −157 dBc/Hz
OUT
= 50 MHz −128 −138 −146 −149 dBc/Hz
OUT
= 20 mA, maximum sample rate, unless otherwise noted.
xOUTFS
Unit Min Typ Max Min Typ Max Min Ty p Max Min Typ Max
RATIO (ACLR), SINGLE CARRIER
f
= 61.44 MSPS, f
DAC
f
= 122.88 MSPS, f
DAC
T
to T
MIN
, AVDD = 1.8 V, DVDD = 1.8 V, DVDDIO = 1.8 V, CVDD = 1.8 V, I
MAX
= 20 MHz −78 −78 −78 −78 dBc
OUT
= 30 MHz −80 −80 −80 −80 dBc
OUT
= 8 mA, maximum sample rate, unless otherwise noted.
xOUTFS
Table 4.
Parameter
SPURIOUS FREE DYNAMIC RANGE (SFDR)
f
= 125 MSPS, f
DAC
f
= 125 MSPS, f
DAC
TWO TONE INTERMODULATION
= 10 MHz 73 76 76 76 dBc
OUT
= 50 MHz 48 48 48 48 dBc
OUT
DISTORTION (IMD)
DAC
f
= 125 MSPS, f
DAC
NOISE SPECTRAL DENSITY (NSD),
OUT
= 50 MHz 50 50 50 50 dBc
OUT
EIGHT-TONE, 500 kHz TONE SPACING f
= 125 MSPS, f
DAC
f
= 125 MSPS, f
DAC
f
= 125 MSPS, f
DAC
W-CDMA ADJACENT CHANNEL LEAKAGE
= 1 MHz −131 −143 −152 −158 dBc/Hz
OUT
= 10 MHz −132 −143 −151 −152 dBc/Hz
OUT
= 50 MHz −128 −138 −140 −141 dBc/Hz
OUT
RATIO (ACLR), SINGLE CARRIER f
= 61.44 MSPS, f
DAC
f
= 122.88 MSPS, f
DAC
= 20 MHz −69 −69 −69 −69 dBc
OUT
= 30 MHz −72 −72 −72 −72 dBc
OUT
Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Rev. B | Page 8 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117

ABSOLUTE MAXIMUM RATINGS

Table 5.
Parameter Rating
AVDD, DVDDIO, CVDD to AVSS,
−0.3 V to +3.9 V
DVSS, CVSS DVDD to DVSS −0.3 V to +2.1 V AVSS to DVSS, CVSS −0.3 V to +0.3 V DVSS to AVSS, CVSS −0.3 V to +0.3 V CVSS to AVSS, DVSS −0.3 V to +0.3 V REFIO, FSADJQ, FSADJI, CMLQ,
−0.3 V to AVDD + 0.3 V
CMLI to AVSS Q OU T P, QOUTN, IOUTP, IOUTN,
−1.0 V to AVDD + 0.3 V
RLQP, RLQN, RLIP, RLIN to AVSS DBn1 (MSB) to D0 (LSB), CS, SCLK,
−0.3 V to DVDDIO + 0.3 V
SDIO, RESET to DVSS CLKIN to CVSS −0.3 V to CVDD + 0.3 V Junction Temperature 125°C Storage Temperature Range −65°C to +150°C
1
n stands for 7 for the AD9114, 9 for the AD9115, 11 for the AD9116, and 13
for the AD9117.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

Table 6.
Package Type θJA θ
40-Lead LFCSP (with No Airflow
29.8 19.0 3.4 °C/W
Movement)
1
These calculations are intended to represent the thermal performance of the indicated packages using a JEDEC multilayer test board. Do not assume the same level of thermal performance in actual applications without a careful inspection of the conditions in the application to determine that they are similar to those assumed in these calculations.
JB
1
θ
1
Unit
JC

ESD CAUTION

Rev. B | Page 9 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
PIN 1 INDICATOR
1DB5 2DB4 3DB3 4DB2 5DVDDIO 6DVSS 7DVDD 8DB1 9DB0 (LSB)
10NC
23
24
25
26
27
28
29
30
22 21
11NC
12NC
13NC
15NC
17CVDD
16DCLKIO
18CLKIN
19CVSS
20CMLQ
14NC
33
FSADJI/AUXI
34
R
EFIO
35
RESET/PINMD
36
SCLK/CLKMD
37
SDIO/FORMAT
38
CS/PWRDN
39
DB7 (MSB)
40
DB6
32
FSADJQ/AUXQ
31
CMLI
TOP VIEW
(Not to S cale)
AD9114
07466-005
NOTES
1. NC = NO CONNECT
2. THE EXP OSED PAD IS CO NNE CTED TO AVS S AND MUST BE SO LDERED TO T HE GROUND PLANE. EXPOSED M E TAL AT PACKAGE CORNERS IS CONNECTED T O THIS PAD.
QOUTP
RLQP
AVSS
AVDD
RLIP
IOUTP
IOUTN
RLIN
QOUTN RLQN
1 to 4
DB[5:2]
Digital Inputs.
9
DB0 (LSB)
Digital Input (LSB).
18
CLKIN
LVCMOS Sampling Clock Input.
21
RLQN

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 2. AD9114 Pin Configuration
Table 7. AD9114 Pin Function Descriptions
Pin No. Mnemonic Description
5 DVDDIO Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal). 6 DVSS Digital Common. 7 DVDD
Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a 1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8 DB1 Digital Inputs
10 to
NC No Connect. These pins are not connected to the chip.
15 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
19 CVSS Sampling Clock Supply Voltage Common. 20 CMLQ
Q DAC Output Common-Mode Level. When the internal on-chip (QR the on-chip QR
resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QR
CML
) is enabled, this pin is connected to
CML
disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally. 22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 24 RLQP
25 AVSS Analog Common. 26 AVDD Analog Supply Voltage Input (1.8 V to 3.3 V). 27 RLIP
28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
CML
) is
Rev. B | Page 10 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QR
) is enabled, this pin is the auxiliary Q DAC output.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
Pin No. Mnemonic Description
29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. 30 RLIN
31 CMLI
32 FSADJQ/AUXQ
33 FSADJI/AUXI
Auxiliary I DAC Output (AUXI). When the internal on-chip (IR 34 REFIO
35 RESET/PINMD
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). 36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
38
CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
39 DB7 (MSB) Digital Input (MSB). 40 DB6 Digital Input. EP (EPAD)
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally.
I DAC Output Common-Mode Level. When the internal on-chip (IR on-chip IR
resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IR
CML
) is enabled, this pin is connected to the
CML
CML
) is disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QR
) is disabled, this pin is the full-scale
SET
current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.
SET
Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IR
) is disabled, this pin is the full-scale
SET
current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.
) is enabled, it is the auxiliary I DAC output.
SET
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in internal reference mode (a 0.1 µF capacitor to AVSS is required).
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode. Pulse RESET high to reset the SPI registers to their default values.
DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer, see the
Retimer section.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format.
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port.
The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the package corners is connected to this pad.
Rev. B | Page 11 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
PIN 1 INDICATOR
1DB7 2DB6
3DB5 4DB4 5DVDDIO 6DVSS 7DVDD 8DB3 9DB2
10DB1
23 QOUTP
24 RLQP
25 AVSS
26 AVDD
27 RLIP
28 IOUTP
29 IOUTN
30 RLIN
22 QOUTN 21 RLQN
11
DB0 (LSB)
12NC
13NC
15NC
17CVDD
16DCLKIO
18CLKIN
19
CVSS
20CMLQ
14NC
33
FSADJI/AUXI
34
REFIO
35
RESET/PINMD
36
SCLK/CLKMD
37
SDIO/FORMAT
38
CS/PWRDN
39
DB9 (MSB)
40
DB8
32
FSADJQ/AUXQ
31
CMLI
TOP VIEW
(Not to S cale)
AD9115
07466-004
NOTES
1. NC = NO CONNECT
2. THE EXP OSED PAD IS CO NNE CTED TO AVS S AND MUST BE SO LDERED TO T HE GROUND PLANE. EXPOSED M E TAL AT PACKAGE CORNERS IS CONNECTED T O THIS PAD.
11
DB0 (LSB)
Digital Input (LSB).
19
CVSS
Sampling Clock Supply Voltage Common.
30
RLIN
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
Figure 3. AD9115 Pin Configuration
Table 8. AD9115 Pin Function Description
Pin No. Mnemonic Description
1 to 4 DB[7:4] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal). 6 DVSS Digital Common. 7 DVDD
Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a 1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8 to 10 DB[3:1] Digital Inputs.
12 to 15 NC No Connect. These pins are not connected to the chip. 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input.
20 CMLQ
Q DAC Output Common-Mode Level. When the internal on-chip (QR the on-chip QR
resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QR
CML
) is enabled, this pin is connected to
CML
disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
21 RLQN
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally. 22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 24 RLQP
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally. 25 AVSS Analog Common. 26 AVDD Analog Supply Voltage Input (1.8 V to 3.3 V). 27 RLIP
28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s. 29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
CML
) is
IOUTN externally.
Rev. B | Page 12 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
32
FSADJQ/AUXQ
Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QR
) is disabled, this pin is the full-
37
SDIO/FORMAT
Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
Pin No. Mnemonic Description
31 CMLI
I DAC Output Common-Mode Level. When the internal on-chip (IR on-chip IR
resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IR
CML
disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
scale current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of
Operation section. Nominal value for this external resistor is 4 kΩ for 8 mA output current. Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QR 33 FSADJI/AUXI
Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IR
SET
current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation
section. Nominal value for this external resistor is 4 kΩ for 8 mA output current. Auxiliary I DAC Output (AUXI). When the internal on-chip (IR 34 REFIO
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
SET
reference output when in internal reference mode (a 0.1 µF capacitor to AVSS is required). 35 RESET/PINMD
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
Pulse RESET high to reset the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). 36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retime, see
the Retimer section.
) is enabled, this pin is connected to the
CML
SET
CML
) is
) is enabled, this pin is the auxiliary Q DAC output.
) is disabled, this pin is the full-scale
SET
) is enabled, it is the auxiliary I DAC output.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down
to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement
input data format. 38
CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the
SPI port. 39 DB9 (MSB) Digital Input (MSB). 40 DB82 Digital Input. EP (EPAD)
The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the
package corners is connected to this pad.
Rev. B | Page 13 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
PIN 1 INDICATOR
1DB9 2DB8 3DB7 4DB6 5DV
DDIO
6DVSS 7DVDD 8DB5 9DB4
10DB3
23 QOUTP
24 RLQP
25 AVSS
26 AVDD
27 RLIP
28 IOUTP
29 IOUTN
30 RLIN
22 QOUTN 21 RLQN
11DB2
12DB1
13
DB0 (LSB)
15NC
17CVDD
16DCLKIO
18CLKIN
19CVSS
20CMLQ
14NC
33
FSADJI/AUXI
34
REFIO
35
RESET/PINMD
36
SCLK/CLKMD
37
SDIO/FORMAT
38
CS/PWRDN
39
DB11 (MSB)
40
DB10
32
FSADJQ/AUXQ
31
CMLI
TOP VIEW
(Not to S cale)
AD9116
NOTES
1. NC = NO CONNECT
2. THE EXP OSED PAD IS CO NNE CTED TO AVS S AND MUST BE SO LDERED TO T HE GROUND PLANE. EXPOSED M E TAL AT PACKAGE CORNERS IS CONNECTED T O THIS PAD.
07466-003
7
DVDD
Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD
24
RLQP
Figure 4. AD9116 Pin Configuration
Table 9. AD9116 Pin Function Descriptions
Pin No. Mnemonic Description
1 to 4 DB[9:6] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal). 6 DVSS Digital Common.
with a 1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads. 8 to 12 DB[5:1] Digital Inputs. 13 DB0 (LSB) Digital Input (LSB). 14, 15 NC No Connect. These pins are not connected to the chip. 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. 20 CMLQ
Q DAC Output Common-Mode Level. When the internal on-chip (QR
the on-chip QR
resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QR
CML
) is enabled, this pin is connected to
CML
disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor,
see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω. 21 RLQN
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally. 22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally. 25 AVSS Analog Common. 26 AVDD Analog Supply Voltage Input (1.8 V to 3.3 V). 27 RLIP
28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s. 29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. 30 RLIN
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
CML
) is
Rev. B | Page 14 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
32
FSADJQ/AUXQ
Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QR
) is disabled, this pin is the full-
37
SDIO/FORMAT
Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
Pin No. Mnemonic Description
31 CMLI
I DAC Output Common-Mode Level. When the internal on-chip (IR on-chip IR
resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IR
CML
disabled, this pin is the common mode load for I DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
scale current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of
Operation section. Nominal value for this external resistor is 4 kΩ for 8 mA output current. Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QR 33 FSADJI/AUXI
Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IR
SET
current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation
section. Nominal value for this external resistor is 4 kΩ for 8 mA output current. Auxiliary I DAC Output (AUXI). When the internal on-chip (IR 34 REFIO
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
SET
reference output when in internal reference mode (a 0.1 µF capacitor to AVSS is required). 35 RESET/PINMD
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
Pulse RESET high to reset the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). 36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retime, see
the Retimer section.
) is enabled, this pin is connected to the
CML
SET
CML
) is
) is enabled, this pin is the auxiliary Q DAC output.
) is disabled, this pin is the full-scale
SET
) is enabled, it is the auxiliary I DAC output.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low
(pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the
twos complement input data format. 38
CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for
the SPI port. 39 DB11 (MSB) Digital Input (MSB). 40 DB10 Digital Input. EP (EPAD)
The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the
package corners is connected to this pad.
Rev. B | Page 15 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
PIN 1 INDICATOR
1DB11 2DB10
3DB9 4DB8 5DVDDIO 6D
VSS
7DVDD 8DB7 9DB6
10DB5
23 QOUTP
24 RLQP
25 AVSS
26 AVDD
27 RLIP
28 IOUTP
29 IOUTN
30 RLIN
22 QOUTN 21 RLQN
11DB4
12DB3
13DB2
15
DB0 (LSB)
17CVDD
16DCLKIO
18CLKIN
19CVSS
20CMLQ
14DB1
33
FSADJI/AUXI
34
REFIO
35
RESET/PINMD
36
SCLK/CLKMD
37
SDIO/FORMAT
38
CS/PWRDN
39
DB13 (MSB)
40
DB12
32
FSADJQ/AUXQ
31
CMLI
TOP VIEW
(Not to S cale)
AD9117
07466-002
NOTES
1. THE EXP OSED PAD IS CO NNE CTED TO AVS S AND MUST BE SO LDERED TO T HE GROUND PLANE. EXPOSED M E TAL AT PACKAGE CORNERS IS CONNECTED T O THIS PAD.
15
DB0 (LSB)
Digital Input (LSB).
20
CMLQ
Q DAC Output Common-Mode Level. When the internal on-chip (QR
) is enabled, this pin is connected to
22
QOUTN
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Figure 5. AD9117 Pin Configuration
Table 10. AD9117 Pin Function Descriptions
Pin No. Mnemonic Description
1 to 4 DB[11:8] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal). 6 DVSS Digital Common. 7 DVDD
Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a 1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8 to 14 DB[7:1] Digital Inputs.
16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common.
the on-chip QR
resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QR
CML
CML
disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
21 RLQN
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTN externally.
23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 24 RLQP
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally. 25 AVSS Analog Common. 26 AVDD Analog Supply Voltage Input (1.8 V to 3.3 V). 27 RLIP
28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s. 29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. 30 RLIN
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
CML
) is
Rev. B | Page 16 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
32
FSADJQ/AUXQ Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QR
) is disabled, this pin is the full-
Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QR
) is enabled, this pin is the auxiliary Q DAC output.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
Pin No. Mnemonic Description
31 CMLI
I DAC Output Common-Mode Level. When the internal on-chip (IR the on-chip IR
resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IR
CML
is disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
scale current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.
SET
33 FSADJI/AUXI
Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IR current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation
section. Nominal value for this external resistor is 4 kΩ for 8 mA output current. Auxiliary I DAC Output (AUXI). When the internal on-chip (IR 34 REFIO
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
SET
reference output when in internal reference mode (a 0.1 µF capacitor to AVSS is required). 35 RESET/PINMD
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
Pulse RESET high to reset the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). 36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retime, see
the
Retimer section.
37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low
(pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the
twos complement input data format. 38
CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for
the SPI port. 39 DB13 (MSB) Digital Input (MSB). 40 DB12 Digital Input. EP (EPAD)
The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the
package corners is connected to this pad.
) is enabled, this pin is connected to
CML
SET
) is disabled, this pin is the full-scale
SET
) is enabled, it is the auxiliary I DAC output.
CML
)
Rev. B | Page 17 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–2.0
–1.5
0 2048 4096 6144 8192 10,240 12,288 14,336 16,384
CODE
PRECALIBRAT ION INL (LSB)
07466-006
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–2.0
–1.5
0 2048 4096 6144 8192 10,240 12,288 14,336 16,384
CODE
PRECALIBRAT ION DNL (LS B)
07466-007
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
0 2048 4096 6144 8192 10,240 12,288 14,336 16,384
CODE
PRECALIBRAT ION INL (LSB)
07466-008
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–2.0
–1.5
0 2048 4096 6144 8192 10,240 12,288 14,336 16,384
CODE
POSTCALIBRATION INL (LSB)
07466-009
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–2.0
–1.5
0 2048 4096 6144 8192 10,240 12,288 14,336 16,384
CODE
POSTCAL IBRATION DNL ( LSB)
07466-010
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
0 2048 4096 6144 8192 10,240 12,288 14,336 16,384
CODE
POSTCALIBRATION INL (LSB)
07466-011

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD, DVDD, DVDDIO, CVDD = 1.8 V, I
= 8 mA, maximum sample rate (125 MSPS), unless otherwise noted.
xOUTFS
Figure 6. AD9117 Precalibration INL at 1.8 V, 8 mA (DVDD = 1.8 V)
Figure 7. AD9117 Precalibration DNL at 1.8 V, 8 mA (DVDD = 1.8 V)
Figure 9. AD9117 Postcalibration INL at 1.8 V, 8 mA (DVDD = 1.8 V)
Figure 10. AD9117 Postcalibration DNL at 1.8 V, 8 mA (DVDD = 1.8 V)
Figure 8. AD9117 Precalibration INL at 3.3 V, 20 mA (DVDD = 1.8 V)
Figure 11. AD9117 Postcalibration INL at 3.3 V, 20 mA (DVDD = 1.8 V)
Rev. B | Page 18 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
0 2048 4096 6144 8192 10,240 12,288 14,336 16,384
CODE
PRECALIBRAT ION DNL (LS B)
07466-012
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
0 512 1024 1536 2048 2560 3072 3584 4096
CODE
PRECALIBRAT ION INL (LSB)
07466-013
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
0 512 1024 1536 2048 2560 3072 3584 4096
CODE
PRECALIBRAT ION DNL (LS B)
07466-014
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
0 2048 4096 6144 8192 10,240 12,288 14,336 16,384
CODE
POSTCAL IBRATION DNL ( LSB)
07466-015
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
0 512 1024 1536 2048 2560 3072 3584 4096
CODE
POSTCALIBRATION INL (LSB)
07466-016
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
0 512 1024 1536 2048 2560 3072 3584 4096
CODE
POSTCAL IBRATION DNL ( LSB)
07466-017
Figure 12. AD9117 Precalibration DNL at 3.3 V, 20 mA
Figure 13. AD9116 Precalibration INL at 1.8 V, 8 mA
Figure 15. AD9117 Postcalibration DNL at 3.3 V, 20 mA
Figure 16. AD9116 Postcalibration INL at 1.8 V, 8 mA
Figure 14. AD9116 Precalibration DNL at 1.8 V, 8 mA
Rev. B | Page 19 of 52
Figure 17. AD9116 Postcalibration DNL at 1.8 V, 8 mA
AD9114/AD9115/AD9116/AD9117 Data Sheet
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
0 512 1024 1536 2048 2560 3072 3584 4096
CODE
PRECALIBRAT ION INL (LSB)
07466-018
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.5
–0.4
0 512 1024 1536 2048 2560 3072 3584 4096
CODE
PRECALIBRAT ION DNL (LS B)
07466-019
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.25
–0.20
0 128 256 384 512 640 768 896 1024
CODE
PRECALIBRAT ION INL (LSB)
07466-020
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
0 512 1024 1536 2048 2560 3072 3584 4096
CODE
POSTCALIBRATION INL (LSB)
07466-021
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.5
–0.4
0 512 1024 1536 2048 2560 3072 3584 4096
CODE
POSTCAL IBRATION DNL ( LSB)
07466-022
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.25
–0.20
0 128 256 384 512 640 768 896 1024
CODE
POSTCALIBRATION INL (LSB)
07466-023
Figure 18. AD9116 Precalibration INL at 3.3 V, 20 mA
Figure 19. AD9116 Precalibration DNL at 3.3 V, 20 mA
Figure 21. AD9116 Postcalibration INL at 3.3 V, 20 mA
Figure 22. AD9116 Postcalibration DNL at 3.3 V, 20 mA
Figure 20. AD9115 Precalibration INL at 1.8 V, 8 mA
Figure 23. AD9115 Postcalibration INL at 1.8 V, 8 mA
Rev. B | Page 20 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
0.08
0.06
0.
02
0.04
–0.02
0
–0.04
–0.06
–0.08
0 128 256 384 512 640 768 896 1024
CODE
PRECALIBRAT ION DNL (LS B)
07466-024
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.25
–0.20
0 128 256 384 512 640 768 896 1024
CODE
PRECALIBRAT ION INL (LSB)
07466-025
0.08
0.06
0.02
0.04
–0.02
0
–0.04
–0.06
–0.08
0 128 256 384 512 640 768 896 1024
CODE
PRECALIBRAT ION DNL (LS B)
07466-026
0.08
0.06
0.
02
0.04
–0.02
0
–0.04
–0.06
–0.08
0 128 256 384 512 640 768 896 1024
CODE
POSTCAL IBRATION DNL ( LSB)
07466-027
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.25
–0.20
0 128 256 384 512 640 768 896 1024
CODE
POSTCALIBRATION INL (LSB)
07466-028
0.08
0.06
0.02
0.04
–0.02
0
–0.04
–0.06
–0.08
0 128 256 384 512 640 768 896 1024
CODE
POSTCAL IBRATION DNL ( LSB)
07466-029
Figure 24. AD9115 Precalibration DNL at 1.8 V, 8 mA
Figure 25. AD9115 Precalibration INL at 3.3 V, 20 mA
Figure 27. AD9115 Postcalibration DNL at 1.8 V, 8 mA
Figure 28. AD9115 Postcalibration INL at 3.3 V, 20 mA
Figure 26. AD9115 Precalibration DNL at 3.3 V, 20 mA
Rev. B | Page 21 of 52
Figure 29. AD9115 Postcalibration DNL at 3.3 V, 20 mA
AD9114/AD9115/AD9116/AD9117 Data Sheet
0.035
0.015
0.
025
0.005
0
–0.
005
–0.015
–0.025
–0.035
0 32 64 96 128 160 192 224 256
CODE
PRECALIBRAT ION INL (LSB)
07466-030
0.025
0.020
0.015
0.010
0.005 0
–0.
005
–0.010 –0.015
–0.020
–0.025
0 32 64 96 128 160 192 224 256
CODE
PRECALIBRAT ION DNL (LS B)
07466-031
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
0 32 64 96 128 160
192 224 256
CO
DE
PRECALIBRAT ION INL (LSB)
07466-032
0.035
0.015
0.
025
0.005
0
–0.005
–0.015
–0.025
–0.035
0 32 64 96 128 160 192 224 256
CODE
POSTCALIBRATION INL (LSB)
07466-033
0.025
0.020
0.015
0.010
0.005 0
–0.005
–0.010 –0.015
–0.020
–0.025
0 32 64 96 128 160 192 224 256
CODE
POSTCAL IBRATION DNL ( LSB)
07466-034
0.03
0.02
0.01
0
–0.01
–0.
02
–0.03
0 32 64 96 128 160
192 224 256
CO
DE
POSTCALIBRATION INL (LSB)
07466-035
Figure 30. AD9114 Precalibration INL at 1.8 V, 8 mA
Figure 31. AD9114 Precalibration DNL at 1.8 V, 8 mA
Figure 33. AD9114 Postcalibration INL at 1.8 V, 8 mA
Figure 34. AD9114 Postcalibration DNL at 1.8 V, 8 mA
Figure 32. AD9114 Precalibration INL at 3.3 V, 20 mA
Figure 35. AD9114 Postcalibration INL at 3.3 V, 20 mA
Rev. B | Page 22 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
0.025
0.020
0.
015
0.010
0.005 0
–0.
005
–0.010 –0.015
–0.020
–0.025
0 32 64 96 128 160 192 224 256
CODE
PRECALIBRAT ION DNL (LS B)
07466-036
–124
–130
–136
–142
–148
–154
–160
0 10 20 30 40
50
f
OUT
(MHz)
NSD (dBc)
AD9117
AD9116
AD9115
AD9114
07466-137
–160
–136
–139
–142
–145
–148
–151
–154
–157
0 10 20 305 15 25 35 40 45 50 55
07466-201
f
OUT
(MHz)
NSD (dBm/Hz)
–40°C
+85°C
+25°C
0.025
0.020
0.015
0.010
0.005 0
–0.005
–0.010 –0.015
–0.020
–0.025
0 32 64 96 128
CODE
160 192 224 256
POSTCAL IBRATION DNL ( LSB)
07466-039
–166
–160
–154
–148
–142
–136
–130
–124
0 10 20 305 15 25 35 40 45 50 55
07466-200
f
OUT
(MHz)
NSD (dBc)
AD9117
AD9116
AD9115
AD9114
–160
–136
–139
–142
–145
–148
–151
–154
–157
0 10 20 305 15 25 35 40 45 50 55
07466-202
f
OUT
(MHz)
NSD (dBm/Hz)
–40°C
+85°C
+25°C
Figure 36. AD9114 Precalibration DNL at 3.3 V, 20 mA
Figure 37. NSD at 8 mA vs. f
OUT
, 1.8 V
Figure 39. AD9114 Postcalibration DNL at 3.3 V, 20 mA
Figure 40. NSD at 20 mA vs. f
OUT
, 3.3 V
Figure 38. AD9117 NSD at Three Temperatures 8 mA vs. f
, 1.8 V
OUT
Figure 41. AD9117 NSD at Three Temperatures 8 mA vs. f
OUT
, 3.3 V
Rev. B | Page 23 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
–166
–160
–154
–148
–142
–136
–130
0
5 10 15 20 25 30 35 40 45 50 55
f
OUT
(MHz)
NSD (dBc)
1.8V, 4mA
1.8V, 8mA
07466-142
07466-090
START 1MHz 1.5MHz/DIV STOP 16M Hz
(dBm)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
50
60
70
80
90
5 10 15 20 25 30 35 40 45 50
f
OUT
(MHz)
IMD
(dBc)
AD9117 AD9116 AD9115 AD9114
07466-144
–166
–160
–154
–148
–142
–136
–130
0 5
10 15 20 25 30 35 40 45 50 55
f
OUT
(MHz)
NSD (dBc)
3.3V, 20mA
3.3V, 8mA
3.3V, 4mA
07466-145
07466-091
START 1MHz 1.5MHz/DIV STOP 16M Hz
(dBm)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
54
66
60
72
84
78
96
90
5 10 15 20 25 30 35 40 45 50
AD9117 AD9116 AD9115 AD9114
f
OUT
(MHz)
IMD (dBc)
07466-147
Figure 42. AD9117 NSD at Two Output Currents vs. f
Figure 43. AD9117 Two Tone Spectrum at 1.8 V
OUT
, 1.8 V
Figure 45. AD9117 NSD at Three Output Currents vs. f
OUT
, 3.3 V
Figure 46. AD9117 Two Tone Spectrum at 3.3 V
Figure 44. All IMD 8 mA vs. f
OUT
, 1.8 V
Figure 47. All IMD 20 mA vs. f
OUT
, 3.3 V
Rev. B | Page 24 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
48
84
78
72
66
60
54
5 10 15 20 25 30 35 40 45 50
07466-195
f
OUT
(MHz)
IMD (dBc)
–40°C
+85°C
+25°C
45
50
55
60
65
70
75
80
85
90
5 10 15 20 25 30 35 40 45 50
0dB
–3dB
–6dB
07466-092
f
OUT
(MHz)
IMD (dBc)
50
56
62
68
74
80
86
5 10 15 20 25 30 35 40 45 50
f
OUT
(MHz)
IMD (dBc)
4mA
8mA
07466-150
63
90
87
84
81
78
75
72
69
66
5 10 15 20 25 30 35 40 45 50
07466-196
f
OUT
(MHz)
IMD (dBc)
–40°C
+85°C
+25°C
55
60
65
70
75
80
85
90
5 10 15 20 25 30 35 40 45 50
0dB
–3dB
–6dB
07466-093
f
IN
(MHz)
IMD (dBc)
56
62
68
74
80
92
86
5 10 15 20 25 30 35 40 45 50
f
OUT
(MHz)
IMD (dBc)
4mA
20mA
8mA
07466-153
Figure 48. AD9117 IMD at Three Temperatures 8 mA vs. f
Figure 49. AD9117 IMD at Three Digital Signal Levels vs. f
OUT
OUT
, 1.8 V
, 1.8 V
Figure 51. AD9117 IMD at Three Temperatures 20 mA vs. f
OUT
, 3.3 V
Figure 52. AD9117 IMD at Three Digital Signal Levels vs. f
OUT
, 3.3 V
Figure 50. AD9117 IMD at Two Output Currents vs. f
, 1.8 V
OUT
Figure 53. AD9117 IMD at Three Output Currents vs. f
OUT
, 3.3 V
Rev. B | Page 25 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
07466-088
START 1MHz 1.5MHz/DIV STOP 16M Hz
(dBm)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
40
50
60
70
80
90
0 10 20 30 40 50 60
f
OUT
(MHz)
SFDR (dBc)
AD9117 AD9116 AD9115 AD9114
07466-155
42
48
54
60
66
72
78
84
90
0 5 10 15 20 25 30 35 40 45 50 55 60
f
OUT
(MHz)
SFDR (dBc)
–40°C +25°C +85°C
07466-156
07466-089
START 1MHz 1.5MHz/DIV STOP 16M Hz
(dBm)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
54
60
66
72
84
78
90
96
0 10 20 30 40 50 60
f
OUT
(MHz)
SFDR (dBc)
AD9117 AD9116 AD9115 AD9114
07466-158
56
62
68
74
80
86
92
98
0 5 10 15 20 25 30 35 40 45 50 55 60
f
OUT
(MHz)
SFDR (dBc)
–40°C +25°C +85°C
07466-159
Figure 54. AD9117 Singe Tone Spectrum, 1.8 V
Figure 55. SFDR at 8 mA vs. f
OUT
, 1.8 V
Figure 57. AD9117 Singe Tone Spectrum, 3.3 V
Figure 58. AD9117 SFDR at 20 mA vs. f
OUT
, 3.3 V
Figure 56. AD9117 SFDR at Three Temperatures 8 mA vs. f
OUT
, 1.8 V
Figure 59. AD9117 SFDR at Three Temperatures 8 mA vs. f
OUT
, 3.3 V
Rev. B | Page 26 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
42
50
58
66
74
82
90
98
0 5 10 15 20 25 30 35 40 45 50 55 60
07466-094
f
OUT
(MHz)
SFDR (dBc)
0dB
–6dB –3dB
42
48
54
60
66
72
78
84
90
96
0 10 20 30 40 50 60
f
OUT
(MHz)
SFDR (dBc)
4mA
8mA
07466-161
CENTER 22.90MHz
TOTAL CARRIER POWER –12.17dBm/7.87420M Hz REF CARRIER POWER –12.17dBm/4.03420MHz RCC FILTER: OFF FILTER ALPHA 0.22
1. –12.17dBm 5. 000M Hz 3.840MHz –77.40 –89.56 –78. 68 –90.84
2. –80.85dBm 10.00MHz 3. 840M Hz –78.90 –91.06 –78.27 –90.43
15.00MHz 3.840MHz –78.02 –90.18 –70.99 –83.15
10dB/DIV
VBW 300kHz
OFFSET
FREQ
INTEG
BW
dBc dBm dBc
LOWER UPPER
dBm
SPAN 38.84MHz
RES BW 30kHz SWEEP 126ms (601pts)
STEP
2dB
AC COUPLED: UNS P E CIFIED
BELOW 20M Hz
INPUT ATT
8.00dB
07466-162
50
58
66
74
82
90
98
0 5 10 15 20 25 30 35 40 45 50 55 60
07466-095
f
OUT
(MHz)
SFDR (dBc)
0dB
–6dB
–3dB
42
48
54
60
66
72
78
84
90
96
0 10 20 30 40 50 60
f
OUT
(MHz)
SFDR (dBc)
4mA
8mA
20mA
07466-164
CENTER 22.90MHz
10dB/DIV
VBW 300kHz
SPAN 38.84MHz
STEP
2dB
INPUT ATT
8.00dB
TOTAL CARRIER POWER –12.17dBm/7.87420M Hz REF CARRIER POWER –12.17dBm/4.03420MHz RCC FILTER: OFF FILTER ALPHA 0.22
1. –12.17dBm 5. 000M Hz 3.840MHz –77.40 –89.56 –78. 68 –90.84
2. –80.85dBm 10.00MHz 3. 840M Hz –78.90 –91.06 –78.27 –90.43
15.00MHz 3.840MHz –78.02 –90.18 –70.99 –83.15
OFFSET
FREQ
INTEG
BW
dBc dBm dBc
LOWER UPPER
RES BW 30kHz SWEEP 126ms (601pts)
AC COUPLED: UNS P E CIFIED
BELOW 20M Hz
07466-165
Figure 60. AD9117 SFDR at Three Digital Signal Levels vs. f
Figure 61. AD9117 SFDR at Two Currents vs. f
OUT
, 1.8 V
OUT
, 1.8 V
Figure 63. AD9117 SFDR at Three Digital Signal Levels vs. f
OUT
., 3.3 V
Figure 64. AD9117 SFDR at Three Currents vs. f
OUT
, 3.3V
Figure 62. AD9117 ACLR One-Carrier, 1.8 V
Figure 65. AD9117 ACLR One-Carrier, 3.3 V
Rev. B | Page 27 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
–78
–72
–66
–60
15 20 25 30 35 40 45
f
OUT
(MHz)
ACLR (dBc)
4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL
07466-166
–80
–74
–68
–62
15 20 25 30 35 40 45
f
OUT
(MHz)
ACLR (dBc)
4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL
07466-167
–80
–74
–68
–62
20 25 30 35 40 45
f
OUT
(MHz)
ACLR (dBc)
4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL
07466-168
–78
–72
–66
–60
15 20 25 30 35 40 45
f
OUT
(MHz)
ACLR (dBc)
4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL 16mA PRECAL 16mA POSTCAL
07466-169
–80
–74
–68
–62
15 25 35 45
f
OUT
(MHz)
ACLR (dBc)
4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL 16mA PRECAL 16mA POSTCAL
07466-170
–80
–74
–68
–62
20 25 30 35 40 45
f
OUT
(MHz)
ACLR (dBc)
4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL 16mA PRECAL 16mA POSTCAL
07466-171
Figure 66. AD9117 One-Carrier W-CDMA First ACLR vs. f
OUT
, 1.8 V
Figure 69. AD9117 One-Carrier W-CDMA First ACLR vs. f
OUT
, 3.3 V
Figure 67. AD9117 One-Carrier W-CDMA Second ACLR vs. f
Figure 68. AD9117 One-Carrier W-CDMA Third ACLR vs. f
OUT
OUT
, 1.8 V
, 1.8 V
Figure 70. AD9117 One-Carrier W-CDMA Second ACLR vs. f
OUT
, 3.3 V
Figure 71. AD9117 One-Carrier W-CDMA Third ACLR vs. f
OUT
, 3.3 V
Rev. B | Page 28 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
CENTER 22.90MHz
10dB/DIV
VBW 300kHz
SPAN 38.84MHz
STEP
2dB
INPUT ATT
8.00dB
TOTAL CARRIER POWER –15.23dBm/7.87420M Hz REF CARRIER POWER –18.09dBm/4.03420MHz RCC FILTER: OFF FILTER ALPHA 0.22
1. –18.09dBm 5. 000M Hz 3.840MHz –72.11 –90.24 –71. 97 –90.09
2. –18.40dBm 10.00MHz 3. 840M Hz –72.98 –91.10 –72.55 –90.68
15.00MHz 3.840MHz –69.93 –88.05 –72.30 –90.42
OFFSET
FREQ
INTEG
BW
dBc dBm dBc
LOWER UPPER
dBm
RES BW 30kHz SWEEP 126ms (601pts)
AC COUPLED: UNS P E CIFIED
BELOW 20M Hz
07466-172
–74
–68
–62
–56
–50
15 20 25 30 35 40
f
OUT
(MHz)
ACLR (dBc)
4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL
07466-173
–74
–68
–62
–56
–50
15 20 25 30 35 40
f
OUT
(MHz)
ACLR (dBc)
4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL
07466-174
CENTER 22.90MHz
10dB/DIV
VBW 300kHz
SPAN 38.84MHz
STEP
2dB
INPUT ATT
8.00dB
TOTAL CARRIER POWER –15.23dBm/7.87420M Hz REF CARRIER POWER –18.09dBm/4.03420MHz RCC FILTER: OFF FILTER ALPHA 0.22
1. –18.09dBm 5. 000M Hz 3.840MHz –72.11 –90.24 –71. 97 –90.09
2. –18.40dBm 10.00MHz 3. 840M Hz –72.98 –91.10 –72.55 –90.68
15.00MHz 3.840MHz –69.93 –88.05 –72.30 –90.42
OFFSET
FREQ
INTEG
BW
dBc dBm dBc
LOWER UPPER
dBm
RES BW 30kHz SWEEP 126ms (601pts)
AC COUPLED: UNS P E CIFIED
BELOW 20M Hz
07466-175
–74
–68
–62
–56
–50
15 20 25 30 35 40
f
OUT
(MHz)
ACLR (dBc)
4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL 16mA PRECAL 16mA POSTCAL
07466-176
–74
–68
–62
–56
–50
15 20 25 30 35 40
f
OUT
(MHz)
ACLR (dBc)
4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL 16mA PRECAL 16mA POSTCAL
07466-177
Figure 72. AD9117 ACLR Two-Carrier, 1.8 V
Figure 73. AD9117 Two-Carrier W-CDMA First ACLR vs. f
OUT
, 1.8 V
Figure 75. AD9117 ACLR Two-Carrier, 3.3 V
Figure 76. AD9117 Two-Carrier W-CDMA First ACLR vs. f
OUT
, 3.3 V
Figure 74. AD9117 Two-Carrier W-CDMA Second ACLR vs. f
OUT
, 1.8 V
Figure 77. AD9117 Two-Carrier W-CDMA Second ACLR vs. f
OUT
, 3.3 V
Rev. B | Page 29 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
–74
–68
–56
–62
–50
20 25 30 35 40
f
OUT
(MHz)
ACLR (dBc)
4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL
07466-178
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.5
–0.4
0
CODE
AUXDAC DNL (LSB)
128 256 384 512 640 768 896 1024
07466-047
CVDD
DVDD
AVDD @ 4mA OUT
AVDD @ 8mA OUT
TOTAL CURRE NT
@ 4mA OUT
TOTAL CURRE NT @ 8mA OUT
40
30
20
10
0
0 20 40 60 80 100 120 140
f
DAC
(MHz)
SUPPLY CURRENT (mA)
07466-048
–74
–68
–56
–62
–50
20 25 30 35 40
f
OUT
(MHz)
ACLR (dBc)
4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL 16mA PRECAL 16mA POSTCAL
07466-181
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–1.0
–0.8
0
CODE
AUXDAC INL (L S B)
128 256
384 512 640 768 896 1024
07466-044
0
10
20
30
40
50
60
70
80
0 20 40 60 80 100 12
0 140
f
DAC
(MHz)
CURRENT (mA)
CVDD
DVDD
AVDD @ 20mA OUT
TOTAL CURRE NT @ 20mA OUT
TOTAL CURRE NT @ 8mA OUT
TOTAL CURRE NT @ 4mA OUT
AVDD @ 8mA OUT
AVDD @ 4mA OUT
07466-183
Figure 78. AD9117 Two-Carrier W-CDMA Third ACLR vs. f
Figure 79. AD9114/AD9115/AD9116/AD9117 AUXDAC DNL
OUT
, 1.8 V
Figure 81. AD9117 Two-Carrier W-CDMA Third ACLR vs. f
OUT
, 3.3 V
Figure 82. AD9114/AD9115/AD9116/AD9117 AUXDAC INL
Figure 80. AD9114/AD9115/AD9116/AD9117 Supply Current vs. f
DAC
, 1.8 V
Figure 83. AD9114/AD9115/AD9116/AD9117Supply Current vs. f
DAC
, 3.3 V
Rev. B | Page 30 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117

TERMINOLOGY

Linearity Error or Integral Nonlinearity (INL)
Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output either increases or remains constant as the digital input increases.
Offset Error
Offset error is the deviation of the output current from the ideal of zero. For I are all 0. For I
, the 0 mA output is expected when the inputs
OUTP
, the 0 mA output is expected when all inputs
OUTN
are set to 1.
Gain Error
Gain error is the difference between the actual and the ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0.
Output Compliance Range
The output compliance range is the range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the ambient value (25°C) to the value at either T
MIN
or T
MAX
. For offset and gain drift, the drift is reported in ppm of full­scale range per degree Celsius (ppm FSR/°C). For reference drift, the drift is reported in parts per million per degree Celsius (ppm/°C).
Power Supply Rejection
Power supply rejection is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages.
Settling Time
Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage (%) or in decibels (dB).
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequenc y, excluding the first six harmonics and dc. The value for SNR is expressed in decibels (dB).
Adjacent Channel Leakage Ratio (ACLR)
ACLR is the ratio in decibels relative to the carrier (dBc) between the measured power within a channel relative to its adjacent channel.
Complex Image Rejection
In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.
Rev. B | Page 31 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
I DAC
Q DAC
AUX1DAC
AUX2DAC
BAND
GAP
CLOCK
DIST
10kΩ
QR
SET
2kΩ
IR
SET
2kΩ
I
REF
100µA
IR
CM
60Ω TO
260Ω
QR
CM
60Ω TO
260Ω
62.5Ω
62.5Ω
62.5Ω
62.5Ω
SPI
INTERFACE
1 INTO 2
INTERLEAVED
DATA
INTERFACE
I DATA
Q DATA
1.8V LDO
1V
AD9117
RLIN
IOUTN IOUTP
RLIP AVDD AVSS RLQP
QOUTP QOUTN
RLQN
DB11
DB10
DB9
DB8
DVDDIO
DVSS
DVDD
DB7
DB6
DB5
DB12
DB13 (MSB)
CS/PWRDN
SDIO/FORMAT
SCLK/CLKMD
RESET/PINMD
REFIO
FSADJQ/AUXQ
FSADJI/AUXI
CMLI
DB4
DB3
DB2
DB1
(LSB) DB0
DCLKIO
CVDD
CLKIN
CVSS
CMLQ
07466-050

THEORY OF OPERATION

Figure 84. Simplified Block Diagram
Figure 84 shows a simplified block diagram of the AD9114/ AD9115/AD9116/AD9117 that consists of two DACs, digital control logic, and a full-scale output current control. Each DAC contains a PMOS current source array capable of providing a maximum of 20 mA. The arrays are divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16 of an MSB current source. The remaining LSBs are binary weighted fractions of the current sources of the middle bits. Implementing the middle and lower bits with current sources, instead of an R-2R ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the high output impedance of the main DACs (that is, >200 MΩ).
The current sources are switched to one or the other of the two output nodes (I switches. The switches are based on the architecture that was pioneered in the AD976x family, with further refinements to reduce distortion contributed by the switching transient. This switch architecture also reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches.
The analog and digital I/O sections of the AD9114/AD9115/
OUTP
or I
) via PMOS differential current
OUTN
AD9116/AD9117 have separate power supply inputs (AVDD and DVDDIO) that can operate independently over a 1.8 V to 3.3 V range. The core digital section requires 1.8 V. An optional on-chip
Rev. B | Page 32 of 52
LDO is provided for DVDDIO supplies greater than 1.8 V, or the
1.8 V can be supplied directly through DVDD. A 1.0 µF bypass capacitor at DVDD (Pin 7) is required when using the LDO.
The core is capable of operating at a rate of up to 125 MSPS. It consists of edge-triggered latches and the segment decoding logic circuitry. The analog section includes PMOS current sources, associated differential switches, a 1.0 V band gap voltage reference, and a reference control amplifier.
Each DAC full-scale output current is regulated by the reference control amplifier and can be set from 4 mA to 20 mA via an external resistor, xR
The external resistor, in combination with both the reference control amplifier and voltage reference, V I
, which is replicated to the segmented current sources with the
xREF
proper scaling factor. The full-scale current, I
Optional on-chip xR grammed between a nominal value of 1.6 kΩ to 8 kΩ (20 mA to 4 mA I
The AD9114/AD9115/AD9116/AD9117 provide the option of setting the output common mode to a value other than AGND via the output common-mode pin (CMLI and CMLQ). This facilitates directly interfacing the output of the AD9114/AD9115/AD9116/ AD9117 to components that require common-mode levels greater t h a n 0 V.
, connected to its full-scale adjust pin (FSADJx).
SET
, sets the reference current,
, respectively).
xOUTFS
resistors are provided that can be pro-
SET
REFIO
xOUTFS
, is 32 × I
xREF
.
Data Sheet AD9114/AD9115/AD9116/AD9117

SERIAL PERIPHERAL INTERFACE (SPI)

The serial port of the AD9114/AD9115/AD9116/AD9117 is a flexible, synchronous serial communications port that allows easy interfacing to many industry-standard microcontrollers and micro­processors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD9114/AD9115/AD9116/AD9117. Single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The serial interface port of the AD9114/ AD9115/AD9116/AD9117 is configured as a single I/O pin on the SDIO pin.

GENERAL OPERATION OF THE SERIAL INTERFACE

There are two phases to a communication cycle on the AD9114/ AD9115/AD9116/AD9117. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9114/AD9115/ AD9116/AD9117, coinciding with the first eight SCLK rising edges. In Phase 2, the instruction byte provides the serial port controller of the AD9114/AD9115/AD9116/AD9117 with infor­mation regarding the data transfer cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9114/AD9115/AD9116/AD9117.
A Logic 1 on Pin 35 (RESET/PINMD), followed by a Logic 0, resets the SPI port timing to the initial state of the instruction cycle. This is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the SPI port. If the SPI port is in the midst of an instruction cycle or a data transfer cycle, none of the present data is written.
The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9114/ AD9115/AD9116/AD9117 and the system controller. Phase 2 of the communication cycle is a transfer of one, two, three, or four data bytes, as determined by the instruction byte. Using a multibyte transfer is the preferred method. Single byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte.

INSTRUCTION BYTE

The instruction byte contains the information shown in Tabl e 11.
N1 and N0 (Bit 6 and Bit 5 of the instruction byte) determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in Tabl e 12.
Table 12. Byte Transfer Count
N1 N0 Description
0 0 Transfer 1 byte 0 1 Transfer 2 bytes 1 0 Transfer 3 bytes 1 1 Transfer 4 bytes
A4, A3, A2, A1, and A0 (Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the instruction byte) determine which register is accessed during the data transfer portion of the communications cycle. For multi­byte transfers, this address is the starting byte address. The following register addresses are generated internally by the AD9114/AD9115/AD9116/AD9117 based on the LSBFIRST bit (Register 0x00, Bit 6).

SERIAL INTERFACE PORT PIN DESCRIPTIONS

SCLK—Serial Clock

The serial clock pin is used to synchronize data to and from the AD9114/AD9115/AD9116/AD9117 and to run the internal state machines. The SCLK maximum frequency is 25 MHz. All data input to the AD9114/AD9115/AD9116/AD9117 is registered on the rising edge of SCLK. This is shown in Figure 85 and Figure 87 for write instructions where the SCLK rising edges are lined up in the middle of the data. All data is driven out of the AD9114/AD9115/ AD9116/AD9117 on the falling edge of SCLK. This is shown in Figure 86 and Figure 88 for read cycles where the SCLK falling edges line up in the middle of the data in the data transfer cycle.
CS

—Chip Select

An active low input starts and gates a communications cycle. It allows more than one device to be used on the same serial commu­nications lines. The SDIO/FORMAT pin reaches a high impedance state when this input is high. Chip select should stay low during the entire communication cycle.

SDIO—Serial Data I/O

The SDIO pin is used as a bidirectional data line to transmit and receive data.
Table 11.
MSB LSB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R/W
R/W (Bit 7 of the instruction byte) determines whether a read or a write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation. Logic 0 indicates a write operation.
N1 N0 A4 A3 A2 A1 A0
Rev. B | Page 33 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
R/W N1 N0 A4 A3 A2 A1 A0 D7ND6ND5
N
D00D10D20D3
0
INSTRUCTI ON CYCLE DATA TRANSFER CYCLE
CS
SCLK
SDIO
07466-291
R/W N1 N0 A4 A3 A2 A1 A0D7D6
N
D5
N
D00D1
0D20
D3
0
INSTRUCTI ON CYCLE DATA TRANSFER CYCLE
SCLK
SDIO
SDO
07466 -290
CS
A0 A1 A2 A3 A4 N0 N1 R/W D0
0D10
D2
0
D7ND6ND5ND4
N
INSTRUCTI ON CYCLE DATA TRANSFER CYCLE
SCLK
SDIO
07466-289
CS
INSTRUCTI ON CYCLE DATA TRANSFER CYCLE
SCLK
SDIO
SDO
A0 A1 A2 A3 A4 N0 N1 R/W D1
0
D2
0
D7
N
D6
N
D5
N
D4
N
D0
07466-288
CS

MSB/LSB TRANSFERS

The serial port of the AD9114/AD9115/AD9116/AD9117 can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the LSBFIRST bit (Register 0x00, Bit 6). The default is MSB first (LSBFIRST = 0).
When LSBFIRST = 0 (MSB first), the instruction and data bytes must be written from the most significant bit to the least significant bit. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes should follow in order from a high address to a low address. In MSB first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communications cycle.
When LSBFIRST = 1 (LSB first), the instruction and data bytes must be written from the least significant bit to the most significant bit. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The serial port internal byte address generator increments for each byte of the multibyte communication cycle.
If the MSB first mode is active, the serial port controller data address of the AD9114/AD9115/AD9116/AD9117 decrements from the data address written toward 0x00 for multibyte I/O operations. If the LSB first mode is active, the serial port controller address increments from the data address written toward 0x1F for multibyte I/O operations.

SERIAL PORT OPERATION

The serial port configuration of the AD9114/AD9115/AD9116/ AD9117 is controlled by Register 0x00. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register can occur during the middle of the communications cycle. Care must be taken to compensate for this new configu­ration for the remaining bytes of the current communications cycle.
The same considerations apply to setting the software reset bit (Register 0x00, Bit 5). All registers are set to their default values except Register 0x00, which remains unchanged.
Use of single-byte transfers or initiating a software reset is recommended when changing serial port configurations to prevent unexpected device behavior.
Figure 86. Serial Register Interface Timing, MSB First Read
Figure 87. Serial Register Interface Timing, LSB First Write
Figure 88. Serial Register Interface Timing, LSB First Read

PIN MODE

The AD9114/AD9115/AD9116/AD9117 can also be operated without ever writing to the serial port. With RESET/PINMD (Pin 35) tied high, the SCLK pin becomes CLKMD to provide for clock mode control (see the Retimer section), the SDIO pin becomes FORMAT and selects the input data format, and
CS
the
/PWRDN pin serves to power down the device. The pins are not latched at power up. If you change the format, it should change with about a 1µs delay.
Operation is otherwise exactly as defined by the default register values in Tabl e 13; therefore, external resistors at FSADJI and FSADJQ are needed to set the DAC currents, and both DACs are active. This is also a convenient quick checkout mode. DAC currents can be externally adjusted in pin mode by sourcing or sinking currents at the FSADJI/AUXI and FSADJQ/AUXQ pins, as desired, with the fixed resistors installed. An op amp output with appropriate series resistance is one of many possibilities. This has the same effect as changing the resistor value. Place at least 10 kΩ resistors in series right at the DAC to guard against accidental short circuits and noise modulation. The REFIO pin can be adjusted ±25% in a similar manner, if desired.
Figure 85. Serial Register Interface Timing, MSB First Write
Rev. B | Page 34 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
Memory R/W
0x12
0x00
CALRSTQ
CALRSTI
CALEN
SMEMWR
SMEMRD
UNCALQ
UNCALI

SPI REGISTER MAP

Table 13.
Name Addr Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SPI Control 0x00 0x00 Reserved LSBFIRST Reset LNGINS Reserved Power-Down 0x01 0x40 LDOOFF LDOSTAT PWRDN Q DACOFF I DACOFF QCLKOFF ICLKOFF EXTREF Data Control 0x02 0x34 TWOS Reserved IFIRST IRISING SIMULBIT DCI_EN DCOSGL DCODBL I DAC Gain 0x03 0x00 Reserved I DACGAIN[5:0] IRSET 0x04 0x00 IRSETEN Reserved IRSET[5:0] IRCML 0x05 0x00 IRCMLEN Reserved IRCML[5:0] Q DAC Gain 0x06 0x00 Reserved Q DACGAIN[5:0] QRSET 0x07 0x00 QRSETEN Reserved QRSET[5:0] QRCML 0x08 0x00 QRCMLEN Reserved QRCML[5:0] AUXDAC Q 0x09 0x00 QAUXDAC[7:0] AUX CTLQ 0x0A 0x00 QAUXEN QAUXRNG[1:0] QAUXOFS[2:0] QAUXDAC[9:8] AUXDAC I 0x0B 0x00 IAUXDAC[7:0] AUX CTLI 0x0C 0x00 IAUXEN IAUXRNG[1:0] IAUXOFS[2:0] IAUXDAC[9:8] Reference Resistor 0x0D 0x00 Reserved RREF[5:0] Cal Control 0x0E 0x00 PRELDQ PRELDI CALSELQ CALSELI CALCLK DIVSEL[2:0] Cal Memory 0x0F 0x00 CAL S TATQ CAL S TATI Reserved CALMEMQ[1:0] CALMEMI[1:0] Memory Address 0x10 0x00 Reserved MEMADDR[5:0] Memory Data 0x11 0x34 Reserved MEMDATA[5:0]
CLKMODE 0x14 0x00 CLKMODEQ[1:0] Searching Reacquire CLKMODEN CLKMODEI[1:0] Version 0x1F 0x09 Version[7:0]
Rev. B | Page 35 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
1: set software reset; write 0 on the next (or any following) cycle to release reset.
Power Down
0x01 7 LDOOFF
0 (default): LDO voltage regulator on.
1: turns off Q DAC clock.
0: data clock input disabled.
0 (default): DCODBL data clock output disabled.

SPI REGISTER DESCRIPTIONS

Reading these registers returns previously written values for all defined register bits, unless otherwise noted.
Table 14.
Register Address Bit Name Description
SPI Control 0x00 6 LSBFIRST 0 (default): MSB first per SPI standard. 1: LSB first per SPI standard.
5 Reset
4 LNGINS 0 (default): the SPI instruction word uses a 5-bit address. 1: the SPI instruction word uses a 13-bit address.
Note that the user must always change the LSB/MSB order in single-byte instructions to avoid erratic behavior due to bit order errors.
Executes software reset of SPI and controllers, reloads default register values, except Register 0x00.
1: powers down the internal voltage reference (external reference required). Data Control 0x02 7 TWOS 0 (default): Unsigned binary input data format. 1: twos complement input data format. 5 IFIRST 0: pairing of data—Q first of pair on data input pads. 1(default): pairing of data—I first of pair on data input pads (default). 4 IRISING 0: Q data latched on DCLKIO rising edge. 1(default): I data latched on DCLKIO rising edge (default). 3 SIMULBIT 0 (default): allows simultaneous input and output enable on DCLKIO. 1: disallows simultaneous input and output enable on DCLKIO. 2 DCI_EN Controls the use of the DCLKIO pad for the data clock input.
1: turns core LDO voltage regulator off. 6 LDOSTAT 0: indicates that the core LDO voltage regulator is off. 1 (default): indicates that the core LDO voltage regulator is on. 5 PWRDN 0 (default): all analog, digital circuitry and SPI logic are powered on. 1: powers down all analog and digital circuitry, except for SPI logic. 4 Q DACOFF 0 (default): turns on Q DAC output current. 1: turns off Q DAC output current. 3 I DACOFF 0 (default): turns on I DAC output current. 1: turns off I DAC output current. 2 QCLKOFF 0 (default): turns on Q DAC clock.
1 ICLKOFF 0 (default): turns on I DAC clock. 1: turns off I DAC clock. 0 EXTREF 0 (default): turns on internal voltage reference.
1(default): data clock input enabled. 1 DCOSGL Controls the use of the DCLKIO pad for the data clock output. 0 (default): data clock output disabled. 1: data clock output enabled; regular strength driver. 0 DCODBL Controls the use of the DCLKIO pad for the data clock output.
1: DCODBL data clock output enabled; paralleled with DCOSGL for 2× drive current. I DAC Gain 0x03 5:0 I DACGAIN[5:0]
DAC I fine gain adjustment; alters the full-scale current, as shown in Figure 99. Default IDACGAIN = 0x00.
Rev. B | Page 36 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
000000 (default): QR
= 2 kΩ.
011: sets AUXDAC Q top of range to 2.5 V.
Register Address Bit Name Description
IRSET 0x04 7 IRSETEN
0 (default): IR
to the FADJI/AUXI pin. Nominal value for this external resistor is 4 kΩ. 1: enables the on-chip IR 5:0 IRSET[5:0]
Changes the value of the on-chip IR
the DAC in ~0.25 dB steps twos complement (nonlinear), see Figure 98. 000000 (default): IR 011111: IR 100000: IR 111111: IR IRCML 0x05 7 IRCMLEN
0 (default): IR
connected to CMLI pin. Recommended value for this external resistor is 0 Ω. 1: enables on-chip IR 5:0 IRCML[5:0]
Changes the value of the on-chip IR
common-mode level of the DAC output stage. 000000 (default): IR 100000: IR 111111: IR Q DAC Gain 0x06 5:0 Q DACGAIN[5:0]
DAC Q fine gain adjustment; alters the full-scale current, as shown in Figure 99.
Default QDACGAIN = 0x00. QRSET 0x07 7 QRSETEN
0 (default): QR
connected to FADJI/AUXI pin. Nominal value for this external resistor is 4 kΩ. 1: enables on-chip QR 5:0 QRSET[5:0]
Changes the value of the on-chip QR
the DAC in ~0.25 dB steps twos complement (nonlinear).
011111: QR 100000: QR 111111: QR QRCML 0x08 7 QRCMLEN
0 (default): QR
connected to CMLQ pin. Recommended value for this external resistor is 0 Ω. 1: enables on-chip QR 5:0 QRCML[5:0]
Changes the value of the on-chip QR
common-mode level of the DAC output stage. 000000 (default): QR 100000: QR 111111: QR AUXDAC Q 0x09 7:0 QAUXDAC[7:0] AUXDAC Q output voltage adjustment word LSBs. 0x3FF: sets AUXDAC Q output to full scale. 0x200: sets AUXDAC Q output to midscale. 0x000 (default): sets AUXDAC Q output to bottom of scale. AUX CTLQ 0x0A 7 QAUXEN 0 (default): AUXDAC Q output disabled. 1: enables AUXDAC Q output. 6:5 QAUXRNG[1:0] 00 (default): sets AUXDAC Q output voltage range to 2 V. 01: sets AUXDAC Q output voltage range to 1.5 V. 10: sets AUXDAC Q output voltage range to 1.0 V. 11: sets AUXDAC Q output voltage range to 0.5 V. 4:2 QAUXOFS[2:0] 000 (default): sets AUXDAC Q top of range to 1.0 V. 001: sets AUXDAC Q top of range to 1.5 V. 010: sets AUXDAC Q top of range to 2.0 V.
resistor value for I channel is set by an external resistor connected
SET
value to be changed for I channel.
SET
resistor; this scales the full-scale current of
SET
= 2 kΩ.
SET
= 8 kΩ.
SET
= 1.6 kΩ.
SET
= 2 kΩ.
SET
resistor value for the I channel is set by an external resistor
CML
adjustment for I channel.
CML
resistor for I channel; this adjusts the
CML
= 60 Ω.
CML
= 160 Ω.
CML
= 260 Ω.
CML
resistor value for Q channel is set by an external resistor
SET
adjustment for Q channel.
SET
resistor; this scales the full-scale current of
SET
SET
= 8 kΩ.
SET
= 1.6 kΩ.
SET
= 2 kΩ.
SET
resistor value for the Q channel is set by an external resistor
CML
adjustment.
CML
resistor for Q channel; this adjusts the
CML
= 60 Ω.
CML
= 160 Ω.
CML
= 260 Ω.
CML
100: sets AUXDAC Q top of range to 2.9 V. 1:0 QAUXDAC[9:8] AUXDAC Q output voltage adjustment word MSBs (default = 00).
Rev. B | Page 37 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
01: sets AUXDAC I output voltage range to 1.5 V.
011: sets AUXDAC I top of range to 2.5 V.
111111: sets the value of R
to 10 kΩ, V
= 1.0 V.
6
PRELDI
0 (default): preloads I DAC calibration reference set to 32.
…
Cal Memory
0x0F 7 CALSTATQ
0 (default): Q DAC calibration in progress.
10: user-calibrated.
Register Address Bit Name Description
AUXDAC I 0x0B 7:0 IAUXDAC[7:0] AUXDAC I output voltage adjustment word LSBs. 0x3FF: sets AUXDAC I output to full scale. 0x200: sets AUXDAC I output to midscale. 0x000 (default): sets AUXDAC I output to bottom of scale. AUX CTLI 0x0C 7 IAUXEN 0 (default): AUXDAC I output disabled. 1: enables AUXDAC I output. 6:5 IAUXRNG[1:0] 00 (default): sets AUXDAC I output voltage range to 2 V.
10: sets AUXDAC I output voltage range to 1.0 V. 11: sets AUXDAC I output voltage range to 0.5 V. 4:2 IAUXOFS[2:0] 000 (default): sets AUXDAC I top of range to 1.0 V. 001: sets AUXDAC I top of range to 1.5 V. 010: sets AUXDAC I top of range to 2.0 V.
100: sets AUXDAC I top of range to 2.9 V. 1:0 IAUXDAC[9:8] AUX DAC I output voltage adjustment word MSBs (default = 00). Reference
Resistor 000000 (default): sets the value of R 011111: sets the value of R 100000: sets the value of R
Cal Control 0x0E 7 PRELDQ 0 (default): preloads Q DAC calibration reference set to 32. 1: preloads Q DAC calibration reference set by user (Cal Address 1).
0x0D 5:0 RREF[5:0]
Permits an adjustment of the on-chip reference voltage and output at REFIO (see Figure 97) twos complement.
to 12 kΩ, V
REF
to 8 kΩ, V
REF
REF
to 10 kΩ, V
REF
= 1.2 V.
REF
= 0.8 V.
REF
REF
= 1.0 V.
REF
1: preloads I DAC calibration reference set by user (Cal Address 1). 5 CALSELQ 0 (default): Q DAC self-calibration done. 1: selects Q DAC self-calibration. 4 CALSELI 0 (default): I DAC self-calibration done. 1: selects I DAC self-calibration. 3 CALCLK 0 (default): calibration clock disabled. 1: calibrates clock enabled. 2:0 DIVSEL[2:0] Calibration clock divide ratio from DAC clock rate. 000 (default): divide by 256. 001: divide by 128.
110: divide by 4. 111: divide by 2.
1: calibration of Q DAC complete. 6 CALSTATI 0 (default): I DAC calibration in progress. 1: calibration of I DAC complete. 3:2 CALMEMQ[1:0] Status of Q DAC calibration memory. 00 (default): uncalibrated. 01: self-calibrated. 10: user-calibrated. 1:0 CALMEMI[1:0] Status of I DAC calibration memory. 00 (default): uncalibrated. 01: self-calibrated.
Memory Address 0x10 5:0 MEMADDR[5:0] Address of static memory to be accessed. Memory Data 0x11 5:0 MEMDATA[5:0] Data for static memory access.
Rev. B | Page 38 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
4
CALEN
0 (default): no action.
1
UNCALQ
0 (default): no action.
2
CLKMODEN
Register Address Bit Name Description
Memory R/W 0x12 7 CALRSTQ 0 (default): no action. 1: clears CALSTATQ. 6 CALRSTI 0 (default): no action. 1: clears CALSTATI.
1: initiates device self-calibration. 3 SMEMWR 0 (default): no action. 1: writes to static memory (calibration coefficients). 2 SMEMRD 0 (default): no action. 1: reads from static memory (calibration coefficients).
1: resets Q DAC calibration coefficients to default (uncalibrated). 0 UNCALI 0 (default): no action. 1: resets I DAC calibration coefficients to default (uncalibrated). CLKMODE 0x14 7:6 CLKMODEQ[1:0]
If CLKMODEN = 0, read only; reports the clock phase chosen by the retime.
4 Searching Datapath retimer status bit. 0 (default): clock relationship established.
3 Reacquire Edge triggered, 0 to 1 causes the retimer to reacquire the clock relationship.
1: CLKMODE values set in CLKMODEI[1:0] override both I and Q retimers. 1:0 CLKMODEI[1:0]
If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer.
Version 0x1F 7:0 Version[7:0]
Depending on CLKMODEN bit setting, these two bits reflect the phase relationship
between DCLKIO and CLKIN, as described in Table 16.
If CLKMODEN = 1, read/write; value in this register sets Q clock phases; force if
needed to better synchronize the DACs (see the Retimer section).
1: indicates that the internal datapath retimer is searching for clock relationship
(device output is not usable while this bit is high).
0 (default): CLKMODEI/CLKMODEQ values computed by the two retimers and read
back in CLKMODEI[1:0] and CLKMODEQ[1:0].
Depending on CLKMODEN bit setting, these two bits reflect the phase relationship
between DCLKIO and CLKIN, as described in Table 16.
If CLKMODEN = 1, read/write; value in this register sets I clock phases; force if
needed to better synchronize the DACs (see the Retimer section).
Hardware version of the device. This register is set to 0x09 for the latest version of
the device.
Rev. B | Page 39 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
DCLKIO
NOTES:
1. DB[n:0], WHERE n I S 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE AD9116, AND 13 FOR T HE AD9117.
DB[n:0]
Z A B C D E F G H
I DATA Z B D F
Q DATA Y A C E
07466-051
DCLKIO
Z A B C D E F G H
I DATA Y A C E
Q DATA X Z B D
07466-052
NOTES:
1. DB[n:0], WHERE n I S 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE AD9116, AND 13 FOR T HE AD9117.
DB[n:0]
DCLKIO
Z A B C D E F G H
I DATA Z B D F
Q DATA A C E G
07466-053
NOTES:
1. DB[n:0], WHERE n I S 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE AD9116, AND 13 FOR T HE AD9117.
DB[n:0]
DCLKIO
Z A B C D E F G H
I DATA Y A C E
Q DATA Z B D F
07466-054
NOTES:
1. DB[n:0], WHERE n I S 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE AD9116, AND 13 FOR T HE AD9117.
DB[n:0]
DCLKIO
DB[n:0]
t
S
t
H
t
StH
07466-055
NOTES:
1. DB[n:0], WHERE n I S 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR T HE AD9116, AND 13 FOR THE AD9117.

DIGITAL INTERFACE OPERATION

Digital data for the I and Q DACs is supplied over a single parallel bus (DB[n:0], where n is 7 for the AD9114, is 9 for the AD9115, is 11 for the AD9116, and 13 for the AD9117) accompanied by a qualifying clock (DCLKIO). The I and Q data are provided to the chip in an interleaved double data rate (DDR) format. The maximum guaranteed data rate is 250 MSPS with a 125 MHz clock. The order of data pairing and the sampling edge selection is user programmable using the IFIRST and IRISING data control bits, resulting in four possible timing diagrams. These timing diagrams are shown in Figure 89, Figure 90, Figure 91, and Figure 92.
Figure 91. Timing Diagram with IFIRST = 1, IRISING = 0
Figure 89. Timing Diagram with IFIRST = 0, IRISING = 0
Figure 92. Timing Diagram with IFIRST = 1, IRISING = 1
Ideally, the rising and falling edges of the clock fall in the center of the keep-in window formed by the setup and hold times, t and t
. Refer to Tabl e 2 for setup and hold times. A detailed
H
S
timing diagram is shown in Figure 93.
Figure 90. Timing Diagram with IFIRST = 0, IRISING = 1
Figure 93. Setup and Hold Times for All Input Modes
In addition to the different timing modes listed in Tabl e 2, the input data can also be presented to the device in either unsigned binary or twos complement format. The format type is chosen via the TWOS data control bit.
Rev. B | Page 40 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
3
2
1
0
D-FF
D-FF
4
D-FFD-FF D-FF
OR
DCLKIO-INT CLKIN-INT
DB[n:0] (INPUT)
TO DAC CORE
I
OUT
I
OUT
DELAY1
DELAY2
DELAY1
RETIMER-CLK
IE
IE
OE
DCLKIO
(INPUT/OUTPUT)
CLKIN
(INPUT)
NOTES D-FFs: 0: RISING OR FALLING EDGE TRIGGERED FOR I OR Q DATA. 1, 2, 3, 4: RISING EDGE TRIGGERED.
RETIMER-CLK
07466-056
NOTES:
1. DB[n:0], WHERE n I S 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE AD9116, AND 13 FOR THE AD9117.
1/2 PERIOD
1/4 PERIOD 1/2 PERIOD
DATA
CLOCK
RETIMER-CLKs
180° 90° 270°
07466-057
Figure 94. Simplified Diagram of AD9114/AD9115/AD9116/AD9117 Timing

DIGITAL DATA LATCHING AND RETIMER SECTION

The AD9114/AD9115/AD9116/AD9117 have two clock inputs, DCLKIO and CLKIN. The CLKIN is the analog clock whose jitter affects DAC performance, and the DCLKIO is a digital clock from an FPGA that needs to have a fixed relationship with the input data to ensure that the data is sampled correctly by the flip-flops on the pads.
Figure 94 is a simplified diagram of the entire data capture system in the AD9114/AD9115/AD9116/AD9117. The double data rate input data (DB[n:0], where n is 7 for the AD9114, is 9 for the AD9115, is 11 for the AD9116, and 13 for the AD9117) is latched at the pads/pins either on the rising edge or the falling edge of the DCLKIO-INT clock, as determined by IRISING, Bit 4 of SPI Address 0x02. Bit 5 of SPI Address 0x02, IFIRST, determines which channel data is latched first (that is, I or Q). The captured data is then retimed to the internal clock (CLKIN-INT) in the retimer block before being sent to the final analog DAC core (D-FF 4), which controls the current steering output switches. All delay blocks depicted in Figure 94 are non-inverting, and any wires without an explicit delay block can be assumed to have no delay.
Only one channel is shown in Figure 94 with the data pads (DB[n:0], where n is 7 for the AD9114, is 9 for the AD9115, is 11 for the AD9116, and 13 for the AD9117) serving as double data rate pads for both channels.
The default PINMD and SPI settings are IE = high (closed) and OE = low (open). These settings are enabled when RESET/PINMD (Pin 35) is held high. In this mode, the user has to supply both DCLKIO and CLKIN. In PINMD, it is also recommended that the DCLKIO and the CLKIN be in phase for proper functioning of the DAC, which can easily be ensured by tying the pins together on the PCB. If the user can access the SPI, setting Bit 2 of SPI Address 0x02, DCI_EN, to logic low causes the CLKIN to be used as the DCLKIO also.
Rev. B | Page 41 of 52
Setting Bit 1 or Bit 0 of SPI Address 0x02, DCOSGL or DCODBL, to logic high allows the user to get a DCLKIO output from the CLKIN input for use in the user’s PCB system.
It is strongly recommended that DCI_EN = DCOSGL = high, or DCI_EN = DCODBL = high not be used, even though the device may appear to function correctly. Similarly, DCOSGL and DCODBL should not be set to logic high simultaneously.

Retimer

The AD9114/AD9115/AD9116/AD9117 have an internal data retimer circuit that compares the CLKIN-INT and DCLKIO-INT clocks and, depending on their phase relationship, selects a retimer clock (RETIMER-CLK) to safely transfer data from the DCLKIO used at the chip’s input interface to the CLKIN used to clock the analog DAC cores (D-FF 4).
The retimer selects one of the three phases shown in Figure 95. The retimer is controlled by the CLKMODE SPI bits as is shown in Ta b le 15.
Figure 95. RETIMER-CLK Phases
Note that, in most cases, more than one retimer phase works and, in such cases, the retimer arbitrarily picks one phase that works. The retimer cannot pick the best or safest phase. If the user has a working knowledge of the exact phase relationship between DCLKIO and CLKIN (and thus DCLKIO-INT and CLKIN-INT because the delay is approximately the same for both clocks and equal to DELAY1), then the retimer can be forced to this phase with CLKMODEN = 1, as described in Tabl e 15 and the following paragraphs.
AD9114/AD9115/AD9116/AD9117 Data Sheet
Table 15. Timer Register List
Bit Name Description
CLKMODEQ[1:0] Q datapath retimer clock selected output. Valid after the searching bit goes low. Searching High indicates that the internal datapath retimer is searching for the clock relationship (DAC is not usable until it is low again). Reacquire Changing this bit from 0 to 1 causes the datapath retimer circuit to reacquire the clock relationship. CLKMODEN 0: Uses the CLKMODEI/CLKMODEQ values (as computed by the two internal retimers) for I and Q clocking. 1: Uses the CLKMODE value set in CLKMODEI[1:0] to override the bits for both the I and Q retimers (that is, force the retimer). CLKMODEI[1:0]
Table 16. CLKMODEI/CLKMODEQ Details
CLKMODEI[1:0]/CLKMODEQ[1:0] DCLKIO-to-CLKIN Phase Relationship RETIMER-CLK Selected
00 0° to 90° Phase 2 01 90° to 180° Phase 3 10 180° to 270° Phase 3 11 270° to 360° Phase 1
When RESET is pulsed high and then returns low (the part is in SPI mode), the retimer runs and automatically selects a suitable clock phase for the RETIMER-CLK within 128 clock cycles. The SPI searching bit, Bit 4 of SPI Address 0x14, returns to low, indicating that the retimer has locked and the part is ready for use. The reacquire bit, Bit 3 of SPI Address 0x14, can be used to reinitiate phase detection in the I and Q retimers at any time. CLKMODEQ[1:0] and CLKMODEI[1:0] bits of SPI Address 0x14 provide readback for the values picked by the internal phase detectors in the retimer (see Tab l e 16).
To force the two retimers (I and Q) to pick a particular phase for the retimer clock (they must both be forced to the same value), CLKMODEN, Bit 2 of the SPI Address 0x14, should be set high and the required phase value is written into CLKMODEI[1:0]. For example, if the DCLKIO and the CLKIN are in phase to first order, the user could safely force the retimers to pick Phase 2 for the RETIMER-CLK. This forcing function may be useful for synchronizing multiple devices.
In pin mode, it is expected that the user tie CLKIN and DCLKIO together. The device has a small amount of programmable func­tionality using the now unused SPI pins (SCLK, SDIO, and If the two chip clocks are tied together, the SCLK pin can be tied to ground, and the chip uses a clock for the retimer that is 180° out of phase with the two input clocks (that is, Phase 2, which is the safest and best option). The chip has an additional option in pin mode when the redefined SCLK pin is high. Use this mode if using pin mode, but CLKIN and DCLKIO are not tied together (that is, not in phase). Holding SCLK high causes the internal clock detector to use the phase detector output to determine which clock to use in the retimer (that is, select a suitable RETIMER-CLK phase). The action of taking SCLK high causes the internal phase detector to reexamine the two clocks and determine the relative phase. Whenever the user wants to reevaluate the relative phase of the two clocks, the SCLK pin can be taken low and then high again.
I datapath retimer clock selected output. Valid after searching goes low. If CLKMODEN = 1, a value written to this register overrides both I and Q automatic retimer values.

ESTIMATING THE OVERALL DAC PIPELINE DELAY

DAC pipeline latency is affected by the phase of the RETIMER­CLK that is selected. If latency is critical to the system and must be constant, the retimer should be forced to a particular phase and not be allowed to automatically select a phase each time.
Consider the case in which DCLKIO = CLKIN (that is, in phase), and the RETIMER-CLK is forced to Phase 2. Assume that IRISING is 1 (that is, Q data is latched on the rising edge and I data is latched on the falling edge). Then the latency to the output for the I channel is three clock cycles (D-FF 1, D-FF 3, and D-FF 4, but not D-FF 2, because it is latched on the half clock cycle or 180°). The latency to the output for the Q channel from the time the falling edge latches it at the pads in D-FF 0 is 2.5 clock cycles (½ clock cycle to D-FF 1, 1 clock cycle to D-FF 3, and 1 clock cycle to D-FF 4). This latency for the AD9114/AD9115/ AD9116/AD9117 is case specific and needs to be calculated based on the RETIMER-CLK phase that is automatically selected or manually forced.
CS
).
Rev. B | Page 42 of 52
CURRENT
SCALING
x32
AD9114/AD9115/ AD9116/AD9117
I DAC
OR
Q DAC
07466-218
I
xOUTFS
xR
SET
0.1µF
REFIO
I
xREF
AVSS
FSADJx
V
BG
1.0V
+
–
Internal
Connect 0.1 µF
Register 0x01, Bit 0 = 0
Data Sheet AD9114/AD9115/AD9116/AD9117

REFERENCE OPERATION

The AD9114/AD9115/AD9116/AD9117 contains an internal
1.0 V band gap reference. The internal reference can be disabled by setting Bit 0 (EXTREF) of the power-down register (Address 0x01) through the SPI interface. To use the internal reference, decouple the REFIO pin to AVSS with a 0.1 μF capacitor, enable the internal reference, and clear Bit 0 of the power-down register (Address 0x01) through the SPI interface. Note that this is the default configuration. The internal reference voltage is present at REFIO. If the voltage at REFIO is to be used anywhere else in the circuit, an external buffer amplifier with an input bias current of less than 100 nA must be used to avoid loading the reference. An example of the use of the internal reference is shown in Figure 96.
Figure 96. Internal Reference Configuration
REFIO serves as either an input or an output, depending on whether the internal or an external reference is used. Tabl e 17 summarizes the reference operation.
Table 17. Reference Operation
Reference Mode REFIO Pin Register Setting
capacitor
External
Apply external capacitor
An external reference can be used in applications requiring tighter gain tolerances or lower temperature drift. In addition, a variable external voltage reference can be used to implement a method for gain control of the DAC output.

Recommendations When Using an External Reference

Apply the external reference to the REFIO pin. The internal reference can be directly overdriven by the external reference, or the internal reference can be powered down to save power consumption.
The external 0.1 µF compensation capacitor on REFIO is not required unless specified by the external voltage reference manufacturer. The input impedance of REFIO is 10 kΩ when the internal reference is powered up and 1 MΩ when it is powered down.
(default) Register 0x01, Bit 0 = 1
(for power saving)
Rev. B | Page 43 of 52

REFERENCE CONTROL AMPLIFIER

The AD9114/AD9115/AD9116/AD9117 contains a control amplifier that regulates the full-scale output current, I The control amplifier is configured as a V-I converter, as shown in Figure 96. The output current, I the V
and an external resistor, xR
REFIO
the DAC Transfer Function section). I
, is determined by the ratio of
xREF
, as stated in Equation 4 (see
SET
is mirrored to the
xREF
segmented current sources with the proper scale factor to set I
, as stated in Equation 3 (see the DAC Transfer Function
xOUTFS
section).
The control amplifier allows a 2.5:1 adjustment span of I from 8 mA to 20 mA by setting I (xR
between 1.6 kΩ and 4 kΩ). The wide adjustment span of
SET
provides several benefits. The first relates directly to the
I
xOUTFS
between 250 µA and 625 µA
xREF
power dissipation of the AD9114/AD9115/AD9116/AD9117, which is proportional to I
(see the DAC Transfer Function
xOUTFS
section). The second benefit relates to the ability to adjust the output over a 8 dB range with 0.25 dB steps, which is useful for controlling the transmitted power. The small signal bandwidth of the reference control amplifier is approximately 500 kHz. This allows the device to be used for low frequency, small signal multiplying applications.

DAC TRANSFER FUNCTION

The AD9114/AD9115/AD9116/AD9117 provides two differential current outputs, IOUTP/IOUTN and QOUTP/ QOUTN. IOUTP and QOUTP provide a near full-scale current output, I when all bits are high (that is, DAC CODE = 2 10, 12, or 14 for the AD9114, AD9115, AD9116, and AD9117, respectively), while IOUTN and QOUTN, the complementary outputs, provide no current. The current outputs appearing at the positive DAC outputs, IOUTP and QOUTP, and at the negative DAC outputs, IOUTN and QOUTN, are a function of both the input code and I
IOUTP = (IDAC CODE/2
QOUTP = (QDAC CODE/2
IOUTN = ((2
QOUTN = ((2
and can be expressed as follows:
xOUTFS
N
) × I
IOUTFS
N
) × I
N
− 1) − IDAC CODE)/2N × I
N
− 1) − QDAC CODE)/2N × I
where: IDAC CODE and QDAC CODE = 0 to 2 representation).
I
and I
IOUTFS
and I
QREF
voltage, V
I
and I
IOUTFS
I
IOUTFS
I
QOUTFS
, respectively, which are nominally set by a reference
are functions of the reference currents, I
QOUTFS
, and external resistors, IR
REFIO
can be expressed as follows:
QOUTFS
= 32 × I
= 32 × I
(3)
IREF
QREF
where:
I I
IREF
QREF
= V
= V
REFIO
REFIO
/IR
(4)
SET
/QR
SET
N
− 1, where N = 8,
(1)
QOUTFS
IOUTFS
N
− 1 (that is, decimal
and QR
SET
SET,
xOUTFS
xOUTFS
xOUTFS
QOUTFS
respectively.
IREF
.
,
(2)
AD9114/AD9115/AD9116/AD9117 Data Sheet
or
I
IOUTFS
I
QOUTFS
= 32 × V
= 32 × V
REFIO
REFIO
/IR
(5)
SET
/QR
SET
A differential pair (IOUTP/IOUTN or QOUTP/QOUTN) typically drives a resistive load directly or via a transformer. If dc coupling is required, the differential pair (IOUTP/IOUTN or QOUTP/QOUTN) should be connected to matching resistive loads, xR
, that are tied to analog common, AVSS. The single-
LOAD
ended voltage output appearing at the positive and negative nodes is
V
= IOUTP × IR
IOUTP
= QOUTP × QR
V
QOUTP
= IOUTN × IR
V
IOUTN
= QOUTN × QR
V
QOUTN
LOAD
LOAD
LOAD
LOAD
(6)
(7)
To achieve the maximum output compliance of 1 V at the nominal 20 mA output current, IR
Substituting the values of IOUTP, IOUTN, I
LOAD
= QR
must be set to 50 Ω.
LOAD
, and V
xREF
IDIFF
can
be expressed as
V
= {(2 × IDAC CODE − (2N − 1))/2N} ×
IDIFF
(32 × V
REFIO
/IR
SET
) × IR
(8)
LOAD
Equation 8 highlights some of the advantages of operating the AD9114/AD9115/AD9116/AD9117 differentially. First, the differential operation helps cancel common-mode error sources associated with IOUTP and IOUTN, such as noise, distortion, and dc offsets. Second, the differential code-dependent current and subsequent voltage, V voltage output (that is, V
, is twice the value of the single-ended
IDIFF
IOUTP
or V
), thus providing twice the
IOUTB
signal power to the load. Note that the gain drift temperature performance for a single-ended output (V
IOUTP
and V
IOUTN
) or differential output of the AD9114/AD9115/AD9116/ AD9117 can be enhanced by selecting temperature tracking resistors for xR
LOAD
and xR
because of their ratiometric relationship, as
SET
shown in Equation 8.

ANALOG OUTPUT

The complementary current outputs in each DAC, IOUTP/ IOUTN and QOUTP/QOUTN, can be configured for single­ended or differential operation. IOUTP/IOUTN and QOUTP/ QOUTN can be converted into complementary single-ended voltage outputs, V a load resistor, xR section by Equation 6 through Equation 8. The differential voltages, V and V
QOUTP
IDIFF
and V voltage via a transformer or a differential amplifier configuration. The ac performance of the AD9114/AD9115/AD9116/AD9117 is optimum and is specified using a differential transformer-coupled output in which the voltage swing at IOUTP and IOUTN is limited to ±0.5 V. The distortion and noise performance of the AD9114/AD9115/AD9116/AD9117 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTP/IOUTN and QOUTP/QOUTN can be
and V
IOUTP
, as described in the DAC Transfer Function
LOAD
and V
QDIFF
, can also be converted to a single-ended
QOUTN
as well as V
IOUTN
, existing between V
QOUTP
IOUTP
and V
QOUTN
and V
IOUTN
via
,
significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise.
The e
nhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude increases. This is due to the first­order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (assuming no source termination). Because the output currents of IOUTP/IOUTN and QOUTP/QOUTN are complementary, they become additive when processed differentially.

SELF-CALIBRATION

The AD9114/AD9115/AD9116/AD9117 have a self-calibration feature that improves the DNL of the device. Performing a self­calibration on the device improves device performance in low frequency applications. The device performance in applications where the analog output frequencies are above 5 MHz are generally influenced more by dynamic device behavior than by DNL and, in these cases, self-calibration is unlikely to produce measurable benefits. The calibration clock frequency is equal to the DAC clock divided by the division factor chosen by the DIVSEL value. There is a fixed pre-divider of 16 and it is multiplied by the DIVSEL, which has a range of divide by 2 -256. Each calibration clock cycle is between 32 and 2048 DAC input clock cycles, depending on the value of DIVSEL[2:0] (Register 0x0E, Bits[2:0]). The frequency of the calibration clock should be between 0.5 MHz and 4 MHz for reliable calibrations. Best results are obtained by setting DIVSEL[2:0] to produce a calibration clock frequency between these values. Separate self-calibration hardware is included for each DAC. The DACs can be self-calibrated individually or simultaneously.
To perform a device self-calibration, use the following procedure:
1. Write 0x00 to Register 0x12. This ensures that the UNCALI
and UNCALQ bits (Bit 1 and Bit 0) are reset.
2. Set up a calibration clock between 0.5 MHz and 4 MHz
using DIVSEL[2:0], and then enable the calibration clock by setting the CALCLK bit (Register 0x0E, Bit 3).
3. Select the DAC(s) to self-calibrate by setting either Bit 4
(CALSELI) for the I DAC and/or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E. Note that each DAC contains independent calibration hardware so that they can be calibrated simultaneously.
4. Start self-calibration by setting Bit 4 (CALEN) in Register 0x12.
Wait approximately 300 calibration clock cycles.
5. Check if the self-calibration has completed by reading
Bit 6 (CA L S TATI) and Bit 7 (C A L STATQ) in Register 0x0F. Logic 1 indicates that the calibration has completed.
6. When the self-calibration has completed, write 0x00 to
Register 0x12.
Rev. B | Page 44 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.
80
0 8 16 24 32 40 48 56
CO
DE
V
REF
(V)
07466-058
20 18
22
16
10
12
14
8 6 4 2
0 10 20 30 40 50 60
xR
SET
CODE
I
F
(mA)
V
OUT_Q
OR V
OUT_I
07466-059
7. Disable the calibration clock by clearing Bit 3 (CALCLK)
in Register 0x0E.
The AD9114/AD9115/AD9116/AD9117 allow reading and writing of the calibration coefficients. There are 32 coefficients in total. The read/write feature of the coefficients can be useful for improving the results of the self-calibration routine by averaging the results of several self-calibration cycles and loading the averaged results back into the device.
To read the calibration coefficients, use the following steps:
1. Select which DAC core to read by setting either Bit 4
(CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E. Write the address of the first coefficient (0x01) to Register 0x10.
2. Set Bit 2 (SMEMRD) in Register 0x12 by writing 0x04 to
Register 0x12.
3. Read the 6-bit value of the first coefficient by reading the
contents of Register 0x11.
4. Clear the SMEMRD bit by writing 0x00 to Register 0x12.
5. Repeat Step 2 through Step 4 for each of the remaining 31
coefficients by incrementing the address by 1 for each read.
6. Deselect the DAC core by clearing either Bit 4 (CALSELI)
for the I DAC and/or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E.
Figure 97. Typical V
Voltage vs. Code
REF

Option 2

While using the internal FSADJx resistors, each main DAC can achieve independently controlled coarse gain using the lower six bits of Register 0x04 (IRSET[5:0]) and Register 0x07 (QRSET[5:0]). Unlike Coarse Gain Option 1, this impacts only the main DAC full-scale output current. The register uses twos complement format and allows the output current to be changed in approximately 0.25 dB steps.
To write the calibration coefficients to the device, use the following steps:
1. Select which DAC core to write to by setting either Bit 4
(CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E.
2. Set Bit 3 (SMEMWR) in Register 0x12 by writing 0x08 to
Register 0x12.
3. Write the address of the first coefficient (0x01) to
Register 0x10.
4. Write the value of the first coefficient to Register 0x11.
5. Repeat Step 2 through Step 4 for each of the remaining 31
coefficients by incrementing the address by one for each write.
6. Clear the SMEMWR bit by writing 0x00 to Register 0x12.
7. Deselect the DAC core by clearing either Bit 4 (CALSELI)
for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E.

COARSE GAIN ADJUSTMENT

Option 1

A coarse full-scale output current adjustment can be achieved using the lower six bits in Register 0x0D. This adds or subtracts up to 20% from the band gap voltage on Pin 34 (REFIO), and the voltage on the FSADJx resistors tracks this change. As a result, the DAC full-scale current varies by the same amount. A secondary effect to changing the REFIO voltage is that the full-scale voltage in the AUXDAC also changes by the same magnitude. The register uses twos complement format, in which 011111 maximizes the voltage on the REFIO node and 100000 minimizes the voltage.
Figure 98. Effect of xR
SET
Code

Option 3

Even when the device is in pin mode, full-scale values can be adjusted by sourcing or sinking current from the FSADJx pins. Any noise injected here appears as amplitude modulation of the output. Thus, a portion of the required series resistance (at least 20 kΩ) must be installed right at the pin. A range of ±10% is quite practical using this method.

Option 4

As in Option 3, when the device is in pin mode, both full-scale values can be adjusted by sourcing or sinking current from the REFIO pin. Noise injected here appears as amplitude modulation of the output; therefore, a portion of the required series resistance (at least 10 kΩ) must be installed at the pin. A range of ±25% is quite practical when using this method.
Rev. B | Page 45 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
11.10
11.00
10.90
10.80
10.70
10.60
10.50 0 8 16 24 32 40 48 56 64
GAIN DAC CODE
I
OUTFS
(mA)
3.3V DAC1
3.3V DAC2
1.8V DAC1
1.8V DAC2
07466-060
I DAC
OR
Q DAC
xR
CM
CML
RLIN
IOUTN
IOUTP
RLIP
62.5Ω
62.5Ω
07466-061
260
220
240
200
180
160
140
120
100
80
60
0 8 16 24
32 40 48 56
CO
DE
RESISTANCE (Ω)
07466-062

Fine Gain

Each main DAC has independent fine gain control using the lower six bits in Register 0x03 (I DACGAIN[5:0]) and Register 0x06 (Q DACGAIN[5:0]). Unlike Coarse Gain Option 1, this impacts only the main DAC full-scale output current. These registers use straight binary format. One application in which straight binary format is critical is for side-band suppression while using a quadrature modulator. This is described in more detail in the Applications Information section.

Using the Internal Common-Mode Resistor

These devices contain an adjustable internal common-mode resistor that can be used to increase the dc bias of the DAC outputs. By default, the common-mode resistor is not connected. When enabled, it can be adjusted from ~60 Ω to ~260 Ω. Each main DAC has an independent adjustment using the lower six bits in Register 0x05 (IRCML[5:0]) and Register 0x08 (QRCML[5:0]).
Figure 99. Typical DAC Gain Characteristics

USING THE INTERNAL TERMINATION RESISTORS

The AD9117/AD9116/AD9115/AD9114 have four 62.5 Ω termination internal resistors (two for each DAC output). To use these resistors to convert the DAC output current to a voltage, connect each DAC output pin to the adjacent load pin. For example, on the I DAC, IOUTP must be shorted to RLIP and IOUTN must be shorted to RLIN. In addition, the CMLI or CMLQ pin must be connected to ground directly or through a resistor. If the output current is at the nominal 20 mA and the CMLI or CMLQ pin is tied directly to ground, this produces a dc common-mode bias voltage on the DAC output equal to 0.5 V. If the DAC dc bias must be higher than 0.5 V, an external resistor can be connected between the CMLI or CMLQ pin and ground. This part also has an internal common-mode resistor that can be enabled. This is explained in the Using the Internal Common-Mode Resistor section.
Figure 101. Typical CML Resistor Value vs. Register Code

Using the CMLx Pins for Optimal Performance

The CMLx pins also serve to change the DAC bias voltages in the parts allowing them to run at higher dc output bias voltages. When running the bias voltage below 0.9 V and an AVDD of
3.3 V, the parts perform optimally when the CMLx pins are tied to ground. When the dc bias increases above 0.9 V, set the CMLx pins at 0.5 V for optimal performance. The maximum dc bias on the DAC output should be kept at or below 1.2 V when the supply is 3.3 V. When the supply is 1.8 V, keep the dc bias close to 0 V and connect the CMLx pins directly to ground.
Figure 100. Simplified Internal Load Options
Rev. B | Page 46 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
AD9114/AD9115/ AD9116/AD9117
IOUTN
IOUTP
29
28
OPTIONAL R
DIFF
R
LOAD
07466-063
2
1
FS
FB
B
FB
REF
CM
IR
R
R
VV
×
−
 
 
+×=
+5V
AD9114/AD9115/ AD9116/AD9117
IOUTP
IOUTN
29
R
FB
V
OUT
REFIO
34
28
R
S
AVSS
25
C
F
C
R
S
R
B
+
–
ADA4899-1
–5V
07466-064

APPLICATIONS INFORMATION

OUTPUT CONFIGURATIONS

The following sections illustrate some typical output configu­rations for the AD9114/AD9115/AD9116/AD9117. Unless otherwise noted, it is assumed that I
is set to a nominal
xOUTFS
20 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration can consist of either an RF transformer or a differential op amp configuration. The trans­former configuration provides the optimum high frequency performance and is recommended for any application that allows ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, signal gain, and/or a low output impedance.
A single-ended output is suitable for applications in which low cost and low power consumption are primary concerns.

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differential-to­single-ended signal conversion, as shown in Figure 102. The distortion performance of a transformer typically exceeds that available from standard op amps, particularly at higher frequencies. Transformer coupling provides excellent rejection of common-mode distortion (that is, even-order harmonics) over a wide frequency range. It also provides electrical isolation and can deliver voltage gain without adding noise. Transformers with different impedance ratios can also be used for impedance matching purposes. The main disadvantages of transformer coupling are low frequency roll-off, lack of power gain, and high output impedance.
A differential resistor, R which the output of the transformer is connected to the load, R
, via a passive reconstruction filter or cable. R
LOAD
reflected by the transformer, is chosen to provide a source termination that results in a low voltage standing wave ratio (VSWR). Note that approximately half the signal power is dissipated across R
DIFF

SINGLE-ENDED BUFFERED OUTPUT USING AN OP AMP

An op amp, such as the ADA4899-1, can be used to perform a single- ended current-to-voltage conversion, as shown in Figure 103. The AD9114/AD9115/AD9116/AD9117 are configured with a pair of series resistors, R R
should be set to 0 Ω. The feedback resistor, RFB, determines
S
the peak-to-peak signal swing by the formula
V
OUT
The common-mode voltage of the output is determined by the formula
The maximum and minimum voltages out of the amplifier are, respectively,
MAX
V
MIN
, off each output. For best distortion performance,
S
= RFB × IFS
VV 1
REF
= V
− IFS × RFB
MAX
, can be inserted in applications in
DIFF
.
 
R
FB
+×=
R
B
DIFF
, as
The center tap on the primary side of the transformer must be connected to a voltage that keeps the voltages on IOUTP and IOUTN within the output common-mode voltage range of the device. Note that the dc component of the DAC output current is equal to I The center tap of the transformer should provide a path for this dc current. In most applications, AGND provides the most convenient voltage for the transformer center tap. The comple­mentary voltages appearing at IOUTP and IOUTN (that is, V
IOUTP
should be maintained with the specified output compliance range of the AD9114/AD9115/AD9116/AD9117.
Figure 102. Differential Output Using a Transformer
and flows out of both IOUTP and IOUTN.
IOUTFS
and V
) swing symmetrically around AGND and
IOUTN
Figure 103. Single-Supply, Single-Ended Buffer
Rev. B | Page 47 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
V
AD9114/AD9115/ AD9116/AD9117
IOUTP
IOUTN
R
FB
V
OUT
REFIO
34
28
R
S
AVSS
25
C
F
C
R
FB
R
B
C
F
R
S
R
B
29
+
–
ADA4841-2
+
–
ADA4841-2
07466-065
kΩ16
5.1
V5.0
 
 
−−=
S
DAC
OUT
R
IV
+
–
OP AMP
AUXDAC
[9:0]
AVDD
RNG0 RNG1
REFIO
2
16kΩ 16kΩ
16kΩ
4kΩ 8kΩ
OFS2 OFS1 OFS0
(OFS > 4 = 4)
AUX PIN
RNG: 00 = 125µA
f
S
01 = 62µA
f
S
10 = 31µA
f
S
11 = 16µA
f
S
07466-066
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2 0
0 10 20 30 40 50 60 70 80 90 100 120 130
DAC CURRE
NT (µA)
OUTPUT (V)
110
R
OFFSET
= 3.3kΩ
R
OFFSET
= 4kΩ
R
OFFSET
= 5.3kΩ
R
OFFSET
= 8kΩ
R
OFFSET
= 16kΩ
OP AMP OUTPUT VOLTAGE vs. CHANGES IN R
OFFSET
AND DAC CURRENT IN µA
07466-067

DIFFERENTIAL BUFFERED OUTPUT USING AN OP AMP

A dual op amp (see the circuit shown in Figure 104) can be used in a differential version of the single-ended buffer shown in Figure 103. The same RC network is used to form a one-pole differential, low-pass filter to isolate the op amp inputs from the high frequency images produced by the DAC outputs. The feed­back resistors, R swing by the formula
V
OUT
The maximum and minimum single-ended voltages out of the amplifier are, respectively,
V
MIN
The common-mode voltage of the differential output is determined by the formula
= V
V
CM
, determine the differential peak-to-peak signal
FB
= 2 × RFB × IFS
R
FB
+×=
R
B
= V
V
REFMAX
− RFB × IFS
MAX
− RFB × IFS
MAX
 
1
 
To keep the pin count reasonable, these auxiliary DACs each share a pin with the corresponding FSADJx resistor. They are, therefore, usable only when enabled and when that DAC is operated on its internal full-scale resistors. A simple I-to-V converter is implemented on-chip with selectable shunt resistors (3.2 kΩ to 16 kΩ) such that if REFIO is set to exactly 1 V, REFIO/2 equals 0.5 V and the following equation describes the no load output voltage:
Figure 105 illustrates the function of all the SPI bits controlling these DACs with the exception of the QAUXEN (Register 0x0A) and IAUXEN (Register 0x0C) bits and gating to prohibit R
< 3.2 kΩ.
S
Figure 104. Single-Supply Differential Buffer

AUXILIARY DACs

The DACs of the AD9114/AD9115/AD9116/AD9117 feature two versatile and independent 10-bit auxiliary DACs suitable for dc offset correction and similar tasks.
Because the AUXDACs are driven through the SPI port, they should never be used in timing-critical applications, such as inside analog feedback loops.
Figure 105. AUXDAC Simplified Circuit Diagram
The SPI speed limits the update rate of the auxiliary DACs. The data is inverted such that I
is full scale at 0x000 and zero
AUXDA C
at 0x1FF, as shown in Figure 106.
Figure 106. AUXDAC Op Amp Output vs. Current, AVDD = 3.3 V No Load,
AUXDAC 0x1FF to 0x000
Rev. B | Page 48 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
AD9114/AD9115/
AD9116/AD9117
AUXDAC1
AD9114/AD9115/
AD9116/AD9117
I DAC
5kΩ
TO
100kΩ
50Ω50Ω
OPTIONAL
PASSIVE
FILTERING
MODULATOR V+
QUADRATURE MODULATOR I OR Q INPUTS
0.1µF
0.1µF
07466-268
AD9114/AD9115/
AD9116/AD9117
AUXDAC
AD9114/AD9115/
AD9116/AD9117
I OR Q DAC
5kΩ
50Ω 50Ω
100Ω
OPTIONAL
LOW- PASS
FILTERING
ADL5370 FAMILY I OR Q INPUTS
07466-269
Two registers are assigned to each DAC with 10 bits for the actual DAC current to be generated, a 3-bit offset (and gain) adjustment, a 2-bit current range adjustment, and an enable/ disable bit. Setting the QAUXOF S (Register 0x0A) and IAUXOFS (Register 0x0C) bits to all 1s disables the respective op amp and routes the DAC current directly to the respective FSADJI/AUXI or FSADJQ/AUXQ pins. This is especially useful when the loads to be driven are beyond the limited capability of the on-chip amplifier.
When not enabled (QAUXEN or IAUXEN = 0), the respective DAC output is in open circuit.

DAC-TO-MODULATOR INTERFACING

The auxiliary DACs can be used for local oscillator (LO) cancellation when the DAC output is followed by a quadrature modulator. This LO feedthrough is caused by the input referred dc offset voltage of the quadrature modulator (and the DAC output offset voltage mismatch) and can degrade system performance. Typical DAC-to-quadrature modulator interfaces are shown in Figure 107 and Figure 108, with the series resistor value chosen to give an appropriate adjustment range. Figure 107 also shows external load resistors in use. Often, the input common­mode voltage for the modulator is much higher than the output compliance range of the DAC, so that ac coupling or a dc level shift is necessary. If the required common-mode input voltage on the quadrature modulator matches that of the DAC, the dc blocking capacitors in Figure 107 can be removed and the on-chip resistors can be connected.
Figure 108. Typical Use of Auxiliary DACs When DC Coupling to Quadrature
Modulator ADL537x Family

CORRECTING FOR NONIDEAL PERFORMANCE OF QUADRATURE MODULATORS ON THE IF-TO-RF CONVERSION

Analog quadrature modulators make it very easy to realize single sideband radios. These DACs are most often used to make radio transmitters, such as in cell phone towers. However, there are several nonideal aspects of quadrature modulator performance. Among these analog degradations are gain mismatch and LO feedthrough.

Gain Mismatch

The gain in the real and imaginary signal paths of the quadrature modulator may not be matched perfectly. This leads to less than optimal image rejection because the cancellation of the negative frequency image is less than perfect.

LO Feedthrough

The quadrature modulator has a finite dc referred offset, as well as coupling from its LO port to the signal inputs. These can lead to a significant spectral spur at the frequency of the quadrature modulator LO.
The AD9114/AD9115/AD9116/AD9117 have the capability to correct for both of these analog degradations. However, understand that these degradations drift over temperature; therefore, if close to optimal single sideband performance is desired, a scheme for sensing these degradations over temperature and correcting them may be necessary.
Figure 108 shows a greatly simplified circuit that takes full advantage of the internal components supplied in the DAC. A low-pass or band-pass passive filter is recommended when spurious signals from the DAC (distortion and DAC images) at the quadrature modulator inputs can affect the system performance. In the example shown in Figure 108, the filter must be able to pass dc to properly bias the modulator. Placing the filter at the location shown in Figure 107 and Figure 108 allows easy design of the filter, because the source and load impedances can easily be designed close to 50 Ω for a 20 mA full-scale output. When the resistance at the modulator inputs is known, an optimum value for the series resistor can be calculated from the modulator input offset voltage ratings.
Figure 107. Typical Use of Auxiliary DACs

I/Q CHANNEL GAIN MATCHING

Rev. B | Page 49 of 52
Fine gain matching is achieved by adjusting the values in the DAC fine gain adjustment registers. For the I DAC, these values are in the I DAC Gain register (Register 0x03, I DACGAIN[5:0]). For the Q DAC, these values are in the Q DAC gain register (Register 0x06, Q DACGAIN[5:0]). These are 6-bit values that cover ±2% of full scale. To perform gain compensation by starting from the default values of zero, raise the value of one of these registers a few steps until it can be determined if the amplitude of the unwanted image is increased or decreased. If the unwanted image increases in amplitude, remove the step and try the same adjustment on the other DAC control register. Iterate register changes until the rejection cannot be improved further. If the fine gain adjustment range is not sufficient to find a null (that is, the register goes full scale with no null apparent), adjust the course gain settings of the two DACs accordingly and try again. Variations on this simple method are possible.
AD9114/AD9115/AD9116/AD9117 Data Sheet
5
–5
–15
–25
–35 –45
–55
–65 –75
–85
–95
0
–10
–20
–30 –40
–50
–60 –70
–80
–90
447.5 449.0 450.0 451.0 452.5
FREQUENCY (MHz)
dB
07466-070
5
–5
–15
–25
–35 –45
–55
–65 –75
–85
–95
0
–10
–20
–30 –40
–50
–60 –70
–80
–90
447.5 449.0 450.0 451.0 452.5
FREQUENCY (MHz)
dB
07466-071
Note that LO feedthrough compensation is independent of phase compensation. However, gain compensation can affect the LO compensation because the gain compensation may change the common-mode level of the signal. The dc offset of some modulators is common-mode level dependent. Therefore, it is recommended that the gain adjustment be performed prior to LO compensation.

LO FEEDTHROUGH COMPENSATION

To achieve LO feedthrough compensation in a circuit, each output of the two AUXDACs must be connected through a 10 kΩ resistor to one side of the differential DAC output. See the Auxiliary DACs section for details of how to use AUXDACs. The purpose of these connections is to drive a very small amount of current into the nodes at the quadrature modulator inputs, thereby adding a slight dc bias to one or the other of the quadrature modulator signal inputs.
To achieve LO feedthrough compensation, the user should start with the default conditions of the AUXDAC registers and then increment the magnitude of one or the other AUXDAC output voltages. While this is being done, the amplitude of the LO feedthrough at the quadrature modulator output should be sensed. If the LO feedthrough amplitude increases, try either decreasing the output voltage of the AUXDAC being adjusted or try adjusting the output voltage of the other AUXDAC. It may take practice before an effective algorithm is achieved. The AD9114/AD9115/AD9116/ AD9117 evaluation board can be used to adjust the LO feedthrough down to the noise floor, although this is not stable over temperature.
Note that gain matching improves the negative frequency image rejection, but it is also related to the phase mismatch in the quadrature modulator. It can be improved by adjusting the relative phase between the two quadrature signals at the digital side or properly designing the low-pass filter between the DACs and quadrature modulators. Phase mismatch is frequency dependent; therefore, routines must be developed to adjust it if wideband signals are desired.
Figure 109. AD9114/AD9115/AD9116/AD9117 and ADL5370 with a Single-
Tone Signal at 450 MHz, No Gain or LO Compensation

RESULTS OF GAIN AND OFFSET CORRECTION

The results of gain and offset correction can be seen in Figure 109 and Figure 110. Figure 109 shows the output spectrum of the quadrature demodulator before gain and offset correction. Figure 110 shows the output spectrum after correction. The LO feedthrough spur at 450 MHz has been suppressed to the noise level. This result can be achieved by applying the correction, but the correction must be repeated after a large change in temperature.
Figure 110. AD9114/AD9115/AD9116/AD9117 and ADL5370 with a Single-
Tone Signal at 450 MHz, Gain and LO Compensation Optimized
Rev. B | Page 50 of 52
Data Sheet AD9114/AD9115/AD9116/AD9117
1
40
10
11
31
30
21
20
4.25
4.10 SQ
3.95
TOP
VIEW
6.00
BSC SQ
PIN 1
INDICATOR
5.75
BSC SQ
12° MAX
0.30
0.23
0.18
0.20 REF
SEATING PLANE
1.00
0.85
0.80
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.80 MAX
0.65 TYP
4.50 REF
0.50
0.40
0.30
0.50
BSC
PIN 1 INDICATOR
0.60 MAX
0.60 MAX
0.25 MIN
EXPOSED
PAD
(BOT TOM V IEW)
COMPLIANT TO JEDEC S TANDARDS MO-220-V JJD- 2
072108-A
FOR PROP E R CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CO NFIGURATI ON AND FUNCTIO N DE S CRIPTIONS SECTION OF THIS DATA SHEET.
0.50
BSC
BOTTOM VIEWTOP VIEW
PIN 1
INDICATOR
EXPOSED
PAD
PIN 1 INDICATOR
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
0.30
0.25
0.18
6.10
6.00 SQ
5.90
0.80
0.75
0.70
FOR PROP E R CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CO NFIGURATI ON AND FUNCTIO N DE S CRIPTIONS SECTION OF THIS DATA SHEET.
0.45
0.40
0.35
0.25 MIN
4.25
4.10 SQ
3.95
COMPLI ANT TO JEDEC STANDARDS MO-220-WJJD.
40
1
11
20
21
30
31
10
05-06-2011-A

OUTLINE DIMENSIONS

Figure 111. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
Figure 112. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm x 6 mm Body, Very Very Thin Quad
(CP-40-9)
Dimensions shown in millimeters
Rev. B | Page 51 of 52
AD9114/AD9115/AD9116/AD9117 Data Sheet
Model1
Temperature Range
Package Description
Package Option
AD9114BCPZRL7
−40°C to +85°C
40-Lead LFCSP_VQ
CP-40-1
AD9117BCPZNRL7
−40°C to +85°C
40-Lead LFCSP_WQ
CP-40-9
AD9116-DPG2-EBZ
Evaluation Board
©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and

ORDERING GUIDE

AD9114BCPZ −40°C to +85°C 40-Lead LFCSP_VQ CP-40-1
AD9115BCPZ −40°C to +85°C 40-Lead LFCSP_VQ CP-40-1 AD9115BCPZRL7 −40°C to +85°C 40-Lead LFCSP_VQ CP-40-1 AD9116BCPZ −40°C to +85°C 40-Lead LFCSP_VQ CP-40-1 AD9116BCPZRL7 −40°C to +85°C 40-Lead LFCSP_VQ CP-40-1 AD9117BCPZ −40°C to +85°C 40-Lead LFCSP_VQ CP-40-1 AD9117BCPZRL7 −40°C to +85°C 40-Lead LFCSP_VQ CP-40-1 AD9117BCPZN −40°C to +85°C 40-Lead LFCSP_WQ CP-40-9
AD9114-DPG2-EBZ Evaluation Board AD9115-DPG2-EBZ Evaluation Board
AD9117-DPG2-EBZ Evaluation Board
1
Z = RoHS Compliant Part.
registered trademarks are the property of their respective owners. D07466-0-5/12(B)
Rev. B | Page 52 of 52
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