ANALOG DEVICES AD9114 Service Manual

TxDAC Digital-to-Analog Converters

AD9114/AD9115/AD9116/AD9117

Rev. B

rights of third parties that may result from its use. Specifications subject to change without notice. No

Trademarks and registered trademarks are the prop erty of their respective owner s.

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Data Sheet

FEATURES

Power dissipation @ 3.3 V, 20 mA output

191 mW @ 10 MSPS

232 mW @ 125 MSPS
Sleep mode: <3 mW @ 3.3 V
Supply voltage: 1.8 V to 3.3 V
SFDR to Nyquist

86 dBc @ 1 MHz output

85 dBc @ 10 MHz output
AD9117 NSD @ 1 MHz output, 125 MSPS, 20 mA: −162 dBc/Hz
Differential current outputs: 4 mA to 20 mA
2 on-chip auxiliary DACs
CMOS inputs with single-port operation
Output common mode: adjustable 0 V to 1.2 V
Small footprint 40-lead LFCSP RoHS-compliant package

APPLICATIONS

Wireless infrastructures

Picocell, femtocell base stations
Medical instrumentation

Ultrasound transducer excitation
Portable instrumentation

Signal generators, arbitrary waveform generators

Dual Low Power, 8-/10-/12-/14-Bit

GENERAL DESCRIPTION

The AD9114/AD9115/AD9116/AD9117 are pin-compatible
dual, 8-/10-/12-/14-bit, low power digital-to-analog converters
(DACs) that provide a sample rate of 125 MSPS. These TxDAC®
converters are optimized for the transmit signal path of commu­nication systems. All the devices share the same interface, package,
and pinout, providing an upward or downward component
selection path based on performance, resolution, and cost.

The AD9114/AD9115/AD9116/AD9117 offer exceptional ac and
dc performance and support update rates up to 125 MSPS.

The flexible power supply operating range of 1.8 V to 3.3 V and
low power dissipation of the AD9114/AD9115/AD9116/AD9117
make them well suited for portable and low power applications.

PRODUCT HIGHLIGHTS

1. Low Power. DACs operate on a single 1.8 V to 3.3 V supply;

total power consumption reduces to 225 mW at 100 MSPS.
Sleep and power-down modes are provided for low power
idle periods.

2. CMOS Clock Input. High speed, single-ended CMOS clock

input supports a 125 MSPS conversion rate.

3. Easy Interfacing to Other Components. Adjustable output

common mode from 0 V to 1.2 V allows for easy interfacing
to other components that accept common-mode levels
greater than 0 V.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com

AD9114/AD9115/AD9116/AD9117 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

Specifications ..................................................................................... 5

DC Specifications ......................................................................... 5

Digital Specifications ................................................................... 7

AC Specifications .......................................................................... 8

Absolute Maximum Ratings ............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution .................................................................................. 9

Pin Configurations and Function Descriptions ......................... 10

Typical Performance Characteristics ........................................... 18

Terminology .................................................................................... 31

Theory of Operation ...................................................................... 32

Serial Peripheral Interface (SPI) ................................................... 33

General Operation of the Serial Interface ............................... 33

Instruction Byte .......................................................................... 33

Serial Interface Port Pin Descriptions ..................................... 33

MSB/LSB Transfers..................................................................... 34

Serial Port Operation ................................................................. 34

Pin Mode ..................................................................................... 34

SPI Register Map ............................................................................. 35

SPI Register Descriptions .............................................................. 36

Digital Interface Operation ........................................................... 40

Digital Data Latching and Retimer Section ............................ 41

Estimating the Overall DAC Pipeline Delay........................... 42

Reference Operation .................................................................. 43

Reference Control Amplifier .................................................... 43

DAC Transfer Function ............................................................. 43

Analog Output ............................................................................ 44

Self-Calibration ........................................................................... 44

Coarse Gain Adjustment ........................................................... 45

Using the Internal Termination Resistors ............................... 46

Applications Information .............................................................. 47

Output Configurations .............................................................. 47

Differential Coupling Using a Transformer ............................... 47

Single-Ended Buffered Output Using an Op Amp ................ 47

Differential Buffered Output Using an Op Amp .................. 48

Auxiliary DACs ........................................................................... 48

DAC-to-Modulator Interfacing ................................................ 49

Correcting for Nonideal Performance of Quadrature

Modulators on the IF-to-RF Conversion ................................ 49

I/Q Channel Gain Matching ..................................................... 49

LO Feedthrough Compensation .............................................. 50

Results of Gain and Offset Correction .................................... 50

Outline Dimensions ....................................................................... 51

Ordering Guide .......................................................................... 52

Rev. B | Page 2 of 52

Data Sheet AD9114/AD9115/AD9116/AD9117

REVISION HISTORY

5/12—Rev. A to Rev. B

Changes to Table 1 ............................................................................ 5

Changes to Table 2 ............................................................................ 7

Changes to Table 3 and Table 4 ....................................................... 8

Changes to Theory of Operation Section .................................... 32

Changes to SCLK—Serial Clock Section ..................................... 33

Changes to Pin Mode Section ........................................................ 34

Changes to Table 14 ........................................................................ 37

Changes to Self-Calibration Section ............................................. 44

Deleted Modifying the Evaluation Board to Use the ADL5370

On-Board Quadrature Modulator Section ......................................... 51

Deleted Evaluation Board Schematics and Artwork Section and

Figure 111 to Figure 133, Renumbered Sequentially ................. 52

Updated Outline Dimensions ........................................................ 51

Changes to Ordering Guide ........................................................... 52

Deleted Bill of Materials Section and Table 18 ............................ 75

3/09—Rev. 0 to R e v. A

Changes to Product Title and General Description Section ....... 1

Changes to Figure 1 ........................................................................... 4

Changed I

= 2 mA to I

OUTFS

= 20 mA..................................... 5

xOUTFS

Changes to Table 1 ............................................................................ 6

Changed I

= 2 mA to I

OUTFS

= 20 mA..................................... 7

xOUTFS

Changes to Table 2 ............................................................................ 7

Changed DVDDIO = 1.8 V to DVDDIO = 3.3 V, Table 3 and

CVDD = 3.3 V to CVDD = 1.8 V, Table 4 ..................................... 8

Changes to Ta bl e 5 and Table 6 ....................................................... 9

Changes to Table 7 .......................................................................... 10

Changes to Table 8 .......................................................................... 12

Changes to Table 9 .......................................................................... 14

Changes to Table 10 ........................................................................ 16

Changes to Typical Performance Characteristics Section ......... 18

Changes to Theory of Operation Section and Figure 84 ........... 32

Added Figure 85 to Figure 88; Renumbered Sequentially ......... 34

Changes to Table 13 ........................................................................ 35

Changes to Table 14 ........................................................................ 36

Changes to Digital Interface Operation Section and Figure 89,

Figure 90, Figure 91, Figure 92, and Figure 93 ............................ 40

Changes to Figure 94, Digital Data Latching Section, and

Retimer Section ............................................................................... 41

Added Reference Operation Section, Reference Control
Amplifier Section, DAC Transfer Function Section, Figure 96,

and Tabl e 17 ..................................................................................... 43

Added Analog Output Section ...................................................... 44

Changes to Auxiliary DACs Section ............................................. 48

Changes to DAC to Modulator Int

erfacing Section, Figure 107,

and Figure 108 ................................................................................. 49

Added Figure 111 to Figure 133 .................................................... 52

Added Table 18 ................................................................................ 75

8/08—Revision 0: Initial Version

Rev. B | Page 3 of 52

AD9114/AD9115/AD9116/AD9117 Data Sheet

I DAC

Q DAC

AUX1DAC

AUX2DAC

BAND

GAP

CLOCK

DIST

10kΩ

QR

SET

2kΩ

IR

SET

2kΩ

I

REF

100µA

IR

CM

60Ω TO

260Ω

QR

CM

60Ω TO

260Ω

62.5Ω

62.5Ω

62.5Ω

62.5Ω

SPI

INTERFACE

1 INTO 2

INTERLEAVED

DATA

INTERFACE

I DATA

Q DATA

1.8V

LDO

1V

AD9117

RLIN

IOUTN
IOUTP

RLIP
AVDD
AVSS
RLQP

QOUTP
QOUTN

RLQN

DB11

DB10

DB9

DB8

DV

DDIO

DVSS

DVDD

DB7

DB6

DB5

DB12

DB13 (MSB)

CS/PWRDN

SDIO/FORMAT

SCLK/CLKMD

RESET/PINMD

REFIO

FSADJQ/AUXQ

FSADJI/AUXI

CMLI

DB4

DB3

DB2

DB1

(LSB) DB0

DCLKIO

CVDD

CLKIN

CVSS

CMLQ

07466-001

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Rev. B | Page 4 of 52

Data Sheet AD9114/AD9115/AD9116/AD9117

SPECIFICATIONS

DC SPECIFICATIONS

T

to T

MIN

, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, I

MAX

Table 1.

AD9114 AD9115 AD9116 AD9117

Parameter

RESOLUTION 8 10 12 14 Bits
ACCURACY, AVDD = DVDDIO =

CVDD = 3.3 V
Differential Nonlinearity (DNL)

Precalibration ±0.02 ±0.06 ±0.4 ±1.4 LSB
Postcalibration ±0.02 ±0.04 ±0.2 ±0.6 LSB

Integral Nonlinearity (INL)

Precalibration ±0.03 ±0.19 ±0.68 ±1.2 LSB
Postcalibration ±0.03 ±0.07 ±0.42 ±0.6 LSB

ACCURACY, AVDD = DVDDIO =CVDD =

1.8 V
Differential Nonlinearity (DNL)

Precalibration ±0.02 ±0.08 ±0.5 ±1.8 LSB
Postcalibration ±0.01 ±0.06 ±0.2 ±1.0 LSB

Integral Nonlinearity (INL)

Precalibration ±0.04 ±0.2 ±0.5 ±1.8 LSB
Postcalibration ±0.02 ±0.1 ±0.3 ±1.1 LSB

MAIN DAC OUTPUTS

Offset Error −1 +1 −1 +1 −1 +1 −1 +1 mV
Gain Error Internal Reference −2 +2 −2 +2 −2 +2 −2 +2 % of FSR
Full-Scale Output Current1

AVDD = 3.3 V 2 8 20 2 8 20 2 8 20 2 8 20 mA
AVDD = 1.8 V 2 8 2 8 2 8 2 8 mA

Output Common-Mode Level

(8 mA CMLx Pin)

Output Compliance Range

AVDD = 3.3 V, 8 mA Output

Common Mode Level = −0.5 −0.9 −0.1 −0.9 −0.1 −0.9 −0.1 −0.9 −0.1 V
Common Mode Level = 0 −0.4 +0.4 −0.4 +0.4 −0.4 +0.4 −0.4 +0.4 V

Common Mode Level = +1.2 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 V
Output Resistance 200 200 200 200 MΩ
Crosstalk, Q DAC to I DAC

= 30 MHz)

(f

OUT

Crosstalk, Q DAC to I DAC

= 60 MHz)

(f

OUT

MAIN DAC TEMPERATURE DRIFT

Offset 0 0 0 0 ppm/°C
Gain ±40 ±40 ±40 ±40 ppm/°C
Reference Voltage ±25 ±25 ±25 ±25 ppm/°C

−0.5 0 +1.2 −0.5 0 +1.2 −0.5 0 +1.2 −0.5 0 +1.2 V

95 95 95 95 dB

76 76 76 76 dB

= 20 mA, maximum sample rate, unless otherwise noted.

xOUTFS

Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max

Rev. B | Page 5 of 52

AD9114/AD9115/AD9116/AD9117 Data Sheet

Guaranteed

AD9114 AD9115 AD9116 AD9117

Parameter

AUXDAC OUTPUTS

Resolution 10 10 10 10 Bits
Full-Scale Output Current

125 125 125 125 µA

(Current Sourcing Mode)

Voltage Output Mode

Output Compliance Range

(Sourcing 1 mA)

Output Compliance Range

(Sinking 1 mA)

Output Resistance in Current

Output Mode AV

to 1 V

SS

AUXDAC Monotonicity

VSS VDD −

VSS +

VDD VSS +

0.25

VSS VDD −

0.25

0.25

VSS VDD −

0.25

VDD VSS +

0.25

VSS VDD −

0.25

VDD VSS +

0.25

VDD V

1 1 1 1 MΩ

10 10 10 10 Bits

REFERENCE OUTPUT

Internal Reference Voltage 0.98 1.025 1.08 0.98 1.025 1.08 0.98 1.025 1.08 0.98 1.025 1.08 V
Output Resistance 10 10 10 10 kΩ

REFERENCE INPUT

Voltage Compliance

AVDD = 3.3 V 0.1 1.25 0.1 1.25 0.1 1.25 0.1 1.25 V
AVDD = 1.8 V 0.1 1.0 0.1 1.0 0.1 1.0 0.1 1.0 V

Input Resistance External

1 1 1 1 MΩ

Reference Mode

DAC MATCHING

Gain Matching −1 +1 −1 +1 −1 +1 −1 +1 % of FSR

ANALOG SUPPLY VOLTAGES

AVDD 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 V
CVDD 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 V

DIGITAL SUPPLY VOLTAGES

DVDD 1.7 1.9 1.7 1.9 1.7 1.9 1.7 1.9 V
DVDDIO 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 V

POWER CONSUMPTION, AVDD =

DVDDIO = CVDD = 3.3 V
f

= 125 MSPS, IF = 12.5 MHz 220 220 220 220 mW

DAC

I

55 55 55 55 mA

AVDD

I

+ I

DVDD

I

CVDD

10 10 10 10 mA

DVDDIO

3 3 3 3 mA
Power-Down Mode with Clock 8.5 8.5 8.5 8.5 mW
Power-Down Mode No Clock 3 3 3 3 mW
Power Supply Rejection Ratio −0.009 −0.009 −0.009 −0.009 % FSR/V

POWER CONSUMPTION, AVDD =

DVDDIO = CVDD = 1.8 V
f

= 125 MSPS, IF = 12.5 MHz 58 58 58 58 mW

DAC

I

24 24 24 24 mA

AVDD

I

DVDD + IDVDDIO

I

CVDD

8 8 8 8 mA

2 2 2 2 mA
Power-Down Mode with Clock 12 12 12 12 mW
Power-Down Mode No Clock 850 850 850 850 µW
Power Supply Rejection Ratio −0.007 −0.007 −0.007 −0.007 % FSR/V

OPERATING RANGE −40 +25 +85 −40 +25 +85 −40 +25 +85 −40 +25 +85 °C

1

Based on a 10 kΩ external resistor.

Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max

V

0.25

Rev. B | Page 6 of 52

Data Sheet AD9114/AD9115/AD9116/AD9117

Minimum SDIO and to SCLK Setup, tDS

10 ns

1.8 V I Channel or DCLKIO Rising Edge

3.3 V I Channel or DCLKIO Rising Edge

DIGITAL SPECIFICATIONS

T

to T

MIN

, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, I

MAX

Table 2.

Parameter Min Typ Max Unit

DAC CLOCK INPUT (CLKIN)

VIH 2.1 3 V
VIL 0 0.9 V
Maximum Clock Rate 125 MSPS

SERIAL PERIPHERAL INTERFACE

Maximum Clock Rate (SCLK) 25 MHz
Minimum Pulse Width High 20 ns
Minimum Pulse Width Low 20 ns

Minimum SCLK to SDIO Hold, tDH 5 ns
Maximum SCLK to Valid SDIO, tDV 20 ns
Minimum SCLK to Invalid SDIO, t

5 ns

DNV

INPUT DATA

1.8 V Q Channel or DCLKIO Falling Edge
Setup 0.25 ns
Hold 1.2 ns

= 20 mA, maximum sample rate, unless otherwise noted.

xOUTFS

Setup 0.13 ns
Hold 1.1 ns

3.3 V Q Channel or DCLKIO Falling Edge
Setup −0.2 ns
Hold 1.5 ns

Setup −0.2 ns
Hold 1.6 ns

DVDDIO = 3.3 V

VIH 2.1 3 V
VIL 0 0.9 V

DVDDIO = 1.8 V

VIH 1.2 1.8 V
VIL 0 0.5 V

Rev. B | Page 7 of 52

AD9114/AD9115/AD9116/AD9117 Data Sheet

W-CDMA ADJACENT CHANNEL LEAKAGE

AD9114

AD9115

AD9116

AD9117

f

= 125 MSPS, f

= 10 MHz

76

76

76

76 dBc

AC SPECIFICATIONS

T

to T

MIN

, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, I

MAX

Table 3.

AD9114 AD9115 AD9116 AD9117

Parameter

DYNAMIC PERFORMANCE

Output Settling Time (tST) to 0.1% 11.5 11.5 11.5 11.5 ns
Output Rise Time (10% to 90%) 0.27 0.27 0.27 0.27 ns
Output Fall Time (90% to 10%) 0.27 0.27 0.27 0.27 ns
Output Noise (I

= 20mA) 1471 465 117 37 pA/√Hz

OUTFS

SPURIOUS FREE DYNAMIC RANGE (SFDR)

f

= 125 MSPS, f

DAC

f

= 125 MSPS, f

DAC

TWO TONE INTERMODULATION

= 10 MHz 76 85 85 85 dBc

OUT

= 50 MHz 55 55 55 55 dBc

OUT

DISTORTION (IMD)

f

= 125 MSPS, f

DAC

f

= 125 MSPS, f

DAC

NOISE SPECTRAL DENSITY (NSD),

= 10 MHz 81 81 81 82 dBc

OUT

= 50 MHz 60 60 60 61 dBc

OUT

EIGHT-TONE, 500 kHz TONE SPACING

f

= 125 MSPS, f

DAC

f

= 125 MSPS, f

DAC

f

= 125 MSPS, f

DAC

= 1 MHz −131 −141 −153 −163 dBc/Hz

OUT

= 10 MHz −132 −143 −153 −157 dBc/Hz

OUT

= 50 MHz −128 −138 −146 −149 dBc/Hz

OUT

= 20 mA, maximum sample rate, unless otherwise noted.

xOUTFS

Unit Min Typ Max Min Typ Max Min Ty p Max Min Typ Max

RATIO (ACLR), SINGLE CARRIER

f

= 61.44 MSPS, f

DAC

f

= 122.88 MSPS, f

DAC

T

to T

MIN

, AVDD = 1.8 V, DVDD = 1.8 V, DVDDIO = 1.8 V, CVDD = 1.8 V, I

MAX

= 20 MHz −78 −78 −78 −78 dBc

OUT

= 30 MHz −80 −80 −80 −80 dBc

OUT

= 8 mA, maximum sample rate, unless otherwise noted.

xOUTFS

Table 4.

Parameter

SPURIOUS FREE DYNAMIC RANGE (SFDR)

f

= 125 MSPS, f

DAC

f

= 125 MSPS, f

DAC

TWO TONE INTERMODULATION

= 10 MHz 73 76 76 76 dBc

OUT

= 50 MHz 48 48 48 48 dBc

OUT

DISTORTION (IMD)

DAC

f

= 125 MSPS, f

DAC

NOISE SPECTRAL DENSITY (NSD),

OUT

= 50 MHz 50 50 50 50 dBc

OUT

EIGHT-TONE, 500 kHz TONE SPACING
f

= 125 MSPS, f

DAC

f

= 125 MSPS, f

DAC

f

= 125 MSPS, f

DAC

W-CDMA ADJACENT CHANNEL LEAKAGE

= 1 MHz −131 −143 −152 −158 dBc/Hz

OUT

= 10 MHz −132 −143 −151 −152 dBc/Hz

OUT

= 50 MHz −128 −138 −140 −141 dBc/Hz

OUT

RATIO (ACLR), SINGLE CARRIER
f

= 61.44 MSPS, f

DAC

f

= 122.88 MSPS, f

DAC

= 20 MHz −69 −69 −69 −69 dBc

OUT

= 30 MHz −72 −72 −72 −72 dBc

OUT

Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max

Rev. B | Page 8 of 52

Data Sheet AD9114/AD9115/AD9116/AD9117

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

AVDD, DVDDIO, CVDD to AVSS,

−0.3 V to +3.9 V

DVSS, CVSS
DVDD to DVSS −0.3 V to +2.1 V
AVSS to DVSS, CVSS −0.3 V to +0.3 V
DVSS to AVSS, CVSS −0.3 V to +0.3 V
CVSS to AVSS, DVSS −0.3 V to +0.3 V
REFIO, FSADJQ, FSADJI, CMLQ,

−0.3 V to AVDD + 0.3 V

CMLI to AVSS
Q OU T P, QOUTN, IOUTP, IOUTN,

−1.0 V to AVDD + 0.3 V

RLQP, RLQN, RLIP, RLIN to AVSS
DBn1 (MSB) to D0 (LSB), CS, SCLK,

−0.3 V to DVDDIO + 0.3 V

SDIO, RESET to DVSS
CLKIN to CVSS −0.3 V to CVDD + 0.3 V
Junction Temperature 125°C
Storage Temperature Range −65°C to +150°C

1

n stands for 7 for the AD9114, 9 for the AD9115, 11 for the AD9116, and 13

for the AD9117.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

Table 6.

Package Type θJA θ

40-Lead LFCSP (with No Airflow

29.8 19.0 3.4 °C/W

Movement)

1

These calculations are intended to represent the thermal performance of the
indicated packages using a JEDEC multilayer test board. Do not assume the
same level of thermal performance in actual applications without a careful
inspection of the conditions in the application to determine that they are
similar to those assumed in these calculations.

JB

1

θ

1

Unit

JC

ESD CAUTION

Rev. B | Page 9 of 52

AD9114/AD9115/AD9116/AD9117 Data Sheet

PIN 1
INDICATOR

1DB5
2DB4
3DB3
4DB2
5DVDDIO
6DVSS
7DVDD
8DB1
9DB0 (LSB)

10NC

23

24

25

26

27

28

29

30

22
21

11NC

12NC

13NC

15NC

17CVDD

16DCLKIO

18CLKIN

19CVSS

20CMLQ

14NC

33

FSADJI/AUXI

34

R

EFIO

35

RESET/PINMD

36

SCLK/CLKMD

37

SDIO/FORMAT

38

CS/PWRDN

39

DB7 (MSB)

40

DB6

32

FSADJQ/AUXQ

31

CMLI

TOP VIEW

(Not to S cale)

AD9114

07466-005

NOTES

1. NC = NO CONNECT

2. THE EXP OSED PAD IS CO NNE CTED TO AVS S AND
MUST BE SO LDERED TO T HE GROUND PLANE.
EXPOSED M E TAL AT PACKAGE CORNERS IS
CONNECTED T O THIS PAD.

QOUTP

RLQP

AVSS

AVDD

RLIP

IOUTP

IOUTN

RLIN

QOUTN
RLQN

1 to 4

DB[5:2]

Digital Inputs.

9

DB0 (LSB)

Digital Input (LSB).

18

CLKIN

LVCMOS Sampling Clock Input.

21

RLQN

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 2. AD9114 Pin Configuration

Table 7. AD9114 Pin Function Descriptions

Pin No. Mnemonic Description

5 DVDDIO Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal).
6 DVSS Digital Common.
7 DVDD

Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD
with a 1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.

8 DB1 Digital Inputs

10 to

NC No Connect. These pins are not connected to the chip.

15
16 DCLKIO Data Input/Output Clock. Clock used to qualify input data.
17 CVDD Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD.

19 CVSS Sampling Clock Supply Voltage Common.
20 CMLQ

Q DAC Output Common-Mode Level. When the internal on-chip (QR
the on-chip QR

resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QR

CML

) is enabled, this pin is connected to

CML

disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor, see
the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.

Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to

QOUTN externally.
22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
24 RLQP

25 AVSS Analog Common.
26 AVDD Analog Supply Voltage Input (1.8 V to 3.3 V).
27 RLIP

28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s.

Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to

QOUTP externally.

Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to

IOUTP externally.

CML

) is

Rev. B | Page 10 of 52

Data Sheet AD9114/AD9115/AD9116/AD9117

Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QR

) is enabled, this pin is the auxiliary Q DAC output.

Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When

Pin No. Mnemonic Description

29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
30 RLIN

31 CMLI

32 FSADJQ/AUXQ

33 FSADJI/AUXI

Auxiliary I DAC Output (AUXI). When the internal on-chip (IR
34 REFIO

35 RESET/PINMD

A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.

37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.

38

CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.

39 DB7 (MSB) Digital Input (MSB).
40 DB6 Digital Input.
EP (EPAD)

Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.

I DAC Output Common-Mode Level. When the internal on-chip (IR
on-chip IR

resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IR

CML

) is enabled, this pin is connected to the

CML

CML

) is
disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor, see
the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.

Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QR

) is disabled, this pin is the full-scale

SET

current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of Operation
section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.

SET

Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IR

) is disabled, this pin is the full-scale

SET

current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation
section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.

) is enabled, it is the auxiliary I DAC output.

SET

Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
reference output when in internal reference mode (a 0.1 µF capacitor to AVSS is required).

This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
Pulse RESET high to reset the SPI registers to their default values.

DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer, see
the

Retimer section.

Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down
to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement
input data format.

Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for
the SPI port.

The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the
package corners is connected to this pad.

Rev. B | Page 11 of 52

AD9114/AD9115/AD9116/AD9117 Data Sheet

PIN 1
INDICATOR

1DB7
2DB6

3DB5
4DB4
5DVDDIO
6DVSS
7DVDD
8DB3
9DB2

10DB1

23 QOUTP

24 RLQP

25 AVSS

26 AVDD

27 RLIP

28 IOUTP

29 IOUTN

30 RLIN

22 QOUTN
21 RLQN

11

DB0 (LSB)

12NC

13NC

15NC

17CVDD

16DCLKIO

18CLKIN

19

CVSS

20CMLQ

14NC

33

FSADJI/AUXI

34

REFIO

35

RESET/PINMD

36

SCLK/CLKMD

37

SDIO/FORMAT

38

CS/PWRDN

39

DB9 (MSB)

40

DB8

32

FSADJQ/AUXQ

31

CMLI

TOP VIEW

(Not to S cale)

AD9115

07466-004

NOTES

1. NC = NO CONNECT

2. THE EXP OSED PAD IS CO NNE CTED TO AVS S AND
MUST BE SO LDERED TO T HE GROUND PLANE.
EXPOSED M E TAL AT PACKAGE CORNERS IS
CONNECTED T O THIS PAD.

11

DB0 (LSB)

Digital Input (LSB).

19

CVSS

Sampling Clock Supply Voltage Common.

30

RLIN

Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to

Figure 3. AD9115 Pin Configuration

Table 8. AD9115 Pin Function Description

Pin No. Mnemonic Description

1 to 4 DB[7:4] Digital Inputs.
5 DVDDIO Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal).
6 DVSS Digital Common.
7 DVDD

Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD
with a 1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.

8 to 10 DB[3:1] Digital Inputs.

12 to 15 NC No Connect. These pins are not connected to the chip.
16 DCLKIO Data Input/Output Clock. Clock used to qualify input data.
17 CVDD Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
18 CLKIN LVCMOS Sampling Clock Input.

20 CMLQ

Q DAC Output Common-Mode Level. When the internal on-chip (QR
the on-chip QR

resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QR

CML

) is enabled, this pin is connected to

CML

disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor, see
the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.

21 RLQN

Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to

QOUTN externally.
22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
24 RLQP

Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to

QOUTP externally.
25 AVSS Analog Common.
26 AVDD Analog Supply Voltage Input (1.8 V to 3.3 V).
27 RLIP

28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.

Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to

IOUTP externally.

CML

) is

IOUTN externally.

Rev. B | Page 12 of 52

Data Sheet AD9114/AD9115/AD9116/AD9117

32

FSADJQ/AUXQ

Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QR

) is disabled, this pin is the full-

37

SDIO/FORMAT

Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.

Pin No. Mnemonic Description

31 CMLI

I DAC Output Common-Mode Level. When the internal on-chip (IR
on-chip IR

resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IR

CML

disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor,
see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.

scale current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of

Operation section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QR
33 FSADJI/AUXI

Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IR

SET

current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation

section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on-chip (IR
34 REFIO

Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V

SET

reference output when in internal reference mode (a 0.1 µF capacitor to AVSS is required).
35 RESET/PINMD

This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.

Pulse RESET high to reset the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.

Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When

DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retime, see

the Retimer section.

) is enabled, this pin is connected to the

CML

SET

CML

) is

) is enabled, this pin is the auxiliary Q DAC output.

) is disabled, this pin is the full-scale

SET

) is enabled, it is the auxiliary I DAC output.

Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down

to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement

input data format.
38

CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.

Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the

SPI port.
39 DB9 (MSB) Digital Input (MSB).
40 DB82 Digital Input.
EP (EPAD)

The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the

package corners is connected to this pad.

Rev. B | Page 13 of 52

AD9114/AD9115/AD9116/AD9117 Data Sheet

PIN 1
INDICATOR

1DB9
2DB8
3DB7
4DB6
5DV

DDIO

6DVSS
7DVDD
8DB5
9DB4

10DB3

23 QOUTP

24 RLQP

25 AVSS

26 AVDD

27 RLIP

28 IOUTP

29 IOUTN

30 RLIN

22 QOUTN
21 RLQN

11DB2

12DB1

13

DB0 (LSB)

15NC

17CVDD

16DCLKIO

18CLKIN

19CVSS

20CMLQ

14NC

33

FSADJI/AUXI

34

REFIO

35

RESET/PINMD

36

SCLK/CLKMD

37

SDIO/FORMAT

38

CS/PWRDN

39

DB11 (MSB)

40

DB10

32

FSADJQ/AUXQ

31

CMLI

TOP VIEW

(Not to S cale)

AD9116

NOTES

1. NC = NO CONNECT

2. THE EXP OSED PAD IS CO NNE CTED TO AVS S AND
MUST BE SO LDERED TO T HE GROUND PLANE.
EXPOSED M E TAL AT PACKAGE CORNERS IS
CONNECTED T O THIS PAD.

07466-003

7

DVDD

Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD

24

RLQP

Figure 4. AD9116 Pin Configuration

Table 9. AD9116 Pin Function Descriptions

Pin No. Mnemonic Description

1 to 4 DB[9:6] Digital Inputs.
5 DVDDIO Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal).
6 DVSS Digital Common.

with a 1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8 to 12 DB[5:1] Digital Inputs.
13 DB0 (LSB) Digital Input (LSB).
14, 15 NC No Connect. These pins are not connected to the chip.
16 DCLKIO Data Input/Output Clock. Clock used to qualify input data.
17 CVDD Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
18 CLKIN LVCMOS Sampling Clock Input.
19 CVSS Sampling Clock Supply Voltage Common.
20 CMLQ

Q DAC Output Common-Mode Level. When the internal on-chip (QR

the on-chip QR

resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QR

CML

) is enabled, this pin is connected to

CML

disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor,

see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
21 RLQN

Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to

QOUTN externally.
22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.

Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to

QOUTP externally.
25 AVSS Analog Common.
26 AVDD Analog Supply Voltage Input (1.8 V to 3.3 V).
27 RLIP

28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
30 RLIN

Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to

IOUTP externally.

Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to

IOUTN externally.

CML

) is

Rev. B | Page 14 of 52

Data Sheet AD9114/AD9115/AD9116/AD9117

32

FSADJQ/AUXQ

Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QR

) is disabled, this pin is the full-

37

SDIO/FORMAT

Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.

Pin No. Mnemonic Description

31 CMLI

I DAC Output Common-Mode Level. When the internal on-chip (IR
on-chip IR

resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IR

CML

disabled, this pin is the common mode load for I DAC and must be connected to AVSS through a resistor, see
the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.

scale current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of

Operation section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QR
33 FSADJI/AUXI

Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IR

SET

current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation

section. Nominal value for this external resistor is 4 kΩ for 8 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on-chip (IR
34 REFIO

Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V

SET

reference output when in internal reference mode (a 0.1 µF capacitor to AVSS is required).
35 RESET/PINMD

This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.

Pulse RESET high to reset the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.

Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When

DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retime, see

the Retimer section.

) is enabled, this pin is connected to the

CML

SET

CML

) is

) is enabled, this pin is the auxiliary Q DAC output.

) is disabled, this pin is the full-scale

SET

) is enabled, it is the auxiliary I DAC output.

Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low

(pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the

twos complement input data format.
38

CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.

Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for

the SPI port.
39 DB11 (MSB) Digital Input (MSB).
40 DB10 Digital Input.
EP (EPAD)

The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the

package corners is connected to this pad.

Rev. B | Page 15 of 52

AD9114/AD9115/AD9116/AD9117 Data Sheet

PIN 1
INDICATOR

1DB11
2DB10

3DB9
4DB8
5DVDDIO
6D

VSS

7DVDD
8DB7
9DB6

10DB5

23 QOUTP

24 RLQP

25 AVSS

26 AVDD

27 RLIP

28 IOUTP

29 IOUTN

30 RLIN

22 QOUTN
21 RLQN

11DB4

12DB3

13DB2

15

DB0 (LSB)

17CVDD

16DCLKIO

18CLKIN

19CVSS

20CMLQ

14DB1

33

FSADJI/AUXI

34

REFIO

35

RESET/PINMD

36

SCLK/CLKMD

37

SDIO/FORMAT

38

CS/PWRDN

39

DB13 (MSB)

40

DB12

32

FSADJQ/AUXQ

31

CMLI

TOP VIEW

(Not to S cale)

AD9117

07466-002

NOTES

1. THE EXP OSED PAD IS CO NNE CTED TO AVS S AND
MUST BE SO LDERED TO T HE GROUND PLANE.
EXPOSED M E TAL AT PACKAGE CORNERS IS
CONNECTED T O THIS PAD.

15

DB0 (LSB)

Digital Input (LSB).

20

CMLQ

Q DAC Output Common-Mode Level. When the internal on-chip (QR

) is enabled, this pin is connected to

22

QOUTN

Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.

Figure 5. AD9117 Pin Configuration

Table 10. AD9117 Pin Function Descriptions

Pin No. Mnemonic Description

1 to 4 DB[11:8] Digital Inputs.
5 DVDDIO Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal).
6 DVSS Digital Common.
7 DVDD

Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD
with a 1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.

8 to 14 DB[7:1] Digital Inputs.

16 DCLKIO Data Input/Output Clock. Clock used to qualify input data.
17 CVDD Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
18 CLKIN LVCMOS Sampling Clock Input.
19 CVSS Sampling Clock Supply Voltage Common.

the on-chip QR

resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QR

CML

CML

disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor,
see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.

21 RLQN

Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.

23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
24 RLQP

Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to

QOUTP externally.
25 AVSS Analog Common.
26 AVDD Analog Supply Voltage Input (1.8 V to 3.3 V).
27 RLIP

28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
30 RLIN

Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to

IOUTP externally.

Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to

IOUTN externally.

CML

) is

Rev. B | Page 16 of 52