Analog Devices AD9100 Datasheet

A1

V

IN

CLK CLK

A2

SWITCH

50V

AD9100

62.3V

CLAMP

C

HOLD

22pF

V

OUT

Ultrahigh Speed

a

FEATURES
Excellent Hold Mode Distortion into 250 V

–88 dB @ 30 MSPS (2.3 MHz VIN)
–83 dB @ 30 MSPS (12.1 MHz V

–74 dB @ 30 MSPS (19.7 MHz V
16 ns Acquisition Time to 0.01%
<1 ps Aperture Jitter
250 MHz Tracking Bandwidth
83 dB Feedthrough Rejection @ 20 MHz

3.3 nV/√Hz Spectral Noise Density

MlL-STD-Compliant Versions Available

APPLICATIONS
A/D Conversion
Direct IF Sampling
Imaging/FLIR Systems
Peak Detectors
Radar/EW/ECM
Spectrum Analysis
CCD ATE

GENERAL DESCRIPTION

The AD9100 is a monolithic track-and-hold amplifier which
sets a new standard for high speed and high dynamic range
applications. It is fabricated in a mature high speed complemen­tary bipolar process. In addition to innovative design topologies,
a custom package is utilized to minimize parasitics and optimize
dynamic performance.

Acquisition time (hold to track) is 13 ns to 0.1% accuracy, and
16 ns to 0.01%. The AD9100 boasts superlative hold-mode
frequency domain performance; when sampling at 30 MSPS
hold mode distortion is less than 83 dBfs for analog frequencies
up to 12 MHz; and –74 dBfs at 20 MHz. The AD9100 can also
drive capacitive loads up to 100 pF with little degradation in
acquisition time; it is therefore well suited to drive 8- and 10-bit
flash converters at clock speeds to 50 MSPS. With a spectral
noise density of 3.3 nV/√Hz and feedthrough rejection of 83 dB
at 20 MHz, the AD9100 is well suited to enhance the dynamic
range of many 8- to 16-bit systems.

)

IN

)

IN

Monolithic Track-and-Hold

AD9100*

FUNCTIONAL BLOCK DIAGRAM

The AD9100 is “user friendly” and easy to apply: (1) it requires
+5 V/–5.2 V power supplies; (2) the hold capacitor and switch
power supply decoupling capacitors are built into the DIP pack­age; (3) the encode clock is differential ECL to minimize clock
jitter; (4) the input resistance is typically 800 kΩ; (5) the analog
input is internally clamped to prevent damage from voltage
transients.

The AD9100 is available in a 20-lead side-brazed “skinny DIP”
package. Commercial, industrial, and military temperature
grade parts are available. Consult the factory for information
about the availability of 883-qualified devices.

PRODUCT HIGHLIGHTS

1. Hold Mode Distortion is guaranteed.

2. Monolithic construction.

3. Analog input is internally clamped to protect against over­voltage transients and ensure fast recovery.

4. Output is short circuit protected.

5. Drives capacitive loads to 100 pF.

6. Differential ECL clock inputs.

*Patent pending.

REV. B

reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Information furnished by Analog Devices is believed to be accurate and

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

AD9100–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(unless otherwise noted, +VS = +5 V; –VS = –5.2 V; R

Test AD9100JD/AD/SD

= 100 V; RIN = 50 V)

LOAD

1

Parameter Conditions Temp Level Min Typ Max Units

DC ACCURACY

Gain ∆V
Offset V

= 2 V Full VI 0.989 0.994 V/V

IN

= 0 V Full VI –5 ±1+5mV

IN

Output Resistance 25°C V 0.4 Ω
Output Drive Capability Full VI ±40 ±60 mA
PSRR ∆V

= 0.5 V p-p Full VI 48 55 dB

S

Pedestal Sensitivity to Supply ∆VS = 0.5 V p-p Full VI 0.9 3 mV/V

ANALOG INPUT/OUTPUT

Output Voltage Range Full VI +2 ±2.2 –2 V
Input Bias Current 25°CVI–8±3+8µA

Input Overdrive Current

2

VIN = ±4 V; RIN = 50 Ω 25°CV ±22 mA

Full VI –16 +16 µA

Input Capacitance 25°C V 1.2 pF
Input Resistance 25°C, T

T

CLOCK/

CLOCK INPUTS
Input Bias Current CL/
Input Low Voltage (V

) Full VI –1.8 –1.5 V

IL

CL = –1.0 V Full VI 4 5 mA

MIN

VI 350 800 kΩ

MAX

VI 200 kΩ

Input High Voltage (VIH) Full VI –1.0 –0.8 V

TRACK MODE DYNAMICS

Bandwidth (–3 dB) V

≤ 0.4 V p-p Full IV 150 250 MHz

OUT

Slew Rate 4 V Step 25°C IV 550 850 V/µs

Overdrive Recovery Time

2

(to 0.1%) VIN = ±4 V to 0 V 25°CV 21 ns

4 V Step Full IV 500 V/µs

2nd Harm. Dist. (20 MHz, 2 V p-p) Full V –65 dBc
3rd Harm. Dist. (20 MHz, 2 V p-p) Full V –75 dBc
Integrated Output Noise (1-200 MHz) 25°CV 45 µV
RMS Spectral Noise @ 10 MHz 25°C V 3.3 nV/√Hz

HOLD MODE DYNAMICS

Worst Harmonic (2.3 MHz, 30 MSPS) V
Worst Harmonic (12.1 MHz, 30 MSPS) V
Worst Harmonic (12.1 MHz, 30 MSPS) V
Worst Harmonic (12.1 MHz, 30 MSPS) V
Worst Harmonic (19.7 MHz, 30 MSPS) V
Hold Noise
Droop Rate

3

4

= 2 V p-p 25°C V –83 dBfs

OUT

= 2 V p-p 25°C IV –80 –72 dBfs

OUT

= 2 V p-p T

OUT

= 2 V p-p T

OUT

= 2 V p-p 25°C V –74 dBfs

OUT

MAX
MIN

25°C V 300 3 t

IV –70 dBfs
IV –77 –68 dBfs

H

V/s rms

VIN = 0 V 25°CVI 110±mV/µs

T
T

MIN
MAX

VI 7 40 ±mV/µs
VI 5 30 ±mV/µs

Feedthrough Rejection (20 MHz) VIN = 2 V p-p Full V 83 dB

TRACK-TO-HOLD SWITCHING

Aperture Delay 25°C V +800 ps
Aperture Jitter 25°CV <1ps
Pedestal Offset V

= 0 V 25°CVI–8±1+8mV

IN

Full VI –10 +10 mV
Transient Amplitude VIN = 0 V Full V ±6mV
Settling Time to 1 mV Full IV 7 10 ns
Glitch Product VIN = 0 V 25°C V 15 pV-s

HOLD-TO-TRACK SWITCHING

Acquisition Time to 0.1% 2 V Step 25°CV 13 ns
Acquisition Time to 0.01% 2 V Step Full IV 16 23 ns
Acquisition Time to 0.01% 4 V Step 25°CV 20 ns

POWER SUPPLY

Power Dissipation Full VI 1.05 1.25 W

Current Full VI 96 118 mA

+V

S

–VS Current Full VI 116 132 mA

NOTES

1

AD9100JD: 0°C to +70°C. AD9100AD: –40°C to +85°C. AD9100SD: –55°C to +125°C. DIP θJA = 38°C/W; this is valid with the device mounted flush to a
grounded 2 oz. copper clad board with 16 sq. inches of surface area and no air flow.

2

The input to the AD9100 is internally clamped at ±2.3 V. The internal input series resistance is nominally 50 Ω.

3

Hold mode noise is proportional to the length of time a signal is held. For example, if the hold time (tH) is 20 ns, the accumulated noise is typically 6 µV (300 V/s 3
20 ns). This value must be combined with the track mode noise to obtain total noise.

4

Min and max droop rates are based on the military temperature range (–55°C to +125°C). Refer to the “Droop Rate vs Temperature” chart for min/max limits over
the commercial and industrial ranges.

Specifications subject to change without notice.

–2–

REV. B

AD9100

WARNING!

ESD SENSITIVE DEVICE

+2V

ANALOG

0V

INPUT

ACQUISITION TIME

(16ns)

TO

HOLD CAPACITOR/

ANALOG OUTPUT

CLOCK

INPUTS

–2V

+2V

0V

–2V

"1"

"0"

"HOLD"

CLOCK (PIN #19)

HOLD

TRACK

SWITCH

DELAY

TIME
(4ns)

Figure 1. Timing Diagram (1 ns/div)

ABSOLUTE MAXIMUM RATINGS

1

Supply Voltages (±VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6 V

Continuous Output Current . . . . . . . . . . . . . . . . . . . . . 70 mA

Analog Input Voltage

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 V

Operating Temperature Range (Case)

AD9100JD . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

AD9100AD . . . . . . . . . . . . . . . . . . . . . . . . .–25°C to +85°C

AD9100SD . . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175°C

Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C

Lead Soldering Temperature (10 sec) . . . . . . . . . . . . . +300°C

NOTES

1

Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.

2

Analog input voltage should not exceed ±VS.

APERTURE

DELAY
(0.8ns)

VOLTAGE

LEVEL HELD

TRACK TO

OBSERVED AT

HOLD CAPACITOR

OBSERVED AT

ANALOG OUTPUT

"TRACK"

CLOCK

HOLD

SETTLING

(7ns)

"HOLD"

EXPLANATION OF TEST LEVELS

Test Level

I – 100% production tested.
II – 100% production tested at +25°C, and sample tested at

specified temperatures.
III – Periodically sample tested.
IV – Parameter is guaranteed by design and characterization

testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at +25°C. 100%

production tested at temperature extremes for extended

temperature devices; sample tested at temperature

extremes for commercial/industrial devices.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9100 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Temperature Package Package

Model* Range Description Option

AD9100JD 0°C to +70°C Ceramic DIP D-20
AD9100AD –40°C to +85°C Ceramic DIP D-20
AD9100SD –55°C to +125°C Ceramic DIP D-20

*Consult factory about availability of parts screened to MIL-STD-883.

REV. B

–3–

EVALUATION BOARD ORDERING INFORMATION

Part Number Description

AD9100/PWB Printed Wiring Board (Only) of Evaluation

Circuit

AD9100/PCB Evaluation Board for AD9100T/H, Assembled

and Tested [Order AD9100T/H (DIP)
Separately]

AD9100

PIN FUNCTION DESCRIPTIONS/CONNECTIONS

Pin No. Description Connection

1–V

S

–5.2 V Power Supply
2, 3, 8, 10–13, 17 GND Common Ground Plane
4V
5, 7 –V

IN

S

Analog Input Signal

–5.2 V Power Supply
6, 15 BYPASS 0.1 µF to Ground
9V
14, 16, 20 +V
18

OUT

S

CLK Complement ECL Clock

Track-and-Hold Output

+5 V, Power Supply

19 CLK “True” ECL Clock

CHIP PAD ASSIGNMENTS

+VS CAP
(NOTE 1)

AD9100

TOP VIEW

(Not to scale)

–VS CAP
(NOTE 1)

HOLD CAP

(NOTE 3)

+VS+V

S

NC

23456789101112

113

32

+V

S

BYPASS

31

(NOTE 2)

+V

30

OUT

BYPASS

29

(NOTE 2)

28

+V

S

27

–V

S

+VS+V

NC

S

14

CLOCK

15

CLOCK

16

GND

17

18 19 20 21 22 23 24 25 26

–V

S

SIZE = 148 3 63 3 15 mils NC = NO CONNECT
NOTES:

1. SUPPLY BYPASS CAPACITOR; 0.01 TO 0.1mF CERAMIC
CONNECTED TO GROUND.

2. 0.01mF CERAMIC CONNECTED BETWEEN PAD 29 AND PAD 31.

3. HOLD CAPACITOR CONNECTED FROM PAD 4 AND PAD 5 TO
GROUND; 10–100pF, NOMINALLY 22pF. DIP PACKAGE DOES NOT
REQUIRE EXTERNAL HOLD CAPACITOR.

+V

GND

S

NC

–V

–V

S

IN

PIN CONFIGURATION

20-Lead Side-Brazed Ceramic DIP

–V

S

GND
GND

V

IN

S

S

AD9100

TOP VIEW

(Not to Scale)

–V

BYPASS

–V

GND GND

V

OUT

GND GND

+V

S

CLK

CLK

GND
+V

S

BYPASS
+V

S

GND

TERMINOLOGY
Analog Delay is the time required for an analog input signal to

propagate from the device input to output.
Aperture Delay tells when the input signal is actually sampled.

It is the time difference between the analog propagation delay of
the front-end buffer and the control switch delay time. (The
time from the hold command transition to when the switch is
opened.) For the AD9100, this is a positive value which means
that the switch delay is longer than the analog delay.

Aperture Jitter is the random variation in the aperture delay.
This is measured in ps-rms and results in phase noise on the
held signal.

Droop Rate is the change in output voltage as a function of
time (dV/dt). It is measured at the AD9100 output with the
device in hold mode and the input held at a specified dc value,
the measurement starts immediately after the T/H switches from
track to hold. Feedthrough Rejection is the ratio of the input
signal to the output signal when in hold mode. This is a mea­sure of how well the switch isolates the input signal from feeding
through to the output.

Hold-to-Track Switch Delay is the time delay from the track
command to the point when the output starts to change and
acquire a new signal.

Pedestal Offset is the offset voltage step measured immediately
after the AD9100 is switched from track to hold with the input
held at zero volts. It manifests itself as an added offset during
the hold time.

Track-to-Hold Settling Time is the time necessary for the
track to hold switching transient to settle to within 1 mV of its
final value.

Track-to-Hold Switching Transient is the maximum peak
switch induced transient voltage which appears at the AD9100
output when it is switched from track to hold.

–4–

REV. B