Analog Devices AD9058 Service Manual

Dual 8-Bit 50 MSPS

a

FEATURES
2 Matched ADCs on Single Chip
50 MSPS Conversion Speed
On-Board Voltage Reference
Low Power (<1 W)
Low Input Capacitance (10 pF)
65 V Power Supplies
Flexible Input Range

APPLICATIONS
Quadrature Demodulation for Communications
Digital Oscilloscopes
Electronic Warfare
Radar

GENERAL DESCRIPTION

The AD9058 combines two independent, high performance,
8-bit analog-to-digital converters (ADCs) on a single monolithic
IC. Combined with an optional on-board voltage reference,
the AD9058 provides a cost-effective alternative for systems
requiring two or more ADCs.

Dynamic performance (SNR, ENOB) is optimized to provide
up to 50 MSPS conversion rates. The unique architecture
results in low input capacitance while maintaining high per­formance and low power (<0.5 W/channel). Digital inputs
and outputs are TTL compatible.

Performance has been optimized for an analog input of 2 V p-p
(±1 V; 0 V to 2 V). Using the on-board 2 V voltage reference,
the AD9058 can be set up for unipolar positive operation
(0 V to 2 V). This internal voltage reference can drive
both ADCs.

Commercial (0°C to 70°C) and military (–55°C to +125°C)
temperature range parts are available. Parts are supplied in
hermetic 48-lead DIP and 44-lead “J” lead packages.

A/D Converter

FUNCTIONAL BLOCK DIAGRAM

AD9058

+V

REF

RF

LO

ENCODE

A

IN

ENCODE

A

IN

QUADRATURE RECEIVER

90ⴗ

8-BIT

ANALOG-

TO-DIGITAL

CONVERTER

–V

REF

2V

8-BIT

ANALOG-

TO-DIGITAL

CONVERTER

–V

REF

G

G

REF

+V

REF

AD9058

AD9058

8

A

8

B

8

Q

8

I

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD9058–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

[ⴞVS = ⴞ5 V; V
GROUND, unless otherwise noted.]1 All specifications apply to either of the two ADCs.

= 2 V (internal); ENCODE = 40 MSPS; AIN = 0 V to 2 V; –V

REF

REF

=

Test AD9058AJD/AJJ AD9058AKD/AKJ

Parameter Temp Level Min Typ Max Min Typ Max Unit

RESOLUTION 8 8 Bits

DC ACCURACY

Differential Nonlinearity 25°CI 0.25 0.65 0.25 0.5 LSB

Full VI 0.8 0.7 LSB

Integral Nonlinearity 25°CI 0.5 1.3 0.5 1.0 LSB

Full VI 1.4 1.25 LSB

No Missing Codes Full VI Guaranteed Guaranteed

ANALOG INPUT

Input Bias Current 25°CI 75 170 75 170 µA

Full VI 340 340 µA
Input Resistance 25°CI 12 28 12 28 kΩ
Input Capacitance 25°CIV 10 15 1015 pF
Analog Bandwidth 25°CV 175 175 MHz

REFERENCE INPUT

Reference Ladder Resistance 25°CI 120 170 220 120 170 220 Ω

Full VI 80 270 80 270 Ω
Ladder Tempco Full V 0.45 0.45 Ω/°C
Reference Ladder Offset 25°CI 8 16 8 16 mV

(Top) Full VI 24 24 mV

Reference Ladder Offset 25°CI 8 23 8 23 mV

(Bottom) Full VI 33 33 mV

Offset Drift Coefficient Full V 50 50 µV/°C

INTERNAL VOLTAGE REFERENCE

Reference Voltage 25°CI 1.95 2.0 2.20 1.95 2.0 2.20 V

Full VI 1.90 2.25 1.90 2.25 V
Temperature Coefficient Full V 150 150 µV/°C
Power Supply Rejection

Ratio (PSRR) 25°CI 10 25 10 25 mV/V

SWITCHING PERFORMANCE

Maximum Conversion Rate
Aperture Delay (t

)25°CIV 0.1 0.8 1.5 0.1 0.8 1.5 ns

A

2

25°CI 50 50 60 MSPS

Aperture Delay Matching 25°CIV 0.2 0 5 0.2 0.5 ns
Aperture Uncertainty (Jitter) 25°CV 10 10 ps, rms
Output Delay (Valid) (t
Output Delay (t

) Tempco Full V 16 16 ps/°C

V

Propagation Delay (t
Propagation Delay (t

2

)

V

2

)

PD

) Tempco Full V –16 –16 ps/°C

PD

25°CI 8 5 8 ns

25°CI 12 12 19 ns

Output Time Skew 25°CV 1 1 ns

ENCODE INPUT

Logic “1” Voltage Full VI 2 2 V
Logic “0” Voltage Full VI 0.8 0.8 V
Logic “1” Current Full VI 600 600 µA
Logic “0” Current Full VI 1000 1000 µA
Input Capacitance 25°CV 5 5 pF
Pulsewidth (High) 25°CI 8 8 ns
Pulsewidth (Low) 25°CI 8 8 ns

–2–

REV. D

AD9058

Test AD9058AJD/AJJ AD9058AKD/AKJ

Parameter Temp Level Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

Transient Response 25°CV 2 2 ns
Overvoltage Recovery Time 25°CV 2 2 ns
Effective Number of Bits (ENOB)

Analog Input @ 2.3 MHz 25°CI 7.7 7.2 7.7 Bits

@ 10.3 MHz 25°CI 7.4 7.1 7.4 Bits

Signal-to-Noise Ratio

3

Analog Input @ 2.3 MHz 25°CI 48 45 48 dB

@ 10.3 MHz 25°CI 46 44 46 dB

3

Signal-to-Noise Ratio

(Without Harmonics)

Analog Input @ 2.3 MHz 25°CI 48 46 48 dB

@ 10.3 MHz 25°CI 47 45 47 dB

Second Harmonic Distortion

Analog Input @ 2.3 MHz 25°CI 58 48 58 dBc

@ 10.3 MHz 25°CI 58 48 58 dBc

Third Harmonic Distortion

Analog Input @ 2.3 MHz 25°CI 58 50 58 dBc

@ 10.3 MHz 25°CI 58 50 58 dBc

Crosstalk Rejection

4

DIGITAL OUTPUTS

Logic “1” Voltage (I

= 2 mA) Full VI 2.4 2.4 V

OH

Logic “0” Voltage (IOL = 2 mA) Full VI 0.4 0.4 V

POWER SUPPLY

5

+VS Supply Current Full VI 127 154 127 154 mA

Supply Current Full VI 27 38 27 38 mA

–V

S

Power Dissipation Full VI 770 960 770 960 mW

NOTES

1

For applications in which +VS may be applied before –VS, or +VS current is not limited to 500 mA, a reverse-biased clamping diode should be inserted between
ground and –VS to prevent destructive latch up. See section entitled “Using the AD9058.”

2

To achieve guaranteed conversion rate, connect each data output to ground through a 2 k Ω pull-down resistor.

3

SNR performance limits for the 48-lead DIP “D” package are 1 dB less than shown. ENOB limits are degraded by 0.3 dB. SNR and ENOB measured with
analog input signal 1 dB below full scale at specified frequency.

4

Crosstalk rejection measured with full-scale signals of different frequencies (2.3 MHz and 3.5 MHz) applied to each channel. With both signals synchronously
encoded at 40 MSPS, isolation of the undesired frequency is measured with an FFT.

5

Applies to both A/Ss and includes internal ladder dissipation.

Specifications subject to change without notice.

3

25°CIV 60 4860 dBc

REV. D

–3–

AD9058

ABSOLUTE MAXIMUM RATINGS

1

Analog Input . . . . . . . . . . . . . . . . . . . . . . . . –1.5 V to +2.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V

+V

S

–VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.8 V to –6 V

Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +V

2

S

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Voltage Reference Current . . . . . . . . . . . . . . . . . . . . . . 53 mA

+V
–V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 V

REF

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.5 V

REF

Operating Temperature Range

AD9058AJD/AJJ/AKD/AKJ . . . . . . . . . . . . . . . 0°C to 70°C

Maximum Junction Temperature

3

AD9058AJD/AJJ/AKD/AKJ . . . . . . . . . . . . . . . . . . . 150°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

NOTES

1

Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.

2

For applications in which +VS may be applied before –VS, or +VS current is
not limited to 500 mA, a reverse-biased clamping diode should be inserted
between ground and –VS to prevent destructive latch up. See section entitled
“Using the AD9058.”

3

Typical thermal impedances: 44-lead hermetic J-leaded ceramic package: θJA = 86.4°C/W;

θJC = 24.9°C/W; 48-lead hermetic: DIP θJA = 40°C/W; θ

= 12°C/W.

JC

EXPLANATION OF TEST LEVELS

Test Level

I. 100% production tested.
II. 100% production tested at 25°C, and sample tested at

specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization

testing.
V. Parameter is a typical value only.
VI. All devices are 100% production tested at 25°C. 100%

production tested at temperature extremes for extended

temperature devices; sample tested at temperature

extremes for commercial/industrial devices.

ORDERING GUIDE

Temperature Package

Model Range Description Option

AD9058AJJ 0°C to 70°C 44-Lead J-Leaded J-44

AD9058AJJ-REEL 0°C to 70°C 44-Lead J-Leaded J-44

Ceramic

Ceramic

2

2

AD9058AKJ 0°C to 70°C 44-Lead J-Leaded J-44

Ceramic, AC Tested

AD9058ATJ/883

3

–55°C to +125°C 44-Lead J-Leaded J-44

Ceramic, AC Tested
AD9058AJD 0°C to 70°C 48-Lead Ceramic DIP D-48
AD9058AKD 0°C to 70°C 48-Lead Ceramic D-48

AD9058ATD/883

3

–55°C to +125°C 48-Lead Ceramic D-48

DIP, AC Tested

DIP, AC Tested

NOTES

1

D = Hermetic ceramic DIP package; J = leaded ceramic package.

2

Hermetically sealed ceramic package; footprint equivalent to PLCC.

3

For specifications, refer to Analog Devices Military Products Databook.

1

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9058 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

+V

S

5V

S

13k⍀

DIGITAL BITS

Equivalent Digital Outputs

ENCODE

Equivalent Encode Circuit

0.1␮F

* INDICATES EACH PIN IS CONNECTED THROUGH 2k⍀

** INDICATES EACH PIN IS CONNECTED THROUGH 100⍀

–4–

WARNING!

ESD SENSITIVE DEVICE

D0–D7*+V

+V

INT

+V

REF

COMP

GROUND

Burn-In Connections

ENCODE**

AD9058

–V

REF

**

A

IN

+V

S

–V

S

+5V

–5.2V

REV. D

AD9058

–V

–V

REF

+V

ENCODE

(MSB)

D

7

PIN CONFIGURATIONS

GROUND D

ENCODE D

REF

REF

S

IN

A

+V

6

7

S

S

GROUND

INT

+V

COMP

NC

+V

AD9058

D

6

D

5

D

4

D

3

D

2

D

1

17

18

(LSB)

0

D

GROUND

TOP VIEW

(Not to Scale)

S

S

+V

–V

NC = NO CONNECT

NC

GROUND

S

+V

+V

GROUND

GROUND

S

–V

S

+V

GROUND

IN

A

(LSB)

0

D

40

39

–V

S

–V

REF

+V

S

ENCODE

D

(MSB)

7

D

6

D

5

D

4

D

3

D

2

GROUND
D

1

29

28

GROUND D

GROUND –V

GROUND –V

GROUND D

ENCODE D

GROUND D7 (MSB)

AD9058AJJ/AKJ Pinouts

1

2

+V

3

S

4

–V

5

REF

–V

6

S

NC D

7

A

8

IN

+V

9

S

10

+V

11

REF

COMP +V

+V

+V

REF

+V

–V

–V

REF

+V

AD9058

12

TOP VIEW

13

INT

(Not to Scale)

14

15

16

S

A

17

IN

NC D

18

19

S

20

21

22

S

23

24

NC = NO CONNECT

AD9058AJD/AKD Pinouts

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

(MSB)

7

6

D

5

4

D

3

D

2

1

D0 (LSB)

GROUND

S

GROUND

S

+V

S

GROUND

S

GROUND

D0 (LSB)

1

D

2

D

3

4

D

5

6

PIN FUNCTION DESCRIPTIONS

J-Lead Ceramic DIP

Pin Number Pin Number

ADC-A ADC-B Mnemonic Function ADC-A ADC-B

343 +V

REF

Top of Internal Voltage Reference Ladder 14 11
442 GROUND Analog Ground Return 15 10
541 +V
640 A
739 –V
838 –V
937 +V

S

IN

S

REF

S

Positive 5 V Analog Supply Voltage 16 9

Analog Input Voltage 17 8

Negative 5 V Supply Voltage 19 6

Bottom of Internal Voltage Reference Ladder 20 5

Positive 5 V Digital Supply Voltage 22 3
10 36 ENCODE TTL Compatible Convert Command 23 2
11 35 D
12–17 34–29 D
18 28 D

(MSB) Most Significant Bit of TTL Digital Output 25 48

7

6–D1

(LSB) Least Significant Bit of TTL Digital Output 32 41

0

TTL Compatible Digital Output Bits 26–31 47–42

19 27 GROUND Digital Ground Return 21, 24, 33 1, 4, 40
20 26 –V

S

Negative 5 V Supply Voltage 34 39
21 25 GROUND Analog Ground Return 35 38
22 24 +V

S

Positive 5 V Analog Supply Voltage 36 37
COMMON PINS COMMON PINS
1 COMP Connection for External (0.1 µF) 12

Compensation Capacitor
2+V

INT

Internal 2 V Reference; Can Drive 13

+V

for Both ADCs

REF

REV. D

–5–

AD9058

THEORY OF OPERATION

The AD9058 contains two separate 8-bit analog-to-digital con­verters (ADCs) on a single silicon die. The two devices can be
operated independently with separate analog inputs, voltage
references, and clocks.

In a traditional flash converter, 256 input comparators are required
to make the parallel conversion for 8-bit resolution. This is in
marked contrast to the scheme used in the AD9058, as shown
in Figure 1.

Unlike traditional “flash,” or parallel, converters, each of the two
ADCs in the AD9058 utilizes a patented interpolating archi­tecture to reduce circuit complexity, die size, and input capacitance.
These advantages accrue because, compared to a conventional
flash design, only half the normal number of input comparator
cells is required to accomplish the conversion.

In this unit, each of the two independent ADCs uses only 128 (2

7

)
comparators to make the conversion. The conversion for the
seven most significant bits (MSBs) is performed by the 128
comparators. The value of the least significant bit (LSB) is
determined by interpolation between adjacent comparators in
the decoding register. A proprietary decoding scheme processes
the comparator outputs and provides an 8-bit code to the output
register of each ADC; the scheme also minimizes error codes.

ANALOG IN

+V

REF

–V

REF

128

127

256

2

1

INTERPOLATING LATCHES

8

DECODE LOGIC

8

LATCHES

Figure 1. Comparator Block Diagram

Analog input range is established by the voltages applied at the
voltage reference inputs (+V

REF

and –V

). The AD9058 can

REF

operate from 0 V to 2 V using the internal voltage reference,
or anywhere between –1 V and +2 V using external references.
Input range is limited to 2 V p-p when using external references.
The internal resistor ladder divides the applied voltage reference
into 128 steps, with each step representing two 8-bit quanti­zation levels.

ANALOG

IN A ⴞ0.5V

ANALOG

IN B ⴞ0.5V

200⍀

0.1␮F

200⍀

800⍀

–2V

800⍀

400⍀

AD9617

AD707

20k⍀

400⍀

AD9617

20k⍀

5⍀

0.1␮F

5⍀

+2V

0.1␮F

ENCODE

8

38

6

2

3

43

1

40

10 36

ENCODE

A

–V

REF A

–V

REF B

A

IN A

+V

INT

+V

REF A

+V

REF B

COMP

A

IN B

AD9058

(J-LEAD)

4, 19, 21,
25, 27, 42

ENCODE

B

D0A(LSB)

D

(MSB)

7A

D0B(LSB)

D7B(MSB)

+5V

1N4001

1k⍀

–5V

10pF

8

74HCT 273

CLOCK

8

74HCT 273

CLOCK

(SEE TEXT)

74HCT04

50⍀

5, 9, 22,
24, 37, 41

+V

S

18
17
16
15
14
13
12
11

28
29
30
31
32
33
34
35

7, 20,
26, 39

–V

S

0.1␮F

Figure 2. AD9058 Using Internal 2 V Voltage Reference

–6–

REV. D

AD9058

ANALOG

IN A

ⴞ0.125V

ANALOG

IN B

ⴞ0.125V

10k⍀ 10k⍀

20k⍀

+5V

1

AD580

2

0.1␮F

50⍀

1/2

AD708

50⍀

3

AD708

400⍀

AD9618

20k⍀

150⍀

400⍀

AD9618

1/2

2N3906

–5V

150⍀

10k⍀

+5V

0.1␮F

5⍀

0.1␮F

5k⍀

2N3904

10⍀

0.1␮F

ENCODE

ⴞ1V

–1V

ⴞ1V

43

38

40

3

6

8

1

+V

+V

A

–V

–V

A

COMP

AD9058

(J-LEAD)

10 36

ENCODE

A

REF A

REF B

IN A

REF A

REF B

IN B

4, 19, 21,
25, 27, 42

ENCODE

B

D0A(LSB)

(MSB)

D

7A

D0B(LSB)

D7B(MSB)

+5V

RZ1

RZ2

1N4001

1k⍀

–5V

10pF

8

74ACT 273

CLOCK

8

74ACT 273

CLOCK

(SEE TEXT)

74ACT04

50k⍀

5, 9, 22,
24, 37, 41

+V

S

0.1␮F

18
17
16
15
14
13
12
11

28
29
30
31
32
33
34
35

7, 20,
26, 39

–V

S

0.1␮F

Figure 3. AD9058 Using External Voltage References

The on-board voltage reference, +V

, is a band gap reference

INT

that has sufficient drive capability for both reference ladders.
It provides a 2 V reference that can drive both ADCs in the
AD9058 for unipolar positive operation (0 V to 2 V).

USING THE AD9058

Refer to Figure 2. Using the internal voltage reference con­nected to both ADCs as shown reduces the number of external
components required to create a complete data acquisition
system. The input ranges of the ADCs are positive unipolar
in this configuration, ranging from 0 V to 2 V. Bipolar input
signals are buffered, amplified, and offset into the proper input
range of the ADC using a good low distortion amplifier such
as the AD9617 or AD9618.

The AD9058 offers considerable flexibility in selecting the analog
input ranges of the ADCs; the two independent ADCs can even
have different input ranges if required. In Figure 3, the AD9058
is shown configured for ±1 V operation.

The “Reference Ladder Offset” shown in the specifications table
refers to the error between the voltage applied to the +V
or –V

(bottom) of the reference ladder and the voltage required

REF

REF

(top)

at the analog input to achieve a 1111 1111 or 0000 0000 transi­tion. This indicates the amount of adjustment range that must be
designed into the reference circuit for the AD9058.

The diode shown between ground and –V

is normally reverse-

S

biased and is used to prevent latch-up. Its use is recommended
for applications in which power supply sequencing might allow

to be applied before –VS; or the +VS supply is not current

+V

S

REV. D

–7–

limited. If the negative supply is allowed to float (the +5 V supply
is powered up before the –5 V supply), substantial +5 V supply
current will attempt to flow through the substrate (V

supply con-

S

tact) to ground. If this current is not limited to <500 mA, the part
may be destroyed. The diode prevents this potentially destructive
condition from occurring.

Timing

Refer to the AD9058 Timing Diagram, Figure 4. The AD9058
provides latched data outputs with no pipeline delay. To conserve
power, the data outputs have relatively slow rise and fall times.
When designing system timing, it is important to observe (1) setup
and hold times; and (2) the intervals when data is changing.

Figure 3 shows 2 kΩ pull-down resistors on each of the D

0–D7

output data bits. When operating at conversion rates higher than
40 MSPS, these resistors help equalize rise and fall times and
ease latching the output data into external latches. The 74ACT
logic family devices have short setup and hold times and are the
recommended choices for speeds of 40 MSPS or more.

Layout

To ensure optimum performance, a single low impedance ground
plane is recommended. Analog and digital grounds should be con­nected together and to the ground plane at the AD9058 device.
Analog and digital power supplies should be bypassed to ground
through 0.1 µF ceramic capacitors as close to the unit as possible.

For prototyping or evaluation, surface-mount sockets are available
from Methode Electronics, Inc. (Part No. 213-0320602) for
evaluating AD9058 surface-mount packages. To evaluate the

AD9058

AD9058 in through-hole PCB designs, use the AD9058AJD/AKD
with individual pin sockets (AMP Part No. 6-330808-0). Alterna­tively, surface-mount AD9058 units can be mounted in a
through-hole socket (Circuit Assembly Corporation, Irvine, Cali­fornia Part No. CA-44SPC-T).

AD9058 APPLICATIONS

Combining two ADCs in a single package is an attractive alterna­tive in a variety of systems when cost, reliability, and space are
important considerations. Different systems emphasize particular
specifications, depending on how the part is used.

In high density digital radio communications, a pair of high
speed ADCs are used to digitize the in-phase (I) and quadrature
(Q) components of a modulated signal. The signal presented to
each ADC in this type of system consists of message-dependent
amplitudes varying at the symbol rate, which is equal to the
sample rates of the converters.

ANALOG

INPUT

ENCODE

D

0–D7

N

VA LID DATA

FOR N

N+1

t

A

t

V

VA LID DATA

FOR N–1

t

PD

t

= APERTURE TIME

A

t

= DATA DELAY OF PRECEDING ENCODE

V

t

= OUTPUT PROPAGATION DELAY

PD

DATA

CHANGING

N+2

VA LID DATA

FOR N+1

Figure 4. Timing Diagram

Figure 5 shows what the analog input to the AD9058 would
look like when observed relative to the sample clock. Signal-to­noise ratio (SNR), transient response, and sample rate are all
critical specifications in digitizing this “eye pattern.”

the time required for the AD9058 to achieve full accuracy when
a step function input is applied. Overvoltage recovery time is the
interval required for the AD9058 to recover to full accuracy after an
overdriven analog input signal is reduced to its input range.

Time domain performance of the ADC is also extremely important
in digital oscilloscopes. When a track-/sample-and-hold is used
ahead of the ADC, its operation becomes similar to that described
above for receivers.

The dynamic response to high frequency inputs can be described by
the effective number of bits (ENOB). The effective number of
bits is calculated with a sine wave curve fit and is expressed as:

ENOB N LOG Error measured Error ideal=−

2

()()

[]

where N is the resolution (number of bits) and measured error is
actual rms error calculated from the converter’s outputs with
a pure sine wave applied as the input.

Maximum conversion rate is defined as the encode (sample)
rate at which SNR of the lowest frequency analog test signal
drops no more than 3 dB below the guaranteed limit.

60

+125 C

55

+25 C

–55 C

50

45

40

HARMONIC DISTORTION – dB

35

30

0.1 1 10 100
INPUT FREQUENCY – MHz

Figure 6. Harmonic Distortion vs. Analog Input Frequency

ANALOG

INPUT

SAMPLE

CLOCK

Figure 5. I and Q Input Signals

Receiver sensitivity is limited by the SNR of the system. For the
ADC, SNR is measured in the frequency domain and calculated
with a Fast Fourier Transform (FFT). The signal-to-noise ratio
equals the ratio of the fundamental component of the signal
(rms amplitude) to the rms level of the noise. Noise is the sum
of all other spectral components, including harmonic distortion,
but excluding dc.

Although the signal being sampled does not have a significant
slew rate at the instant it is encoded, dynamic performance of
the ADC and the system is still critical. Transient response is

–8–

55

50

45

40

35

SIGNAL-TO-NOISE RATIO (SNR) – dB

30

0.1 1 10 100
INPUT FREQUENCY – MHz

+25 C AND +125 C

–55 C

Figure 7. Dynamic Performance vs. Analog Input
Frequency

8.0

7.2

6.4

5.5

EFFECTIVE NUMBER OF BITS (ENOB)

REV. D

MECHANICAL INFORMATION

AD9058

Die Dimensions . . . . . . . . . 106 mils × 108 mils × 15 (± 2) mils

Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 4 mils × 4 mils

Metallization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold

Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None

Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V

Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride

Die Attach . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic)

Bond Wire . . . . . . . . . 1 mil–1.3 mil, Gold; Gold Ball Bonding

S

–V

–V

A

S

+V

GROUND

+V

REF

+V

COMP

+V

REF

GROUND

+V

A

INT

IN

S

S

IN

S

REF

–V

–V

+V

S

+V

7

D

ENCODE

(MSB)

7

D

ENCODE

6D5

D

6

D

4

5

4

D

D

1

D3D

D2D

(LSB)

D

0

GROUND

–V

S

GROUND

+V

S

+V

S

GROUND

–V

S

GROUND

D0 (LSB)

1

2

3

D

D

D

(MSB)

S

REF

REV. D

–9–

AD9058

OUTLINE DIMENSIONS

44-Lead Ceramic Leaded Chip Carrier — J-Formed Leads [JLCC]

(J-44)

Dimensions shown in inches and (millimeters)

0.650 (16.51)

0.610 (15.49)

0.025 (0.64)
MIN

0.032 (0.81)

0.020 (0.51)

0.023 (0.58)

0.013 (0.33)

0.005 (0.13)

0.225 (5.72)

0.200 (5.08)

0.125 (3.18)

0.078 (1.98)

0.054 (1.37)

0.135 (3.43)

0.100 (2.54)

0.662 (16.82)

0.628 (15.95)

39

40

0.050
(1.27)

BSC

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

PIN 1

6

0.700 (17.78)

0.680 (17.27)

SQ

TOP VIEW

SQ

29

28

18

177

0.040 (1.02)

3 PLACES

0.500 (12.70)

0.492 (12.50)

REF

x 45

48-Lead Side-Brazed Solder Lid Ceramic DIP [DIP/SB]

(D-48)

Dimensions shown in inches and (millimeters)

0.098 (2.49)

MIN

PIN 1

MAX

48

1 24

2.424 (63.57) MAX

0.023 (0.58)

0.014 (0.36)

0.110 (2.79)

0.090 (2.29)

MAX

0.070 (1.78)

0.030 (0.76)

25

0.620 (15.75)

0.590 (14.99)

SEATING
PLANE

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MIN

PIN 1 INDEX

0.065 (1.65)

BOTTOM VIEW

0.630 (16.00)

0.520 (13.21)

0.015 (0.38)

0.008 (0.20)

0.020 (0.51)
REF
x 45

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

–10–

REV. D

AD9058

Revision History

Location Page

5/03—Data Sheet changed from REV. C to REV. D

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6/01—Data Sheet changed from REV. B to REV. C

Edits to ELECTRICAL CHARACTERISTICS headings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edits to Pinout captions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edits to Layout section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

REV. D

–11–

C00562–0–5/03(D)

–12–