ANALOG DEVICES AD9022 Service Manual

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12-Bit 20 MSPS

a

FEATURES
Monolithic
12-Bit 20 MSPS A/D Converter
Low Power Dissipation: 1.4 Watts
On-Chip T/H and Reference
High Spurious-Free Dynamic Range
TTL Logic

APPLICATIONS
Radar Receivers
Digital Communications
Digital Instrumentation
Electro-Optics

PRODUCT DESCRIPTION

The AD9022 is a high speed, high performance, monolithic
12-bit analog-to-digital converter. All necessary functions, in­cluding track-and-hold (T/H) and reference, are included
on-chip to provide a complete conversion solution. It is a
companion unit to the AD9023; the primary difference between
the two is that all logic for the AD9022 is TTL-compatible,
while the AD9023 utilizes ECL logic for digital inputs and out­puts. Pinouts for the two parts are nearly identical.

Operating from +5 V and –5.2 V supplies, the AD9022 pro­vides excellent dynamic performance. Sampling at 20 MSPS
with A
typically 76 dB; with A
typically 65 dB.

The onboard T/H has a 110 MHz bandwidth and, more impor­tantly, is designed to provide excellent dynamic performance for
analog input frequencies above Nyquist. This feature is neces­sary in many undersampling signal processing applications, such
as in direct IF-to-digital conversion.

To maintain dynamic performance at higher IFs, monolithic
RF track-and-holds (such as the AD9100 and AD9101
Samplifier™) can be used with the AD9022 to process signals
up to and beyond 70 MHz.

= 1 MHz, the spurious-free dynamic range (SFDR) is

IN

= 9.6 MHz, SFDR is 74 dB. SNR is

IN

Monolithic A/D Converter

AD9022

FUNCTIONAL BLOCK DIAGRAM

ANALOG

INPUT

ENCODE

With DNL typically less than 0.5 LSB and 20 ns transient re­sponse settling time, the AD9022 provides excellent results
when low-frequency analog inputs must be oversampled (such
as CCD digitization). The full scale analog input is ± 1 V with a
300 Ω input impedance. The analog input can be driven directly
from the signal source, or can be buffered by the AD96xx series
of low noise, low distortion buffer amplifiers.

All timing is internal to the AD9022; the clock signal initiates
the conversion cycle. For best results, the encode command
should contain as little jitter as possible. High speed layout
practices must be followed to ensure optimum A/D perfor­mance.

The AD9022 is built on a trench isolated bipolar process and
utilizes an innovative multipass architecture (see the block
diagram). The unit is packaged in 28-lead ceramic DIPs and
gullwing surface mount packages. The AD9022 is specified to
operate over the industrial (–25°C to +85°C) and military
(–55°C to +125°C) temperature ranges.

T/H

5-BIT

ADC

DAC

+2V
REF

T/H

AD9022

16

5-BIT

ADC

DAC

DIGITAL

ERROR

CORRECTION

8

4-BIT

ADC

12

TTL

+5V

–5.2V

GND

Samplifier is a trademark of Analog Devices, Inc.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

AD9022–SPECIFICA TIONS

ELECTRICAL CHARACTERISTICS

Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Min Typ Max Units

RESOLUTION 12 12 12 Bits
DC ACCURACY

Differential Nonlinearity +25°C I 0.6 0.75 0.4 0.5 0.6 0.75 LSB

Full VI 1.0 1.0 1.0 LSB

Integral Nonlinearity +25°C I 1.3 2.5 1.3 2.0 1.3 2.5 LSB

Full VI 1.6 3.0 1.6 3.0 1.6 3.0 LSB
No Missing Codes Full VI Guaranteed Guaranteed Guaranteed
Offset Error +25°CI 525 525 525 mV

Full VI 15 35 15 35 15 35 mV
Gain Error +25°C I 0.5 2.5 0.5 2.5 0.5 2.5 % FS

Full VI 0.6 3.5 0.6 3.5 0.6 3.5 % FS
Thermal Noise +25°C V 0.57 0.57 0.57 LSB, rms

ANALOG INPUT

Input Voltage Range ±1.024 ±1.024 ±1.024 V
Input Resistance Full IV 240 300 360 240 300 360 240 300 360 Ω
Input Capacitance +25°CV 5 5 5 pF
Analog Bandwidth +25°C V 110 110 110 MHz

SWITCHING PERFORMANCE

Minimum Conversion Rate +25°C IV 4 4 4 MSPS
Maximum Conversion Rate Full VI 20 20 20 MSPS
Aperture Delay (t
Aperture Uncertainty (Jitter) +25°C V 6 6 6 ps, rms
Output Delay (tOD) Full VI 15 27.5 15 27.5 15 27.5 ns

) +25°C IV 0.55 0.71 0.85 0.55 0.71 0.85 0.55 0.71 0.85 ns

A

1

(+VS = +5 V; –VS = –5.2 V; Encode = 20 MSPS, unless otherwise noted)

Test AD9022AQ/AZ AD9022BQ/BZ AD9022SQ/SZ

ENCODE INPUT

Logic Compatibility TTL TTL TTL
Logic “1” Voltage Full VI 2.0 2.0 2.0 V
Logic “0” Voltage Full VI 0.8 0.8 0.8 V
Logic “1” Current Full VI 8 20 8 20 8 20 µA
Logic “0” Current Full VI 8 20 8 20 8 20 µA
Input Capacitance +25°CV 6 6 6 pF
Pulsewidth (High) +25°C IV 22.5 125 22.5 125 22.5 125 ns
Pulsewidth (Low) +25°C IV 20 125 20 125 20 125 ns

DYNAMIC PERFORMANCE

Transient Response +25°C V 20 20 20 ns
Overvoltage Recovery Time +25°C V 20 20 20 ns
Harmonic Distortion

Analog Input @ 1.2 MHz +25°C I 65 73 70 75 65 73 dBc

@ 1.2 MHz Full V 70 72 70 dBc
@ 4.3 MHz +25°C V 73 75 73 dBc
@ 9.6 MHz +25°C I 63 72 69 74 63 72 dBc
@ 9.6 MHz Full V 68 72 68 dBc

Signal-to-Noise Ratio

Analog Input @ 1.2 MHz +25°C I 62 64 64 66 62 64 dB

Signal-to-Noise Ratio

(Without Harmonics)
Analog Input @ 1.2 MHz +25°C I 63 66 65 67 63 66 dB

2

@ 1.2 MHz Full V 63 65 63 dB
@ 4.3 MHz +25°C V 64 66 64 dB
@ 9.6 MHz +25°C I 61 63 63 65 61 63 dB
@ 9.6 MHz Full V 62 63 62 dB

2

@ 1.2 MHz Full V 64 66 64 dB
@ 4.3 MHz +25°C V 66 66 66 dB
@ 9.6 MHz +25°C I 62 65 64 66 62 65 dB
@ 9.6 MHz Full V 63 65 63 dB

–2–

REV. B

AD9022

Test AD9022AQ/AZ AD9022BQ/BZ AD9022SQ/SZ

Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Min Typ Max Units

Two-Tone Intermodulation

Distortion Rejection

DIGITAL OUTPUTS

Logic Compatibility TTL TTL TTL
Logic “1” Voltage Full VI 2.4 2.4 2.4 V
Logic “0” Voltage Full VI 0.5 0.5 0.5 V
Output Coding Offset Binary Offset Binary Offset Binary

POWER SUPPLY

+V

Supply Voltage Full VI 4.75 5.0 5.25 4.75 5.0 5.25 4.75 5.0 5.25 mA

S

+VS Supply Current Full VI 100 120 100 120 100 120 mA
–V

Supply Voltage Full VI –5.45 –5.2 –4.95 –5.45 –5.2 –4.95 –5.45 –5.2 –4.95 mA

S

–VS Supply Current Full VI 180 220 180 220 180 220 mA
Power Dissipation Full VI 1.4 1.9 1.4 1.9 1.4 1.9 W
Power Supply

Rejection Ratio (PSRR)

NOTES

1

AD9022 load is a single LS latch.

2

RMS signal-to-rms noise with analog input signal 1 dB below full scale at specified frequency. Tested at 55% duty cycle.

3

Intermodulation measured with analog input frequencies of 8.9 MHz and 9.8 MHz at 7 dB below full scale.

4

PSRR is sensitivity of offset error to power supply variations within the 5% limits shown.

Specifications subject to change without notice.

3

1

4

+25°C V 74 74 74 dBc

Full V 32 32 32 mV/V

N

ANALOG

ENCODE

DATA

OUTPUT

IN

t

a

t

= 0.7 TYPICAL

a

t

OD

t

OD

AD9022 Timing Diagram

ABSOLUTE MAXIMUM RATINGS

1

+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V

–V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–6 V

S

Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . –1.5 V to +1.5 V

Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+V

to 0 V

S

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Operating Temperature Range

AD9022AQ/AZ/BQ/BZ . . . . . . . . . . . . . . . –25°C to +85°C

AD9022SQ/SZ . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Maximum Junction Temperature

2

. . . . . . . . . . . . . . . . +175°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

NOTES

1

Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.

2

Typical thermal impedances: “Q” Package (Ceramic DIP): θJC = 10°C/W; θJA =
35°C/W. “Z” Package (Gullwing Surface Mount): θJC = 13°C/W; θJA = 45°C/W.

N + 1

N + 2

= 15–27.5 TYPICAL

N – 2 N – 1

NN – 3

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD9022AQ/BQ –25°C to +85°C 28-Lead Ceramic DIP Q-28
AD9022AZ/BZ –25°C to +85°C 28-Pin Ceramic Z-28

Leaded Chip Carrier
AD9022SQ –55°C to +125°C 28-Lead Ceramic DIP Q-28
AD9022SZ –55°C to +125°C 28-Pin Ceramic Z-28

Leaded Chip Carrier

REV. B

–3–

AD9022

EXPLANATION OF TEST LEVELS
Test Level

I – 100% production tested.
II – 100% production tested at +25°C, and sample tested at

specified temperatures. AC testing done on sample basis.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization

testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at +25°C. 100%

production tested at temperature extremes for extended

temperature devices; guaranteed by design and character-

ization testing for industrial devices.

DIE LAYOUT AND MECHANICAL INFORMATION

Die Dimensions . . . . . . . . . . . . . . . . 205 × 228 × 21 (±1) mils

Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils

Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum

Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None

Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V

S

Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4,080

Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride

Bond Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum

PIN FUNCTION DESCRIPTIONS

Pin No. Name Function

1–3 D3–D1 Digital output bits of ADC; TTL

compatible.

4 D0 (LSB) Least significant bit of ADC output;

TTL compatible.
5 NC No Connection Internally
6+V

S

+5 V Power Supply
7 GND Ground
8 ENCODE Encode clock input to ADC. Internal

T/H is placed in hold mode (ADC is

encoding) on rising edge of encode

signal.
9 GND Ground
10 +V

S

+5 V Power Supply
11 GND Ground
12 A
13 –V
14 +V
15 –V

IN

S

S

S

Noninverting input to T/H amplifier.

–5.2 V Power Supply

+5 V Power Supply

–5.2 V Power Supply
16 GND Ground
17 COMP Should be connected to –V

through

S

0.1 µF capacitor.

18 D11 (MSB) Most significant bit of ADC output;

TTL compatible.
19–25 D10–D4 Digital output bits of ADC; TTL

compatible.
26 +V
27 –V

S

S

+5 V Power Supply

–5.2 V Power Supply
28 GND Ground

–4–

PIN DESIGNATIONS

D3

1
2

D2

3

D1

D0 (LSB)

ENCODE

4
5

NC

6

+V

S

AD9022

7

GND

GND

GND

NC = NO CONNECT
COMPENSATION (PIN 17) SHOULD BE
CONNECTED TO –V

+V

A

IN

–V
+V

8
9

10

S

11

12

13

S

14

S

TOP VIEW

(Not to Scale)

S

GND

28
27

–V

S

26

+V

S

25

D4

24

D5
D6

23
22

D7
D8

21

D9

20

D10

19

D11(MSB)

18

COMP

17

GND

16

–V

15

S

THROUGH 0.01mF

REV. B