Analog Devices AD8698 Service Manual

Dual Precision, Rail-to-Rail Output

FEATURES

Low offset voltage: 100 µV max
Low offset voltage drift: 2 µV/°C max
Low input bias current: 700 pA max
Low noise: 8 nV/√Hz
High common-mode rejection: 118 dB min
Wide operating temperature: −40°C to +85°C
No phase reversal

APPLICATIONS

Photodiode amplifier
Sensors and controls
Multipole filters
Integrator

GENERAL DESCRIPTION

The AD8698 is a high precision, rail-to-rail output, low noise,
low input bias current operational amplifier. Offset voltage is a
respectable 100 µV max and drift over temperature is below
2 µV/°C, eliminating the need for manual offset trimming. The
AD8698 is ideal for high impedance sensors, minimizing offset
errors due to input bias and offset currents.

OUT A

–IN A

+IN A

8-Lead SOIC

1

2

3

(Not to Scale)

V–

4

Operational Amplifier

CONNECTION DIAGRAMS

(R-8)

8

AD8698

TOP VIEW

7

6

5

V+

OUT B

–IN B

+IN B

OUT A

04807-0-069

Figure 1.

–IN A

+IN A

V–

1

2

3

(Not to Scale)

4

AD8698

8-Lead MSOP

(RM-8)

AD8698

TOP VIEW

8

7

6

5

V+

OUT B

–IN B

+IN B

04807-0-070

The rail-to-rail output maximizes dynamic range in a variety of
applications, such as photodiode amplifiers, DAC I/V
amplifiers, filters, and ADC input amplifiers.

The AD8698 dual amplifiers are offered in 8-lead MSOP and
narrow 8-lead SOIC packages. The MSOP version is available
in tape and reel only.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD8698

TABLE OF CONTENTS

Specifications .................................................................................... 3

Instrumentation Amplifier ....................................................... 15

Absolute Maximum Ratings ........................................................... 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Typical Performance Characteristics............................................. 6

Applications .................................................................................... 14

Input Overvoltage Protection................................................... 14

Driving Capacitive Loads.......................................................... 14

REVISION HISTORY

4/04—Revision 0: Initial Version

Composite Amplifier ................................................................. 15

Low Noise Applications ............................................................ 16

Driving ADCs............................................................................. 16

Using the AD8698 in Active Filter Designs ........................... 16

Outline Dimensions....................................................................... 17

Ordering Guide .......................................................................... 17

Rev. 0 | Page 2 of 20

AD8698

SPECIFICATIONS

VS = ±15 V, VCM = 0 V (@TA = 25oC, unless otherwise noted.)

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS 20 100 µV

Offset Voltage Drift

∆V

OS

/∆T

−40°C < T

−40°C < T

< +85°C

A

< +85°C

A

Input Bias Current IB 700 pA

−40°C < T

< +85°C

A

Input Offset Current IOS 700 pA

Input Voltage Range IVR

−40°C < T

−40°C < T

< +85°C

A

< +85°C −13.5V

A

Common-Mode Rejection Ratio CMRR VCM = ±13.5 V 118 132 dB
Large Signal Voltage Gain AVO
Input Capacitance C
C

DIFF

4.6 pF

CM

R

= 2 kΩ, VO = ±13.5 V

L

6.5 pF

OUTPUT CHARACTERISTICS

Output Voltage Swing (Ref. to GND) VOH

V

OH

(Ref. to GND) VOL

VOL

I

= 1 mA, −40°C < TA < +85°C

L

= 5 mA, −40°C < TA < +85°C

I

L

= 1 mA, −40°C < TA < +85°C

I

L

I

= 5 mA, −40°C < TA < +85°C

L

POWER SUPPLY

Power Supply Rejection Ratio PSRR ±2.5 V < VS < ±15 V 114 132 dB
Supply Current ISY V

Supply Voltage VS

= 0 V 2.8 3.2 mA

O

−40°C < T

−40°C < T

< +85°C

A

< +85°C

A

DYNAMIC PERFORMANCE

Slew Rate SR

R

= 2 kΩ

L

Gain Bandwidth Product GBP 1 MHz

Phase Margin ØO 60 Degrees

NOISE PERFORMANCE

Input Noise Voltage en p-p 0.1 Hz < f < 10 Hz 0.6 µV p-p

Input Voltage Noise Density en f = 10 Hz 15

Input Voltage Noise Density en f = 1 kHz 8

Current Noise Density in f = 1 kHz 0.2

300 µV

0.6 2 µV/°C

1500 pA

1500 pA

13.5 V

900 1450 V/mV

14.85 14.93 V

14.6 14.8 V

−14.93 −14.6

−14.82 −14.5

V

V

3.8 mA
±2.5 ±15 V

0.4 V/µs

nV/√Hz
nV/√Hz
pA/√Hz

Rev. 0 | Page 3 of 20

AD8698

VS = ±2.5 V, VCM = 0 V (@TA = 25oC, unless otherwise noted.)

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS 20 100 µV

Offset Voltage Drift

Input Bias Current IB

∆V

OS

/∆T

−40°C < T

−40°C < T

−40°C < T

< +85°C

A

< +85°C

A

< +85°C

A

Input Offset Current IOS 700 pA

Input Voltage Range IVR

−40°C < T

−40°C < T

< +85°C

A

< +85°C −1.5

A

Common-Mode Rejection Ratio CMRR VCM = ±13.5 V 105 120 dB
Large Signal Voltage Gain AVO
Input Capacitance C
C

6.4 pF

DIFF

4.6 pF

CM

R

= 2 kΩ, VO = ±13.5 V

L

OUTPUT CHARACTERISTICS

Output Voltage Swing (Ref. to GND) VOH
V

OH

(Ref. to GND) VOL

VOL I

I

= 1 mA, −40°C < TA < +85°C

L

I

= 5 mA, −40°C < TA < +85°C

L

= 1 mA, −40°C < TA < +85°C

I

L

= 5 mA, TA = 25°C

L

I

= 5mA, −40°C<TA<+85°C

L

POWER SUPPLY

Power Supply Rejection Ratio PSRR ±2.5 V < VS < ±15 V 114 132 dB
Supply Current ISY V

Supply Voltage Vs

= 0 V 2.3 2.8 mA

O

−40°C < T

−40°C < T

< +85°C

A

< +85°C

A

DYNAMIC PERFORMANCE

Slew Rate SR

R

= 2 kΩ

L

Gain Bandwidth Product GBP 1 MHz

Phase Margin Øo 60 Degrees

NOISE PERFORMANCE

Input Noise Voltage en p-p 0.1 Hz < f < 10Hz 0.6 µV p-p

Input Voltage Noise Density en f = 10 Hz 15

Input Voltage Noise Density en f =1 kHz 8

Current Noise Density in f = 1 kHz 0.2

300 µV

2 µV/°C

700 pA
1500 pA

1500 pA

+1.5 V

600 1200 V/mV

2.35 2.44 V

2.1 2.29 V

−2.43 −2.2

−2.15 −1.9

−1.6

V

V

3.3 mA
±2.5 ±15 V

0.4 V/µs

nV/√Hz
nV/√Hz
pA/√Hz

Rev. 0 | Page 4 of 20

AD8698

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage ±15 V
Input Voltage ±VS
Differential Input Voltage ±VS
Output Short-Circuit Duration

to Gnd
Storage Temperature Range

R, RM Packages
Operating Temperature Range
Junction Temperature Range

R, RM Packages
Lead Temperature Range

(Soldering, 60 Sec)

Indefinite

−65°C to +150°C

−40°C to +85°C

−65°C to +150°C

+300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, i.e., θJA is specified

for devices soldered in circuit boards for surface-mount
packages.

Table 4. Thermal Resistance

Package Type

MSOP-8 (RM) 210 45 °C/W
SOIC-8 (R) 158 43 °C/W

θJC

θ

JA

Unit

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 1000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 5 of 20

AD8698

TYPICAL PERFORMANCE CHARACTERISTICS

NUMBER OF AMPLIFIERS

80

70

60

50

40

30

20

10

VS = ±15V

100

80

60

40

20

GAIN (dB)

0

–20

VS = ±15V

225

180

135

90

45

0

–45

PHASE MARGIN (Degrees)

0

0 0.2 0.4 0.6 0.8 1.0 1.2

TCV

(µV/°C)

OS

Figure 2. Input Offset Voltage Drift Distribution

80

70

60

50

40

30

20

NUMBER OF AMPLIFIERS

10

0

–100 –80 –60 –40 –20 0 40 8020 60 100

V

(µV)

OS

Figure 3. Offset Voltage Distribution

70

60

50

VS = ±15V

VS = ±15V

04807-0-034

04807-0-058

–40

10k 1M100k 10M

FREQUENCY (Hz)

Figure 5. Open-Loop Gain and Phase vs. Frequency

50

40

AV = 100

30

20

AV= 10

10

0

CLOSED-LOOP GAIN (dB)

–10

–20

AV= 1

10k1k 100k 1M 10M

FREQUENCY (Hz)

Figure 6. Closed-Loop Gain vs. Frequency

60

)

45

Ω

VS = ±15V

VS = ±15V

–90

04807-0-001

04807-0-009

40

30

20

NUMBER OF AMPLIFIERS

10

0

–400 –320 –240 –160 –80 0 160 32080 240 400

(pA)

I

B

Figure 4. Input Bias Distribution

04807-0-060

Rev. 0 | Page 6 of 20

30

OUTPUT IMPEDANCE (

15

0

10 100 1k 10k 100k 1M

AV = 100

FREQUENCY (Hz)

AV= 10

AV= 1

Figure 7. Output Impedance vs. Frequency

04807-0-007

AD8698

VS = ±15V

= 4V p-p

V

IN

= 1nF

C

L

VOLTAGE (1V/DIV)

–200

0

V

IN

15

V

OUT

VOLTAGE (V) VOLTAGE (mV)

TIME (100

µ

s/DIV)

04807-0-037

Figure 8. Large Signal Transient Response

VS = ±15V

= 200mV p-p

V

IN

C

= 1nF

L

VOLTAGE (100mV/DIV)

VOLTAGE (V) VOLTAGE (mV)

TIME (100

µ

s/DIV)

04807-0-044

Figure 9. Small Signal Transient Response

50

VS = ±15V

= 200mV

V

IN

= 1

A

V

200

–15

120

100

0

0

0

VS = ±15V
V

= 200mV p-p

IN

A

= –100

V

TIME (10µs/DIV)

Figure 11. Positive Overvoltage Recovery

V

IN

V

OUT

TIME (400µs/DIV)

Figure 12. Negative Overvoltage Recovery

VS = ±15V
V

= 200mV

IN

A

= –100

V

VS = ±15V

04807-0-041

04807-0-040

30

20

OVERSHOOT (%)

10

0

1000 15000 500 2000 2500 3000

CAPACITIVE LOAD (pF)

04807-0-013

Figure 10. Overshoot vs. Load Capacitance

80

60

CMRR (dB)

40

20

0

10k1k 100k 1M 10M

FREQUENCY (Hz)

Figure 13. CMRR vs. Frequen cy

04807-0-003

Rev. 0 | Page 7 of 20

AD8698

100

80

VS = ±15V

100

VS = ±15V

60

40

20

0

10 100 1k 10k 100k 1M

–PSRR

FREQUENCY (Hz)

+PSRR

Figure 14. PSRR v s. Frequency

VS = ±15V

VOLTAGE (200nV/DIV)

04807-0-005

10

1

CURRENT NOISE DENSITY (nV/√Hz)

0.1

20

10

0

–10

–20

SHORT-CIRCUIT CURRENT (mA)

–30

10.1 10 100 1k

FREQUENCY (Hz)

Figure 17. Current Noise Density vs. Frequency

–I

SC

+I

SC

VS = ±15V

04807-0-033

VOLTAGE NOISE DENSITY (nV/√Hz)

100

TIME (1s/DIV)

Figure 15. Input Voltage Noise

10

1

10.1 10 100 1k

FREQUENCY (Hz)

Figure 16. Voltage Noise Density vs. Frequency

VS = ±15V

04807-0-035

04807-0-032

14.96

14.95

14.94

14.93

14.92

14.91

14.90

OUTPUT SWING (V)

14.89

14.88

14.87

–40

200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

Figure 18. Short-Circuit Current vs. Temperature

200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

Figure 19. Output Swing vs. Temperature

VS = ±15V
I

= 1mA

L

–V

OL

04807-0-030

V

OH

04807-0-019

Rev. 0 | Page 8 of 20

AD8698

14.90

14.85

VS = ±15V
I

= 5mA

L

140

VS = ±15V

138

14.80

14.75

14.70

OUTPUT VOLTAGE SWING (V)

14.65

14.60

∆ OFFSET VOLTAGE (µV)

200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

Figure 20. Output Voltage Swing vs. Temperature

30

20

10

0

–10

–20

V

OH

–V

OL

VS = ±15V

04807-0-020

136

PSRR (dB)

134

132

130

100

50

–50

∆ INPUT BIAS CURRENT (pA)

200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

04807-0-029

Figure 23. PSRR vs. Temperature

VS = ±15V

0

–30

155

150

145

140

135

CMRR (dB)

130

125

120

200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

Figure 21. ∆ Offset Voltage vs. Temperature

VS = ±15V

200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

Figure 22. CMRR vs. Temperature

04807-0-023

04807-0-027

–100

6

5

4

3

OUTPUT SWING (V)

2

∆

1

0

Figure 25. ∆

200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

04807-0-025

Figure 24. ∆ Input Bias Current vs. Temperature

VS = ±15V

V

OL

V

OH

50101520

LOAD CURRENT (mA)

Output Voltage Swing from Rails vs. Load Current

04807-0-015

Rev. 0 | Page 9 of 20

AD8698

3.5

VS = ±15V

3.0

100

VS = ±2.5V

80

60

225

180

135

2.5

SUPPLY CURRENT (mA)

2.0

1.5

0

–20

–40

–60

–80

–100

CHANNEL SEPARATION (dB)

–120

–140

200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

Figure 26. Supply Current vs. Temperature

VS = ±15V

10k1k 100k 1M 10M

FREQUENCY (Hz)

Figure 27. Channel Separation

04807-0-017

04807-0-010

40

20

GAIN (dB)

0

–20

–40

10k 1M100k 10M

FREQUENCY (Hz)

Figure 29. Open-Loop Gain and Phase vs. Frequency

60

)

45

Ω

30

AV= 100

OUTPUT IMPEDANCE (

15

0

10 100 1k 10k 100k 1M

FREQUENCY (Hz)

AV= 10

AV= 1

Figure 30. Output Impedance vs. Frequency

VS = ±2.5V

90

45

0

–45

–90

PHASE MARGIN (Degrees)

04807-0-002

04807-0-008

70

60

50

40

30

20

NUMBER OF AMPLIFIERS

10

0

–100 –80 –60 –40 –20 0 40 8020 60 100

(µV)

V

OS

Figure 28. Offset Voltage Distribution

VS = ±2.5V

04807-0-059

Rev. 0 | Page 10 of 20

VS = ±2.5V
V

= 2V p-p

IN

C

= 1nF

L

0

VOLTAGE (500mV/DIV)

TIME (100

µ

s/DIV)

04807-0-038

Figure 31. Large Signal Transient Response

AD8698

VOLTAGE (100mV/DIV)

50

40

30

20

OVERSHOOT (%)

VS = ±2.5V
V

= 200mV p-p

IN

C

= 1nF

L

TIME (100

µ

s/DIV)

Figure 32. Small Signal Transient Response

VS = ±2.5V

= 200mV

V

IN

= 1

A

V

04807-0-045

200

0

0

–2.5

VOLTAGE (V) VOLTAGE (mV)

120

100

80

60

CMRR (dB)

40

V

IN

V

OUT

TIME (4

µ

s/DIV)

Figure 35. Negative Overvoltage Recovery

VS = ±2.5V
V

= 200mV p-p

IN

A

= –100

V

VS = ±2.5V

04807-0-042

10

0

0

–200

2.5

0

VOLTAGE (V) VOLTAGE (mV)

VS = ±2.5V
V
A

1000 15000 500 2000 2500 3000

CAPACITIVE LOAD (pF)

Figure 33. Overshoot vs. Load Capacitance

V

IN

V

OUT

= 200mV p-p

IN

= –100

V

µ

s/DIV)

TIME (4

Figure 34. Positive Overvoltage Recovery

04807-0-014

04807-0-043

20

0

10k1k 100k 1M 10M

FREQUENCY (Hz)

Figure 36. CMRR vs. Frequen cy

100

80

60

PSRR (dB)

40

20

0

10 100 1k 10k 100k 1M

–PSRR

FREQUENCY (Hz)

+PSRR

Figure 37. PSRR v s. Frequency

VS = ±2.5V

04807-0-004

04807-0-006

Rev. 0 | Page 11 of 20

AD8698

20

10

0

–10

–20

SHORT-CIRCUIT CURRENT (mA)

V)

µ

OFFSET VOLTAGE (

∆

30

VS = ±2.5V

20

10

0

–10

–20

–I

SC

+I

SC

VS = ±2.5V

–30

Figure 38. Short-Circuit Current vs. Temperature

2.46

2.45

2.44

2.43

2.42

2.41

OUTPUT VOLTAGE (V)

2.40

2.39

2.38

Figure 39. Output Swing vs. Temperature

2.5

2.3

2.1

1.9

OUTPUT VOLTAGE SWING (V)

1.7

200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

–V

OL

VS = ±2.5V
I

= 1mA

L

–V

OL

VS = ±2.5V
I

= 5mA

L

04807-0-031

–30

200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

04807-0-024

Figure 41. ∆ Offset Voltage vs. Temperature

134

VS = ±2.5V

132

V

OH

04807-0-021

130

CMRR (dB)

128

126

124

200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

04807-0-028

Figure 42. CMRR vs. Temperature

–20

VS = ±2.5V

–30

V

OH

–40

–50

–60

INPUT OFFSET CURRENT (pA)

∆

–70

1.5
200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

Figure 40. Output Voltage Swing vs. Temperature

04807-0-022

Rev. 0 | Page 12 of 20

–80

200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

Figure 43. ∆ Input Bias Current vs. Temperature

04807-0-026

AD8698

2500

VS = ±2.5V

2000

3.0

2.5

1500

1000

OUTPUT SWING (mV)

∆

500

0

3.0

2.5

2.0

1.5

1.0

SUPPLY CURRENT (mA)

0.5

Figure 44. ∆

VS = ±2.5V

V

OL

V

OH

50101520

LOAD CURRENT (mA)

Output Voltage Swing from Rails vs. Load Current

04807-0-016

2.0

1.5

1.0

SUPPLY CURRENT (mA)

0.5

0

0 5 10 15 20 25 30 35

SUPPLY VOLTAGE (V)

Figure 47. Supply Current vs. Supply Voltage

0

–20

–40

–60

–80

–100

CHANNEL SEPARATION (dB)

–120

VS = ±2.5V

04807-0-012

0

200–40 –20–60 40 60 80 100

TEMPERATURE (°C)

Figure 45. Supply Current vs. Temperature

VS = ±5V
V

= 11.4V p-p

IN

04807-0-018

–140

10k1k 100k 1M 10M

FREQUENCY (Hz)

04807-0-011

Figure 48. Channel Separation

VOLTAGE (2V/DIV)

TIME (400

µ

s/DIV)

04807-0-039

Figure 46. No Phase Reversal

Rev. 0 | Page 13 of 20

AD8698

APPLICATIONS

INPUT OVERVOLTAGE PROTECTION

The AD8698 has internal protective circuitry which allows
voltages at either input to exceed the supply voltage. However,
if voltages applied at either input exceed the supply voltage by
more than 2 V, it is recommended to use a resistor in series
with the inputs to limit the input current and prevent damaging
the device.

The value of the resistor can be calculated from the following
formula:

−

VV

IN

S

500

+

R

S

DRIVING CAPACITIVE LOADS

The AD8698 is stable even when driving heavy capacitive
loads in any configuration. Although the AD8698 will safely
drive capacitive loads well over 10 nF, it is recommended to
use external compensation should the amplifier be subjected
to driving a load exceeding 50 nF. This is particularly
important in positive unity gain configurations, the worst
case for stability.
with a 68 nF load in response to a 400 mV signal at its
positive input; the overshoot is less than 25% without any
external compensation. Using a simple “snubber” network
reduces the overshoot to less than 10% as shown in

Figure 50.

VS = ±15V

= 68nF

C

L

A

= 1

V

VOLTAGE (100mV/DIV)

mA5

≤

Figure 49 shows the output of the AD8698

VS = ±15V

= 68nF

C

L

R

= 30Ω

S

C

= 5nF

S

= 1

A

V

VOLTAGE (100mV/DIV)

TIME (10µs/DIV)

Figure 50. Compensated Capacitive Load Drive with Snubber

The snubber network consists of a simple RC network
whose values are determined empirically.

V–

+

–

V+

400mV

R

S

C

S

C

L

04807-0-063

Figure 51. Snubber Network

Table 5 provides a few starting values for optimum

compensation.

Table 5. Compensation Values

CL (nF)

R

(Ω)

S

C

(nF)

S

47 20 7
68 30 5
100 50 3

The use of the snubber network does not recover the loss of
bandwidth incurred by the load capacitance. The AD8698
maintains a unity gain bandwidth of 1 MHz with load
capacitances of up to 1 nF.

04807-0-061

TIME (10µs/DIV)

Figure 49. Heavy Capacitive Load Drive without Compensation

04807-0-057.

Rev. 0 | Page 14 of 20

AD8698

V2V

V

10M

1M

100k

10k

UNITY GAIN BANDWIDTH (MHz)

1k

1 10 100

LOAD CAPACITANCE (nF)

Figure 52. Unity Gain Bandwidth vs. Load Capacitance

Figure 52 shows the unity gain bandwidth as a function of load
capacitance.

INSTRUMENTATION AMPLIFIER

Instrumentation amplifiers are used in applications requiring
precision, accuracy, and high CMRR. One popular application
is signal conditioning in process control, test automation, and
measurement instrumentation, where the amplifier is used to
amplify small signals.

The triple op amp implementation uses the AD8698 at the
front end with the OP184 for optimum accuracy.

The circuit in Figure 53
performance, high CMRR, as well as the benefit of an output
that swings to the supplies.

The CMRR of the in-amp will be limited by the choice of
resistor tolerance. R5 is an optional potentiometer that can be
used to calibrate the circuit for maximum gain. R7 can be
trimmed for optimum CMRR.

The output voltage is given by:

⎛

+=

VV

1

⎜

IN

O

⎝

enjoys a high overall gain, excellent dc

2R

3R

2

⎞

⎛

⎞

⎟

⎜

⎟

1R

4R

⎠

⎝

⎠

04807-0-062

1

V+

V–

1/2 AD8698

V–

V+

1/2 AD8698

Figure 53. Three Op Amp In-Amp

COMPOSITE AMPLIFIER

The dc accuracy of the AD8698 and the ac performance of the
OP184 are combined in the circuit shown in Figure 54. The
composite amplifier provides a higher bandwidth, a lower offset
voltage, and a higher loop, thereby reducing the gain error
substantially.

The circuit shown exhibits a total output rms noise of less than
500 µV, corresponding to less than 3 mV of peak-to-peak noise
over approximately a 3 MHz bandwidth. Cf is used to minimize
peaking.

The circuit has an inverting gain of 10. In applications with
higher closed-loop gains, Cf is necessary to maintain a
sufficient phase margin and ensure stability. This results in a
narrower closed-loop bandwidth.

10kΩ

R1

1kΩ

IN

V–

V+

1/2 AD8698

Figure 54. Composite Amplifier Circuit

R1

1kΩ

R3
9kΩ

R4
2kΩ

R5
10kΩ

R3
9kΩ

R1

9.8kΩ

R2

Cf

20pF

V–

V+

OP184

R2

10kΩ

V+

V–

04807-0-065

OP184

R7

400Ω

04807-0-064

Rev. 0 | Page 15 of 20

AD8698

V

LOW NOISE APPLICATIONS

In some applications, it is critical to minimize the noise, and
although the AD8698 has a low noise of typically 8 nV/
1 kHz, paralleling the two amplifiers within the same package
reduces the total noise referred to the input to approximately

5.5 nV/

√Hz. This simple technique is depicted in Figure 55.

V

IN

R1

1kΩ

V+

V–

10kΩ

R3

100Ω

R2

√Hz at

V

OUT

If a higher gain is desired, the corner frequency should be
chosen accordingly. For example, if the amplifier is configured
with a gain of 10, the corner frequency of the filter should not
be more than 10 kHz.

An example of an active filter is the Sallen Key. This topology
gives the user the flexibility of implementing a low-pass or a
high-pass filter by simply interchanging the resistors and the
capacitors.

In the high-pass filter of Figure 56, the damping factor Q is set

√2 for a maximally flat response (Butterworth).

to 1/

The gain is unity and the bandwidth is 10 kHz with the values
shown.

V–

R3

1kΩ

V+

10kΩ

R4

R5

100Ω

04807-0-066

Figure 55. Paralleling Amplifiers

DRIVING ADCs

The AD8698 can drive extremely heavy capacitive loads
without any compensation. Sometimes capacitors are placed at
the output of the amplifier to absorb transient currents while
the op amp is interfaced with the ADC. Most op amps need a
small resistor with the output to isolate the load capacitance.

This results in a loss of bandwidth and slows the amplifier
down substantially. However, the AD8698 maintains a unity
gain bandwidth of 1 MHz with loads of up to 1 nF, as shown in
Figure 52.

USING THE AD8698 IN ACTIVE FILTER DESIGNS

The AD8698 is recommended for unity gain filter designs with
a corner frequency of up to 100 kHz, one tenth of the op amp’s
unity gain bandwidth.

C1

1nF

V

IN

C2

1nF

R2

22kΩ

R1

11kΩ

V+

V–

04807-0-067

Figure 56. Two Pole High-Pass Filter

R1

11kΩ

IN

R2

11kΩ

C2

1nF

C1

2nF

V+

V–

04807-0-068

Figure 57. Two Pole Low-Pass Filter

The circuit of Figure 57 has a bandwidth of 10 kHz and a
maximally flat response. In this case, the damping factor is
controlled by the ratio of the capacitors and the gain is unity.

Rev. 0 | Page 16 of 20

AD8698

Y

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

85

6.20 (0.2440)

5.80 (0.2284)

41

1.27 (0.0500)
BSC

0.25 (0.0098)

0.10 (0.0040)

COPLANARIT

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

× 45°

Figure 58. 8-Lead Small Outline IC [SOIC] (R-8)—Dimensions shown in millimeters

3.00

BSC

85

3.00

BSC

PIN 1

0.65 BSC

0.15

0.00

0.38

0.22

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187AA

4

SEATING
PLANE

4.90

BSC

1.10 MAX

0.23

0.08

8°
0°

0.80

0.60

0.40

Figure 59. 8-Lead Small Outline IC [SOIC] (RM-8)—Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Package Package Description Package Option Branding

AD8698ARM-R2 –40°C to +85°C MSOP RM-8 A02
AD8698ARM-REEL –40°C to +85°C MSOP RM-8 A02
AD8698AR –40°C to +85°C SOIC R-8
AD8698AR-REEL –40°C to +85°C SOIC R-8
AD8698AR-REEL7 –40°C to +85°C SOIC R-8

Rev. 0 | Page 17 of 20

AD8698

NOTES

Rev. 0 | Page 18 of 20

AD8698

NOTES

Rev. 0 | Page 19 of 20

AD8698

NOTES

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04807-0-4/04(0)

Rev. 0 | Page 20 of 20