Low supply current: 250 μA/amp maximum
High slew rate: 9 V/μs
Bandwidth: 3.5 MHz typical
Low offset voltage: 1 mV maximum @ 25°C
Low input bias current: 20 pA maximum @ 25°C
CMRR: 90 dB typical
Fast settling time
Unity gain stable
APPLICATIONS
Portable telecommunications
Low power industrial and instrumentation
Loop filters
Active and precision filters
Integrators
Strain gauge amplifiers
Portable medical instrumentation
Supply current monitoring
JFET Operational Amplifiers
AD8682/AD8684
PIN CONFIGURATIONS
OUT A
1
V–
AD8682
2
TOP VIEW
3
(Not to Scale)
4
–IN A
+IN A
Figure 1. 8-Lead SOIC_N and 8-Lead MSOP
OUT A
1
2
–IN A
+IN A
3
V+
4
AD8684
5
+IN B
6
–IN B
OUT B
7
TOP VIEW
(Not to Scale)
Figure 2. 14-Lead SOIC_N and 14-Lead TSSOP
8
7
6
5
14
13
12
11
10
9
8
V+
OUT B
–IN B
+IN B
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
6278-001
06278-002
GENERAL DESCRIPTION
The AD8682 and AD8684 are dual and quad low power, precision
(1 mV) JFET amplifiers featuring excellent speed at low supply
currents. The slew rate is typically 9 V/μs with a supply current
under 250 μA per amplifier. These unity-gain stable amplifiers
have a typical gain bandwidth of 3.5 MHz. The JFET input stage
ensures bias current is typically a few picoamps and below 125 pA
maximum over the full temperature operating range.
The devices are ideal for portable, low power applications,
especially with high source impedance. The devices are unity gain
stable and can drive higher capacity loads (G = 1, noninverting),
as an example of their excellent dynamic response over a wide
range of conditions, delivering dc precision performance at low
quiescent currents.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
VS = ±15.0 V, TA = 25°C, VCM = 0 V, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 0.35 1 mV
AD8682 +25°C ≤ TA ≤ +85°C 2.5 mV
−40°C ≤ TA ≤ +25°C 3 mV
AD8684 +25°C ≤ TA ≤ +85°C 3.5 mV
−40°C ≤ TA ≤ +25°C 4 mV
Input Bias Current IB 6 20 pA
−40°C ≤ TA ≤ +85°C 125 pA
Input Offset Current IOS 20 pA
−40°C ≤ TA ≤ +85°C 100 pA
Input Voltage Range −11 +15 V
Common-Mode Rejection Ratio CMRR −11 V ≤ VCM ≤ +15 V, −40°C ≤ TA ≤ +85°C 70 90 dB
Large Signal Voltage Gain AVO R
R
Offset Voltage Drift ΔVOS/ΔT 10 μV/°C
Bias Current Drift ΔIB/ΔT 8 pA/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH R
Output Voltage Low VOL R
Short-Circuit Limit ISC Source 3 10 mA
Sink −12 −8 mA
Open-Loop Output Impedance Z
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V, −40°C ≤ TA ≤ +85°C 92 114 dB
Supply Current/Amplifier ISY V
Supply Voltage Range VS ±4.5 ±18 V
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ 7 9 V/μs
Full-Power Bandwidth BWP 1% distortion 125 kHz
Settling Time tS To 0.01% 1.6 μs
Gain Bandwidth Product GBP 3.5 MHz
Phase Margin ØM 55 Degrees
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 1.3 μV p-p
Voltage Noise Density en f = 1 kHz 36 nV/√Hz
Current Noise Density in 0.01 pA/√Hz
f = 1 MHz 200 Ω
OUT
= 10 kΩ 20 V/mV
L
= 10 kΩ, −40°C ≤ TA ≤ +85°C 15 V/mV
L
= 10 kΩ +13.5 +13.9 V
L
= 10 kΩ −13.9 −13.5 V
L
= 0 V, −40°C ≤ TA ≤ +85°C 210 250 μA
O
Rev. A | Page 3 of 16
AD8682/AD8684
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage ±18 V
Input Voltage ±18 V
Differential Input Voltage1 36 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
1
For supply voltages less than ±18 V, the absolute maximum input voltage is
equal to the supply voltage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Figure 3. AD8682 Open-Loop Gain and Phase vs. Frequency
= 25°C
A
180
135
90
45
0
–45
–90
PHASE (Degree)
70
60
50
A
= 100
VCL
40
30
A
= 10
VCL
20
10
A
= 1
VCL
0
CLOSED-LOOP GAIN (dB)
–10
–20
–30
06278-003
1k
10k1M10M100k
FREQUENCY ( Hz)
VS = ±15V
= 25°C
T
A
Figure 6. AD8682 Closed-Loop Gain vs. Frequency
06278-006
45
VS = ±15V
40
= 10kΩ
R
L
35
30
25
20
15
OPEN-LOOP GAIN (V/mV)
10
5
0
–75
–2510012525
TEMPERATURE (°C)
Figure 4. AD8682 Open-Loop Gain vs. Temperature
80
VS = ±15V
= 2kΩ
R
L
70
= 100mV p-p
V
IN
A
= 1
VCL
T
= 25°C
60
A
50
40
30
OVERSHOOT (%)
20
10
+OS
–OS
30
25
20
TE (V/µs)
15
10
SLEW
5
75500–50
06278-004
0
–75
–2510012525
TEMPERATURE (°C)
–SR
+SR
75500–50
VS = ±15V
= 10kΩ
R
L
= 50pF
C
L
06278-007
Figure 7. Slew Rate vs. Temperature
1000
VS = ±15V
= 0V
V
CM
100
10
1
INPUT BIAS CURRENT (pA)
0
0
200400500
LOAD CAPACITANCE (pF)
300100
Figure 5. Small Signal Overshoot vs. Load Capacitance
06278-005
0.1
–75
Figure 8. AD8682 Input Bias Current vs. Temperature
Rev. A | Page 5 of 16
–2510012525
TEMPERATURE (°C)
75500–50
06278-008
AD8682/AD8684
√
www.BDTIC.com/ADI
1000
Hz)
100
VS = ±15V
T
= 25°C
A
20
15
10
5
0
TA = 25°C
R
= 10kΩ
L
V
OH
10
VOLTAGE NOISE DENSITY (nV/
1
10
10010k1k
FREQUENCY (Hz)
Figure 9. Voltage Noise Density vs. Frequency
1000
VS = ±15V
T
= 25°C
A
100
10
1
INPUT BIAS CURRENT (pA)
0.1
–15
COMMON-MO DE VOLTAGE (V)
50–10
Figure 10. Input Bias Current vs. Common-Mode Voltage
–5
–10
OUTPUT VOLTAGE SWING (V)
–15
–20
0
06278-009
SUPPLY VOLTAGE (V)
V
OL
±15±5
±20±10
06278-012
Figure 12. Output Voltage Swing vs. Supply Voltage
1000
VS = ±15V
= 25°C
T
A
100
A
= 100
VCL
10
A
= 10
VCL
1
OUTPUT IMPEDANCE (Ω)
A
= 1
VCL
1015–5
06278-010
0.1
1k
10k1M100100k
FREQUENCY (Hz)
06278-013
Figure 13. Closed-Loop Output Impedance vs. Frequency
480
TA = 25°C
475
470
465
460
SUPPLY CURRENT (µA)
455
450
0
SUPPLY VOLTAGE (V)
Figure 11. AD8682 Supply Current vs. Supply Voltage
480
475
470
465
460
SUPPLY CURRENT (µA)
455
450
–50
±15±5
±20±10
06278-011
–2550100
TEMPERATURE (°C)
750
12525
06278-014
Figure 14. AD8682 Supply Current vs. Temperature
Rev. A | Page 6 of 16
AD8682/AD8684
www.BDTIC.com/ADI
16
VS = ±15V
= 25°C
T
A
14
12
10
8
6
4
ABSOLUTE OUT PUT VOLTAGE (V)
2
0
LOAD RESISTANCE (Ω)
V
OL
V
OH
1k10k100
Figure 15. Absolute Output Voltage vs. Load Resistance
140
VS = ±15V
T
= 25°C
A
120
100
80
60
40
PSRR (dB)
20
0
–20
–40
–60
1k
10k1M100100k
FREQUENCY (Hz)
+PSRR
–PSRR
Figure 16. AD8682 PSRR vs. Frequency
06278-015
06278-016
30
25
20
15
10
5
MAXIMUM OUTPUT SWING (V p -p)
0
100
1k100k1M10k
FREQUENCY (Hz)
Figure 18. Maximum Output Swing vs. Frequency
140
120
100
80
60
40
20
CMRR (dB)
0
–20
–40
–60
1k
10k1M100100k
FREQUENCY (Hz)
Figure 19. AD8682 CMRR vs. Frequency
VS = ±15V
T
= 25°C
A
R
= 10kΩ
L
A
= 1
VCL
VS = ±15V
= 25°C
T
A
06278-018
06278-019
14
12
10
8
6
4
SHORT-CIRCUIT CURRENT (mA)
2
0
–50
–2550100
TEMPERATURE (°C)
SINK
SOURCE
750
Figure 17. AD8682 Short-Circuit Current vs. Temperature
VS = ±15V
T
= 25°C
A
12525
06278-017
Rev. A | Page 7 of 16
20
18
16
14
12
10
UNITS
8
6
4
2
0
–1.0 –0.8 –0. 6 –0.4 –0.200.2 0.4 0.6 0.81.0
V
(µV)
OS
VS= ±15V
= 25°C
T
A
100 × AD8682
(200 OP AMPS)
Figure 20. AD8682 VOS Distribution
06278-020
AD8682/AD8684
www.BDTIC.com/ADI
400
360
320
280
240
200
UNITS
160
120
80
40
0
0
4128
20
16
TCVOS (µV/°C)
Figure 21. AD8682 TCVOS Distribution SOIC_N Package
VS = ±15V
300 × AD8682
(600 OP AMPS)
28323624
06278-021
1000
100
10
INPUT BIAS CURRENT (pA)
1
0.1
–50–250255075100125
–75
TEMPERATURE (°C)
Figure 24. AD8684 Input Bias Current vs. Temperature
06278-024
50
45
40
35
30
25
20
15
OPEN-LOOP GAIN (V/mV)
10
5
0
–50–250255075100125
TEMPERATURE (°C)
Figure 22. AD8684 Open-Loop Gain vs. Temperature
60
50
A
= 100
VCL
40
30
A
= 10
VCL
20
10
A
= 1
VCL
CLOSED-LOOP GAIN (dB)
0
VS = ±15V
= 25°C
T
A
950
945
940
935
930
925
SUPPLY CURRENT (µA)
920
915
910
0102030
06278-022
SUPPLY VOLTAGE (V)
40
06278-025
Figure 25. AD8684 Relative Supply Current vs. Supply Voltage
950
945
940
935
930
925
SUPPLY CURRENT (µA)
920
–10
–20
1k10k100k1M100M10M
FREQUENCY (Hz)
Figure 23. AD8684 Closed-Loop Gain vs. Frequency
06278-023
915
910
–50–250255075100125
Figure 26. AD8684 Supply Current vs. Temperature
Rev. A | Page 8 of 16
TEMPERATURE (°C)
06278-026
AD8682/AD8684
www.BDTIC.com/ADI
140
120
100
80
60
PSRR (dB)
40
20
PSRR–
VS = ±15V
PSRR+
40
35
30
25
20
UNITS
15
10
5
VS = ±15V
T
= 25°C
A
100 × AD8684
(400 OP AMPS)
0
1k10k100k1M10M
FREQUENCY (Hz)
Figure 27. AD8684 PSRR vs. Frequency
14
12
10
8
6
4
SHORT-CIRCUIT CURRENT (mA)
2
0
–50–250255075100
SINK
SOURCE
TEMPERATURE (°C)
Figure 28. AD8684 Shor t-Circuit Current vs. Temperature
140
120
100
VS = ±15V
125
0
–1.0 –0.8 –0.61.0
06278-027
–0.4 –0. 200.2 0. 4 0.6 0.8
(µV)
V
OS
06278-030
Figure 30. AD8684 VOS Distribution Package
800
700
600
500
400
UNITS
300
200
100
0
06278-028
Figure 31. AD8684 TCV
24605652484440363228201612840
TCVOS (µV/°C)
Distribution Package
OS
VS = ±15V
300 × AD8684
(1200 OP AMPS)
06278-031
80
60
CMRR (dB)
40
20
0
1k10k100k1M10M
FREQUENCY (Hz)
06278-029
Figure 29. AD8684 CMRR vs. Frequency
Rev. A | Page 9 of 16
AD8682/AD8684
Ω
www.BDTIC.com/ADI
APPLICATIONS INFORMATION
The AD8682 and AD8684 are dual and quad JFET op amps that
are optimized for high speed at low power. This combination
makes these amplifiers excellent choices for battery-powered or
low power applications that require above average performance.
Applications benefiting from this performance combination
include telecommunications, geophysical exploration, portable
medical equipment, and navigational instrumentation.
HIGH-SIDE SIGNAL CONDITIONING
There are many applications requiring the sensing of signals near
the positive rail. The AD8682 and the AD8684 were tested and
are guaranteed over a common-mode range (−11 V ≤ V
+15 V) that includes the positive supply.
The AD8682/AD8684 are commonly used in the sensing of
power supply currents and in current sensing applications, such
as the partial circuit shown in Figure 32. In this circuit, the voltage
drop across a low value resistor, such as the 0.1 Ω shown here, is
amplified and compared to 7.5 V. The output can then be used
for current limiting.
15V
100kΩ
500kΩ
0.1
100kΩ
Figure 32. High-Side Signal Conditioning
500kΩ
1/2
AD8682
≤
CM
R
L
06278-042
PHASE INVERSION
Most JFET input amplifiers invert the phase of the input signal
if either input exceeds the input common-mode range. For the
AD8682/AD8684, negative signals in excess of approximately
14 V cause phase inversion. This is caused by saturation of the
input stage leading to the forward-biasing of a drain-gate diode.
A simple fix for this in noninverting applications is to place
a resistor in series with the noninverting input. This limits the
amount of current through the forward-biased diode and prevents
shutting down of the output stage. For the AD8682/AD8684,
a value of 200 kΩ has been found to work; however, it adds
a significant amount of noise.
15
10
5
0
OUT
V
–5
–10
–15
V
IN
Figure 33. AD8682 Phase Reversal
151050–5–10–15
06278-043
ACTIVE FILTERS
The wide bandwidth and high slew rates of the AD8682/AD8684
make either one an excellent choice for many filter applications.
There are many active filter configurations, but the four most
popular configurations are: Butterworth, elliptical, Bessel, and
Chebyshev. Each type has a response that is optimized for a
given characteristic, as shown in Tab l e 4 .
Table 4.
Type Selectivity Overshoot Phase Amplitude (Pass Band) Amplitude (Stop Band)
Butterworth Moderate Good Maximum flat
Chebyshev Good Moderate Nonlinear Equal ripple
Elliptical Best Poor Equal ripple
Bessel (Thompson) Poor Best Linear
Rev. A | Page 10 of 16
Equal ripple
AD8682/AD8684
V
www.BDTIC.com/ADI
PROGRAMMABLE STATE VARIABLE FILTER
The circuit shown in Figure 34 can be used to accurately program
the Q factor; the cutoff frequency, f
; and the gain of a 2-pole
C
state variable filter. The AD8684 has been used in this design
because of its high bandwidth, low power, and low noise. This
circuit takes only three packages to build because of the quad
configuration of the op amps and DACs.
The DACs shown are used in voltage mode; therefore, many
values are dependent on the accuracy of the DAC only and not
on the absolute values of the DAC resistive ladders. As a result, this
makes the circuit unusually accurate for a programmable filter.
Adjusting DAC 1 changes the signal amplitude across R1; therefore,
the DAC attenuation × R1 determines the amount of signal current
that charges the integrating capacitor, C1.
This cutoff frequency can be expressed as
1D1
=
f
C
R1C1
⎞
⎛
⎟
⎜
2562π
⎠
⎝
where D1 is the digital code for the DAC.
DAC3 is used to set the gain. The gain equation is
Gain
R4
=
R5
⎛
⎜
⎝
256
⎞
⎟
⎠
D3
DAC 2 is used to set the Q of the circuit. Adjusting this DAC
controls the amount of feedback from the band-pass node to
the input summing node. Note that the digital value of the
DAC is in the numerator; therefore, zero code is not a valid
operating point.
IN
DAC 3
1/4
DAC8408
1/4
AD8684
R5
2kΩ
2kΩ
R2Q256
=
R4
2kΩ
C1
R1
2kΩ
1/4
AD8684
DAC 2
1/4
DAC8408
1000pF
HIGH PASS
R3
2kΩ
1/4
AD8684
DAC 1
1/4
DAC8408
R2
2kΩ
1/4
AD8684
1/4
AD8684
1/4
AD8684
R6
⎛
⎜
⎝
D2R3
R7
2kΩ
DAC8408
⎞
⎟
⎠
DAC 4
1/4
BAND PASS
1/4
AD8684
R1
2kΩ
C1
1000pF
1/4
AD8684
LOW
PASS
Figure 34. Programmable State Variable Filter
Rev. A | Page 11 of 16
06278-044
AD8682/AD8684
www.BDTIC.com/ADI
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
CONTROLL ING DIMENSI ONS ARE IN MILLIME TERS; INCH DIM ENSIONS
(IN PARENTHESES) ARE ROUNDED-OF F MILLIMETER E QUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESI GN.
85
1
1.27 (0.0500)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-A A
BSC
6.20 (0.2440)
5.80 (0.2284)
4
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
8°
0°
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
0.40 (0.0157)
45°
060506-A
Figure 35. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.20
3.00
2.80
8
5
3.20
3.00
2.80
1
5.15
4.90
4.65
4
PIN 1
0.65 BSC
0.95
0.85
0.75
0.15
0.38
0.00
0.22
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
1.10 MAX
SEATING
PLANE
0.23
0.08
8°
0°
0.80
0.60
0.40
Figure 36. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. A | Page 12 of 16
AD8682/AD8684
www.BDTIC.com/ADI
4.00 (0.1575)
3.80 (0.1496)
0.25 (0.0098)
0.10 (0.0039)
COPLANARIT Y
0.10
CONTROLL ING DIMENSIONS ARE IN MILLI METERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROP RIATE FOR USE I N DESIGN.
8.75 (0.3445)
8.55 (0.3366)
BSC
8
7
6.20 (0.2441)
5.80 (0.2283)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
0.25 (0.0098)
0.17 (0.0067)
14
1
1.27 (0.0500)
0.51 (0.0201)
0.31 (0.0122)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
0.50 (0.0197)
0.25 (0.0098)
8°
0°
1.27 (0.0500)
0.40 (0.0157)
45°
060606-A
Figure 37. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
5.10
5.00
4.90
1.05
1.00
0.80
4.50
4.40
4.30
PIN 1
14
0.65
BSC
0.15
0.05
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
0.30
0.19
8
6.40
BSC
71
SEATING
PLANE
1.20
MAX
COPLANARITY
0.20
0.09
0.10
8°
0°
0.75
0.60
0.45
Figure 38. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding