Analog Devices AD8677 Service Manual

p

130 μV Maximum Offset Voltage

O

Amp in TSOT

FEATURES PIN CONFIGURATIONS

Low offset voltage: 130 µV max
Input offset drift: 1.5 µV/°C max
Low noise: 0.25 V p-p
High gain, CMRR and PSRR: 115 dB min
Low supply current: 1.1 mA
Wide supply voltage range: ±4 V to ±18 V operation

APPLICATIONS

Medical and industrial instrumentation
Sensors and controls

Thermocouple
RTDs
Strain bridges
Shunt current measurements

Precision filters

GENERAL DESCRIPTION

The AD8677 is the next generation of precision, ultralow offset
amplifiers. It builds on the high performance of the OP07 and
integrates lower power (1.1 mA typical), lower input bias
current (±1 nA maximum), and higher CMRR/PSRR (130 dB)
in the small TSOT package. Operation is fully specified from ±5
V to ±15 V supply.

1

OUT

+IN

NULL

Figure 2. 8-Lead SOIC_N (R-8)

AD8677

V–

2

TOP VIEW

(Not to Scale)

3

Figure 1. 5-Lead TSOT (UJ-5)

1

2

–IN

AD8677

TOP VIEW

3

+IN

(Not to Scale)

4

V–

NC = NO CONNECT

5

4

8

7

6

5

V+

–IN

05578-001

NULL

V+

OUT

NC

AD8677

05578-002

The AD8677 provides higher accuracy than industry-standard
OP07-type amplifiers due to Analog Devices’ iPolar™ process,
which supports enhanced performance in a smaller footprint.
These performance enhancements include wider output swing,
lower power, and higher CMRR (common-mode rejection
ratio) and PSRR (power supply rejection ratio). The AD8677
maintains stability of offsets and gain virtually regardless of
variations in time or temperature. Excellent linearity and gain
accuracy can be maintained at high closed-loop gains.

The AD8677 is fully specified over the extended industrial tem­perature range of −40°C to +125°C. The AD8677 amplifier is
available in the tiny, 5-lead TSOT and the popular 8-lead,
narrow SOIC lead-free packages.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD8677

TABLE OF CONTENTS

Features.............................................................................................. 1

Absolute Maximum Ratings ............................................................5

Applications....................................................................................... 1

General Description ......................................................................... 1

Pin Configurations ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

REVISION HISTORY

11/05—Revision 0: Initial Version

Thermal Resistance.......................................................................5

ESD Caution...................................................................................5

Typical Performance Characteristics..............................................6

Outline Dimensions....................................................................... 13

Ordering Guide .......................................................................... 13

Rev. 0 | Page 2 of 16

AD8677

SPECIFICATIONS

VS = ±5.0 V, TA = +25°C, unless otherwise specified.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS 40 130 μV

Input Bias Current

I

B

−40°C ≤ TA ≤ +125°C

0.2 1 nA

−40°C ≤ TA ≤ +125°C

Input Offset Current IOS 0.1 1 nA

−40°C ≤ TA ≤ +125°C

Input Voltage Range −3.5 +3.5 V
Common-Mode Rejection Ratio CMRR

Open-Loop Gain AVO

/ΔT −40°C ≤ TA ≤ +125°C

ΔV

OS

= ±3 V

V

CM

−40°C ≤ TA ≤ +125°C
= 2 kΩ to ground, VO = ±3 V

R

L

−40°C ≤ TA ≤ +125°C

OUTPUT CHARACTERISTICS

Output Voltage Swing V

OUT

= 10 kΩ to ground ±3.95 ±4.1

R

L

−40°C ≤ TA ≤ +125°C ±3.95
= 2 kΩ to ground ±3.9 ±4

R

L

−40°C ≤ TA ≤ +125°C ±3.9

Short-Circuit Limit ISC 27 mA
Output Current IO V

= 3.5 V 15 mA

O

POWER SUPPLY

Power Supply Rejection Ratio PSRR

Supply Current/Amplifier ISY V

= ±4.0 V to ±18.0 V

V

S

−40°C ≤ TA ≤ +125°C

= 0 V 1.1 1.25 mA

O

−40°C ≤ TA ≤ +125°C

DYNAMIC PERFORMANCE

Slew Rate SR

= 10 kΩ

R

L

Gain Bandwidth Product GBP 0.6 MHz
Phase Margin 80 Degrees

NOISE PERFORMANCE

Voltage Noise e

0.1 Hz to 10 Hz 0.28 μV p-p

n p-p

Voltage Noise Density en f = 1 kHz 10
Current Noise Density in f = 1 kHz 0.074

350 μV

1 nA

1 nA

120 127 dB

120 dB
1000 10000 V/mV
1000 V/mV

0.5 1.4 μV/°C

V

V

V

V

115 130 dB
110 dB

1.7 mA

0.2 V/μs

nV/√Hz
pA/√Hz

Rev. 0 | Page 3 of 16

AD8677

VS = ±15 V, TA = +25°C, unless otherwise specified.

Table 2.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS 45 130 μV

Input Bias Current

I

B

−40°C ≤ TA ≤ +125°C

0.2 1 nA

−40°C ≤ TA ≤ +125°C

Input Offset Current IOS 0.2 1 nA

−40°C ≤ TA ≤ +125°C

Input Voltage Range −13.5 +13.5 V
Common-Mode Rejection Ratio CMRR VCM = ±13.0 V 120 140 dB

Open Loop Gain AVO

Offset Voltage Drift

/ΔT −40°C ≤ TA ≤ +125°C

ΔV

OS

−40°C ≤ TA ≤ +125°C
= 2 kΩ to ground, VO = ±11 V

R

L

−40°C ≤ TA ≤ +125°C

OUTPUT CHARACTERISTICS

Output Voltage Swing V

OUT

= 10 kΩ to ground ±13.95

R

L

−40°C ≤ TA ≤ +125°C ±13.9
= 2 kΩ to ground ±13.75

R

L

−40°C ≤ TA ≤ +125°C ±13.7

Short Circuit Limit ISC 30 mA
Output Current IO V

= 13.5 V 15 mA

O

POWER SUPPLY

Power Supply Rejection Ratio PSRR

Supply Current/Amplifier ISY V

= ±4.0 V to ±18.0 V

V

S

−40°C ≤ TA ≤ +125°C

= 0 V 1.1 1.3 mA

O

−40°C ≤ TA ≤ +125°C

DYNAMIC PERFORMANCE

Slew Rate SR

= 10 kΩ

R

L

Gain Bandwidth Product GBP 0.6 MHz
Phase Margin 80 Degrees

NOISE PERFORMANCE

Voltage Noise e

0.1 Hz to 10 Hz 0.25 μV p-p

n p-p

Voltage Noise Density en f = 1 kHz 10
Current Noise Density in f = 1 kHz 0.074

350 μV

1 nA

1 nA

120 dB
1000 10000 V/mV
1000 V/mV

0.5 1.5 μV/°C

14 V
V

13.8 V
V

115 130 dB
110 dB

1.8 mA

0.2 V/μs

nV/√Hz
pA/√Hz

Rev. 0 | Page 4 of 16

AD8677

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Value

Supply Voltage ±18 V
Input Voltage ±V Supply
Differential Input Voltage ±0.7 V
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range

UJ-5, R Package −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range

RM, R Package −65°C to +150°C
Lead Temperature (Soldering, 10 sec) +300°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 4.

5-Lead TSOT (UJ-5) 207 61 °C/W
8-Lead SOIC (R-8) 158 43 °C/W

JA

θ

Unit Package Type θ

JC

Rev. 0 | Page 5 of 16

AD8677

TYPICAL PERFORMANCE CHARACTERISTICS

50

45

40

35

30

25

20

15

NUMBER OF AMPL IFIERS

10

5

0

–100 –80 –60 –40 –20 0 20 40 60 80 100

VOS (µV)

Figure 3. Input Offset Voltage Distribution

40

35

VS = ±15V

05578-003

VS = ±5V

NUMBER OF AMPL IFIERS

200

150

45

40

35

30

25

20

15

10

5

0

011.050.900.750.600.450.300.15

Figure 6. TCV

TCVOS (µV/°C)

vs. Number of Amplifiers

OS

VS = ±15V

05578-048

.20

VS = ±15V

30

25

20

15

NUMBER OF AMPLIFIERS

10

5

0

–100 –80 –60 –40 –20 0 20 40 60 80 100

VOS (µV)

Figure 4. Input Offset Voltage Distribution

50

40

30

20

NUMBER OF AMPL IFIERS

10

0

010.900.750.600.450.300.15

Figure 5. TCV

TCVOS (µV/°C)

vs. Number of Amplifiers

OS

100

50

(µV)

0

OS

V

–50

–100

–150

05578-004

–200

–50 0 50 100 150

VS = ±5V

05578-047

.05

200

150

100

50

(µV)

0

OS

V

–50

–100

–150

–200

–50 0 50 100 150

TEMPERATURE (°C)

Figure 7. Offset Voltage vs. Temperature

TEMPERATURE (°C)

Figure 8. Offset Voltage vs. Temperature

05578-005

VS = ±5V

05578-006

Rev. 0 | Page 6 of 16

AD8677

–

–

1.6

1.4

1.2

1.0

(mA)

SY

I

0.8

0.6

0.4
–50 0 50 100 150

VS = ±15V

VS = ±5V

TEMPERATURE (°C)

Figure 9. Supply Current vs. Temperature

14.40

14.35

14.30

(V)

14.25

OH

V

14.20

14.15

14.10
–50 0 50 100 150

Figure 10. +V

4.45
V

= ±5V

S

R

= 10kΩ

L

4.40

TEMPERATURE (°C)

vs. Temperature

OUT

VS = ±15V
R

= 10kΩ

L

05578-007

05578-009

13.92

–13.94

–13.96

–13.98

–14.00

(V)

OL

–14.02

V

–14.04

–14.06

–14.08

–14.10

–50 0 50 100 150

Figure 12. −V

3.98

–4.00

–4.02

–4.04

–4.06

(V)

OL

–4.08

V

–4.10

–4.12

–4.14

–4.16

–50 0 50 100 150

Figure 13. −V

0

–0.1

TEMPERATURE (°C)

vs. Temperature

OUT

TEMPERATURE (°C)

vs. Temperature

OUT

V

S

R

L

V

S

R

L

V

S

= ±15V
= 10kΩ

= ±5V
= 10kΩ

= ±15V

05578-011

05578-012

4.35

(V)

4.30

OH

V

4.25

4.20

4.15

–50 0 50 100 150

Figure 11. +V

TEMPERATURE (°C)

vs. Temperature

OUT

05578-010

–0.2

(nA)

B

I

–0.3

–0.4

–0.5

–50 0 50 100 150

TEMPERATURE (°C)

Figure 14. Input Bias Current vs. Temperature

05578-013

Rev. 0 | Page 7 of 16

AD8677

0

–0.05

–0.10

–0.15

–0.20

(nA)

B

I

–0.25

–0.30

–0.35

–0.40

–50 0 50 100 150

TEMPERATURE (°C)

Figure 15. Input Bias Current vs. Temperature

146

144

142

140

138

134

134

CMRR (dB)

132

130

128

126

124

–50 0 50 100 150

VS = ±15V

= ±5V

V

S

TEMPERATURE (°C)

Figure 16. CMRR vs. Temperature

16000

14000

12000

V

S

= ±15V

V

R

=±5V

S

= 2kΩ

L

05578-014

05578-015

150

VS = ±4V TO ±18V

140

PSRR (dB)

130

120

–50 0 50 100 150

TEMPERATURE (°C)

Figure 18. PSRR vs. Temperature

40

V

= ±15V

S

30

(mA)

SC

I

20

10

–50 0 50 100 150

V

= ±5V

S

TEMPERATURE (° C)

Figure 19. Short Circuit Current vs. Temperature

1.4

1.2

1.0

05578-019

05578-020

10000

(V/mV)

8000

VO

A

6000

4000

2000

–50 0 50 100 150

V

= ±5V

S

TEMPERATURE (°C)

Figure 17. Open-Loop Gain vs. Temperature

05578-017

Rev. 0 | Page 8 of 16

0.8

0.6

0.4

SUPPLY CURRENT (mA)

0.2

0

0 1020304

SUPPLY VOLTAGE (V)

Figure 20. Supply Current vs. Total Supply Voltages

05578-022

0

AD8677

V

V

10

VS= ±15V

VOH = +V

OUT

(V)

OUT

1

–

SY

V

VOL = –V

OUT

50

40

G=+100

30

G=+10

20

10

CLOSED-LOOP GAIN (dB)

G=+1

0

VS=±15V

= 28mV

V

IN

=

∞

R

L

CL= 20pF

0.1

0.01 0.1 1 10 100

I

LOAD

(mA)

Figure 21. Output Voltage Swing vs. Load Current

10

VS= ±5V

(V)

OUT

1

–

SY

V

0.1

0.01 0.1 1 10 100

VOL = –V

I

LOAD

OUT

VOH = +V

(mA)

Figure 22. Output Voltage Swing vs. Load Current

100

80

60

40

GAIN

20

0

VS= ±15V

–20

R

=

∞

L

CL= 20pF

Φm = 80 Degrees

–40

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

GAIN

Figure 23. Open-Loop Gain and Phase vs. Frequency

PHASE

OUT

100

80

60

40

20

0

05578-023

–10

100 1k 10k 100k 1M

FREQUENCY (Hz)

05578-026

Figure 24. Closed-Loop Gain vs. Frequency

50

G=+100

40

30

G=+10

20

10

CLOSED-LOOP GAIN (dB)

05578-024

G=+1

0

–10

100 1k 10k 100k 1M

FREQUENCY (Hz)

VS=±5V

= 28mV

V

IN

=

∞

R

L

CL= 20pF

05578-027

Figure 25. Closed-Loop Gain vs. Frequency

30

VS= ±15V

= ±50mV

V

IN

G = +1

PHASE MARGIN ( Degrees)

25

20

15

OVERSHOOT (%)

10

5

05578-025

0

01108

C

LOAD

642

–OS

(nF)

+OS

05578-028

2

Figure 26. Overshoot vs. Capacitive Load

Rev. 0 | Page 9 of 16

AD8677

30

25

20

VS= ±5V

= ±50mV

V

IN

G = +1

–OS

+OS

100

10

VS= ±15V

= 28mV

V

IN

=

∞

R

L

CL= 20pF

G = +100

15

OVERSHOOT (%)

10

5

0

0246810

C

LOAD

(nF)

Figure 27. Overshoot vs. Capacitive Load

112

VS= ±15V

110

108

106

104

CMRR (dB)

102

100

98

96

100 1M10k 100k1k

FREQUENCY (Hz)

Figure 28. CMRR vs. Frequency

100

–PSRR

80

05578-029

12

05578-030

(Ω)

OUT

R

0.1

0.01

100

(Ω)

OUT

R

0.1

0.01

100

1

10 1M10k 100k1k100

G = +10

FREQUENCY (Hz)

Figure 30. Output Impedance vs. Frequency

VS= ±5V

= 28mV

V

IN

=

∞

R

L

CL= 20pF

10

1

10 1M10k 100k1k100

G = +100

G = +10

FREQUENCY (Hz)

Figure 31. Output Impedance vs. Frequency

VS = ±15V

G = +1

05578-032

G = +1

05578-033

60

PSRR (dB)

40

20

0

10 1M10k 100k1k100

+PSRR

FREQUENCY (Hz)

Figure 29. PSRR vs. Frequency

05578-031

Rev. 0 | Page 10 of 16

10

VOLTAGE NOISE DENSIT Y (nV/ Hz)

1

0.1 1k100101

FREQUENCY (Hz)

Figure 32. Voltage Noise Density vs. Frequency

05578-034

AD8677

V

V

10

VS= ±15V

1

VS = ±5V

= 1nF

C

L

G = +1

= 4V p-p

V

IN

(pA/ Hz)

n

i

0.1

0.01

0.1 1k100101

VS = ±5V AND ±15V
C
G = +1
V

2

OUTPUT VOLTAGE (100mV/DIV)

FREQUENCY (Hz)

Figure 33. Current Noise Density vs. Frequency

= 1nF

L

= 100mV p-p

IN

TIME (100µs/DIV)

Figure 34. Small Signal Transient

2

OUTPUT VO LTAGE ( 1V/DIV)

05578-035

TIME (100µs/DIV)

05578-039

Figure 36. Large Signal Transient

400m

200mV

0V

–200mV

0V

–5V

–10V

–15V

05578-036

–20V

V

IN

V

OUT

TIME (10µ s/DIV)

VS = ±15V

= 200mV

V

IN

G = –100
RECOVERY = 1µs

05578-040

Figure 37. Positive Overload Recovery

VS = ±15V

= 1nF

C

L

G = +1

= 4V p-p

V

IN

2

OUTPUT VOLT AGE (1V/DIV)

TIME (100µs/DIV)

05578-038

Figure 35. Large Signal Transient

400m

200mV

–200mV

15V

10V

–5V

V

0V

5V

0V

IN

V

OUT

TIME (10µ s/DIV)

Figure 38. Negative Overload Recovery

VS = ±15V

= 200mV

V

IN

G = –100
RECOVE RY = 5µs

05578-041

Rev. 0 | Page 11 of 16

AD8677

V

T

V

1200m

600mV

–600mV

–2V

–4V

–6V

–8V

1200m

600mV

–600mV

–2V

–4V

VOLTAGE NOISE (0.2µV/DIV)

VS = ±15V
VN p-p = 0.24µV

1

TIME (1s/ DIV)

Figure 42. Voltage Noise (0.1 Hz to 10 Hz)

20kΩ

V+

7

5

V

TRIM RANGE I S

OS

TYPICALLY ±3.5mV

OUTPUT

–

INPU

+

2

–

AD8677

3

+

1

8

4

V–

Figure 43. Optional Offset Nulling Circuit

05578-045

05578-049

VS = ±5V

= 600mV

V

IN

G = –10

V

0V

0V

IN

V

OUT

TIME (4µs/DIV)

RECOVERY = 2.4µ s

05578-042

Figure 39. Positive Overload Recovery

VS = ±5V

= 600mV

V

IN

G = –10

V

0V

4V

2V

0V

IN

V

OUT

RECOVERY = 5.6µ s

TIME (4µs/DIV)

Figure 40. Negative Overload Recovery

05578-043

2

VS = ±5V

= ±5.7V

V

IN

V

IN

V

OUT

TIME (4 00µs/DIV)

05578-044

Figure 41. No Phase Reversal

Rev. 0 | Page 12 of 16

AD8677

OUTLINE DIMENSIONS

2.90 BSC

54

0.50

0.30

2.80 BSC

0.95 BSC

*

1.00 MAX

SEATING
PLANE

0.20

0.08

1.60 BSC

*

0.90

0.87

0.84

0.10 MAX

123

PIN 1

1.90

BSC

*

COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.

Figure 44. 5-Lead Thin Small Outline Transistor Package [TSOT]

(UJ-5)

Dimensions shown in millimeters

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

8°
4°
0°

0.60

0.45

0.30

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Figure 45. 8-Lead Standard Small Outline Package [SOIC_N]

5.00 (0.1968)

4.80 (0.1890)

85

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

BSC

6.20 (0.2440)

5.80 (0.2284)

41

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

× 45°

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD8677ARZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8677ARZ-REEL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8677ARZ-REEL7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8677AUJZ-R2 −40°C to +125°C 5-Lead Thin Small Outline Transistor Package [TSOT] UJ-5 A0E
AD8677AUJZ-REEL −40°C to +125°C 5-Lead Thin Small Outline Transistor Package [TSOT] UJ-5 A0E
AD8677AUJZ-REEL7 −40°C to +125°C 5-Lead Thin Small Outline Transistor Package [TSOT] UJ-5 A0E

1

Z = Pb-free part.

1

1

1

1

1

1

Rev. 0 | Page 13 of 16

AD8677

NOTES

Rev. 0 | Page 14 of 16

AD8677

NOTES

Rev. 0 | Page 15 of 16

AD8677

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05578-0-11/05(0)

Rev. 0 | Page 16 of 16