ANALOG DEVICES AD 8672 ARZ Datasheet

Precision, Very Low Noise, Low Input

–

+

Data Sheet

FEATURES

Very low noise: 2.8 nV/√Hz, 77 nV p-p
Wide bandwidth: 10 MHz
Low input bias current: 12 nA max
Low offset voltage: 75 μV max
High open-loop gain: 120 dB min
Low supply current: 3 mA typ per amplifier
Dual-supply operation: ±5 V to ±15 V
Unity-gain stable
No phase reversal

APPLICATIONS

PLL filters
Filters for GPS
Instrumentation
Sensors and controls
Professional quality audio

GENERAL DESCRIPTION

The AD8671/AD8672/AD8674 are very high precision amplifiers
featuring very low noise, very low offset voltage and drift, low
input bias current, 10 MHz bandwidth, and low power
consumption. Outputs are stable with capacitive loads of over
1000 pF. Supply current is less than 3 mA per amplifier at 30 V.

The AD8671/AD8672/AD8674’s combination of ultralow noise,
high precision, speed, and stability is unmatched. The MSOP
version of the AD8671/AD8672 requires only half the board
space of comparable amplifiers.

Applications for these amplifiers include high quality PLL
filters, precision filters, medical and analytical instrumentation,
precision power supply controls, ATE, data acquisition, and
precision controls as well as professional quality audio.

The AD8671/AD8672 are specified over the extended industrial
temperature range (−40°C to +125°C), and the AD8674 is specified
over the industrial temperature range (−40°C to +85°C).

Bias Current Operational Amplifiers

AD8671/AD8672/AD8674

PIN CONFIGURATIONS

NC

1

AD8671

2

IN

TOP VIEW

IN

3

(Not to Scale)

V–

4

NC = NO CONNECT

Figure 1. 8-Lead SOIC_N (R-8) and 8-Lead MSOP (RM-8)

OUT A

1

AD8672

2

–IN A
+IN A

V–

TOP VIEW

3

(Not to Scale)

4

Figure 2. 8-Lead SOIC-N (R-8) and 8-Lead MSOP (RM-8)

OUT A

1

–IN A

2
3

+IN A

+IN B
–IN B

OUT B

V+

AD8674

4

TOP VIEW

(Not to Scale)

5
6
7

Figure 3. 14-Lead SOIC_N (R-14) and 14-Lead TSSOP (RU-14)

The AD8671, AD8672, and AD8674 are members of a growing
series of low noise op amps offered by Analog Devices, Inc.

Table 1. Voltage Noise

Package 0.9 nV 1.1 nV 1.8 nV 2.8 nV 3.8 nV

Single AD797 AD8597 ADA4004-1 AD8675 AD8671
Dual AD8599 ADA4004-2 AD8676 AD8672
Quad ADA4004-4 AD8674

NC

8
7

V+
OUT

6

NC

5

03718-B-001

V+

8
7

OUT B

6

–IN B
+IN B

5

03718-B-003

OUT D

14

–IN D

13
12

+IN D

11

V–

10

+IN C

9

–IN C
OUT C

8

03718-B-005

The AD8671/AD8672 are available in the 8-lead SOIC and
8-lead MSOP packages. The AD8674 is available in 14-lead
SOIC and 14-lead TSSOP packages.

Surface-mount devices in MSOP packages are available in tape
and reel only.

Rev. F Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devi ces for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] ©2004–2013 Analog Devices, Inc. All rights reserved.

Technical Support www.analog.com

AD8671/AD8672/AD8674 Data Sheet

TABLE OF CONTENTS

Specifications ..................................................................................... 3

Output Phase Reversal ............................................................... 12

Electrical Characteristics, ±5.0 V ............................................... 3

Electrical Characteristics, ±15 V ................................................ 4

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Typical Performance Characteristics ............................................. 6

Applications ..................................................................................... 11

Power Dissipation Calculations ................................................ 11

Unity-Gain Follower Applications ........................................... 11

REVISION HISTORY

3/13—Rev. E to Rev. F

Added Figure 7 .............................................................................. 6

Updated Outline Dimensions ................................................... 15

Changes to Ordering Guide ...................................................... 17

6/10—Rev. D to Rev. E

Added Table 1 and Preceding Sentence ..................................... 1

12/09—Rev. C to Rev. D

Changes to Features and General Description Sections .......... 1

Changes to Absolute Maximum Ratings Section, Table 3,

and Table 4 ................................................................................ 5

Added Power Dissipation Calculations Section ..................... 11

Updated Outline Dimensions ................................................... 15

Changes to Ordering Guide ...................................................... 17

Total Noise vs. Source Resistance ............................................. 12

Total Harmonic Distortion (THD) and Noise ....................... 13

Driving Capacitive Loads .......................................................... 13

GPS Receiver ............................................................................... 14

Band-Pass Filter .......................................................................... 14

PLL Synthesizers and Loop Filters ........................................... 14

Outline Dimensions ....................................................................... 15

Ordering Guide .......................................................................... 17

4/04—Rev. A to Rev. B

Changes to Figure 32 .................................................................. 11

Changes to Figures 36, 37, and 38 ............................................ 12

1/04—Rev. 0 to Rev. A

Added AD8672 and AD8674 parts .............................. Universal

Changes to Specifications ............................................................. 3

Deleted Figure 3 ............................................................................. 6

Changes to Figures 7, 8, and 9 ..................................................... 6

Changes to Figure 37 .................................................................. 12

Added new Figure 32 ................................................................. 10

6/05—Rev. B to Rev. C

Changes to Figure 6 ...................................................................... 1

Updated Outline Dimensions ................................................... 14

Changes to Ordering Guide ...................................................... 16

Rev. F | Page 2 of 20

Data Sheet AD8671/AD8672/AD8674

Offset Voltage Drift

∆VOS/∆T

–40°C < TA < +125°C

–40°C < TA < +125°C

–40

+8

+40

nA

Output Voltage High

VOH

RL = 600 Ω

+3.7

+3.9 V

Settling Time

tS

To 0.1% (4 V step, G = 1)

1.4 µs

f = 10 kHz

–105

dB

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS, ±5.0 V

VS = ±5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS 20 75 µV
–40°C < TA < +125°C 30 125 µV

AD8671 0.3 0.5 µV/°C

AD8672/AD8674 0.3 0.8 µV/°C
Input Bias Current IB –12 +3 +12 nA
+25°C < TA < +125°C –20 +5 +20 nA

Input Offset Current IOS –12 +6 +12 nA
+25°C < TA < +125°C –20 +6 +20 nA
–40°C < TA < +125°C –40 +8 +40 nA
Input Voltage Range –2.5 +2.5 V
Common-Mode Rejection Ratio CMRR VCM = –2.5 V to +2.5 V 100 120 dB
Large Signal Voltage Gain AVO RL = 2 kΩ, VO = –3 V to +3 V 1000 6000 V/mV
Input Capacitance, Common Mode C
Input Capacitance, Differential Mode C
Input Resistance, Common Mode RIN 3.5 GΩ
Input Resistance, Differential Mode R

OUTPUT CHARACTERISTICS

Output Voltage High VOH RL = 2 kΩ, –40°C to +125°C +3.8 +4.0 V
Output Voltage Low VOL RL = 2 kΩ, –40°C to +125°C –3.9 –3.8 V

6.25 pF

INCM

7.5 pF

INDM

15 MΩ

INDM

Output Voltage Low VOL RL = 600 Ω –3.8 –3.7 V
Output Current I

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = ±4 V to ±18 V

AD8671/AD8672 110 130 dB

AD8674 106 115 dB
Supply Current/Amplifier ISY VO = 0 V 3 3.5 mA

–40°C < TA < +125°C 4.2 mA
DYNAMIC PERFORMANCE

Slew Rate SR RL = 2 kΩ 4 V/µs

To 0.01% (4 V step, G = 1) 5.1 µs
Gain Bandwidth Product GBP 10 MHz

NOISE PERFORMANCE

Peak-to-Peak Noise e
Voltage Noise Density en f = 1 kHz 2.8 3.8 nV/√Hz
Current Noise Density in f = 1 kHz 0.3 pA/√Hz
Channel Separation

AD8672/AD8674 CS f = 1 kHz –130 dB

±10 mA

OUT

0.1 Hz to 10 Hz 77 100 nV p-p

n p-p

Rev. F | Page 3 of 20

AD8671/AD8672/AD8674 Data Sheet

AD8671

0.3

0.5

µV/°C

AD8672/AD8674

0.3

0.8

µV/°C

Input Capacitance, Differential Mode

C

7.5 pF

OUTPUT CHARACTERISTICS

Power Supply Rejection Ratio

PSRR

VS = ±4 V to ±18 V

f = 10 kHz

–105

dB

ELECTRICAL CHARACTERISTICS, ±15 V

VS = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.

Table 3.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS 20 75 µV
–40°C < TA < +125°C 30 125 µV
Offset Voltage Drift ∆VOS/∆T –40°C < TA < +125°C

Input Bias Current IB –12 +3 +12 nA
+25°C < TA < +125°C –20 +5 +20 nA
–40°C < TA < +125°C –40 +8 +40 nA
Input Offset Current IOS –12 +6 +12 nA
+25°C < TA < +125°C –20 +6 +20 nA
–40°C < TA < +125°C –40 +8 +40 nA
Input Voltage Range –12 +12 V
Common-Mode Rejection Ratio CMRR VCM = –12 V to +12 V 100 120 dB
Large Signal Voltage Gain AVO RL = 2 kΩ, VO = –10 V to +10 V 1000 6000 V/mV
Input Capacitance, Common Mode C

Input Resistance, Common Mode RIN 3.5 GΩ
Input Resistance, Differential Mode R

6.25 pF

INCM

INDM

15 MΩ

INDM

Output Voltage High VOH RL = 2 kΩ, –40°C to +125°C +13.2 +13.8 V
Output Voltage Low VOL RL = 2 kΩ, –40°C to +125°C –13.8 –13.2 V
Output Voltage High VOH RL = 600 Ω +11 +12.3 V
Output Voltage Low VOL RL = 600 Ω –12.4 –11 V
Output Current I

±20 mA

OUT

Short Circuit Current ISC ±30 mA

POWER SUPPLY

AD8671/AD8672 110 130 dB
AD8674 106 115 dB

Supply Current/Amplifier ISY VO = 0 V 3 3.5 mA
–40°C <TA < +125°C 4.2 mA
DYNAMIC PERFORMANCE

Slew Rate SR RL = 2 kΩ 4 V/µs

Settling Time tS To 0.1% (10 V step, G = 1) 2.2 µs

To 0.01% (10 V step, G = 1) 6.3 µs

Gain Bandwidth Product GBP 10 MHz
NOISE PERFORMANCE

Peak-to-Peak Noise e

0.1 Hz to 10 Hz 77 100 nV p-p

n p-p

Voltage Noise Density en f = 1 kHz 2.8 3.8 nV/√Hz

Current Noise Density in f = 1 kHz 0.3 pA/√Hz

Channel Separation

AD8672/AD8674 CS f = 1 kHz –130 dB

Rev. F | Page 4 of 20

Data Sheet AD8671/AD8672/AD8674

Input Voltage

VS– to VS+

Operating Temperature Range

Package Type

θ

θJC

Unit

the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

ESD precautions are recommended to avoid performance

ABSOLUTE MAXIMUM RATINGS

Table 4.1

Parameter Rating

Supply Voltage 36 V

Differential Input Voltage ±0.7 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range

All Packages –65°C to +150°C

8-Lead Packages –40°C to +125°C
14-Lead Packages –40°C to +85°C

Junction Temperature Range

All Packages –65°C to +150°C

Lead Temperature Range (Soldering, 60 sec) 300°C

1

Absolute maximum ratings apply at 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

See the Applications section for a related discussion on power.

Table 5. Package Characteristics

1

JA

8-Lead MSOP (RM) 142 44 °C/W
8-Lead SOIC_N (R) 120 43 °C/W
14-Lead SOIC_N (R) 90 36 °C/W
14-Lead TSSOP (RU) 112 35 °C/W

1

θJA is specified for the worst-case conditions, that is., θJA is specified for the

device soldered on a 4-layer circuit board for surface-mount packages.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

electrostatic discharges. Therefore, proper
degradation or loss of functionality.

Rev. F | Page 5 of 20

AD8671/AD8672/AD8674 Data Sheet

03718-B-007

FREQUENCY (Hz)

VOLTAGE NOISE DENSITY (nV/√Hz)

4

8

12

16

20

24

28

32

0

0 10 20 30 40

50

60 70

80 90

100

V

S

=

±

15V

03718-B-008

FREQUENCY (kHz)

VOLTAGE NOISE DENSITY (nV/√Hz)

0

4.5

9.0

13.5

18.0

22.5

27.0

31.5

0 0.1

0.2 0.3 0.4

0.5

0.6

0.7 0.8

0.9

1.0

V

S

=

±

15V

03718-B-009

FREQUENCY (kHz)

VOLTAGE NOISE DENSITY (nV/√Hz)

0

1 102 3 4 5 6 7 8 90

2.5

5.0

7.5

10.0

12.5

15.0

17.5
VS = ±15V

0.1

1

10

1 10

100

1k 10k

CURRENT NOIS E DE NS ITY (pA/√Hz)

FREQUENCY (Hz)

03718-112

0

5

10

15

20

25

30

35

40

45

–35

VOS(µV)

NUMBER OF AMP LIFIE RS

–25 –5–15

0 45–30 –20 –

10 5 10

15 20 25

30 35 40

03718-B-010

V

S

=

±5V

TA = 25

°C

0

5

10

15

20

25

30

35

–35

VOS(µV)

NUMBER OF AMP LIFIE RS

–25 –5–15 0 50–30 –20 –10

5 10 15 20 25 30 35 40

03718-B-011

45

VS = ±

15V

TA = 25°

C

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. Voltage Noise Density vs. Frequency

Figure 5. Voltage Noise Density vs. Frequency

Figure 7. Current Noise Density V

= ±15 V

S

Figure 8. Input Offset Voltage Distribution

Figure 6. Voltage Noise Density vs. Frequency

Rev. F | Page 6 of 20

Figure 9. Input Offset Voltage Distribution

Data Sheet AD8671/AD8672/AD8674

6

7

8

9

10

11

12

13

14

15

16

V

OS

(µV)

TEMPERATURE (°C)

–40 85

25 125

03718-B-012

VS = ±15V

V

S

=

±5V

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

I

B

(nA)

TEMPERATURE (°C)

–40 8525 125

+I

B

–I

B

03718-B-013

V

S

= ±5V

–

1.0

–

0.5

0

0.5

1.0

1.5

2.0

2.5

I

B

(nA)

TEMPERATURE (°C)

–40 8525 125

+I

B

–I

B

03718-B-014

V

S

= ±15V

2.4

2.6

2.8

3.0

3.2

3.4

I

SY

(mA)

3.6

3.8

4.0

TEMPERATURE (°C)

–

40

8525 125

V

S

= ±

15V

V

S

=

±

5V

03718-B-015

10.0

10.5

11.0

11.5

12.0

12.5

13.0

13.5

14.0

14.5

OUTPUT VOLTAGE (V)

TEMPERATURE (°C)

–40 8525 125

RL= 600Ω

RL= 2kΩ

03718-B-016

VS= ±15V

–14.5

–14.0

–13.5

–13.0

–12.5

–12.0

–11.5

–11.0

OUTPUT VOLTAGE (V)

TEMPERATURE (°

C)

–40 8525 125

RL= 600Ω

RL = 2kΩ

03718-B-017

V

S

= ±15V

Figure 10. Input Offset Voltage vs. Temperature

Figure 11. Input Bias Current vs. Temperature

Figure 13. Supply Current vs. Temperature

Figure 14. Output Voltage High vs. Temperature

Figure 12. Input Bias Current vs. Temperature

Rev. F | Page 7 of 20

Figure 15. Output Voltage Low vs. Temperature

AD8671/AD8672/AD8674 Data Sheet

FREQUENCY (Hz)

OPEN-LOOP GAIN (dB)

–10

0

10

100k

03718-B-018

10M

1M

–40

–30

–

20

20

30

40

50

V

SY

=

±15V

R

L

= 10kΩ

CL = 20pF

F

M

= 59

°

GAIN

PHASE

OPEN-LOOP PHASE (dB)

–45

45

–180

–

135

–90

90

135

180

225

0

60

270

0

5000

10000

15000

20000

25000

30000

A

VO

(V/mV)

TEMPERATURE (°C)

–

40 8525 125

±5V

±15V

03718-B-019

FREQUENCY (Hz)

1k 1M

CLOSED-LOOP GAIN (dB)

–10

0

10

20

40

50

100k10k 10M

03718-B-020

30

–20

–30

–40

–50

100M

AV = 100

A

V

= 10

A

V

= 1

VSY =

±

15V

V

IN

= 10mV
RL = ∞
CL = 20pF

FREQUENCY (Hz)

1k 10M

IMPEDANCE (Ω)

40

50

60

70

90

100

100k10k 100M

03718-B-021

80

30

20

10

0

A

VO

= 100

100

A

VO

= 10

A

VO

= 1

1M

V

SY

= ±15V

V

IN

= 4V

R

L

= 2kΩ

03718-B-022

VOLTAGE (1V/DIV)

TIME (100µs/DIV)

VSY = ±15V
VIN = 200mV p-p
RL = 2k

Ω

03718-B-023

VOLTAGE (50mV/DIV)

TIME (10µs/DIV)

Figure 16. Open-Loop Gain and Phase Shift vs. Frequency

Figure 17. Open-Loop Gain vs. Temperature

Figure 19. Output Impedance vs. Frequency

Figure 20. Large Signal Transient Response

Figure 18. Closed-Loop Gain vs. Frequency

Figure 21. Small Signal Transient Response

Rev. F | Page 8 of 20

Data Sheet AD8671/AD8672/AD8674

60

50

–OS

40

30

20

SMALL SIGNAL OVERSHOOT (%)

10

+OS

0

100

1k

CAPACITANCE (pF)

Figure 22. Small Signal Overshoot vs. Load Capacitance

VS = ±15V

= 200mV p-p

V

IN

= –100

A

V

= 10k

R

L

V

IN

VOLTAGE (200mV/DIV)

V

OUT

TIME (4s/DIV)

Figure 23. Positive Overdrive Recovery

VSY = ±15V
V

= 200mV p-p

IN

A

= –100

V

R

= 10k

V

IN

VOLTAGE (200mV/DIV)

V

OUT

L

VS =±15

10k

03718-B-024

0V

0V

03718-B-025

0V

0V

160

140

120

100

CMRR (dB)

–20

–40

160

140

120

100

80

60

40

PSRR (dB)

20

–20

–40

135

134

133

132

131

PSRR (dB)

130

129

128

VSY = ±15V

80

60

40

20

0

1k 1M

100

10

100k10k

FREQUENCY (Hz)

10M

100M

03718-B-027

Figure 25. CMRR vs. Fre quency

VSY = ±15V

–PSRR

+PSRR

0

100

10

1k 1M

FREQUENCY (Hz)

100k10k 10M

03718-B-028

Figure 26. PSRR v s. Frequency

VS= ±2.5V TO ±18V

TIME (4s/DIV)

Figure 24. Negative Overdrive Recovery

03718-B-026

Rev. F | Page 9 of 20

127

–40 8525 125

TEMPERATURE (°C)

Figure 27. PSRR vs. Temperature

03718-B-029

AD8671/AD8672/AD8674 Data Sheet

03718-B-030

VS = ±15V

TIME (1µs/DIV)

VOLTAGE NOISE (50nV/DIV)

FREQUENCY (Hz)

CHANNEL SEPARATION (dB)

100

–

120

–

40

–

20

0

1k 10k 100k 1M

–

60

–

140

–80

–

100

10M

100M

03718-B-031

VS = ±15V, ±5V

Figure 29. Channel Separation

Figure 28. 0.1 Hz to 10 Hz Input Voltage Noise

Rev. F | Page 10 of 20

Data Sheet AD8671/AD8672/AD8674

HznV/

2

10

9

C

n

qI

kTe =

03718-B-032

REF1 +OVER

23.23%
CH2 +OVER

7.885%

VOLTAGE (1V/DIV)

OUTPUT UNCOMPENSATE D

OUTPUT
COMPENSATED

TIME (100ns/DIV)

APPLICATIONS

POWER DISSIPATION CALCULATIONS

To achieve low voltage noise in a bipolar op amp, the current
must be increased. The emitter-base theoretical voltage noise is
approximately

Therefore, the rise above ambient temperature is

504 mW × 112°C/W = 56°C

With an ambient temperature of 50°C, the junction temperature
is 106°C. This is less than the specified absolute maximum junction
temperature, but for systems with long product lifetimes (years),
this should be considered carefully.

To achieve the low voltage noise of 2.8 nV/√Hz, the input stage
current is higher than most op amps with an equivalent gain
bandwidth product. The thermal noise of a 1 kΩ resistor is
4 nV/√Hz, which is higher than the voltage noise of AD8671
family. Low voltage noise requires using low values of resistors,
so low voltage noise op amps should have good drive capability,
such as a 600 Ω load. This means that the second stage and
output stage are also biased at higher currents. As a result, the
supply current of a single op amp is 3.5 mA maximum at room
temperature.

Junction temperature has a direct affect on reliability. For more
information, visit the following Analog Devices, Inc., website:

http://www.analog.com/en/quality-and-reliability/reliability­data/content/index.html

MTTF and FIT calculations can be done based on the junction
temperature and IC process. Use the following equation to
determine the junction temperature:

T

= TA + PD × θJA

J

For the AD8671 single in the 8-lead MSOP package, the thermal
resistance, θ

, is 142°C/W. If the ambient temperature is 30°C

JA

and the supply voltages are ±12 V, the power dissipation is

24 V × 3.5 mA = 84 mW

Note that these calculations do not include the additional
dissipation caused by the load current on each op amp. Possible
solutions to reduce junction temperature include system level
considerations such as fans, Peltier thermoelectric coolers, and
heat pipes. Board considerations include operation on lower
voltages, such as ±12 V or ±5 V, and using two dual op amps
instead of one quad op amp. If the extremely low voltage noise
and high gain bandwidth is not required, using other quad op
amps, such as ADA4091-4, OP4177, ADA4004-4, OP497, or

AD704 can be considered.

UNITY-GAIN FOLLOWER APPLICATIONS

When large transient pulses (>1 V) are applied at the positive
terminal of amplifiers (such as the OP27, LT1007, OPA227, and
AD8671) with back-to-back diodes at the input stage, the use of
a resistor in the feedback loop is recommended to avoid having
the amplifier load the signal generator. The feedback resistor,
R

, should be at least 500 Ω. However, if large values must be

F

used for R
with R
capacitance and R

Figure 30 shows the uncompensated output response with a
10 kΩ resistor in the feedback and the compensated response
with C

, a small capacitor, CF, should be inserted in parallel

F

to compensate for the pole introduced by the input

F

.

F

= 15 pF.

F

Therefore, the rise above ambient temperature is

84 mW × 142°C/W = 12°C

If the ambient temperature is 30°C, the junction temperature is
42°C. The previously mentioned website that details the effect
of the junction temperature on reliability has a calculator that
requires only the part number and the junction temperature to
determine the process technology.

For the AD8674 single in the 14-Lead TSSOP package, the thermal
resistance, θ
8-lead package, the four op amps are powered simultaneously. If
the ambient temperature is 50°C and the supply voltages are ±15 V,
the power dissipation is

30 V × 4.2 mA × four op amps = 504 mW

, is 112°C/W. Although θJA is lower than it is for the

JA

Figure 30. Transient Output Response

Rev. F | Page 11 of 20

AD8671/AD8672/AD8674 Data Sheet

OUTPUT PHASE REVERSAL

Phase reversal is a change of polarity in the amplifier transfer
function that occurs when the input voltage exceeds the supply
voltage. The AD8671/AD8672/AD8674 do not exhibit phase
reversal even when the input voltage is 1 V beyond the supplies.

VSY = ±15V

V

IN

V

VOLTAGE (1V/DIV)

OUT

TOTAL NOISE VS. SOURCE RESISTANCE

The low input voltage noise of the AD8671/AD8672/AD8674
makes them a great choice for applications with low source
resistance. However, because they have low input current noise,
they can also be used in circuits with substantial source
resistance.

Figure 32 shows the voltage noise, current noise, thermal noise,
and total rms noise of the AD8671 as a function of the source
resistance.

For R

< 475 Ω, the input voltage noise, en, dominates.

S

For 475 Ω < R
For R

> 412 kΩ, the input current noise dominates.

S

1000

< 412 kΩ, thermal noise dominates.

S

TIME (10s/DIV)

Figure 31. Output Phase Reversal

100k

C

i

n

e

n

1M

03718-B-034

03718-B-033

TOTAL NOISE (nV/Hz)

100

10

e

n_t

A

1

10

100 10k

1k

SOURCE RESISTANCE ()

(4kRST)

1/2

B

Figure 32. Noise vs. Source Resistance

Rev. F | Page 12 of 20

Data Sheet AD8671/AD8672/AD8674

Hz

100 1k 10k

PERCENTAGE

LT1007

0.0001

0.0002

0.0005

0.0010

0.0020

0.0050

0.0100

0.0200

0.0500

0.1000

5020 500200

5k

2k

AD8671

20k

03718-B-035

VS = ±5V
V

IN

= 2.5V

R

L

= 600Ω

03718-B-036

V

SY

=

±15V

R

L

= 2k

Ω

CL = 1nF
V

IN

= 100mV

A

V

= +1

CH2 +OVER

39.80%
CH2 –

OVER

39.80%

TIME (10µ

s/DIV)

VOLTAGE (500mV/DI V )

500Ω

R

F

V

CC

220pF

C

F

V

IN

V

EE

R

G

500Ω

10Ω

R

S

1nF

C

L

03718-B-037

2kΩ

R

L

03718-B-038

VSY = ±15V
R

L

= 2kΩ

C

L

= 1nF

C

F

= 220pF

V

IN

= 100mV

A

V

= +2

CH2 +OVER

5.051%
CH2 –OVER

6.061%

TIME (10µs/DIV)

VOLTAGE (100mV/DI V )

TOTAL HARMONIC DISTORTION (THD) AND NOISE

The AD8671/AD8672/AD8674 exhibit low total harmonic
distortion (THD) over the entire audio frequency range. This
makes them suitable for applications with high closed-loop
gains, including audio applications. Figure 33 shows
approximately 0.0006% of THD + N in a positive unity gain, the
worst-case configuration for distortion.

Figure 34. AD8671 Capacitive Load Drive

Figure 33. Total Harmonic Distortion and Noise

DRIVING CAPACITIVE LOADS

The AD8671/AD8672/AD8674 can drive large capacitive loads
without causing instability. However, when configured in unity
gain, driving very large loads can cause unwanted ringing or
instability.

Figure 34 shows the output of the AD8671 with a capacitive
load of 1 nF. If heavier loads are used in low closed-loop gain or
unity-gain configurations, it is recommended to use external
compensation as shown in the circuit in Figure 35. This
technique reduces the overshoot and prevents the op amp from
oscillation. The trade-off of this circuit is a reduction in output
swing. However, a great added benefit stems from the fact that
the input signal and the op amp’s noise are filtered, and thus the
overall output noise is kept to a minimum.

The output response of the circuit is shown in Figure 36.

Rev. F | Page 13 of 20

Figure 35. Recommended Capacitive Load Circuit

Figure 36. Compensated Load Drive

AD8671/AD8672/AD8674 Data Sheet

AD8671

BAND-PASS FILTER

LOW NOISE OP AMP

MIXER

DEMODULATOR

LOW-PASS FILTER

VGA

ADC

AD10200

AD831

AD8671

AD630

AD8610

AD8369

CODE GENERATOR

03718-B-039

18k

Ω

10kΩ

2.25kΩ

R3

R

B

R

A

V

CC

V

EE

2.25kΩ

R2

2.25k

Ω

R1

1nF

C2

V

IN

1nF

C2

03718-B-040

RCfoπ

=

2

2

K

Q−=

4

2

A

B

R

R

K +=1

Hz

100k1k100 10k

1M

03718-B-041

10M

V

S

= ±15V

200

µV/DIV

10kΩ

R1

V

CC

V

EE

1nF

03718-B-042

VCO

C1

CHARGE

PUMP

PHASE

DETECTOR

IN

D

Figure 37. Simplified Block Diagram of a GPS Receiver

GPS RECEIVER

GPS receivers require low noise to minimize RF effects. The
precision of the AD8671 makes it an excellent choice for such
applications. Its very low noise and wide bandwidth make it
suitable for band-pass and low-pass filters without the penalty
of high power consumption.

Figure 37 shows a simplified block diagram of a GPS receiver.
The next section details the design equations.

BAND-PASS FILTER

Filters are useful in many applications; for example, band-pass
filters are used in GPS systems, as discussed in the previous
section. Figure 38 shows a second-order band-pass KRC filter.

The band-pass response is shown in Figure 39.

The equal component topology yields a center frequency

where:

and

Figure 38. Band-Pass KRC Filter

Rev. F | Page 14 of 20

Figure 39. Band-Pass Response

PLL SYNTHESIZERS AND LOOP FILTERS

Phase-lock loop filters are used in AM/FM modulation.

Loop filters in PLL design require accuracy and care in their
implementation. The AD8671/AD8672/AD8674 are ideal
candidates for such filter design; the low offset voltage and low
input bias current minimize the output error. In addition to the
excellent dc specifications, the AD8671/AD8672/AD8674 have
a unique performance at high frequencies; the high open-loop
gain and wide bandwidth allow the user to design a filter with a
high closed-loop gain if desirable. To optimize the filter design,
it is recommended to use small value resistors to minimize the
thermal noise. A simple example is shown in Figure 40.

Figure 40. PLL Filter Simplified Block Diagram

Data Sheet AD8671/AD8672/AD8674

OUTLINE DIMENSIONS

5.00(0.1968)

4.80(0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES)ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

Figure 41. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

3.20

3.00

2.80

8

5

3.20

3.00

2.80

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

1

0.65 BSC

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 42. 8-Lead Mini Small Outline Package [MSOP]

5.15

4.90

4.65

4

15° MAX

6°
0°

0.23

0.09

0.40

0.25

1.10 MAX

(RM-8)

Dimensions shown in millimeters

0.80

0.55

0.40

10-07-2009-B

Rev. F | Page 15 of 20

AD8671/AD8672/AD8674 Data Sheet

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIME NSIONS ARE IN MILLIMETERS; INCH DIMENSIO NS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMET E R EQUIVALENTS FOR
REFERENCE ONLYAND ARE NO T APPROPRIATE FOR USE IN DE S IGN.

8.75 (0.3445)

8.55 (0.3366)

BSC

8

6.20 (0.2441)

5.80 (0.2283)

7

1.75 (0.0689)

1.35 (0.0531)

SEATING
PLANE

0.25 (0.0098)

0.17 (0.0067)

14

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-012-AB

0.50 (0.0197)

0.25 (0.0098)

8°
0°

1.27 (0.0500)

0.40 (0.0157)

45°

060606-A

Figure 43. 14-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-14)

Dimensions shown in millimeters and (inches)

5.10

5.00

4.90

4.50

4.40

4.30

PIN 1

1.05

1.00

0.80

0.15

0.05

COPLANARITY

0.10

14

1

0.65 BSC

0.30

0.19

COMPLIANT TO JEDEC S TANDARDS MO-153-AB-1

Figure 44. 14-Lead Thin Shrink Small Outline Package [TSSOP]

8

6.40

BSC

7

1.20

0.20

MAX

0.09

SEATING
PLANE

8°
0°

(RU-14)

Dimensions shown in millimeters

0.75

0.60

0.45

061908-A

Rev. F | Page 16 of 20

Data Sheet AD8671/AD8672/AD8674

Model1

Temperature Range

Package Description

Package Option

Branding

AD8672ARZ-REEL

–40°C to +125°C

8-Lead SOIC_N

R-8

ORDERING GUIDE

AD8671ARZ –40°C to +125°C 8-Lead SOIC_N R-8
AD8671ARZ-REEL –40°C to +125°C 8-Lead SOIC_N R-8
AD8671ARZ-REEL7 –40°C to +125°C 8-Lead SOIC_N R-8
AD8671ARMZ –40°C to +125°C 8-Lead MSOP RM-8 A0V
AD8671ARMZ-REEL –40°C to +125°C 8-Lead MSOP RM-8 A0V
AD8672AR –40°C to +125°C 8-Lead SOIC_N R-8
AD8672AR-REEL –40°C to +125°C 8-Lead SOIC_N R-8
AD8672AR-REEL7 –40°C to +125°C 8-Lead SOIC_N R-8
AD8672ARZ –40°C to +125°C 8-Lead SOIC_N R-8

AD8672ARZ-REEL7 –40°C to +125°C 8-Lead SOIC_N R-8
AD8672ARMZ –40°C to +125°C 8-Lead MSOP RM-8 A0W
AD8672ARMZ-REEL –40°C to +125°C 8-Lead MSOP RM-8 A0W
AD8674ARZ –40°C to +85°C 14-Lead SOIC_N R-14
AD8674ARZ-REEL –40°C to +85°C 14-Lead SOIC_N R-14
AD8674ARZ-REEL7 –40°C to +85°C 14-Lead SOIC_N R-14
AD8674ARU –40°C to +85°C 14-Lead TSSOP RU-14
AD8674ARUZ –40°C to +85°C 14-Lead TSSOP RU-14
AD8674ARUZ-REEL –40°C to +85°C 14-Lead TSSOP RU-14

1

Z = RoHS Compliant Part.

Rev. F | Page 17 of 20

AD8671/AD8672/AD8674 Data Sheet

NOTES

Rev. F | Page 18 of 20

Data Sheet AD8671/AD8672/AD8674

NOTES

Rev. F | Page 19 of 20

AD8671/AD8672/AD8674 Data Sheet

NOTES

©2004–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D03718–0–3/13(F)

Rev. F | Page 20 of 20