ANALOG DEVICES AD8610, AD8620 Service Manual

Precision, Very Low Noise,

Low Input Bias Current, Wide Bandwidth

JFET Operational Amplifier

AD8610/AD8620

FEATURES
Low Noise 6 nV/

√

Hz

Low Offset Voltage: 100 ␮V Max
Low Input Bias Current 10 pA Max
Fast Settling: 600 ns to 0.01%
Low Distortion
Unity Gain Stable
No Phase Reversal
Dual-Supply Operation: ⴞ5 V to ⴞ13 V

APPLICATIONS
Photodiode Amplifier
ATE
Instrumentation
Sensors and Controls
High Performance Filters
Fast Precision Integrators
High Performance Audio

GENERAL DESCRIPTION

The AD8610/AD8620 is a very high precision JFET input amplifier
featuring ultralow offset voltage and drift, very low input voltage
and current noise, very low input bias current, and wide bandwidth.
Unlike many JFET amplifiers, the AD8610/AD8620 input bias
current is low over the entire operating temperature range. The
AD8610/AD8620 is stable with capacitive loads of over 1000 pF
in noninverting unity gain; much larger capacitive loads can be
driven easily at higher noise gains. The AD8610/AD8620 swings to
within 1.2 V of the supplies even with a 1 kΩ load, maximizing
dynamic range even with limited supply voltages. Outputs slew at
50 V/µs in either inverting or noninverting gain configurations, and
settle to 0.01% accuracy in less than 600 ns. Combined with the
high input impedance, great precision, and very high output drive, the

FUNCTIONAL BLOCK DIAGRAMS

8-Lead MSOP and SOIC
(RM-8 and R-8 Suffixes)

1

NULL

ⴚIN
ⴙIN

Vⴚ

NC = NO CONNECT

8

AD8610

45

NC
Vⴙ
OUT
NULL

8-Lead SOIC

(R-8 Suffix)

1

OUTA

ⴚINA
ⴙINA

Vⴚ

8

AD8620

45

Vⴙ
OUTB

ⴚINB
ⴙINB

AD8610/AD8620 is an ideal amplifier for driving high performance
A/D inputs and buffering D/A converter outputs.

Applications for the AD8610/AD8620 include electronic instru­ments; ATE amplification, buffering, and integrator circuits;
CAT/MRI/ultrasound medical instrumentation; instrumentation
quality photodiode amplification; fast precision filters (including
PLL filters); and high quality audio.

The AD8610/AD8620 is fully specified over the extended
industrial (–40°C to +125°C) temperature range. The AD8610
is available in the narrow 8-lead SOIC and the tiny MSOP8
surface-mount packages. The AD8620 is available in the narrow
8-lead SOIC package. MSOP8 packaged devices are available
only in tape and reel.

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD8610/AD8620–SPECIFICATIONS

(@ VS = ⴞ5.0 V, VCM = 0 V, TA = 25ⴗC, unless otherwise noted.)

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage (AD8610B) V

Offset Voltage (AD8620B) V

Offset Voltage (AD8610A/AD8620A) V

Input Bias Current I

Input Offset Current I

B

OS

OS

OS

OS

–40°C < T

–40°C < T

+25°C < T
–40°C < T

–40°C < T
–40°C < T

–40°C < T
–40°C < T

< +125°C80200 µV

A

< +125°C80300 µV

A

< 125°C90350 µV

A

< +125°C 150 850 µV

A

–10 +2 +10 pA

< +85°C –250 +130 +250 pA

A

< +125°C –2.5 +1.5 +2.5 nA

A

–10 +1 +10 pA

< +85°C –75 +20 +75 pA

A

< +125°C –150 +40 +150 pA

A

45 100 µV

45 150 µV

85 250 µV

Input Voltage Range –2 +3 V
Common-Mode Rejection Ratio CMRR V
Large Signal Voltage Gain A
Offset Voltage Drift (AD8610B) ∆V
Offset Voltage Drift (AD8620B) ∆V

VO

/∆T –40°C < TA < +125°C 0.5 1 µV/°C

OS

/∆T –40°C < TA < +125°C 0.5 1.5 µV/°C

OS

= –2.5 V to +1.5 V 90 95 dB

CM

RL = 1 kΩ, VO = –3 V to +3 V 100 180 V/mV

Offset Voltage Drift (AD8610A/AD8620A) ∆VOS/∆T –40°C < TA < +125°C 0.8 3.5 µV/°C

OUTPUT CHARACTERISTICS

Output Voltage High V
Output Voltage Low V
Output Current I

OH

OL

OUT

RL = 1 kΩ, –40°C < TA < +125°C 3.8 4 V
RL = 1 kΩ, –40°C < TA < +125°C–4–3.8 V
V

> ±2 V ± 30 mA

OUT

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = ±5 V to ±13 V 100 110 dB
Supply Current/Amplifier I

SY

VO = 0 V 2.5 3.0 mA
–40°C < TA < +125°C 3.0 3.5 mA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 2 kΩ 40 50 V/µs
Gain Bandwidth Product GBP 25 MHz
Settling Time t

S

AV = +1, 4 V Step, to 0.01% 350 ns

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 1.8 µV p-p
Voltage Noise Density e
Current Noise Density i
Input Capacitance C

n

n

IN

f = 1 kHz 6 nV/√Hz
f = 1 kHz 5 fA/√Hz

Differential 8pF
Common-Mode 15 pF

Channel Separation C

S

f = 10 kHz 137 dB
f = 300 kHz 120 dB

Specifications subject to change without notice.

REV. D–2–

AD8610/AD8620

ELECTRICAL SPECIFICATIONS

(@ VS = ⴞ13 V, VCM = 0 V, TA = 25ⴗC, unless otherwise noted.)

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage (AD8610B) V

OS

45 100 µV

–40°C < TA < +125°C80200 µV

Offset Voltage (AD8620B) V

Offset Voltage (AD8610A/AD8620A) V

Input Bias Current I

OS

–40°C < T

OS

+25°C < T
–40°C < T

B

–40°C < T

< +125°C80300 µV

A

< 125°C90350 µV

A

< +125°C 150 850 µV

A

–10 +3 +10 pA

< +85°C –250 +130 +250 pA

A

45 150 µV

85 250 µV

–40°C < TA < +125°C –3.5 +3.5 nA

Input Offset Current I

OS

–40°C < T

< +85°C –75 +20 +75 pA

A

–10 +1.5 +10 pA

–40°C < TA < +125°C –150 +40 +150 pA

Input Voltage Range –10.5 +10.5 V
Common-Mode Rejection Ratio CMRR V
Large Signal Voltage Gain A
Offset Voltage Drift (AD8610B) ∆V
Offset Voltage Drift (AD8620B) ∆V

VO

/∆T –40°C < TA < +125°C 0.5 1 µV/°C

OS

/∆T –40°C < TA < +125°C 0.5 1.5 µV/°C

OS

= –10 V to +10 V 90 110 dB

CM

RL = 1 kΩ, VO = –10 V to +10 V 100 200 V/mV

Offset Voltage Drift (AD8610A/AD8620A) ∆VOS/∆T –40°C < TA < +125°C 0.8 3.5 µV/°C

OUTPUT CHARACTERISTICS

Output Voltage High V
Output Voltage Low V
Output Current I
Short Circuit Current I

OH

OL

OUT

SC

RL = 1 kΩ, –40°C < TA < +125°C +11.75 +11.84 V
RL = 1 kΩ, –40°C < TA < +125°C –11.84 –11.75 V
V

> 10 V ±45 mA

OUT

±65 mA

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = ±5 V to ±13 V 100 110 dB
Supply Current/Amplifier I

SY

VO = 0 V 3.0 3.5 mA
–40°C < TA < +125°C 3.5 4.0 mA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 2 kΩ 40 60 V/µs
Gain Bandwidth Product GBP 25 MHz
Settling Time t

S

AV = 1, 10 V Step, to 0.01% 600 ns

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 1.8 µV p-p
Voltage Noise Density e
Current Noise Density i
Input Capacitance C

n

n

IN

f = 1 kHz 6 nV/√Hz
f = 1 kHz 5 fA/√Hz

Differential 8pF
Common-Mode 15 pF

Channel Separation C

S

f = 10 kHz 137 dB
f = 300 kHz 120 dB

Specifications subject to change without notice.

REV. D

–3–

AD8610/AD8620

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.3 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

S––

to V

S+

Differential Input Voltage . . . . . . . . . . . . . . . ± Supply Voltage

Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite

Storage Temperature Range

R, RM Packages . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C

Operating Temperature Range

AD8610/AD8620 . . . . . . . . . . . . . . . . . . . .–40°C to +125°C

Junction Temperature Range

R, RM Packages . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C

Lead Temperature Range (Soldering, 10 sec) . . . . . . . . 300°C

*Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option Branding

AD8610AR –40°C to +125°C 8-Lead SOIC RN-8
AD8610AR-REEL –40°C to +125°C 8-Lead SOIC RN-8
AD8610AR-REEL7 –40°C to +125°C 8-Lead SOIC RN-8
AD8610ARM-REEL –40°C to +125°C 8-Lead MSOP RM-8 B0A
AD8610ARM-R2 –40°C to +125°C 8-Lead MSOP RM-8 B0A
AD8610ARZ* –40°C to +125°C 8-Lead SOIC RN-8
AD8610ARZ-REEL* –40°C to +125°C 8-Lead SOIC RN-8
AD8610ARZ-REEL7* –40°C to +125°C 8-Lead SOIC RN-8
AD8610BR –40°C to +125°C 8-Lead SOIC RN-8
AD8610BR-REEL –40°C to +125°C 8-Lead SOIC RN-8
AD8610BR-REEL7 –40°C to +125°C 8-Lead SOIC RN-8
AD8610BRZ* –40°C to +125°C 8-Lead SOIC RN-8
AD8610BRZ-REEL* –40°C to +125°C 8-Lead SOIC RN-8
AD8610BRZ-REEL7* –40°C to +125°C 8-Lead SOIC RN-8
AD8620AR –40°C to +125°C 8-Lead SOIC RN-8
AD8620AR-REEL –40°C to +125°C 8-Lead SOIC RN-8
AD8620AR-REEL7 –40°C to +125°C 8-Lead SOIC RN-8
AD8620BR –40°C to +125°C 8-Lead SOIC RN-8
AD8620BR-REEL –40°C to +125°C 8-Lead SOIC RN-8
AD8620BR-REEL7 –40°C to +125°C 8-Lead SOIC RN-8

Package Type ␪JA* ␪

JC

Unit

8-Lead MSOP (RM) 190 44 °C/W
8-Lead SOIC (RN) 158 43 °C/W

*θJA is specified for worst-case conditions; i.e., θ

soldered in circuit board for surface-mount packages.

is specified for a device

JA

*Pb-free part

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8610/AD8620 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. D–4–

Typical Performance Characteristics–AD8610/AD8620

14

12

10

8

6

4

NUMBER OF AMPLIFIERS

2

0

ⴚ150

ⴚ250

ⴚ50

INPUT OFFSET VOLTAGE – ␮V

VS = ⴞ13V

50 150

250

TPC 1. Input Offset Voltage at±13 V

600

400

200

0

–200

–400

INPUT OFFSET VOLTAGE – ␮V

–600

–40 25 85 125

TEMPERATURE – ⴗC

V

S

= ⴞ5V

600

VS = ⴞ13V

400

200

0

ⴚ200

ⴚ400

INPUT OFFSET VOLTAGE – ␮V

ⴚ600

ⴚ40

25 85 125

TEMPERATURE – ⴗC

TPC 2. Input Offset Voltage vs.
Temperature at±13 V (300 Amplifiers)

14

12

10

8

6

4

NUMBER OF AMPLIFIERS

2

0

00.2 0.6 1.0 1.4 1.8 2.2 2.6

VS = ⴞ5V OR ⴞ13V

TCVOS – ␮V/ⴗC

18

16

14

12

10

8

6

4

NUMBER OF AMPLIFIERS

2

0

ⴚ150

ⴚ250

ⴚ50

INPUT OFFSET VOLTAGE – ␮V

VS = ⴞ5V

50 150

250

TPC 3. Input Offset Voltage at±5 V

3.6

3.4

3.2

3.0

2.8

2.6

2.4

INPUT BIAS CURRENT – pA

2.2

2.0
ⴚ10 ⴚ5

COMMON-MODE VOLTAGE – V

0510

VS = ⴞ13V

TPC 4. Input Offset Voltage vs.
Temperature at±5 V (300 Amplifiers)

3.0

2.5

2.0

1.5

1.0

SUPPLY CURRENT – mA

0.5

0

013123456789101112

SUPPLY VOLTAGE – ⴞV

TPC 7. Supply Current vs.
Supply Voltage

TPC 5. Input Offset Voltage Drift

3.05

2.95

2.85

2.75

SUPPLY CURRENT – mA

2.65

2.55
ⴚ40

25 85 125

TEMPERATURE – ⴗC

VS = ⴞ13V

TPC 8. Supply Current vs.
Temperature at±13 V

TPC 6. Input Bias Current vs.
Common-Mode Voltage

2.65
VS = ⴞ5V

2.60

2.55

2.50

2.45

2.40

SUPPLY CURRENT – mA

2.35

2.30

ⴚ40

25 85 125

TEMPERATURE – ⴗC

TPC 9. Supply Current vs.

±

Temperature at

5 V

REV. D

–5–

AD8610/AD8620

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

OUTPUT VOLTAGE TO SUPPLY RAIL– V

0

RESISTANCE LOAD – ⍀

TPC 10. Output Voltage to
Supply Rail vs. Load

12.05
VS = ⴞ13V

= 1k⍀

R

L

12.00

11.95

11.90

11.85

OUTPUT VOLTAGE HIGH – V

11.80

ⴚ40

25 85 125

TEMPERATURE – ⴗC

TPC 13. Output Voltage High

±

vs. Temperature at

13 V

VS = ⴞ13V

4.25
VS = ⴞ5V

= 1k⍀

R

L

4.20

4.15

4.10

4.05

OUTPUT VOLTAGE HIGH – V

4.00

100M10M1M100k10k1k100

3.95

ⴚ40

25 85 125

TEMPERATURE – ⴗC

TPC 11. Output Voltage High vs.

±

Temperature at

ⴚ11.80

ⴚ11.85

ⴚ11.90

ⴚ11.95

OUTPUT VOLTAGE LOW – V

ⴚ12.00

ⴚ12.05

ⴚ40

5 V

25 85 125

TEMPERATURE – ⴗC

VS = ⴞ13V

= 1k⍀

R

L

TPC 14. Output Voltage Low vs.
Temperature at±13 V

OUTPUT VOLTAGE LOW – V

ⴚ3.95

ⴚ4.00

ⴚ4.05

ⴚ4.10

ⴚ4.15

ⴚ4.20

ⴚ4.25

ⴚ4.30

ⴚ40

25 85 125

TEMPERATURE – ⴗC

VS = ⴞ5V
RL = 1k⍀

TPC 12. Output Voltage Low vs.

±

Temperature at

120

VS = ⴞ13V

100

R

= 1k⍀

L

MARKER AT 27MHz

80

␪

= 69.5

M

C

= 20pF

L

60

40

20

0

GAIN – dB

ⴚ20

ⴚ40

ⴚ60

ⴚ80

1

FREQUENCY – MHz

5 V

10

TPC 15. Open-Loop Gain
and Phase vs. Frequency

270

225

180

135

90

45

0

ⴚ45

ⴚ90

ⴚ135

ⴚ180

200100

PHASE – Degrees

60

40

G = 100

20

G = 10

0

G = 1

CLOSED-LOOP GAIN – dB

ⴚ20

ⴚ40

10k 100k 1M1k 10M 100M

FREQUENCY – Hz

V

S

RL = 2k⍀
C

L

TPC 16. Closed-Loop Gain vs.
Frequency

= ⴞ13V

= 20pF

260

240

220

200

180

– V/mV

VO

A

160

140

120

100

ⴚ40

25 85 125

TEMPERATURE – ⴗC

= ⴞ13V

V

S

= ⴞ10V

V

O

= 1k⍀

R

L

TPC 17. AVO vs. Temperature at±13 V

190

180

170

160

150

– V/mV

140

VO

A

130

120

110

100

ⴚ40

25 85 125

TEMPERATURE – ⴗC

VS = ⴞ5V

= ⴞ3V

V

O

RL = 1k⍀

TPC 18. AVO vs. Temperature at±5 V

REV. D–6–

AD8610/AD8620

M

160

140

120

100

80

60

40

PSRR – dB

20

0

–20

–40

+PSRR

–PSRR

FREQUENCY – Hz

= ⴞ13V

V

S

60M10k 100k 1M 10M100 1k

TPC 19. PSRR vs. Frequency at ±13 V

140

120

100

80

60

CMRR – dB

40

20

0

10 60M10k 100k 1M 10M100 1k

FREQUENCY – Hz

V

S

= ⴞ13V

TPC 22. CMRR vs. Frequency

160

140

120

100

80

60

40

PSRR – dB

20

0

–20

–40

–PSRR

10k 100k 1M 10M100 1k
FREQUENCY – Hz

+PSRR

V

S

= ⴞ5V

60

TPC 20. PSRR vs. Frequency at ±5 V

VS = ⴞ13V
VIN = ⴚ300mV p-p

= ⴚ100

A

V

= 10k⍀

R

L

0V

CH2 = 5V/DIV

VOLTA GE – 300mV/DIV

0V

V

IN

V

OUT

TIME – 4␮s/DIV

TPC 23. Positive Overvoltage Recovery

122

121

120

119

PSRR – dB

118

117

116

ⴚ40

25 85

TEMPERATURE – ⴗC

125

TPC 21. PSRR vs. Temperature

VS = ⴞ13V

= 300mV p-p

V

IN

= ⴚ100

A

V

= 10k⍀

R

L

= 0pF

C

L

V

0V

VOLTA GE – 300mV/DIV

CH2 = 5V/DIV

IN

V

OUT

TIME – 4␮s/DIV

TPC 24. Negative Overvoltage
Recovery

0V

V

= ⴞ13V

S

p-p = 1.8␮V

V

IN

P-P VOLTAGE NOISE – 1␮V/DIV

TIME – 1s/DIV

TPC 25. 0.1 Hz to 10 Hz Input Voltage
Noise

1,000

VSY = ⴞ13V

100

10

VOLTA G E NOISE DENSITY – nV/ Hz

1

11M100 10k10 1k 100k

FREQUENCY – Hz

TPC 26. Input Voltage Noise vs.
Frequency

100

90

80

70

60

– ⍀

50

OUT

Z

40

30

20

10

GAIN = 100

0

1k 100M10k 100k 1M 10M

TPC 27. Z

GAIN = 10

FREQUENCY – Hz

vs. Frequency

OUT

VS = ⴞ13V

GAIN = 1

REV. D

–7–

AD8610/AD8620

100

90

80

70

60

– ⍀

50

OUT

Z

40

30

20

10

0

GAIN = 100

1k 100M10k 100k 1M 10M

TPC 28. Z

40

VS = ⴞ5V

35

= 2k⍀

R

L

= 100mV

V

IN

30

25

20

15

10

SMALL SIGNAL OVERSHOOT – %

5

0

1 10k10 100 1k

CAPACITANCE – pF

GAIN = 10

FREQUENCY – Hz

vs. Frequency

OUT

+OS

VS = ⴞ5V

GAIN = 1

ⴚOS

TPC 31. Small Signal Overshoot vs.
Load Capacitance

3000

2500

2000

1500

– pA

B

I

1000

500

0

025

TEMPERATURE – ⴗC

85 125

TPC 29. Input Bias Current vs.
Temperature

VS = ⴞ13V
VIN = ⴞ14V

= +1

A

V

VOLTA GE – 5V/DIV

FREQ = 0.5kHz

V

TIME – 400␮s/DIV

OUT

V

IN

TPC 32. No Phase Reversal

40

VS = ⴞ13V

= 2k⍀

R

35

L

= 100mV p-p

V

IN

30

25

20

15

10

SMALL SIGNAL OVERSHOOT – %

5

0

1 10k10 100 1k

CAPACITANCE – pF

+OS

ⴚOS

TPC 30. Small Signal Overshoot vs.
Load Capacitance

VOLTA GE – 5V/DIV

VS = ⴞ13V

p-p = 20V

V

IN

= +1

A

V

R

= 2k⍀

L

= 20pF

C

L

TIME – 1␮s/DIV

TPC 33. Large Signal Response at
G = +1

VOLTA GE – 5V/DIV

TIME – 400ns/DIV

TPC 34. +SR at G = +1

VS = ⴞ13V

p-p = 20V

V

IN

= +1

A

V

= 2k⍀

R

L

= 20pF

C

L

VOLTA GE – 5V/DIV

VS = ⴞ13V

p-p = 20V

V

IN

= +1

A

V

R

= 2k⍀

L

= 20pF

C

L

TIME – 400ns/DIV

TPC 35. –SR at G = +1

VOLTA GE – 5V/DIV

VS = ⴞ13V
V

p-p = 20V

IN

= ⴚ1

A

V

R

= 2k⍀

L

= 20pF

C

L

TIME – 1␮s/DIV

TPC 36. Large Signal Response at G = –1

REV. D–8–

AD8610/AD8620

FREQUENCY – kHz

0 350

50 100

150 200 250

300

138

136

120

128

126

124

122

132

130

134

CS – dB

VS = ⴞ13V

p-p = 20V

V

IN

= ⴚ1

A

V

= 2k⍀

R

L

SR = 50V/␮s
C

= 20pF

L

VOLTA GE – 5V/DIV

TIME – 400ns/DIV

TPC 37. +SR at G = –1

CS(dB) = 20 log (V

+

V

IN

20V p-p

–

0

/ 10 ⴛ VIN)

OUT

+13V

U1

3

V+

2

V–

–13V

Figure 1. Channel Separation Test Circuit

FUNCTIONAL DESCRIPTION

The AD8610/AD8620 is manufactured on Analog Devices, Inc.’s
proprietary XFCB (eXtra Fast Complementary Bipolar) process.
XFCB is fully dielectrically isolated (DI) and used in conjunc­tion with N-channel JFET technology and trimmable thin-film
resistors to create the world’s most precise JFET input amplifier.
Dielectrically isolated NPN and PNP transistors fabricated on
XFCB have F

greater than 3 GHz. Low TC thin film resistors

T

enable very accurate offset voltage and offset voltage tempco
trimming. These process breakthroughs allowed Analog Devices’
world class IC designers to create an amplifier with faster slew
rate and more than 50% higher bandwidth at half of the current
consumed by its closest competition. The AD8610 is uncondi­tionally stable in all gains, even with capacitive loads well in
excess of 1 nF. The AD8610B achieves less than 100 µV of offset
and 1 µV/°C of offset drift, numbers usually associated with very
high precision bipolar input amplifiers. The AD8610 is offered in
the tiny 8-lead MSOP as well as narrow 8-lead SOIC surface­mount packages and is fully specified with supply voltages from
±5 V to ±13 V. The very wide specified temperature range, up to
125°C, guarantees superior operation in systems with little or no
active cooling.

The unique input architecture of the AD8610 features extremely
low input bias currents and very low input offset voltage. Low
power consumption minimizes the die temperature and maintains
the very low input bias current. Unlike many competitive JFET
amplifiers, the AD8610/AD8620 input bias currents are low even
at elevated temperatures. Typical bias currents are less than 200 pA
at 85°C. The gate current of a JFET doubles every 10°C resulting
in a similar increase in input bias current over temperature.
Special care should be given to the PC board layout to minimize
leakage currents between PCB traces. Improper layout and
board handling generates leakage current that exceeds the bias
current of the AD8610/AD8620.

REV. D

R4

2k⍀

0

VS = ⴞ13V
V
AV = ⴚ1
R
SR = 55V/␮s

C

5

2k⍀

0

p-p = 20V

IN

= 2k⍀

L

= 20pF

L

R1

20k⍀

V–

V+

U2

VOLTA GE – 5V/DIV

TIME – 400ns/DIV

TPC 38. –SR at G = –1

R2

6

2k⍀

7

0

0

Figure 2. AD8620 Channel Separation Graph

Power Consumption

A major advantage of the AD8610/AD8620 in new designs is
the saving of power. Lower power consumption of the AD8610
makes it much
for high-density

more attractive for portable instrumentation and

systems, simplifying thermal management, and

reducing power supply performance requirements. Compare the

consumption

power

of the AD8610/AD8620 versus the OPA627

in Figure 3.

8

7

OPA627

6

5

4

SUPPLY CURRENT – mA

3

AD8610

2

–75 125–50

–25 0 25 50 75 100

TEMPERATURE – ⴗC

Figure 3. Supply Current vs. Temperature

–9–

AD8610/AD8620

Driving Large Capacitive Loads

The AD8610 has excellent capacitive load driving capability and
can safely drive up to 10 nF when operating with ±5 V supply.
Figures 4 and 5 compare the AD8610/AD8620 against the OPA627
in the noninverting gain configuration driving a 10 kΩ resistor and
10,000 pF capacitor placed in parallel on its output, with a square
wave input set to a frequency of 200 kHz. The AD8610 has much
less ringing than the OPA627 with heavy capacitive loads.

VS = ⴞ5V
R

= 10k⍀

L

= 10,000pF

C

L

VOLTA GE – 20mV/DIV

TIME – 2␮s/DIV

Figure 4. OPA627 Driving CL = 10,000 pF

VS = ⴞ5V

R

= 10k⍀

L

C

= 10,000pF

L

+5V

3

VIN = 50mV

2k⍀ 2k⍀

7

2

4

–5V

2␮F

Figure 6. Capacitive Load Drive Test Circuit

VS = ⴞ5V
R

= 10k⍀

L

= 2␮F

C

L

VOLTA GE – 50mV/DIV

TIME – 20␮s/DIV

Figure 7. OPA627 Capacitive Load Drive, AV = +2

VS = ⴞ5V
RL = 10k⍀

= 2␮F

C

L

VOLTA GE – 20mV/DIV

TIME – 2␮s/DIV

Figure 5. AD8610/AD8620 Driving CL = 10,000 pF

The AD8610/AD8620 can drive much larger capacitances without
any external compensation. Although the AD8610/AD8620 is stable
with very large capacitive loads, remember that this capacitive
loading will limit the bandwidth of the amplifier. Heavy
loads will also increase the amount of overshoot and ringing

capacitive

at the

output. Figures 7 and 8 show the AD8610/AD8620 and the OPA627
in a noninverting gain of +2 driving 2 µF of capacitance load. The

Slew Rate (Unity Gain Inverting vs. Noninverting)

Amplifiers generally have a faster slew rate in an inverting unity
gain configuration due to the absence of the differential input
capacitance. Figures 9 through 12 show the performance of the
AD8610 configured in a gain of –1 compared to the OPA627.
The AD8610 slew rate is more symmetrical, and both the positive
and negative transitions are much cleaner than in the OPA627.

ringing on the OPA627 is much larger in magnitude and continues
more than 10 times longer than the AD8610.

VOLTA GE – 50mV/DIV

TIME – 20␮s/DIV

Figure 8. AD8610/AD8620 Capacitive Load Drive, AV = +2

REV. D–10–

AD8610/AD8620

VS = ⴞ13V

= 2k⍀

R

L

G = –1

SR = 54V/␮s

VOLTA GE – 5V/DIV

TIME – 400ns/DIV

Figure 9. (+SR) of AD8610/AD8620 in Unity Gain of –1

VS = ⴞ13V
RL = 2k⍀
G = –1

SR = 42.1V/␮s

VOLTA GE – 5V/DIV

TIME – 400ns/DIV

Figure 10. (+SR) of OPA627 in Unity Gain of –1

VS = ⴞ13V

= 2k⍀

R

L

G = –1

SR = 56V/␮s

VOLTA GE – 5V/DIV

TIME – 400ns/DIV

Figure 12. (–SR) of OPA627 in Unity Gain of –1

The AD8610 has a very fast slew rate of 60 V/µs even when config-
ured in a noninverting gain of +1. This is the toughest condition to
impose on any amplifier since the input common-mode capacitance
of the amplifier generally makes its SR appear worse. The slew
rate of an amplifier varies according to the voltage difference
between its two inputs. To observe the maximum SR as specified
in the AD8610 data sheet, a difference voltage of about 2 V between
the inputs must be ensured. This will be required for virtually any
JFET op amp so that one side of the op amp input circuit is com­pletely off, maximizing the current available to charge and discharge
the internal compensation capacitance. Lower differential
drive voltages will produce lower slew rate readings. A JFET­input op amp with a slew rate of 60 V/µs at unity gain with

= 10 V might slew at 20 V/µs if it is operated at a gain of

V

IN

+100 with V

= 100 mV.

IN

The slew rate of the AD8610/AD8620 is double that of the OPA627
when configured in a unity gain of +1 (see Figures 13 and 14).

VS = ⴞ13V
R

= 2k⍀

L

G = –1

SR = 54V/␮s

VOLTA GE – 5V/DIV

TIME – 400ns/DIV

Figure 11. (–SR) of AD8610/AD8620 in Unity Gain of –1

VS = ⴞ13V
R

= 2k⍀

L

G = +1

SR = 85V/␮s

VOLTA GE – 5V/DIV

TIME – 400ns/DIV

Figure 13. (+SR) of AD8610/AD8620 in Unity Gain of +1

REV. D

–11–

AD8610/AD8620

VS = ⴞ13V
R

= 2k⍀

L

G = +1

SR = 23V/␮s

VOLTA GE – 5V/DIV

TIME – 400ns/DIV

Figure 14. (+SR) of OPA627 in Unity Gain of +1

The slew rate of an amplifier determines the maximum frequency
at which it can respond to a large signal input. This frequency
(known as full-power bandwidth, or FPBW) can be calculated
from the equation:

FPBW

SR

=

V

×

2π

()

PEAK

for a given distortion (e.g., 1%).

CH1 = 20.8V

p-p

diodes greatly interfere with many application circuits such as
precision rectifiers and comparators. The AD8610 is free from
these limitations.

+13V

3

7

14V

V1

0

2

–13V

6

4

AD8610

Figure 16. Unity Gain Follower

No Phase Reversal

Many amplifiers misbehave when one or both of the inputs are
forced beyond the input common-mode voltage range. Phase
reversal is typified by the transfer function of the amplifier,
effectively reversing its transfer polarity. In some cases, this can
cause lockup and even equipment damage in servo systems, and
may cause permanent damage or nonrecoverable parameter
shifts to the amplifier itself. Many amplifiers feature compensation
circuitry to combat these effects, but some are only effective for
the inverting input. The AD8610/AD8620 is designed to prevent
phase reversal when one or both inputs are forced beyond their
input common-mode voltage range.

V

IN

0V

CH2 = 19.4V

VOLTA GE – 10V/DIV

0V

Input Overvoltage Protection

When the input of an amplifier is driven below VEE or above V
by more than one VBE, large currents will flow from the substrate
through the negative supply (V–) or the positive supply
respectively, to the input pins, which can destroy the device.

p-p

TIME – 400ns/DIV

Figure 15. AD8610 FPBW

(V+),

If the

THD Readings vs. Common-Mode Voltage

Total harmonic distortion of the AD8610/AD8620 is well below

0.0006% with any load down to 600 Ω. The AD8610/AD8620

CC

outperforms the OPA627 for distortion, especially at frequen­cies above 20 kHz.

input source can deliver larger currents than the maximum forward
current of the diode (>5 mA), a series resistor can be

added to
protect the inputs. With its very low input bias and offset current, a
large series resistor can be placed in front of the AD8610
limit current to below damaging levels. Series resistance
will generate less than 25 µV of offset. This 10 kΩ will allow

inputs to

of 10 kΩ

input

voltages more than 5 V beyond either power supply. Thermal noise
generated by the resistor will add 7.5 nV/√Hz to the noise of the
AD8610. For the AD8610/AD8620, differential voltages equal to
the supply voltage will not cause any problem (see Figure 15).
In this context, it should also be noted that the high breakdown
voltage of the input FETs eliminates the need to
diodes between the inputs of the amplifier, a practice

include clamp

that is

mandatory on many precision op amps. Unfortunately, clamp

VOLTA GE – 5V/DIV

V

OUT

0

TIME – 400␮s/DIV

Figure 17. No Phase Reversal

0.1

0.01

THD+N – %

0.001

0.0001
10 80k

100 1k 10k

FREQUENCY – Hz

VSY = ⴞ13V
V

= 5V rms

IN

BW = 80kHz

OPA627

AD8610

Figure 18. AD8610 vs. OPA627 THD + Noise @ VCM = 0 V

REV. D–12–

0.1

ERROR BAND – %

1.2k

1.0k

0

0.001 100.01

SETTLING TIME – ns

0.1 1

800

600

200

400

OPA627

CL – pF

0 2000500

SETTLING TIME –

␮

s

1000 1500

ERROR BAND ⴞ0.01%

3.0

2.0

0.0

1.0

2.5

1.5

0.5

VSY = ⴞ13V
R

= 600⍀

L

AD8610/AD8620

0.01

THD + N – %

0.001

4V rms

10 20k

2V rms

6V rms

100 1k 10k

FREQUENCY – Hz

Figure 19. THD + Noise vs. Frequency

Noise vs. Common-Mode Voltage

AD8610 noise density varies only 10% over the input range as
shown in Table I.

Table I. Noise vs. Common-Mode Voltage

VCM at F = 1 kHz (V) Noise Reading (nV/√Hz)

–10 7.21
–5 6.89

06.73
+5 6.41
+10 7.21

Settling Time

The AD8610 has a very fast settling time, even to a very tight error
band, as can be seen from Figure 20. The AD8610 is configured
in an inverting gain of +1 with 2 kΩ input and feedback resistors.
The output is monitored with a 10 ×, 10 M, 11.2 pF scope probe.

1.2k

1.0k

800

600

400

SETTLING TIME – ns

200

0

0.001

0.1 1

ERROR BAND – %

100.01

Figure 20. AD8610 Settling Time vs. Error Band

REV. D

–13–

Figure 21. OPA627 Settling Time vs. Error Band

The AD8610/AD8620 maintains this fast settling when loaded
with large capacitive loads as shown in Figure 22.

Figure 22. AD8610 Settling Time vs. Load Capacitance

3.0

ERROR BAND ⴞ0.01%

2.5

2.0

1.5

1.0

SETTLING TIME – ␮s

0.5

0.0
0 2000500

1000 1500

CL – pF

Figure 23. OPA627 Settling Time vs. Load Capacitance

Output Current Capability

The AD8610 can drive very heavy loads due to its high output
current. It is capable of sourcing or sinking 45 mA at ±10 V output.
The short circuit current is quite high and the part is capable of
sinking about 95 mA and sourcing over 60 mA while operating with

AD8610/AD8620

supplies of ±5 V. Figures 24 and 25 compare the load current
versus output voltage of AD8610/AD8620 and OPA627.

10

1

V

EE

V

CC

DELTA FROM RESPECTIVE RAIL – V

0.1

0.00001 1

0.0001 0.001 0.01 0.1
LOAD CURRENT – A

Figure 24. AD8610 Dropout from ±13 V vs. Load Current

10

V

CC

V

1

DELTA FROM RESPECTIVE RAIL – V

0.1

0.00001 1

0.0001 0.001 0.01 0.1

EE

LOAD CURRENT – A

Figure 25. OPA627 Dropout from ±15 V vs. Load Current

Although operating conditions imposed on the AD8610 (±13 V)
are less favorable than the OPA627 (±15 V), it can be seen that the
AD8610 has much better drive capability (lower headroom to the
supply) for a given load current.

Operating with Supplies Greater than ± 13 V

The AD8610 maximum operating voltage is specified at ±13 V.
When ±13 V is not readily available, an inexpensive LDO can
provide ±12 V from a nominal ±15 V supply.

Input Offset Voltage Adjustment

Offset of AD8610 is very small and normally does not require
additional offset adjustment. However, the offset adjust pins can
be used as shown in Figure 26 to further reduce the dc offset. By
using resistors in the range of 50 kΩ, offset trim range is ±3.3 mV.

+V

S

7

2

3

4

–V

AD8610

5

S

6

1

R1

V

OUT

Figure 26. Offset Voltage Nulling Circuit

Programmable Gain Amplifier (PGA)

The combination of low noise, low input bias current, low input
offset voltage, and low temperature drift make the AD8610 a
perfect solution for programmable gain amplifiers. PGAs are often
used immediately after sensors to increase the dynamic
the measurement circuit. Historically, the large ON resistance

range of

of
switches, combined with the large IB currents of amplifiers,
created a large dc offset in PGAs. Recent and improved monolithic
switches

and amplifiers completely remove these problems. A PGA

discrete circuit is shown in Figure 27. In Figure 27, when the 10 pA
bias current of the AD8610 is dropped across the (<5 Ω) RON of
the switch, it results in a negligible offset error.

When high precision resistors are used, as in the circuit of Figure 27,
the error introduced by the PGA is within the 1/2 LSB requirement
for a 16-bit system.

+5V

V

IN

G

A

A0

B

A1

74HC139

100⍀

AD8610

U10

5

5pF

1

IN1

Y0

Y1

Y2

Y3

16

IN2

9

IN3

8

IN4

V

LVDD

ADG452

V

SS

4

–5V

–5V

+5V+5V

GND

1312

S1

3

D1

2

S2

14

D2

15

S3

11

D3

10

S4

6

D4

7

5

10k⍀

1k⍀

10k⍀

1k⍀

100⍀

11⍀

V

OUT

G = 1

G = 10

G = 10 0

G = 1000

Figure 27. High Precision PGA

1. Room temperature error calculation due to RON and IB:

∆Ω

VIR

=× = × =

OS B ON

Total Offset Offset V

()

Total Offset Offset Trimmed V

(_ )

Total Offset

VpV V

2510

pA pV

=+

AD8610

=+

AD8610

=+ ≅

510 5

µµ

∆

OS

∆

OS

2. Full temperature error calculation due to RON and IB:

∆ΩVIR

(C)(C) (C)

@@ @85 85 85

°= °× °=

OS B ON

pA . nV

250 15 3 75

×=

3. Temperature coefficient of switch and AD8610/AD8620

combined is essentially the same as the T

∆∆ ∆∆ ∆∆

VTtotal V T V T I R

/( ) /( ) /( )

OS OS OS B ON

∆∆

VTtotal

/( ) . V/C. nV/ C .V/C

OS

=+×
=°+ °≅°

05 006 05µµ

AD8610

of the AD8610:

CVOS

REV. D–14–

AD8610/AD8620

High Speed Instrumentation Amplifier (IN AMP)

The three op amp instrumentation amplifiers shown in Figure 28
can provide a range of gains from unity up to 1,000 or higher. The
instrumentation amplifier configuration features high common­mode rejection, balanced differential inputs, and stable, accurately
defined gain. Low input bias currents and fast settling are achieved
with the JFET input AD8610/AD8620. Most instrumentation
amplifiers cannot match the high frequency performance of this
circuit. The circuit bandwidth is 25 MHz at a gain of 1, and close
to 5 MHz at a gain of 10. Settling time for the entire circuit is
550 ns to 0.01% for a 10 V step (gain = 10). Note that the resistors
around the input pins need to be small enough in value so that
the RC time constant they form in combination with stray circuit
capacitance does not reduce circuit bandwidth.

V+

V

IN1

1/2 AD8620

U1

V–

C5

10pF

R1 1k⍀

R4 2k⍀

RG

V

IN2

R7

2k⍀

R8 2k⍀

1/2 AD8620

C4
15pF

U

1

V+

AD8610

U2

V–

R5 2k⍀

15pF

V

OUT

R6
2k⍀

C3

In active filter applications using operational amplifiers, the
dc accuracy of the amplifier is critical to optimal filter performance.
The amplifier’s offset voltage and bias current contribute to output
error. Input offset voltage is passed by the filter, and may be
amplified to produce excessive output offset. For low frequency
applications requiring large value input resistors, bias and offset
currents flowing through these resistors will also generate an
offset voltage.

At higher frequencies, an amplifier’s dynamic response must be
carefully considered. In this case, slew rate, bandwidth, and open­loop gain play a major role in amplifier selection. The slew rate
must be both fast and symmetrical to minimize distortion. The
amplifier’s bandwidth, in conjunction with the filter’s gain, will
dictate the frequency response of the filter. The use of a high perfor­mance

amplifier such as the AD8610/AD8620 will minimize both

dc and ac errors in all active filter applications.

Second-Order Low-Pass Filter

Figure 29 shows the AD8610 configured as a second-order
Butterworth low-pass filter. With the values as shown, the corner
frequency of the filter will be 1 MHz. The wide bandwidth of
the AD8610/AD8620 allows a corner frequency up to tens of
megaHertz. The following equations can be used for component
selection:

R1 R2

== −

User Selected Typical Values

.

1 414

fR

2

π

()( )()

CUTOFF

.

0 707

fR

2

π

()( )()

CUTOFF

C1

C2

=

=

()

1

1

:k k

10 100

ΩΩ

where C1 and C2 are in farads.

C1

22pF

+13V

R2 1k⍀

C2

10pF

Figure 28. High Speed Instrumentation Amplifier

High Speed Filters

The four most popular configurations are Butterworth, Elliptical,
Bessel, and Chebyshev. Each type has a response that is optimized
for a given characteristic as shown in Table II.

Table II. Filter Types

Type Sensitivity Overshoot Phase Amplitude (Pass Band)

Butterworth Moderate Good Max Flat
Chebyshev Good Moderate Nonlinear Equal Ripple
Elliptical Best Poor Equal Ripple
Bessel (Thompson) Poor Best Linear

REV. D

–15–

V

IN

R2

10k⍀R110k⍀

11pF

C2

AD8610

U1

–13V

5

Figure 29. Second-Order Low-Pass Filter

V

OUT

AD8610/AD8620

High Speed, Low Noise Differential Driver

The AD8620 is a perfect candidate as a low noise differential
driver for many popular ADCs. There are also other applications,
such as balanced lines, that require differential drivers. The circuit
of Figure 30 is a unique line driver widely used in industrial applica­tions. With ±13 V supplies, the line driver can deliver a differential
signal of 23 V p-p into a 1 kΩ load. The high slew rate and wide
bandwidth of the AD8620 combine to yield a full power bandwidth
of 145 kHz while the low noise front end produces a referred-to­input noise voltage spectral density of 6 nV/√Hz. The design is a
transformerless, balanced transmission system where output
common-mode rejection of noise is of paramount importance.
Like the transformer-based design, either output can be shorted
to ground for unbalanced line driver applications without changing
the circuit gain of 1. This allows the design to be easily set to
noninverting, inverting, or differential operation.

U2

3

V+

1k⍀

R4

1k⍀

3

V+

6

AD8610

V–

2

R8

0

1k⍀

R9

1k⍀

R3

2

R1

1k⍀

5

6

U3

1

V–

1/2 OF AD8620

V+

7

1/2 OF AD8620

V–

R2

1k⍀

R10
50⍀

R12

1k⍀

R11
50⍀

R13
1k⍀

VO2 – VO1 = VIN

V

1

O

R5
1k⍀

R6
10k⍀

R7
1k⍀

VO2

0

Figure 30. Differential Driver

REV. D–16–

OUTLINE DIMENSIONS

0.25 (0.0098)

0.17 (0.0067)

1.27 (0.0500)

0.40 (0.0157)

0.50 (0.0196)

0.25 (0.0099)

ⴛ 45ⴗ

8ⴗ
0ⴗ

1.75 (0.0688)

1.35 (0.0532)

SEATING

PLANE

0.25 (0.0098)

0.10 (0.0040)

85

41

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

1.27 (0.0500)
BSC

6.20 (0.2440)

5.80 (0.2284)

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-012AA

8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

3.00

BSC

AD8610/AD8620

8-Lead Standard Small Outline Package [SOIC]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

85

3.00
BSC

1

PIN 1

0.65 BSC

0.15

0.00

0.38

0.22

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187AA

4

SEATING
PLANE

4.90
BSC

1.10 MAX

0.23

0.08

8ⴗ
0ⴗ

0.80

0.60

0.40

REV. D

–17–

AD8610/AD8620

Revision History

Location Page

2/04—Data Sheet changed from REV. C to REV. D.

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

10/02—Data Sheet changed from REV. B to REV. C.

Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edits to Figure 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5/02—Data Sheet changed from REV. A to REV. B.

Addition of part number AD8620 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal

Addition of 8-Lead SOIC (R-8 Suffix) Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Additions to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Change to ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Additions to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Replace TPC 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Add Channel Separation Test Circuit Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Add Channel Separation Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Changes to Figure 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Addition of High-Speed, Low Noise Differential Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Addition of Figure 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

–18–

REV. D

–19–

C02730–0–2/04(D)

–20–