ANALOG DEVICES AD 8608 ARZ Datasheet

Precision, Low Noise, CMOS, Rail-to-Rail,

O

O

O

Input/Output Operational Amplifiers

Data Sheet

FEATURES

Low offset voltage: 65 μV maximum
Low input bias currents: 1 pA maximum
Low noise: 8 nV/√Hz
Wide bandwidth: 10 MHz
High open-loop gain: 1000 V/mV
Unity gain stable
Single-supply operation: 2.7 V to 5.5 V
5-ball WLCSP for single (AD8605) and 8-ball WLCSP for

dual (AD8606)

APPLICATIONS

Photodiode amplification
Battery-powered instrumentation
Multipole filters
Sensors
Barcode scanners
Audio

GENERAL DESCRIPTION

The AD8605, AD8606, and AD86081 are single, dual, and quad
rail-to-rail input and output, single-supply amplifiers. They
feature very low offset voltage, low input voltage and current
noise, and wide signal bandwidth. They use the Analog Devices,
Inc. patented DigiTrim® trimming technique, which achieves
superior precision without laser trimming.

The combination of low offsets, low noise, very low input bias
currents, and high speed makes these amplifiers useful in a
wide variety of applications. Filters, integrators, photodiode
amplifiers, and high impedance sensors all benefit from the
combination of performance features. Audio and other ac
applications benefit from the wide bandwidth and low
distortion. Applications for these amplifiers include optical
control loops, portable and loop-powered instrumentation,
and audio amplification for portable devices.

The AD8605, AD8606, and AD8608 are specified over the
extended industrial temperature range (−40°C to +125°C). e

AD8605 single is available in 5-lead SOT-23 and 5-ball WLCSP

packages. The AD8606 dual is available in an 8-lead MSOP, an
8-ball WLSCP, and a narrow SOIC surface-mounted package.
The AD8608 quad is available in a 14-lead TSSOP package and
a narrow 14-lead SOIC package. The 5-ball and 8-ball WLCSP
offer the smallest available footprint for any surface-mounted
operational amplifier. The WLCSP, SOT-23, MSOP, and TSSOP
versions are available in tape-and-reel only.

1

Protected by U.S. Patent No. 5,969,657.

Rev. N Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

AD8605/AD8606/AD8608

PIN CONFIGURATIONS

BALLA1
CORNER

OUTA V+ OUTB

A1 A2 A3

–INA –INB

B1 B3

+INA V– +INB

–IN A

+IN A

+IN B

–IN B

UT B

–IN A
+IN A

V+
+IN B
–IN B

UT B

V+

C1 C2 C3

AD8606

TOP VIEW

(BALL SIDE DO WN)

1

2

3

AD8608

TOP VIEW

4

(Not to Scal e)

5

6

7

1

(Not to Scale)

7

AD8608

TOP VIEW

14

OUT

+IN

V–

1

AD8605

TOP VIEW

2

(Not to Scale)

3

V+

5

–IN

4

2731-001

Figure 1. 5-Lead SOT-23 (RJ Suffix) Figure 2. 8-Ball WLCSP (CB Suffix)

TOP VIE W

(BUMP SIDE DO WN)

OUT V+

135

V–

2

+IN –IN

4

AD8605 ONLY

02731-006

OUT A

Figure 3. 5-Ball WLCSP (CB Suffix) Figure 4. 14-Lead SOIC_N (R Suffix)

18

UT A

–IN A

+IN A

AD8606

TOP VIEW
(Not to Scale)
45

V–

V+

OUT B

–IN B

+IN B

Figure 5. 8-Lead MSOP (RM Suffix),

OUT A

02731-003

Figure 6. 14-Lead TSSOP (RU Suffix)

8-Lead SOIC_N (R Suffix)

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] ©2002–2013 Analog Devices, Inc. All rights reserved.

Technical Support www.analog.com

02731-057

14

OUT D

13

–IN D

12

+IN D

11

V–

10

+IN C

9

–IN C

8

OUT C

02731-004

OUT D
–IN D
+IN D
V–
+IN C
–IN C

8

OUT C

02731-002

AD8605/AD8606/AD8608 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Pin Configurations ........................................................................... 1

Revision History ............................................................................... 3

5 V Electrical Specifications ............................................................ 4

2.7 V Electrical Specifications ......................................................... 6

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Typical Performance Characteristics ............................................. 9

Applications Information .............................................................. 16

Output Phase Reversal ............................................................... 16

Maximum Power Dissipation ................................................... 16

Input Overvoltage Protection ................................................... 16

THD + Noise ............................................................................... 16

Total Noise Including Source Resistors ................................... 17

Channel Separation .................................................................... 17

Capacitive Load Drive ............................................................... 17

Light Sensitivity .......................................................................... 18

WLCSP Assembly Considerations ........................................... 18

I-V Conversion Applications ........................................................ 19

Photodiode Preamplifier Applications .................................... 19

Audio and PDA Applications ................................................... 19

Instrumentation Amplifiers ...................................................... 20

DAC Conversion ........................................................................ 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 24

Rev. N | Page 2 of 24

Data Sheet AD8605/AD8606/AD8608

REVISION HISTORY

4/13—Rev. M to Rev. N

Changes to Input Overvoltage Section and THD + Noise

Section ......................................................................................... 16

Changes to Total Noise Including Source Resistors Section ...... 17

Updated Outline Dimensions ................................................... 24

2/13—Rev. L to Rev. M

Updated Outline Dimensions ................................................... 21

Changes to Ordering Guide ...................................................... 24

2/12—Rev. K to Rev. L

Changed Functional Block Diagrams Section to Pin

Configuration Section ................................................................. 1

Changes to Figure 11 ................................................................... 9

Added Figure 33 ......................................................................... 13

8/11—Rev. J to Rev. K

Changes to Figure 20 ................................................................... 2

Updated Outline Dimensions ................................................... 20

Changes to Ordering Guide ...................................................... 23

8/10—Rev. I to Rev. J

Changes to Figure 10 and Figure 11 .......................................... 9

Changes to Figure 15 ................................................................. 10

Changes to Figure 36 ................................................................. 13

Changes to Figure 42 ................................................................. 14

Updated Outline Dimensions ................................................... 20

Changes to Ordering Guide ...................................................... 23

9/08—Rev. H to Rev. I

Changes to Input Overvoltage Protection Section ................ 15

Changes to Ordering Guide ...................................................... 22

2/08—Rev. G to Rev. H

Changes to Features ..................................................................... 1

Changes to Table 1 ....................................................................... 4

Changes to Table 2 ....................................................................... 6

Changes to Figure 11 ................................................................... 9

Changes to Figure 13, Figure 14, and Figure 16 Captions .... 10

Changes to Figure 15, Figure 17, and Figure 18 ..................... 10

Changes to Figure 34 and Figure 35 Captions........................ 13

Changes to Figure 36 ................................................................. 13

Changes to Figure 37 Caption .................................................. 14

Changes to Figure 38 and Figure 41 ........................................ 14

Changes to Figure 45 ................................................................. 15

Changes to Audio and PDA Applications Section ................. 18

Changes to Figure 52 ................................................................. 18

Changes to Ordering Guide ...................................................... 22

10/07—Rev. F to Rev. G

Changes to Figure 2...................................................................... 1

Updated Outline Dimensions ................................................... 20

8/07—Rev. E to Rev. F

Added 8-Ball WLCSP Package ..................................... Universal

Changes to Features ..................................................................... 1

Changes to Table 1 ....................................................................... 3

Changes to Table 2 ........................................................................ 5

Changes to Table 4 ........................................................................ 7

Updated Outline Dimensions................................................... 19

Changes to Ordering Guide ...................................................... 21

1/06—Rev. D to Rev. E

Changes to Table 1 ........................................................................ 3

Changes to Table 2 ........................................................................ 5

Changes to Table 4 ........................................................................ 6

Changes to Figure 12 Caption ..................................................... 8

Changes to Figure 26 and Figure 27 Captions ....................... 11

Changes to Figure 33 Caption .................................................. 12

Changes to Figure 44 ................................................................. 14

Updated Outline Dimensions................................................... 19

Changes to Ordering Guide ...................................................... 20

5/04—Rev. C to Rev. D

Updated Format ............................................................. Universal

Edit to Light Sensitivity Section ............................................... 16

Updated Outline Dimensions................................................... 19

Changes to Ordering Guide ...................................................... 20

7/03—Rev. B to Rev. C

Changes to Features ....................................................................... 1

Change to General Description .................................................... 1

Addition to Functional Block Diagrams ..................................... 1

Addition to Absolute Maximum Ratings .................................... 4

Addition to Ordering Guide ......................................................... 4

Change to Equation in Maximum Power Dissipation

Section .......................................................................................... 11

Added Light Sensitivity Section ................................................ 12

Added New Figure 8; Renumbered Subsequently .................. 13

Added New MicroCSP Assembly Considerations Section .... 13

Changes to Figure 9 .................................................................... 13

Change to Equation in Photodiode Preamplifier

Applications Section .................................................................. 13

Changes to Figure 12 .................................................................. 14

Change to Equation in D/A Conversion Section .................... 14

Updated Outline Dimensions ................................................... 15

3/03—Rev. A to Rev. B

Changes to Functional Block Diagram ....................................... 1

Changes to Absolute Maximum Ratings..................................... 4

Changes to Ordering Guide ........................................................ 4

Changes to Figure 9 ................................................................... 13

Updated Outline Dimensions.................................................... 15

11/02—Rev. 0 to Rev. A

Change to Electrical Characteristics ............................................ 2

Changes to Absolute Maximum Ratings..................................... 4

Changes to Ordering Guide ......................................................... 4

Change to TPC 6 ........................................................................... 5

Updated Outline Dimensions.................................................... 15

5/02—Revision 0: Initial Version

Rev. N | Page 3 of 24

AD8605/AD8606/AD8608 Data Sheet

Input Bias Current

IB

0.2

1

pA

Phase Margin

ΦM 65 Degrees

5 V ELECTRICAL SPECIFICATIONS

VS = 5 V, VCM = VS/2, TA = 25°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS

AD8605/AD8606 (Exce pt WLCSP) VS = 3.5 V, VCM = 3 V 20 65 µV
AD8608 VS = 3.5 V, VCM = 2.7 V 20 75 µV
AD8605/AD8606/AD8608 VS = 5 V, VCM = 0 V to 5 V 80 300 µV

−40°C < TA < +125°C 750 µV

AD8605/AD8606 −40°C < TA < +85°C 50 pA
AD8605/AD8606 −40°C < TA < +125°C 250 pA
AD8608 −40°C < TA < +85°C 100 pA
AD8608 −40°C < TA < +125°C 300 pA

Input Offset Current IOS 0.1 0.5 pA

−40°C < TA < +85°C 20 pA

−40°C < TA < +125°C 75 pA

Input Voltage Range 0 5 V

Common-Mode Rejection Ratio CMRR VCM = 0 V to 5 V 85 100 dB

−40°C < TA < +125°C 75 90 dB

Large Signal Voltage Gain AVO RL = 2 kΩ, VO = 0.5 V to 4.5 V 300 1000 V/mV

Offset Voltage Drift

AD8605/AD8606 ΔVOS/ΔT −40°C < TA < +125°C 1 4.5 µV/°C
AD8608 ΔVOS/ΔT −40°C < TA < +125°C 1.5 6.0 µV/°C

INPUT CAPACITANCE

Common-Mode Input Capacitance C

Differential Input Capacitance C
OUTPUT CHARACTERISTICS

Output Voltage High VOH IL = 1 mA 4.96 4.98 V

IL = 10 mA 4.7 4.79 V

−40°C < TA < +125°C 4.6 V

Output Voltage Low VOL IL = 1 mA 20 40 mV

IL= 10 mA 170 210 mV

−40°C < TA < +125°C 290 mV

Output Current I

Closed-Loop Output Impedance Z
POWER SUPPLY

Power Supply Rejection Ratio PSRR

AD8605/AD8606 VS = 2.7 V to 5.5 V 80 95 dB
AD8605/AD8606 WLCSP VS = 2.7 V to 5.5 V 75 92 dB
AD8608 VS = 2.7 V to 5.5 V 77 92 dB

−40°C < TA < +125°C 70 90 dB

Supply Current/Amplifier ISY I

−40°C < TA < +125°C 1.4 mA
DYNAMIC PERFORMANCE

Slew Rate SR RL = 2 kΩ, CL = 16 pF 5 V/µs

Settling Time tS To 0.01%, 0 V to 2 V step, AV = 1 <1 µs

Unity Gain Bandwidth Product GBP 10 MHz

8.8 pF

COM

2.6 pF

DIFF

±80 mA

OUT

f = 1 MHz, AV = 1 1 Ω

OUT

= 0 mA 1 1.2 mA

OUT

Rev. N | Page 4 of 24

Data Sheet AD8605/AD8606/AD8608

Current Noise Density

in

f = 1 kHz

0.01 pA/√Hz

Parameter Symbol Conditions Min Typ Max Unit

NOISE PERFORMANCE

Peak-to-Peak Noise en p-p f = 0.1 Hz to 10 Hz 2.3 3.5 µV p-p
Voltage Noise Density en f = 1 kHz 8 12 nV/√Hz
en f = 10 kHz 6.5 nV/√Hz

Rev. N | Page 5 of 24

AD8605/AD8606/AD8608 Data Sheet

Input Bias Current

IB

0.2

1

pA

POWER SUPPLY

Slew Rate

SR

RL = 2 kΩ, CL = 16 pF

5 V/µs

2.7 V ELECTRICAL SPECIFICATIONS

VS = 2.7 V, VCM = VS/2, TA = 25°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS

AD8605/AD8606 (Exce pt WLCSP) VS = 3.5 V, VCM = 3 V 20 65 µV
AD8608 VS = 3.5 V, VCM = 2.7 V 20 75 µV
AD8605/AD8606/AD8608 VS = 2.7 V, VCM = 0 V to 2.7 V 80 300 µV

−40°C < TA < +125°C 750 µV

AD8605/AD8606 −40°C < TA < +85°C 50 pA
AD8605/AD8606 −40°C < TA < +125°C 250 pA
AD8608 −40°C < TA < +85°C 100 pA
AD8608 −40°C < TA < +125°C 300 pA

Input Offset Current IOS 0.1 0.5 pA

−40°C < TA < +85°C 20 pA

−40°C < TA < +125°C 75 pA

Input Voltage Range 0 2.7 V

Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.7 V 80 95 dB

−40°C < TA < +125°C 70 85 dB

Large Signal Voltage Gain AVO RL = 2 kΩ, VO = 0.5 V to 2.2 V 110 350 V/mV

Offset Voltage Drift

AD8605/AD8606 ΔVOS/ΔT −40°C < TA < +125°C 1 4.5 µV/°C
AD8608 ΔVOS/ΔT −40°C < TA < +125°C 1.5 6.0 µV/°C

INPUT CAPACITANCE

Common-Mode Input Capacitance C

Differential Input Capacitance C
OUTPUT CHARACTERISTICS

Output Voltage High VOH IL = 1 mA 2.6 2.66 V

−40°C < TA < +125°C 2.6 V

Output Voltage Low VOL IL = 1 mA 25 40 mV

−40°C < TA < +125°C 50 mV

Output Current I

Closed-Loop Output Impedance Z

8.8 pF

COM

2.6 pF

DIFF

±30 mA

OUT

f = 1 MHz, AV = 1 1.2 Ω

OUT

Power Supply Rejection Ratio PSRR

AD8605/AD8606 VS = 2.7 V to 5.5 V 80 95 dB
AD8605/AD8606 WLCSP VS = 2.7 V to 5.5 V 75 92 dB
AD8608 VS = 2.7 V to 5.5 V 77 92 dB

−40°C < TA < +125°C 70 90 dB

Supply Current/Amplifier I

−40°C < TA < +125°C 1.5 mA
DYNAMIC PERFORMANCE

Settling Time tS To 0.01%, 0 V to 1 V step, AV = 1 <0.5 µs

Unity Gain Bandwidth Product GBP 9 MHz

Phase Margin Φ

I

SY

M

= 0 mA 1.15 1.4 mA

OUT

50 Degrees

Rev. N | Page 6 of 24

Data Sheet AD8605/AD8606/AD8608

Current Noise Density

in

f = 1 kHz

0.01 pA/√Hz

Parameter Symbol Conditions Min Typ Max Unit

NOISE PERFORMANCE

Peak-to-Peak Noise en p-p f = 0.1 Hz to 10 Hz 2.3 3.5 µV p-p
Voltage Noise Density en f = 1 kHz 8 12 nV/√Hz
en f = 10 kHz 6.5 nV/√Hz

Rev. N | Page 7 of 24

AD8605/AD8606/AD8608 Data Sheet

All Packages

−65°C to +150°C

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage 6 V
Input Voltage GND to V
Differential Input Voltage 6 V
Output Short-Circuit Duration to GND Observe Derating Curves
Storage Temperature Range

All Packages −65°C to +150°C
Operating Temperature Range

All Packages −40°C to +125°C
Junction Temperature Range

Lead Temperature (Soldering, 60 sec) 300°C

S

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Table 4.

Package Type θ

5-Ball WLCSP (CB) 170 °C/W
5-Lead SOT-23 (RJ) 240 92 °C/W
8-Ball WLCSP (CB) 115 °C/W
8-Lead MSOP (RM) 206 44 °C/W
8-Lead SOIC_N (R) 157 56 °C/W
14-Lead SOIC_N (R) 105 36 °C/W
14-Lead TSSOP (RU) 148 23 °C/W

1

θJA is specified for the worst-case conditions, that is, a device soldered in a

circuit board for surface-mount packages.

1

θJC Unit

JA

ESD CAUTION

Rev. N | Page 8 of 24

Data Sheet AD8605/AD8606/AD8608

OFFSET VO

LTAGE (µV)

NUMBER OF AMPLIFIERS

4500

4000

0

2000

1500

1000

500

3000

2500

3500

300–200

–100

0

100

200

–300

V

S

= 5V
TA = 25°C
VCM = 0V

T

O 5V

02731-007

TCVOS (µV/°C)

12

0

4.80.4

NUMBER OF AMPLIFIERS

0.8 1.6 2.4 3.2

4.0

16

8

4

24

20

4.4

V

S

= 5V

T

A

= –40°C

TO +125°C

V

CM

= 2.5V

0 1.2

2.0 2.8 3.6

02731-008

TCVOS (µV/°C)

20

10

0

2.60.2

NUMBER OF AMPLIFIERS

0.4 0.6 0.8 1.0 1.2 1.4

1.6 1.8 2.0

14

6

2

2.2 2.4

12

16

8

4

18

0

V

S

= 5V
TA = –40°C TO +125°C
V

CM

= 2.5V

02731-009

0

02731-010

–0.30

–0.25

–0.20

–0.15

–0.10

–0.05

0.05

0.10

0.15

0.20

0.

25

0.

30

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

VCM(V)

V

OS

(

mV)

VS = 5V

250

200

150

100

50

0

–150

–100

–50

–50 –25 0 25 50 75 100 125

INPUT BIAS CURRE NT (pA)

TEMPERATURE (°C)

02731-011

VSY = 5V
V

CM

= V

SY

/2

AD8605
AD8606
AD8608

LOAD CURRENT ( mA)

1k

10

0.1

0.001 100.01

OUTPUT S

A

TURA

TION VOLT

AGE (mV)

0.1

1

100

1

SINKSOURCE

VS = 5V
T

A

= 25°C

02731-012

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 7. Input Offset Voltage Distribution

Figure 8. AD8608 Input Offset Voltage Drift Distribution

Figure 10. Input Offset Voltage vs. Common-Mode Voltage

(200 Units, 5 Wafer Lots, Including Process Skews)

Figure 11. Input Bias Current vs. Temperature

Figure 9. AD8605/AD8606 Input Offset Voltage Drift Distribution

Figure 12. Output Saturation Voltage vs. Load Current

Rev. N | Page 9 of 24

AD8605/AD8606/AD8608 Data Sheet

TEMPER

ATURE (°C)

5.00

4.95

4.70

OUTPUT VOLTAGE (V)

4.85

4.75

4.90

4.80

V

OH

@ 1m

A LOAD

V

S

= 5V

V

OH

@ 10mA

LOAD

–40 –25

–10 5

20

35 50

65

80 95

110

125

02731-013

0.25

0

0.15

0.05

0.20

0.10

TEMPERA

TURE (°C)

OUTPUT VOLTAGE (V)

V

OL

@ 1m

A

LOAD

VS = 5V

V

OL

@ 10m

A

LOAD

–40 –25

–10 5

20

35 50

65 80 95 110 125

02731-014

GAIN (dB)

100

80

–100

60

40

20

0

–20

–40

–60

–80

225

180

–225

135

90

45

0

–45

–90

–135

–180

PHASE (Degrees)

FREQUENCY ( Hz )

10k 40M

100k 1M 10M

VS = ±2.5V
R

L

= 2kΩ

CL = 20pF

ΦM = 64°

02731-015

PHASE

GAIN

FREQUENCY (Hz)

6

5

0

1k 10M10k

OUTPUT SWING (V p-p)

100k 1M

4

3

1

2

V

S

= 5V

V

IN

= 4.9V p-p
TA = 25°C
R

L

= 2kΩ

AV = 1

02731-016

FREQUENCY

(Hz)

100

90

0

1k

100M10k

100k 1M

10M

80

70

20

60

50

30

10

40

V

S

= 5V

A

V

= 100

A

V

= 1

A

V

= 10

02731-017

OUTPUT IMPEDANCE (Ω)

FREQUENCY (Hz)

10k

CMRR (dB)

100k 1M

20

120

1k 10M

90

80

70

60

50

40

30

110

100

VS = 5V

02731-018

Figure 13. Output Voltage Swing High vs. Temperature

Figure 14. Output Voltage Swing Low vs. Temperature

Figure 16. Closed-Loop Output Voltage Swing (FPBW)

Figure 17. Output Impedance vs. Frequency

Figure 15. Open-Loop Gain and Phase vs. Frequency

Rev. N | Page 10 of 24

Figure 18. Common-Mode Rejection Ratio (CMRR) vs. Frequency

Data Sheet AD8605/AD8606/AD8608

FREQUENCY (Hz)

140

80

–60

1k 10M10k

PSRR (dB)

100k 1M

40

0

–40

100

120

60

20

–20

VS = 5V

02731-019

CAP

ACITANCE (pF)

45

40

0

10 1k100

SMALL SIGNAL OVERSHOOT (%)

35

30

10

25

20

15

5

VS = 5V
RL =

∞

TA = 25°C
AV = –1

+OS

–OS

02731-020

TEMPER

ATURE (°C)

2.0

0

SUPPLY CURRENT/AMPLIFIE R ( mA)

–40 125–25 –10 95 110

1.5

1.0

0.5

5 20 35 50 65 80

02731-021

VS = 2.7V

VS = 5V

SUPPLY VOLTAGE (V)

1.0

0.4

0

SUPPLY CURRENT/AMPLIFIE R ( mA)

0.9

0.5

0.3

0.1

0.7

0.6

0.2

0.8

0 5.04.54.03.53.02.52.01.51.00.5

02731-022

TIME (1s/DIV)

VOLTAGE NOISE (1µV/DIV)

V

S

= 5V

02731-023

TIME (200ns/DIV)

VO

LTAG E ( 50mV /DIV)

02731-024

V

S

= ±2.5V

RL = 10kΩ
CL = 200pF
A

V

= 1

Figure 19. PSRR vs. Frequency

Figure 20. Small Signal Overshoot vs. Load Capacitance

Figure 22. Supply Current/Amplifier vs. Supply Voltage

Figure 23. 0.1 Hz to 10 Hz Input Voltage Noise

Figure 21. Supply Current/Amplifier vs. Temperature

Figure 24. Small Signal Transient Response

Rev. N | Page 11 of 24

AD8605/AD8606/AD8608 Data Sheet

TIME (400ns/DIV)

VOLTAGE (1V/DIV)

VS = ±2.5V
R

L

= 10kΩ

C

L

= 200pF

A

V

= 1

02731-025

TIME (400ns/DIV)

2.5V

–50mV

0V

V

OUT

V

IN

0V

V

S

= ±2.5V

R

L

= 10kΩ

A

V

= –100

V

IN

= 50mV

02731-026

V

S

= ±2.5V
RL = 10kΩ
AV = –100
V

IN

= 50mV

TIME (1µs/DIV)

–2.5V
50mV

0V

0V

02731-027

FREQUENCY

(kHz)

36

20

4

32

28

12

8

24

16

V

S

= ±2.5V

VOLTAGE NOISE DENSITY (nV/ Hz)

0 1.00.90.80.70.60.50.40.3

0.2

0.1

02731-028

0

6.7

20.1

13.4

26.8

40.2

33.5

53.6

46.9

FREQUENCY (kHz)

VS = ±2.5V

VOLTAGE NOISE DENSITY (nV/ Hz)

0 10987654321

02731-029

0

14.9

44.7

29.8

59.6

89.4

74.5

119.2

104.3

FREQUENCY (Hz)

V

S

= ±2.5V

VOLTAGE NOISE DENSITY (nV/ Hz)

0 100908070605040302010

02731-030

Figure 25. Large Signal Transient Response

Figure 26. Positive Overload Recovery

Figure 28. Voltage Noise Density vs. Frequency

Figure 29. Voltage Noise Density vs. Frequency

Figure 27. Negative Overload Recovery

Figure 30. Voltage Noise Density vs. Frequency

Rev. N | Page 12 of 24

Data Sheet AD8605/AD8606/AD8608

1800

1600

0

NUMBER OF AMPLIFIERS

800

600

400

200

1200

1000

1400

OFFSET VOLTAGE (µV)

300–200 –100

200

–300

VS = 2.7V
TA = 25°C
VCM = 0V TO 2.7V

0 100

02731-031

COMMON-MODE VOLTAGE (V)

300

200

–300

0

2.7

INPUT OFFSET VOLTAGE (µV)

100

0

–200

–100

1.8

0.90

VS = 2.7V
TA = 25°C

02731-032

250

200

150

100

50

0

–150

–100

–50

–50 –25 0

25 50 75 100 125

INPUT BIAS CURRE NT (pA)

TEMPERATURE (°C)

02731-039

V

SY

= 2.7V

V

CM

= VSY/2

AD8605
AD8606
AD8608

LOAD CURRENT ( mA)

1k

10

0.1

0.001 100.01

OUTPUT SATUR

ATION VOLTAGE (mV)

0.1

1

100

1

SOURCE

SINK

VS = 2.7V
T

A

= 25°C

02731-033

TEMPERATURE (°C)

2.680

2.675

2.650
5 20 1255035

OUTPUT VOLTAGE (V)

65 80 95 110

2.665

2.655

2.670

2.660

–10–25–40

V

S

= 2.7V

V

OH

@ 1mA LOAD

02731-034

0.045

0.025

0

0.035

0.015

0.005

0.030

0.040

0.020

0.010

TEMPERATURE (°C)

5 20 1255035

OUTPUT VOLTAGE (V)

65 80 95 110–10–25–40

V

S

= 2.7V

VOL @ 1mA LOAD

02731-035

Figure 31. Input Offset Voltage Distribution

Figure 32. Input Offset Voltage vs. Common-Mode Voltage

(200 Units, 5 Wafer Lots, Including Process Skews)

Figure 34. Output Saturation Voltage vs. Load Current

Figure 35. Output Voltage Swing High vs. Temperature

Figure 33. Input Bias Current vs. Temperature

Figure 36. Output Voltage Swing Low vs. Temperature

Rev. N | Page 13 of 24

AD8605/AD8606/AD8608 Data Sheet

FREQUENCY ( Hz )

10k 40M

100k

GAIN (dB)

100

80

–100

60

40

20

0

–20

–40

–60

–80

225

180

–225

135

90

45

0

–45

–90

–135

–180

PHASE (Degrees)

1M

10M

02731-036

V

S

= 2.7V
RL = 2kΩ
C

L

= 20pF

Φ

M

= 52.5°

PHASE

GAIN

FREQUENC

Y

(Hz)

3.0

2.5

0

1k

10M10k

OUTPUT SWING (V p-p)

100k 1M

2.0

1.5

0.5

1.0

02731-037

V

S

= 2.7V

V

IN

= 2.6V p-p

T

A

= 25°C

R

L

= 2kΩ

A

V

= 1

FREQUENCY (Hz)

100

90

0

1k

100M

10k 100k 1M 10M

80

70

20

60

50

30

10

40

A

V

= 100

A

V

= 10

A

V

= 1

VS = 2.7V

02731-038

OUTPUT IMPEDANCE (Ω)

CAPACITANCE (pF)

60

50

0

10 1k100

SMALL SIGNAL OVERSHOOT (%)

30

20

10

40

–OS

+OS

V

S

= 2.7V

T

A

= 25°C

A

V

= 1

02731-039

TIME (1s/DIV)

V

S

= 2.7V

VOLTAGE NOISE (1µV/ DIV)

02731-040

TIME (200ns/DIV)

VOLT

AGE (50mV/DIV)

02731-041

VS = ±1.35V
RL = 10kΩ
CL = 200pF
A

V

= 1

Figure 37. Open-Loop Gain and Phase vs. Frequency

Figure 38. Closed-Loop Output Voltage Swing vs. Frequency (FPBW)

Figure 40. Small Signal Overshoot vs. Load Capacitance

Figure 41. 0.1 Hz to 10 Hz Input Voltage Noise

Figure 39. Output Impedance vs. Frequency

Figure 42. Small Signal Transient Response

Rev. N | Page 14 of 24

Data Sheet AD8605/AD8606/AD8608

TIME (400ns/DIV)

VOLTAGE (500mV/DIV )

VS = ±1.35V
RL = 10kΩ
CL = 200pF
AV = 1

02731-042

Figure 43. Large Signal Transient Response

Rev. N | Page 15 of 24

AD8605/AD8606/AD8608 Data Sheet

JA

A

J

DISS

TT

P

θ

−

=

mA5≤

−

S

S

IN

R

VV

TIME (4µs/DIV)

VO

LT

AGE (2V/DIV)

V

OUT

V

IN

V

S

= ±2.5V
VIN = 6V p-p
A

V

= 1
RL = 10kΩ

02731-043

AMBIENT TEMPERATURE (°C)

1.0

0.8

0

–45

130–20

POWER DISSI

PA

TION (W)

30 80 105

0.6

0.4

0.2

1.7

1.8

1.6

1.4

1.2

02731-044

TSSOP-14

5 55

1.5

1.3

1.1

0.9

0.7

0.5

0.3

0.1

5-LEAD SO

T

-23

MSOP-8

SOIC-14

WLCSP-5

SOIC-8

FREQUENC

Y (Hz)

0.1

0.01

0.0001
20 20k100

THD + NOISE ( %)

1k

0.001

10k

VSY = ±2.5V
AV = 1
BW = 80kHz

02731-045

APPLICATIONS INFORMATION

OUTPUT PHASE REVERSAL

Phase reversal is defined as a change in polarity at the output of
the amplifier when a voltage that exceeds the maximum input
common-mode voltage drives the input.

Phase reversal can cause permanent damage to the amplifier; it
can also cause system lockups in feedback loops. The AD8605
does not exhibit phase reversal even for inputs exceeding the
supply voltage by more than 2 V.

MAXIMUM POWER DISSIPATION

Power dissipated in an IC causes the die temperature to
increase, which can affect the behavior of the IC and the
application circuit performance.

The absolute maximum junction temperature of the AD8605/

AD8606/AD8608 is 150°C. Exceeding this temperature could

damage or destroy the device.
The maximum power dissipation of the amplifier is calculated

according to

Figure 44. No Phase Reversal

where:

T
T

θ
Figure 45 compares the maximum power dissipation with

temperature for the various AD860x family packages.

INPUT OVERVOLTAGE PROTECTION

The AD860x has internal protective circuitry. However, if the
voltage applied at either input exceeds the supplies by more
than 0.5 V, external resistors should be placed in series with
the inputs. The resistor values can be determined by

The remarkable low input offset current of the AD860x (<1 pA)
allows the use of larger value resistors. With a 10 kΩ resistor at
the input, the output voltage has less than 10 nV of error voltage.
A 10 kΩ resistor has less than 13 nV/√Hz of thermal noise at
room temperature.

THD + NOISE

Total harmonic distortion is the ratio of the input signal in V rms
to the total harmonics in V rms throughout the spectrum.
Harmonic distortion adds errors to precision measurements
and adds unpleasant sonic artifacts to audio systems.

The AD860x has a low total harmonic distortion. Figure 46 shows
that the AD8605 has less than 0.005% or −86 dB of THD + N
over the entire audio frequency range. The AD8605 is configured
in positive unity gain, which is the worst case, and with a load
of 10 kΩ.

is the junction temperature.

J

is the ambient temperature.

A

is the junction-to-ambient thermal resistance.

JA

Figure 45. Maximum Power Dissipation vs. Ambient Temperature

Figure 46. THD + Noise vs. Frequency

Rev. N | Page 16 of 24

Data Sheet AD8605/AD8606/AD8608

(

)

SS

nn

TOTAL

n

TRk

R

ie

e 4

2

2

,

+

+

=

( )

BWeE

TOTALnn,

=

CHANNEL SEPARATION (dB)

FREQUENCY (Hz)

10M1M100k10k1k100 100M

–20

0

–40

–60

–80

–100

–120

–140

–160

–180

02731-046

TIME (10µ s/DIV)

VOLT

AGE (100mV/DIV)

02731-047

VS = ±2.5V
A

V

= 1
RL = 10kΩ
C

L

= 1000pF

R

S

C

S

R

L

C

L

V+

V–

4

2

3

8

1

AD8605

V

IN

200mV

02731-049

TOTAL NOISE INCLUDING SOURCE RESISTORS

The low input current noise and input bias current of the
AD860x make it the ideal amplifier for circuits with substantial
input source resistance, such as photodiodes. Input offset voltage
increases by less than 0.5 nV per 1 kΩ of source resistance at
room temperature and increases to 10 nV at 85°C. The total
noise density of the circuit is

where:

e

is the input voltage noise density of the AD860x.

n

i

is the input current noise density of the AD860x.

n

R

is the source resistance at the noninverting terminal.

S

k is Boltzmann’s constant (1.38 × 10
T is the ambient temperature in Kelvin (T = 273 + °C).

For example, with R

= 10 kΩ, the total voltage noise density is

S

roughly 15 nV/√Hz.
For R

< 3.9 kΩ, en dominates and e

S

The current noise of the AD860x is so low that its total density
does not become a significant term unless R

The total equivalent rms noise over a specific bandwidth is
expressed as

−23

J/K).

≈ en.

n, TOTAL

is greater than 6 MΩ.

S

A snubber network, shown in Figure 49, helps reduce the signal
overshoot to a minimum and maintain stability. Although this
circuit does not recover the loss of bandwidth induced by large
capacitive loads, it greatly reduces the overshoot and ringing.
This method does not reduce the maximum output swing of the
amplifier.

Figure 47. Channel Separation vs. Frequency

where BW is the bandwidth in hertz.
Note that the previous analysis is valid for frequencies greater

than 100 Hz and assumes relatively flat noise, above 10 kHz. For
lower frequencies, flicker noise (1/f) must be considered.

CHANNEL SEPARATION

Channel separation, or inverse crosstalk, is a measure of the signal
feed from one amplifier (channel) to another on the same IC.

The AD8606 has a channel separation of greater than −160 dB
up to frequencies of 1 MHz, allowing the two amplifiers to
amplify ac signals independently in most applications.

CAPACITIVE LOAD DRIVE

The AD860x can drive large capacitive loads without oscillation.
Figure 48 shows the output of the AD8606 in response to a
200 mV input signal. In this case, the amplifier is configured
in positive unity gain, worst case for stability, while driving a
1000 pF load at its output. Driving larger capacitive loads in
unity gain can require the use of additional circuitry.

Figure 48. AD8606 Capacitive Load Drive Without Snubber

Figure 49. Snubber Network Configuration

Rev. N | Page 17 of 24

AD8605/AD8606/AD8608 Data Sheet

TIME (10µ s/DIV)

VOLTAGE (100mV/DIV)

V

S

= ±2.5V
AV = 1
RL = 10kΩ
RS = 90Ω
C

L

= 1000pF
CS = 700pF

02731-048

C

(pF)

RS (Ω)

C

(pF)

WAVELENGTH (nm)

3500

0

350

INPUT BIAS CURRE NT (pA)

2500

3000

2000

500

1000

1500

450 550 650 750 850

1mW/cm

2

4000

4500

5000

3mW/cm

2

2mW/cm

2

02731-050

Figure 50 shows a scope of the output at the snubber circuit.
The overshoot is reduced from over 70% to less than 5%, and
the ringing is eliminated by the snubber. Optimum values for R
and C

are determined experimentally.

S

S

Figure 50. Capacitive Load Drive with Snubber

Table 5 summarizes a few optimum values for capacitive loads.

Table 5.

L

S

500 100 1000
1000 70 1000
2000 60 800

An alternate technique is to insert a series resistor inside the
feedback loop at the output of the amplifier. Typically, the value
of this resistor is approximately 100 Ω. This method also reduces
overshoot and ringing but causes a reduction in the maximum
output swing.

LIGHT SENSITIVITY

The AD8605ACB (WLCSP package option) is essentially a
silicon die with additional postfabrication dielectric and
intermetallic processing designed to contact solder bumps
on the active side of the chip. With this package type, the die
is exposed to ambient light and is subject to photoelectric
effects. Light sensitivity analysis of the AD8605ACB mounted
on standard PCB material reveals that only the input bias
current (I
illuminated directly by high intensity light. No degradation in
electrical performance is observed due to illumination by low
intensity (0.1 mW/cm
increases with increasing wavelength and intensity of incident
light; I
3 mW/cm
shown in Figure 51 are not normal for most applications, that is,
even though direct sunlight can have intensities of 50 mW/cm
office ambient light can be as low as 0.1 mW/cm

) parameter is impacted when the package is

B

2

) ambient light. Figure 51 shows that IB

can reach levels as high as 4500 pA at a light intensity of

B

2

and a wavelength of 850 nm. The light intensities

2

.

Rev. N | Page 18 of 24

2

Figure 51. AD8605ACB Input Bias Current Response to Direct Illumination of

Varying Intensity and Wavelength

When the WLCSP package is assembled on the board with the
bump side of the die facing the PCB, reflected light from the
PCB surface is incident on active silicon circuit areas and results
in the increased I

. No performance degradation occurs due to

B

illumination of the backside (substrate) of the AD8605ACB.
The AD8605ACB is particularly sensitive to incident light with
wavelengths in the near infrared range (NIR, 700 nm to 1000 nm).
Photons in this waveband have a longer wavelength and lower
energy than photons in the visible (400 nm to 700 nm) and near
ultraviolet (NUV, 200 nm to 400 nm) bands; therefore, they can
penetrate more deeply into the active silicon. Incident light with
wavelengths greater than 1100 nm has no photoelectric effect
on the AD8605ACB because silicon is transparent to wavelengths
in this range. The spectral content of conventional light sources
varies. Sunlight has a broad spectral range, with peak intensity
in the visible band that falls off in the NUV and NIR bands;
fluorescent lamps have significant peaks in the visible but not
the NUV or NIR bands.

Efforts have been made at a product level to reduce the effect of
ambient light; the under bump metal (UBM) has been designed
to shield the sensitive circuit areas on the active side (bump
side) of the die. However, if an application encounters any light
sensitivity with the AD8605ACB, shielding the bump side of the
WLCSP package with opaque material should eliminate this
effect. Shielding can be accomplished using materials such as
silica-filled liquid epoxies that are used in flip-chip underfill
techniques.

WLCSP ASSEMBLY CONSIDERATIONS

For detailed information on the WLCSP PCB assembly and
reliability, see Application Note AN-617, MicroCSP™ Wafer

,

Level Chip Scale Package.

Data Sheet AD8605/AD8606/AD8608

R

D

I

D

C

D

50p

F

AD8605

V

OUT

PHOTODIODE

V

OS

R

F

10MΩ

C

F

10pF

02731-051

BF

D

F

OSO

IR

R

R

VE +















+=

1

FF

t

MAX

CR

f

f

π

2

=

5V

4

2

3

8

1

HEADPHONES

5V

4

6

5

8

7

C1

1µF

V1
500mV

1/2
AD8606

C3

100µF

1/2
AD8606

C4

100µF

C2

1µF

V2
500mV

02731-052

R1

20kΩ

R2

20kΩ

R7

20kΩ

R8

20kΩ

R4

20Ω

R3

1kΩ

R6

20Ω

R5

1kΩ

I-V CONVERSION APPLICATIONS

PHOTODIODE PREAMPLIFIER APPLICATIONS

The low offset voltage and input current of the AD8605 make
it an excellent choice for photodiode applications. In addition,
the low voltage and current noise make the amplifier ideal for
application circuits with high sensitivity.

Figure 52. Equivalent Circuit for Photodiode Preamp

The input bias current of the amplifier contributes an error
term that is proportional to the value of R

The offset voltage causes a dark current induced by the shunt
resistance of the Diode R

. These error terms are combined at

D

the output of the amplifier. The error voltage is written as

Typically, R

is smaller than RD, thus RF/RD can be ignored.

F

.

F

At room temperature, the AD8605 has an input bias current of

0.2 pA and an offset voltage of 100 µV. Typical values of R

are

D

in the range of 1 GΩ.
For the circuit shown in Figure 52, the output error voltage is

approximately 100 µV at room temperature, increasing to about
1 mV at 85°C.

The maximum achievable signal bandwidth is

is the unity gain frequency of the amplifier.

where f

t

AUDIO AND PDA APPLICATIONS

The low distortion and wide dynamic range of the AD860x
make it a great choice for audio and PDA applications,
including microphone amplification and line output buffering.

Figure 53 shows a typical application circuit for headphone/
line-out amplification.

R1 and R2 are used to bias the input voltage at half the supply,
which maximizes the signal bandwidth range. C1 and C2 are
used to ac couple the input signal. C1, R1, and R2 form a high­pass filter whose corner frequency is 1/[2π(R1||R2)C1].

The high output current of the AD8606 allows it to drive heavy
resistive loads.

The circuit in Figure 53 is tested to drive a 16 Ω headphone. The
THD + N is maintained at approximately −60 dB throughout the
audio range.

Figure 53. Single-Supply Headphone/Speaker Amplifier

Rev. N | Page 19 of 24

AD8605/AD8606/AD8608 Data Sheet

AD8605

5V

V2

V1

R1

1kΩ

R3

1kΩ

R2

10kΩ

R4

10kΩ

V

OUT

R4
R3

R2
R1

=

V

OUT

= (V2 – V1)

R2
R1

02731-053

FREQUENCY (Hz)

120

100

0

100

10M1k

CMRR (dB)

10k 100k 1M

60

40

20

80

AV = 10

VSY = ±2.5V

AV = 1

02731-054

R2

AD8605

V

OS

R

F

C

F

R2 R2

V+

V–

02731-055

R

RR

V

REF















+

=

1

Req

R

VE

F

OS

O

R

FB

V

DD

DB11

OUT1

AD7545

AGND

R

CS

R

P

V

IN

15V

V

OUT

V

REF

1/2
AD8606

1/2
AD8606

C1
33pF

02731-056

R4

5kΩ

R2

10kΩ

R1

10kΩ

R3

20kΩ

INSTRUMENTATION AMPLIFIERS

The low offset voltage and low noise of the AD8605 make it an
ideal amplifier for instrumentation applications.

Difference amplifiers are widely used in high accuracy circuits
to improve the common-mode rejection ratio. Figure 54 shows
a simple difference amplifier. Figure 55 shows the common­mode rejection for a unity gain configuration and for a gain of 10.

Making (R4/R3) = (R2/R1) and choosing 0.01% tolerance yields
a CMRR of 74 dB and minimizes the gain error at the output.

Figure 54. Difference Amplifier, A

= 10

V

Figure 55. Difference Amplifier CMRR vs. Frequency

DAC CONVERSION

The low input bias current and offset voltage of the AD8605
make it an excellent choice for buffering the output of a current
output DAC.

Figure 56 shows a typical implementation of the AD8605 at the
output of a 12-bit DAC.

The DAC8143 output current is converted to a voltage by the
feedback resistor. The equivalent resistance at the output of the
DAC varies with the input code, as does the output capacitance.

To optimize the performance of the DAC, insert a capacitor in
the feedback loop of the AD8605 to compensate the amplifier
for the pole introduced by the output capacitance of the DAC.
Typical values for C
adjusted for the best frequency response. The total error at the
output of the op amp can be computed by

where Req is the equivalent resistance seen at the output of the
DAC. As previously mentioned, Req is code dependent and
varies with the input. A typical value for Req is 15 kΩ.
Choosing a feedback resistor of 10 kΩ yields an error of less
than 200 µV.

Figure 57 shows the implementation of a dual-stage buffer
at the output of a DAC. The first stage is used as a buffer.
Capacitor C1 with Req creates a low-pass filter, and thus,
provides phase lead to compensate for frequency response.
The second stage of the AD8606 is used to provide voltage
gain at the output of the buffer.

Grounding the positive input terminals in both stages reduces
errors due to the common-mode output voltage. Choosing R1,
R2, and R3 to match within 0.01% yields a CMRR of 74 dB and
maintains minimum gain error in the circuit.

Rev. N | Page 20 of 24

Figure 56. Simplified Circuit of the DAC8143 with AD8605 Output Buffer

range from 10 pF to 30 pF; it can be

F

Figure 57. Bipolar Operation

Data Sheet AD8605/AD8606/AD8608

0

0

OUTLINE DIMENSIONS

0.940

0.900

0.860

BALL A1

IDENTIFIER

0.610

0.555

0.500

SEATING

PLANE

TOP VIEW

(BALL S IDE DOW N)

SIDE VIEW

0.280

0.260

0.240

1.330

1.290

1.250

0.50

BSC

0.866
REF

0.50 BSC

COPLANARIT Y

0.05

0.230

0.200

0.170

Figure 58. 5-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-5-1)

Dimensions shown in millimeters

3.00

2.90

2.80

12

BOTTOM VIEW

(BALL SIDE UP)

A

B

C

02-15-2013-B

.15 MAX
.05 MIN

1.30

1.15

0.90

1.70

1.60

1.50

5

123

4

1.90
BSC

0.50 MAX

0.35 MIN

COMPLIANT TO JEDEC STANDARDS MO-178-AA

0.95 BSC

1.45 MAX

0.95 MIN

3.00

2.80

2.60

SEATING
PLANE

0.20 MAX

0.08 MIN

10°

0.55

0.60

5°

BSC

0°

0.45

0.35

11-01-2010-A

Figure 59. 5-Lead Small Outline Transistor Package [SOT-23]

(RJ-5)

Dimensions shown in millimeters

Rev. N | Page 21 of 24

AD8605/AD8606/AD8608 Data Sheet

COMPLIANT TO JEDEC STANDARDS MO-187-AA

6°
0°

0.80

0.55

0.40

4

8

1

5

0.65 BSC

0.40

0.25

1.10 MAX

3.20

3.00

2.80

COPLANARITY

0.10

0.23

0.09

3.20

3.00

2.80

5.15

4.90

4.65

PIN 1

IDENTIFIER

15° MAX

0.95

0.85

0.75

0.15

0.05

10-07-2009-B

C

O

NT

RO

LLIN

G DI

MEN

SION

S AR

E IN

M

I

L

L

I

ME

T

E

R

S

;

I

NC

H D

I

ME

NS

I

ONS

(

I

N P

AR

ENT

HES

ES) A

RE R

OUN

DED

-O

F

F

M

I

L

LI

M

E

T

E

R

EQ

U

IV

AL

E

NT

S FO

R

RE

F

ER

ENC

E ON

LYA

ND A

RE NO

T A

PP

RO

P

R

I

A

T

E

F

O

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E

SI

GN.

C

O

M

P

L

IA

N

T

T

O

J

E

D

EC

S

TA

ND

A

RDS

MS-

012-

AA

0

12

40

7

-A

0

.2

5

(

0

.

0

0

9

8

)

0

.

1

7

(

0

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0

0

6

7)

1

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7

(0

.050

0)

0.40

(0.

015

7)

0

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(0

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1

96

)

0.

2

5 (

0.

0

09

9

)

4

5°

8

°

0

°

1

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5 (

0

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68

8

)

1

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5

(0

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5

3

2)

SE

A

TI

NG

P

L

A

N

E

0.2

5 (

0.

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5

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3

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6

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(

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4

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1

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Figure 60. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

Figure 61. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

Rev. N | Page 22 of 24

Data Sheet AD8605/AD8606/AD8608

1.480

1.430

1.380

1.825

1.775

1.725

0.27

0.24

0.21

0.380

0.355

0.330

0.340

0.320

0.300

0.675

0.595

0.515

08-10-2012-A

BOTTOM VIEW

(BALL SIDE UP)

TOP VIEW

(BALL SIDE DOWN)

SIDE VIEW

1.00

REF

0.50

BSC

BALL A1

IDENTIFIER

SEATING

PLANE

COPLANARITY

0.05

A

123

B

C

CONTROLLING DIMENSIONSARE IN MI LLIMETERS; INCH DI M E NS IONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE O NLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-012-AB

060606-A

14

8

7

1

6.20 (0.2441)

5.80 (0.2283)

4.00 (0.1575)

3.80 (0.1496)

8.75 (0.3445)

8.55 (0.3366)

1.27 (0.0500)
BSC

SEATING
PLANE

0.25 (0.0098)

0.10 (0.0039)

0.51 (0.0201)

0.31 (0.0122)

1.75 (0.0689)

1.35 (0.0531)

0.50 (0.0197)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

0.25 (0.0098)

0.17 (0.0067)

COPLANARITY

0.10

8°
0°

45°

Figure 62. 8-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-8-1)

Dimensions shown in millimeters

Figure 63. 14-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-14)

Dimensions shown in millimeters and (inches)

Rev. N | Page 23 of 24

AD8605/AD8606/AD8608 Data Sheet

COMPLI ANT TO JEDEC STANDARDS MO-153-AB- 1

061908-A

8°
0°

4.50

4.40

4.30

14

8

7

1

6.40
BSC

PIN 1

5.10

5.00

4.90

0.65 BSC

0.15

0.05

0.30

0.19

1.20
MAX

1.05

1.00

0.80

0.20

0.09

0.75

0.60

0.45

COPLANARITY

0.10

SEATING
PLANE

AD8606ARMZ-R7

−40°C to +125°C

8-Lead MSOP

RM-8

B6A#

©2002–2013 Analog Devices, Inc. All rights reserved. Trademarks and

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option Branding

AD8605ACBZ-REEL −40°C to +125°C 5-Ball WLCSP CB-5-1 A1J
AD8605ACBZ-REEL7 −40°C to +125°C 5-Ball WLCSP CB-5-1 A1J
AD8605ART-REEL −40°C to +125°C 5-Lead SOT-23 RJ-5 B3A
AD8605ARTZ-R2 −40°C to +125°C 5-Lead SOT-23 RJ-5 B3A#
AD8605ARTZ-REEL −40°C to +125°C 5-Lead SOT-23 RJ-5 B3A#
AD8605ARTZ-REEL7 −40°C to +125°C 5-Lead SOT-23 RJ-5 B3A#
AD8606ARM-REEL −40°C to +125°C 8-Lead MSOP RM-8 B6A

AD8606ARMZ-REEL −40°C to +125°C 8-Lead MSOP RM-8 B6A#
AD8606AR −40°C to +125°C 8-Lead SOIC_N R-8
AD8606AR-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8606AR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
AD8606ARZ −40°C to +125°C 8-Lead SOIC_N R-8
AD8606ARZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8606ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
AD8606ACBZ-REEL7 −40°C to +125°C 8-Ball WLCSP CB-8-1 B6A#
AD8608ARZ −40°C to +125°C 14-Lead SOIC_N R-14
AD8608ARZ-REEL −40°C to +125°C 14-Lead SOIC_N R-14
AD8608ARZ-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14
AD8608ARUZ −40°C to +125°C 14-Lead TSSOP RU-14
AD8608ARUZ-REEL −40°C to +125°C 14-Lead TSSOP RU-14

1

Z = RoHS Compliant Part, # denotes RoHS compliant product (except for CB-5-1) may be top or bottom marked.

registered trademarks are the property of their respective owners.
D02731-0-4/13(N)

Figure 64. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters and (inches)

Rev. N | Page 24 of 24