Datasheet AD8605 Datasheet (Analog Devices)

Precision Low Noise CMOS Rail-to-Rail

A

O

A

O

FEATURES

Low offset voltage: 65 µV maximum
Low input bias currents: 1 pA maximum

Hz

Low noise: 8 nV/√
Wide bandwidth: 10 MHz
High open-loop gain: 120 dB
Unity gain stable
Single-supply operation: 2.7 V to 5.5 V
MicroCSP™

GENERAL DESCRIPTION

The AD8605, AD8606, and AD86081 are single, dual, and quad
rail-to-rail input and output, single-supply amplifiers. They
feature very low offset voltage, low input voltage and current
noise, and wide signal bandwidth. They use Analog Devices’
patented DigiTrim® trimming technique, which achieves
superior precision without laser trimming.

The combination of low offsets, low noise, very low input bias
currents, and high speed makes these amplifiers useful in a
wide variety of applications. Filters, integrators, photodiode
amplifiers, and high impedance sensors all benefit from the
combination of performance features. Audio and other ac
applications benefit from the wide bandwidth and low
distortion. Applications for these amplifiers include optical
control loops, portable and loop-powered instrumentation,
and audio amplification for portable devices.

The AD8605, AD8606, and AD8608 are specified over the
extended industrial temperature range (−40°C to +125°C). The
AD8605 single is available in the 5-lead SOT-23 and 5-bump
MicroCSP packages. The 5-bump MicroCSP offers the smallest
available footprint for any surface-mount operational amplifier.
The AD8606 dual is available in an 8-lead MSOP package and a
narrow SOIC surface-mount package. The AD8608 quad is
available in a 14-lead TSSOP and a narrow 14-lead SOIC
package. MicroCSP, SOT, MSOP, and TSSOP versions are
available in tape and reel only.

Input/Output Operational Amplifiers

AD8605/AD8606/AD8608

APPLICATIONS

Photodiode amplification
Battery-powered instrumentation
Multipole filters
Sensors
Barcode scanners
Audio

FUNCTIONAL BLOCK DIAGRAMS

OUT

1

V–

AD8605

2

3

+IN

Figure 1. 5-Lead SOT-23 (RT Suffix) Figure 2. 8-Lead SOIC (R Suffix)

TOP VIEW

(BUMP SIDE DOWN)

OUT V+

135

V–

+IN –IN

AD8605 ONLY

Figure 3. 5-Bump MicroCSP

(CB Suffix)

OUT A

–IN A
+IN A

V–

18

AD8606

45

Figure 5. 8-Lead MSOP (RM Suffix) Figure 6. 14-Lead TSSOP (RU Suffix)

V+

5

–IN

4

02731-D-001

2

4

02731-D-006

OUT

–IN A
+IN A

OUT A

–IN A
+IN A

+IN B
–IN B

OUT B

1
2

AD8608

3
4

V–

1

2

3

AD8608

4

V+

5

6

7

8
7
6
5

14

13

12

11

10

9

8

V+
OUT B
–IN B
+IN B

OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C

02731-D-005

02731-D-004

Figure 4. 14-Lead SOIC (R Suffix)

02731-D-003

UT
–IN A
+IN A

+IN B
–IN B

UT B

V+
OUT B

–IN B
+IN B

1

AD8608

V+

7

OUT D

14

–IN D
+IN D
V–
+IN C
–IN C

8

OUT C

02731-D-002

1

Protected by U.S. Patent No. 5,969,657; other patents pending.

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD8605/AD8606/AD8608

TABLE OF CONTENTS

5 V Electrical Specifications............................................................ 3

Channel Separation.................................................................... 14

2.7 V Electrical Specifications......................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Typical Performance Characteristics............................................. 7

Application Information................................................................ 13

Output Phase Reversal............................................................... 13

Maximum Power Dissipation ...................................................13

Input Overvoltage Protection................................................... 13

THD + Noise............................................................................... 13

Total Noise Including Source Resistors................................... 14

REVISION HISTORY

5/04—Data Sheet Changed from Rev. C to Rev. D

Updated Format............................................................. Universal

Edit to Light Sensitivity Section ...............................................16

Updated Outline Dimensions................................................... 19

Changes to Ordering Guide......................................................20

7/03—Data Sheet Changed from Rev. B to Rev. C

Changes to Features.......................................................................1

Change to General Description................................................... 1

Addition to Functional Block Diagrams ....................................1

Addition to Absolute Maximum Ratings................................... 4

Addition to Ordering Guide ........................................................4

Change to Equation In Maximum Power Dissipation

Section........................................................................................11

Added Light Sensitivity Section.................................................12

Added New Figure 8 and Renumbered Subsequent Figures .13

Added New MicroCSP Assembly Considerations Section ....13

Changes to Figure 9.....................................................................13

Change to Equation in Photodiode Preamplifier

Applications Section ................................................................13

Changes to Figure 12...................................................................14

Change to Equation in D/A Conversion Section ....................14

Updated Outline Dimensions ................................................... 15

Capacitive Load Drive ...............................................................14

Light Sensitivity .......................................................................... 15

MicroCSP Assembly Considerations....................................... 15

I-V Conversion Applications........................................................ 16

Photodiode Preamplifier Applications ....................................16

Audio and PDA Applications ................................................... 16

Instrumentation Amplifiers ...................................................... 17

D/A Conversion ......................................................................... 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 19

3/03—Data Sheet Changed from Rev. A to Rev. B

Changes to Functional Block Diagram.......................................1

Changes to Absolute Maximum Ratings.................................... 4

Changes to Ordering Guide ....................................................... 4

Changes to Figure 9 ....................................................................13

Updated Outline Dimensions.................................................... 15

11/02—Data Sheet Changed from Rev. 0 to Rev. A

Change to Electrical Characteristics........................................... 2

Changes to Absolute Maximum Ratings.................................... 4

Changes Ordering Guide .............................................................4

Change to TPC 6 ..........................................................................5

Updated Outline Dimensions.................................................... 15

Rev. D | Page 2 of 20

AD8605/AD8606/AD8608

5 V ELECTRICAL SPECIFICATIONS

Table 1. @ VS = 5 V, VCM = VS/2, TA = 25°C, unless otherwise noted.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS

AD8605/AD8606 VS = 3.5 V, VCM = 3 V 20 65 µV
AD8608 VS = 3.5 V, VCM = 2.7 V 20 75 µV

V

−40°C < TA < +125°C 750 µV
Input Bias Current IB 0.2 1 pA

AD8605/AD8606 −40°C < TA < +85°C 50 pA
AD8605/AD8606 −40°C < TA < +125°C 250 pA
AD8608 −40°C < TA < +85°C 100 pA
AD8608 −40°C < TA < +125°C 300 pA

Input Offset Current IOS 0.1 0.5 pA

−40°C < TA < +85°C 20 pA

−40°C < TA < +125°C 75 pA
Input Voltage Range 0 5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 5 V 85 100 dB

−40°C < TA < +125°C 75 90 dB
Large Signal Voltage Gain AVO VO = 0.5 V to 4.5 V 300 1,000 V/mV
R
Offset Voltage Drift

AD8605/AD8606 ∆VOS/∆T 1 4.5 µV/°C
AD8608 ∆VOS/∆T 1.5 6.0 µV/°C

INPUT CAPACITANCE

Common-Mode Input Capacitance 8.8 pF
Differential Input Capacitance 2.59 pF

OUTPUT CHARACTERISTICS

Output Voltage High VOH IL = 1 mA 4.96 4.98 V
I

−40°C < TA < +125°C 4.6 V
Output Voltage Low VOL IL = 1 mA 20 40 mV
I

−40°C < TA < +125°C 290 mV
Output Current I
Closed-Loop Output Impedance Z

±80 mA

OUT

f = 1 MHz, AV = 1 10 Ω

OUT

POWER SUPPLY

Power Supply Rejection Ratio PSRR

AD8605/AD8606 VS = 2.7 V to 5.5 V 80 95 dB
AD8608 VS = 2.7 V to 5.5 V 77 92 dB

−40°C < TA < +125°C 70 90 dB
Supply Current/Amplifier ISY VO = 0 V 1 1.2 mA

−40°C < TA < +125°C 1.4 mA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 2 kΩ 5 V/µs
Settling Time tS To 0.01%, 0 V to 2 V step < 1 µs
Full Power Bandwidth BWP < 1% distortion 360 kHz
Gain Bandwidth Product GBP 10 MHz
Phase Margin

ϕ

O

= 5 V, VCM = 0 V to 5 V 80 300 µV

S

= 2 kΩ, VCM = 0 V

L

= 10 mA 4.7 4.79 V

L

= 10 mA 170 210 mV

L

65 Degrees

Rev. D | Page 3 of 20

AD8605/AD8606/AD8608

Parameter Symbol Conditions Min Typ Max Unit

NOISE PERFORMANCE

Peak-to-Peak Noise en p-p f = 0.1 Hz to 10 Hz 2.3 3.5 µV p-p
Voltage Noise Density en f = 1 kHz 8 12

Voltage Noise Density en f = 10 kHz 6.5
Current Noise Density in f = 1 kHz 0.01

nV/√
nV/√
pA/√

Hz
Hz
Hz

Rev. D | Page 4 of 20

AD8605/AD8606/AD8608

2.7 V ELECTRICAL SPECIFICATIONS

Table 2. @ VS = 2.7 V, VCM = VS/2, TA = 25°C, unless otherwise noted.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage VOS

AD8605/AD8606
AD8608

Input Bias Current IB

AD8605/AD8606
AD8605/AD8606
AD8608
AD8608

Input Offset Current IOS

Input Voltage Range
Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.7 V 80 95

Large Signal Voltage Gain AVO RL = 2 kΩ, VO= 0.5 V to 2.2 V 110 350
Offset Voltage Drift

AD8605/AD8606 ∆VOS/∆T
AD8608 ∆VOS/∆T

INPUT CAPACITANCE

Common-Mode Input Capacitance
Differential Input Capacitance

OUTPUT CHARACTERISTICS

Output Voltage High VOH IL = 1 mA 2.6 2.66

Output Voltage Low VOL IL = 1 mA

Output Current I
Closed-Loop Output Impedance Z

POWER SUPPLY

Power Supply Rejection Ratio PSRR

AD8605/AD8606
AD8608

Supply Current/Amplifier ISY VO = 0 V

DYNAMIC PERFORMANCE

Slew Rate SR RL = 2 kΩ
Settling Time tS To 0.01%, 0 V to 1 V step
Gain Bandwidth Product GBP
Phase Margin

NOISE PERFORMANCE

VS = 3.5 V, VCM = 3 V
VS = 3.5 V, VCM = 2.7 V

= 2.7 V, VCM = 0 V to 2.7 V

V

S

−40°C < T

< +125°C

A

−40°C < TA < +85°C

−40°C < TA < +125°C

−40°C < TA < +85°C

−40°C < TA < +125°C

−40°C < T

−40°C < T

< +85°C

A

< +125°C

A

0

20 65 µV
20 75 µV
80 300 µV

750 µV

0.2 1 pA
50 pA
250 pA
100 pA
300 pA

0.1 0.5 pA
20 pA
75 pA

2.7 V

−40°C < T

< +125°C 70 85

A

1 4.5 µV/°C

1.5 6.0 µV/°C

8.8

2.59

−40°C < T

−40°C < T

OUT

f = 1 MHz, AV = 1

OUT

< +125°C 2.6

A

< +125°C

A

25 40 mV

50 mV

±30
12

VS = 2.7 V to 5.5 V 80 95
VS = 2.7 V to 5.5 V 77 92

−40°C < T

−40°C < T

< +125°C 70 90

A

< +125°C

A

1.15 1.4 mA

1.5 mA

ϕ

O

5
< 0.5
9
50

Peak-to-Peak Noise en p-p f = 0.1 Hz to 10 Hz 2.3 3.5 µV p-p
Voltage Noise Density en f = 1 kHz 8 12

Voltage Noise Density en f = 10 kHz 6.5
Current Noise Density in f = 1 kHz 0.01

dB
dB
V/mV

pF
pF

V
V

mA
Ω

dB
dB
dB

V/µs
µs
MHz
Degrees

Hz

nV/√

Hz

nV/√

Hz

pA/√

Rev. D | Page 5 of 20

AD8605/AD8606/AD8608

ABSOLUTE MAXIMUM RATINGS

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Table 3.

Parameter Rating

Supply Voltage 6 V
Input Voltage GND to V
Differential Input Voltage 6 V
Output Short-Circuit Duration

Observe Derating Curves

to GND

Storage Temperature Range

All Packages −65°C to +150°C

Operating Temperature Range

AD8605/AD8606/AD8608 −40°C to +125°C

Junction Temperature Range

All Packages −65°C to +150°C

Lead Temperature Range

300°C

(Soldering, 60 sec)

S

Table 4. Package Type

Package Type θ

1

θJC Unit

JA

5-Bump MicroCSP (CB) 220 220 °C/W
5-Lead SOT-23 (RT) 230 92 °C/W
8-Lead MSOP (RM) 210 45 °C/W
8-Lead SOIC (R) 158 43 °C/W
14-Lead SOIC (R) 120 36 °C/W
14-Lead TSSOP (RU) 180 35 °C/W

1

θJA is specified for worst-case conditions, i.e., θJA is specified for device in

socket for PDIP packages; θ
board for surface-mount packages.

is specified for device soldered onto a circuit

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. D | Page 6 of 20

AD8605/AD8606/AD8608

TYPICAL PERFORMANCE CHARACTERISTICS

4500

VS = 5V
TA = 25°C

4000

V

= 0V TO 5V

CM

3500

3000

2500

2000

1500

NUMBER OF AMPLIFIERS

1000

500

0

–300

OFFSET VOLTAGE (mV)

Figure 7. Input Offset Voltage Distribution

24

20

16

12

8

NUMBER OF AMPLIFIERS

4

0

0 1.2 2.0 2.8 3.6

0.8 1.6 2.4 3.2 4.0
TCVOS (mV/°C)

VS = 5V
T

= –40°C TO +125°C

A

V

= 2.5V

CM

Figure 8. AD8608 Input Offset Voltage Drift Distribution

NUMBER OF AMPLIFIERS

20

18

16

14

12

10

8

6

4

2

0

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

0

TCVOS (mV/°C)

= 5V

V

S

T

= –40°C TO +125°C

A

V

= 2.5V

CM

4.4

2.2 2.4

300–200 –100 0 100 200

4.80.4

2.60.2

Figure 9. AD8605/AD8606 Input Offset Voltage Drift Distribution

02731-D-007

8
0
0

­D

­1
3
7
2
0

02731-D-009

300

VS = 5V
T

= 25°C

A

200

100

0

–100

INPUT OFFSET VOLTAGE (mV)

–200

–300

COMMON-MODE VOLTAGE (V)

Figure 10. Input Offset Voltage vs. Common-Mode Voltage

(200 Units, 5 Wafer Lots, Including Process Skews)

360

VS = ±2.5V

320

280

240

200

160

120

INPUT BIAS CURRENT (pA)

80

40

0

0 12525

50 75 100

TEMPERATURE (°C)

AD8605/AD8606

AD8608

Figure 11. Input Bias Current vs. Temperature

1k

VS = 5V
T

= 25°C

A

100

(mV)

10

OUT

–V

SY

V

1

0.1

0.001 100.01
LOAD CURRENT (mA)

0.1

SINKSOURCE

1

Figure 12. Output Voltage to Supply Rail vs. Load Current

02731-D-010

02731-D-011

02731-D-012

Rev. D | Page 7 of 20

AD8605/AD8606/AD8608

5.000

6

4.950
V

= 5V

S

4.900

4.850

4.800

OUTPUT VOLTAGE (V)

4.750

4.700

–40 –25 –10 5 20 35 50 65 80 95 110 125

V

@ 10mA LOAD

OH

TEMPERATURE (°C)

VOH @ 1mA LOAD

Figure 13. Output Voltage Swing vs. Temperature

0.250
= 5V

V

S

0.200

0.150

0.100

OUTPUT VOLTAGE (V)

0.050

0

–40 –25 –10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

@ 10mA LOAD

V

OH

VOH @ 1mA LOAD

Figure 14. Output Voltage Swing vs. Temperature

100

80

60

40

20

0

GAIN (dB)

–20

–40

–60

–80

–100

10k 100M100k 1M 10M

FREQUENCY (Hz)

V
R
C
f

Figure 15. Open-Loop Gain and Phase vs. Frequency

= ±2.5V

S

= 2kV

L

= 20pF

L

= 648

M

5

VS = 5V

4

= 4.9V p-p

V

IN

T

= 25°C

A

= 2k

Ω

R

L

3

AV = 1

2

OUTPUT SWING (V p-p)

1

02731-D-013

02731-D-014

225

180

135

90

45

0

–45

PHASE (Degrees)

–90

–135

–180

02731-D-015

–225

0

1k 10M10k

100k 1M

FREQUENCY (Hz)

Figure 16. Closed-Loop Output Voltage Swing

100

VS = ±2.5V

90

80

70

60

50

40

30

OUTPUT IMPEDANCE (Ω)

20

10

0

1k 100M10k

AV = 100

AV = 10

100k 1M 10M
FREQUENCY (Hz)

Figure 17. Output Impedance vs. Frequency

120

VS = ±2.5V

110

100

90

80

70

CMRR (dB)

60

50

40

30

20

1k 10M

10k

100k 1M

FREQUENCY (Hz)

Figure 18. Common-Mode Rejection Ratio vs. Frequency

AV = 1

02731-D-016

02731-D-017

02731-D-018

Rev. D | Page 8 of 20

AD8605/AD8606/AD8608

140

VS = 5V

120

100

80

60

40

PSRR (dB)

20

0

–20

–40

–60

1k 10M10k

Figure 19. PSRR v s. Frequency

45

VS = 5V

40

R

=

L

T

= 25°C

A

35

A

= 1

V

30

25

20

15

10

SMALL SIGNAL OVERSHOOT (%)

5

0

10 1k100

CAPACITANCE (pF)

100k 1M

FREQUENCY (Hz)

02731-D-019

+OS

–OS

02731-D-020

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

SUPPLY CURRENT/AMPLIFIER (mA)

0.1

V/DIV)

µ

VOLTAGE NOISE (1

0

0 5.04.54.03.53.02.52.01.51.00.5

SUPPLY VOLTAGE (V)

Figure 22. Supply Current vs. Supply Voltage

VS = 5V

TIME (1s/DIV)

02731-D-022

02731-D-023

Figure 20. Small Signal Overshoot vs. Load Capacitance

2.0

1.5

= 2.7V

V

1.0

0.5

0

–0.5

SUPPLY CURRENT/AMPLIFIER (mA)

–1.0

–1.5

–50 125–35 –20 95 11052035506580

S

TEMPERATURE (°C)

= 5V

V

S

Figure 21. Supply Current vs. Temperature

02731-D-021

Figure 23. 0.1 Hz to 10 Hz Input Voltage Noise

VS = ±2.5V
R

= 10kΩ

L

C

= 200pF

L

A

= 1

V

VOLTAGE (50mV/DIV)

TIME (200ns/DIV)

02731-D-024

Figure 24. Small Signal Transient Response

Rev. D | Page 9 of 20

AD8605/AD8606/AD8608

0

0

VS = ±2.5V
RL = 10k

Ω

CL = 200pF
A

= 1

V

36

VS = ±2.5V

32

28

24

20

Hz)

√

VOLTAGE NOISE DENSITY (nV/

VOLTAGE NOISE DENSITY (nV/√Hz)

53.6

46.9

40.2

33.5

26.8

20.1

13.4

16

12

8

4

0 1.00.90.80.70.60.50.40.30.20.1

6.7

0

VS = ±2.5V

01987654321

FREQUENCY (kHz)

Figure 28. Voltage Noise Density

FREQUENCY (kHz)

02731-D-028

02731-D-029

0

VOLTAGE (1V/DIV)

TIME (400ns/DIV)

Figure 25. Large Signal Transient Response

+2.5V

V

V

–50mV

TIME (400ns/DIV)

VS = ±2.5V
R

= 10kΩ

L

A

= 100

V

V

= 50mV

IN

02731-D-025

02731-D-026

0V

0V

Figure 26. Negative Overload Recovery

VS = ±2.5V
R

= 10kΩ

L

A

= 100

V

V

= 50mV

IN

+2.5V

–50mV

TIME (400ns/DIV)

Figure 27. Positive Overload Recovery

119.2

104.3

99.4

74.5

59.6

44.7

29.8

VOLTAGE NOISE DENSITY (nV/√Hz)

14.9

02731-D-027

0

0 100908070605040302010

Figure 29. Voltage Noise Density

VS = ±2.5V

FREQUENCY (Hz)

Figure 30. Voltage Noise Density

02731-D-030

Rev. D | Page 10 of 20

AD8605/AD8606/AD8608

1800

VS = 2.7V
TA = 25°C

1600

VCM = 0V TO 2.7V

1400

1200

1000

800

600

NUMBER OF AMPLIFIERS

400

200

0
–300

OFFSET VOLTAGE (µV)

0 100

Figure 31. Input Offset Voltage Distribution

300

VS = 2.7V
TA = 25°C

200

V)

µ

100

0

–100

INPUT OFFSET VOLTAGE (

–200

–300

0

COMMON-MODE VOLTAGE (V)

1.80.90

Figure 32. Input Offset Voltage vs. Common-Mode Voltage

(200 Units, 5 Wafer Lots, Including Process Skews)

1k

VS = 2.7V
T

= 25°C

A

100

SOURCE

10

SINK

OUTPUT VOLTAGE (mV)

1

0.1

0.001 100.01

0.1

LOAD CURRENT (mA)

1

Figure 33. Output Voltage to Supply Rail vs. Load Current

02731-D-031

300–200 –100 200

02731-D-032

2.7

02731-D-033

OUTPUT VOLTAGE (V)

2.680

2.675

2.670

2.665

2.660

2.655

2.650

VS = 2.7V

–10–25–40

VOH @ 1mA LOAD

5 20 1255035

TEMPERATURE (°C)

Figure 34. Output Voltage Swing vs. Temperature

0.045
VS = 2.7V

0.040

0.035

0.030

0.025

0.020

0.015

OUTPUT VOLTAGE (V)

0.010

0.005

0

5 20 1255035

TEMPERATURE (°C)

VOH @ 1mA LOAD

Figure 35. Output Voltage Swing vs. Temperature

100

80

60

40

20

0

GAIN (dB)

–20

–40

–60

–80

–100

10k 100M100k

1M 10M

FREQUENCY (Hz)

Figure 36. Open-Loop Gain and Phase vs. Frequency

65 80 95 110

65 80 95 110–10–25–40

VS = ±1.35V
R

= 2kΩ

L

C

= 20pF

L

f

= 52.5°

M

02731-D-034

02731-D-035

225

180

135

90

45

0

–45

PHASE (Degrees)

–90

–135

–180

–225

02731-D-036

Rev. D | Page 11 of 20

AD8605/AD8606/AD8608

3.0

2.5
VS = 2.7V

= 2.6V p-p

V

IN

2.0
TA = 25°C

R

= 2k

Ω

L

AV = 1

1.5

1.0

OUTPUT SWING (V p-p)

0.5

VS = 2.7V

VOLTAGE NOISE (1µV/DIV)

0

1k 10M10k

100k 1M

FREQUENCY (Hz)

Figure 37. Closed-Loop Output Voltage Swing vs. Frequency

100

VS = ±1.35V

90

80

70

60

50

40

30

OUTPUT IMPEDANCE (Ω)

20

10

0

1k

Figure 38. Output Impedance vs. Frequency

60

VS = 2.7V
T

= 25°C

A

50

A

= 1

V

40

30

20

AV = 100

AV = 10

AV = 1

100k 1M 10M

FREQUENCY (Hz)

–OS

+OS

100M10k

02731-D-037

02731-D-038

TIME (1s/DIV)

Figure 40. 0.1 Hz to 10 Hz Input Voltage Noise

VS = 1.35V
R

= 10kΩ

L

C

= 200pF

L

A

= 1

V

VOLTAGE (50mV/DIV)

TIME (200ns/DIV)

Figure 41. Small Signal Transient Response

VS = 1.35V
R

= 10k

Ω

L

CL = 200pF
A

= 1

V

VOLTAGE (1V/DIV)

02731-D-040

02731-D-041

SMALL SIGNAL OVERSHOOT (%)

10

0

10 1k100

CAPACITANCE (pF)

Figure 39. Small Signal Overshoot vs. Load Capacitance

02731-D-039

Rev. D | Page 12 of 20

TIME (400ns/DIV)

Figure 42. Large Signal Transient Response

02731-D-042

AD8605/AD8606/AD8608

(

)

−

APPLICATION INFORMATION

OUTPUT PHASE REVERSAL

Phase reversal is defined as a change in polarity at the output of
the amplifier when a voltage that exceeds the maximum input
common-mode voltage drives the input.

Phase reversal can cause permanent damage to the amplifier; it
may also cause system lockups in feedback loops. The AD8605
does not exhibit phase reversal even for inputs exceeding the
supply voltage by more than 2 V.

VS = ±2.5V
V

= 5V p-p

IN

A

= 1

V

R

= 10k

Ω

L

VOLTAGE (2V/DIV)

V

OUT

V

IN

Figure 44 compares the maximum power dissipation with
temperature for the various AD8605 family packages.

2.0

1.8

1.6

1.4

1.2

1.0

0.8
SOT-23

0.6

POWER DISSIPATION (W)

0.4

0.2

0

0 10020

Figure 44. Maximum Power Dissipation vs. Temperature

SOIC-14

SOIC-8

TSSOP

MSOP

40 60 80

TEMPERATURE (°C)

02731-D-044

TIME (4µs/DIV)

Figure 43. No Phase Reversal

02731-D-043

MAXIMUM POWER DISSIPATION

Power dissipated in an IC causes the die temperature to
increase. This can affect the behavior of the IC and the
application circuit performance.

The absolute maximum junction temperature of the AD8605/
AD8606/AD8608 is 150°C. Exceeding this temperature could
cause damage or destruction of the device. The maximum
power dissipation of the amplifier is calculated according to
the following formula:

TT

−

J

P

=

DISS

where:

= junction temperature

T

J

= ambient temperature

T

A

θ

= junction to-ambient-thermal resistance

JA

A

θ

JA

INPUT OVERVOLTAGE PROTECTION

The AD8605 has internal protective circuitry. However, if the
voltage applied at either input exceeds the supplies by more
than 2.5 V, external resistors should be placed in series with the
inputs. The resistor values can be determined by the formula

VV

IN

S

()

R

200

Ω+

S

mA

5

≤

The remarkable low input offset current of the AD8605 (<1 pA)
allows the use of larger value resistors. With a 10 kΩ resistor at
the input, the output voltage has less than 10 nV of error
voltage. A 10 kΩ resistor has less than 13 nV/√

Hz

of thermal

noise at room temperature.

THD + NOISE

Total harmonic distortion is the ratio of the input signal in V
rms to the total harmonics in V rms throughout the spectrum.
Harmonic distortion adds errors to precision measurements
and adds unpleasant sonic artifacts to audio systems.

The AD8605 has a low total harmonic distortion. Figure 45
shows that the AD8605 has less than 0.005% or −86 dB of THD
+ N over the entire audio frequency range. The AD8605 is
configured in positive unity gain, which is the worst case, and
with a load of 10 kΩ.

Rev. D | Page 13 of 20

AD8605/AD8606/AD8608

0.1
VSY = 2.5V
AV = 1
B

= 22kHz

W

The AD8606 has a channel separation of greater than −160 dB
up to frequencies of 1 MHz, allowing the two amplifiers to
amplify ac signals independently in most applications.

0.01

THD + N (%)

0.001

0.0001
20 20k100

FREQUENCY (Hz)

1k

Figure 45. THD + N

02731-D-045

10k

TOTAL NOISE INCLUDING SOURCE RESISTORS

The low input current noise and input bias current of the
AD8605 make it the ideal amplifier for circuits with substantial
input source resistance such as photodiodes. Input offset voltage
increases by less than 0.5 nV per 1 kΩ of source resistance at
room temperature and increases to 10 nV at 85°C. The total
noise density of the circuit is

n

,

TOTAL

2

where:

e

is the input voltage noise density of the AD8605

n

is the input current noise density of the AD8605

i

n

R

is the source resistance at the noninverting terminal

S

k is Boltzmann’s constant (1.38 × 10
T is the ambient temperature in Kelvin (T = 273 + °C)

For example, with R
roughly 15 nV/√

For R

< 3.9 kΩ, en dominates and e

S

Hz

2

()

++=

nn

= 10 kΩ, the total voltage noise density is

S

TRkRiee 4

SS

−23

J/K)

.

≈ en.

n,TOTAL

0

–20

–40

–60

–80

–100

–120

CHANNEL SEPARATION (dB)

–140

–160

–180

FREQUENCY (Hz)

Figure 46. Channel Separation vs. Frequency

10M1M100k10k1k100 100M

02731-D-046

CAPACITIVE LOAD DRIVE

The AD8605 can drive large capacitive loads without oscillation.
Figure 47 shows the output of the AD8606 in response to a
200 mV input signal. In this case, the amplifier was configured
in positive unity gain, worst case for stability, while driving a
1,000 pF load at its output. Driving larger capacitive loads in
unity gain may require the use of additional circuitry.

VS = ±2.5V
AV = 1
R

= 10k

Ω

L

CL = 1

VOLTAGE (100mV/DIV)

The current noise of the AD8605 is so low that its total density
does not become a significant term unless R

is greater than

S

6 MΩ. The total equivalent rms noise over a specific bandwidth
is expressed as

()

=

BWeE

TOTALnn,

where BW is the bandwidth in hertz.

Note that the analysis above is valid for frequencies greater than
100 Hz and assumes relatively flat noise, above 10 kHz. For
lower frequencies, flicker noise (1/f) must be considered.

CHANNEL SEPARATION

Channel separation, or inverse crosstalk, is a measure of the
signal feed from one amplifier (channel) to an other on the
same IC.

Rev. D | Page 14 of 20

TIME (10µs/DIV)

Figure 47. Capacitive Load Drive without Snubber

02731-D-047

A snubber network, shown in Figure 48, helps reduce the signal
overshoot to a minimum and maintain stability. Although this
circuit does not recover the loss of bandwidth induced by large
capacitive loads, it greatly reduces the overshoot and ringing.
This method does not reduce the maximum output swing of
the amplifier.

Figure 49 shows a scope photograph of the output at the
snubber circuit. The overshoot is reduced from over 70% to
less than 5%, and the ringing is eliminated by the snubber.
Optimum values for R

and CS are determined experimentally.

S

AD8605/AD8606/AD8608

V+

4

200mV

V

IN

2

3

AD8605

8

V–

1

R

RLC

S

C

S

L

Figure 48. Snubber Network Configuration

VS = ±2.5V
AV = 1
R

= 10k

Ω

L

RS = 90

Ω

CL = 1,000pF
C

= 700pF

S

VOLTAGE (100mV/DIV)

TIME (10µs/DIV)

02731-D-048

Figure 49. Capacitive Load Drive with Snubber

Table 5 summarizes a few optimum values for capacitive loads.

Table 5.

CL (pF) RS (Ω) CS (pF)

500 100 1,000
1,000 70 1,000
2,000 60 800

An alternate technique is to insert a series resistor inside the
feedback loop at the output of the amplifier. Typically, the value
of this resistor is approximately 100 Ω. This method also
reduces overshoot and ringing but causes a reduction in the
maximum output swing.

LIGHT SENSITIVITY

The AD8605ACB (MicroCSP package option) is essentially
a silicon die with additional post fabrication dielectric and
intermetallic processing designed to contact solder bumps on
the active side of the chip. With this package type, the die is
exposed to ambient light and is subject to photoelectric effects.
Light sensitivity analysis of the AD8605ACB mounted on
standard PCB material reveals that only the input bias current

) parameter is impacted when the package is illuminated

(I

B

directly by high intensity light. No degradation in electrical
performance is observed due to illumination by low intensity
(0.1 mW/cm
with increasing wavelength and intensity of incident light;

can reach levels as high as 4500 pA at a light intensity of

I

B

3 mW/cm

2

) ambient light. Figure 50 shows that IB increases

2

and a wavelength of 850 nm. The light intensities

shown in Figure 50 are not normal for most applications, i.e.,

2

even though direct sunlight can have intensities of 50 mW/cm
office ambient light can be as low as 0.1 mW/cm

2

.

,

When the MicroCSP package is assembled on the board with
the bump-side of the die facing the PCB, reflected light from the
PCB surface is incident on active silicon circuit areas and results

02731-D-049

in the increased I
illumination of the backside (substrate) of the AD8605ACB.

. No performance degradation occurs due to

B

The AD8605ACB is particularly sensitive to incident light with
wavelengths in the near infrared range (NIR, 700 nm to 1000
nm). Photons in this waveband have a longer wavelength and
lower energy than photons in the visible (400 nm to 700 nm)
and near ultraviolet bands (NUV, 200 nm to 400 nm); therefore,
they can penetrate more deeply into the active silicon. Incident
light with wavelengths greater than 1100 nm has no photo­electric effect on the AD8605ACB because silicon is trans­parent to wave lengths in this range. The spectral content of
conventional light sources varies: sunlight has a broad spectral
range, with peak intensity in the visible band that falls off in the
NUV and NIR bands; fluorescent lamps have significant peaks
in the visible but not in the NUV or NIR bands.

Efforts have been made at a product level to reduce the effect
of ambient light; the under bump metal (UBM) has been
designed to shield the sensitive circuit areas on the active side
(bump-side) of the die. However, if an application encounters
any light sensitivity with the AD8605ACB, shielding the bump
side of the MicroCSP package with opaque material should
eliminate this effect. Shielding can be accomplished using
materials such as silica filled liquid epoxies that are used in
flip chip underfill techniques.

5000

4500

4000
3500

3000

2500

2000

1500

INPUT BIAS CURRENT (pA)

1000

500

2mW/cm

0

350

450 550 650 750 850

WAVELENGTH (nm)

3mW/cm

2

2

1mW/cm

2

02731-D-050

Figure 50. AD8605ACB Input Bias Current Response to Direct Illumination of

Varying Intensity and Wavelength

MICROCSP ASSEMBLY CONSIDERATIONS

For detailed information on MicroCSP PCB assembly and
reliability, refer to ADI Application Note AN-617 on the ADI

www.analog.com.

website

Rev. D | Page 15 of 20

AD8605/AD8606/AD8608

I-V CONVERSION APPLICATIONS

PHOTODIODE PREAMPLIFIER APPLICATIONS

The low offset voltage and input current of the AD8605 make it
an excellent choice for photodiode applications. In addition, the
low voltage and current noise make the amplifier ideal for
application circuits with high sensitivity.

C

F

10pF

R

F

10MΩ

PHOTODIODE

C

R

D

D

I

D

50pF

Figure 51. Equivalent Circuit for Photodiode Preamp

The input bias current of the amplifier contributes an error
term that is proportional to the value of R

The offset voltage causes a dark current induced by the shunt
resistance of the diode R

D

the output of the amplifier. The error voltage is written as

+VOS–

AD8605

.

F

V

OUT

. These error terms are combined at

02731-D-051

At room temperature, the AD8605 has an input bias current of

0.2 pA and an offset voltage of 100 µV. Typical values of R

D

are

in the range of 1 GΩ.

For the circuit shown in Figure 9, the output error voltage is
approximately 100 µV at room temperature, increasing to about
1 mV at 85°C.

Where f

is the unity gain frequency of the amplifier, the

t

maximum achievable signal bandwidth is

f

fπ=

MAX

t

2

CR

F

T

AUDIO AND PDA APPLICATIONS

The AD8605’s low distortion and wide dynamic range make it a
great choice for audio and PDA applications, including
microphone amplification and line output buffering.

Figure 52 shows a typical application circuit for headphone/line
out amplification.

R1 and R2 are used to bias the input voltage at half the supply.
This maximizes the signal bandwidth range. C1 and C2 are used
to ac couple the input signal. C1 and R2 form a high-pass filter
whose corner frequency is 1/2πR1C1.

VE +

Ty pi ca ll y, R

⎛
⎜

OSO

⎜
⎝

F

⎞

R

F

⎟

+= 1

⎟

R

D

⎠

IR

BF

is smaller than RD, thus RF/RD can be ignored.

R1

C1

10kΩ

1µF

V1
500mV

1µF

V2
500mV

R2

10kΩ

C2

Figure 52. Single-Supply Headphone/Speaker Amplifier

3

2

5

6

5V

8

1/2
AD8606

4

5V

8

1/2
AD8606

4

The high output current of the AD8605 allows it to drive heavy
resistive loads.

The circuit of Figure 52 was tested to drive a 16 W headphone.
The THD + N is maintained at approximately −60 dB
throughout the audio range.

C3

100µF

1

100µF

7

R4

20Ω

HEADPHONES

R3
1kΩ

C4

R6

20Ω

R5
1kΩ

02731-D-052

Rev. D | Page 16 of 20

AD8605/AD8606/AD8608

V

V

INSTRUMENTATION AMPLIFIERS

The low offset voltage and low noise of the AD8605 make it a
great amplifier for instrumentation applications.

Difference amplifiers are widely used in high accuracy circuits
to improve the common-mode rejection ratio.

Figure 53 shows a simple difference amplifier. The CMRR of the
circuit is plotted versus frequency. Figure 54 shows the
common-mode rejection for a unity gain configuration and for
a gain of 10.

Making (R4/R3) = (R2/R1) and choosing 0.01% tolerance yields
a CMRR of 74 dB and minimizes the gain error at the output.

V1

R4R3R2

=

R1

V

= (V2–V1)

OUT

R1

1kΩ

R2
R1

5V

AD8605

R2

10kΩ

V

OUT

REF

Figure 55. Simplified Circuit of the DAC8143 with AD8605 Output Buffer

To optimize the performance of the DAC, insert a capacitor in
the feedback loop of the AD8605 to compensate the amplifier
from the pole introduced by the output capacitance of the DAC.
Typical values for C
adjusted for the best frequency response. The total error at the
output of the op amp can be computed by the formula:

RRR

R2

C

F

R

F

R2 R2

V

OS

V+

AD8605

V–

are in the range of 10 pF to 30 pF; it can be

F

02731-D-055

V2

120

VSY = ±2.5V

100

80

60

CMRR (dB)

40

20

0

100 10M1k

R3

1kΩ

Figure 53. Difference Amplifier, A

AV = 10

AV = 1

10k 100k 1M
FREQUENCY (Hz)

R4

10kΩ

= 10

V

02731-D-053

02731-D-054

Figure 54. Difference Amplifier CMRR vs. Frequency

D/A CONVERSION

The low input bias current and offset voltage of the AD8605
make it an excellent choice for buffering the output of a current
output DAC.

Figure 55 shows a typical implementation of the AD8605 at the
output of a 12-bit DAC.

The DAC8143 output current is converted to a voltage by the
feedback resistor. The equivalent resistance at the output of the
DAC varies with the input code, as does the output capacitance.

⎛
⎜

1

VE

OSO

⎜
⎝

⎞

R

F

⎟

Re

⎟

q

⎠

+=

where Req is the equivalent resistance seen at the output of the
DAC. As mentioned above, Req is code dependant and varies
with the input. A typical value for Req is 15 kΩ. Choosing a
feedback resistor of 10 kΩ yields an error of less than 200 µV.

Figure 56 shows the implementation of a dual-stage buffer at
the output of a DAC. The first stage is used as a buffer.
Capacitor C1, with Req, creates a low-pass filter and thus
provides phase lead to compensate for frequency response. The
second stage of the AD8606 is used to provide voltage gain at
the output of the buffer.

Grounding the positive input terminals in both stages reduces
errors due to the common-mode output voltage. Choosing R1,
R2, and R3 to match within 0.01% yields a CMRR of 74 dB and
maintains minimum gain error in the circuit.

R

15V

V

DD

AD7545

V

REF

R

P

IN

DB11

CS

C1

R

FB

OUT1

AGND

33pF

1/2
AD8606

R4

5kΩ10%

Figure 56. Bipolar Operation

R1

10kΩ

R3
20kΩ

R2

10kΩ

1/2
AD8606

V

OUT

02731-D-056

Rev. D | Page 17 of 20

AD8605/AD8606/AD8608

Y

R

OUTLINE DIMENSIONS

2.90 BSC

4 5

1.60 BSC

1

2

PIN 1

1.30

1.15

0.90

0.15MAX

1.90
BSC

COMPLIANT TO JEDEC STANDARDS MO-178AA

Figure 57. 5-Lead Small Outline Transistor Package [SOT-23] (RT-5)

8.75 (0.3445)

8.55 (0.3366)

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

14
1

1.27 (0.0500)
BSC

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-012AB

Figure 58. 14-Lead Standard Small Outline Package [SOIC]

2.80 BSC

3

0.95 BSC

1.45 MAX

0.50

SEATING

0.30

PLANE

8

6.20 (0.2441)

7

5.80 (0.2283)

1.75 (0.0689)

1.35 (0.0531)

SEATING
PLANE

Narrow Body (R-14)

0.22

0.08

0.25 (0.0098)

0.17 (0.0067)

10°

5°
0°

0.50 (0.0197)

0.25 (0.0098)

8°
0°

1.27 (0.0500)

0.40 (0.0157)

0.60

0.45

0.30

× 45°

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARIT

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

85

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

BSC

6.20 (0.2440)

5.80 (0.2284)

41

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

× 45°

Figure 60. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8)

5.10

5.00

4.90

14

4.50

4.40

4.30

PIN 1

0.15

0.05

0.65
BSC

1.05

1.00

0.80

COMPLIANT TO JEDEC STANDARDS MO-153AB-1

0.30

0.19

8

6.40
BSC

71

1.20
MAX

SEATING
PLANE

0.20

0.09

COPLANARITY

0.10

8°
0°

0.75

0.60

0.45

Figure 61. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14)

3.00
BSC

85

3.00

BSC

PIN 1

0.65 BSC

0.15

0.00

0.38

0.22

COPLANARITY

0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA

4

SEATING
PLANE

4.90
BSC

1.10 MAX

0.23

0.08

8°
0°

Figure 59. 8-Lead Mini Small Outline Package [MSOP] (RM-8)

0.80

0.60

0.40

0.94

0.90

0.86

PIN 1

IDENTIFIE

TOP VIEW

(BALL SIDE DOWN)

1.33

1.29

1.25

Figure 62. 5-Bump 2 × 1 × 2 Array MicroCSP [ WLCSP] (CB-5)

0.37

0.36

0.35

0.50 REF

SEATING

0.17

0.14

0.12

PLANE

0.87

0.23

0.18

0.14

0.21

BOTTOM VIEW

0.50

0.50

0.20

Rev. D | Page 18 of 20

AD8605/AD8606/AD8608

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD8605ACB-REEL −40°C to +125°C 5-Bump MicroCSP CB-5 B3A
AD8605ACB-REEL7 −40°C to +125°C 5-Bump MicroCSP CB-5 B3A
AD8605ART-R2 −40°C to +125°C 5-Lead SOT-23 RT-5 B3A
AD8605ART-REEL −40°C to +125°C 5-Lead SOT-23 RT-5 B3A
AD8605ART-REEL7 −40°C to +125°C 5-Lead SOT-23 RT-5 B3A
AD8605ARTZ-REEL
AD8605ARTZ-REEL71 −40°C to +125°C 5-Lead SOT-23 RT-5 B3A
AD8606ARM-R2 −40°C to +125°C 8-Lead MSOP RM-8 B6A
AD8606ARM-REEL −40°C to +125°C 8-Lead MSOP RM-8 B6A
AD8606AR −40°C to +125°C 8-Lead SOIC R-8
AD8606AR-REEL −40°C to +125°C 8-Lead SOIC R-8
AD8606AR-REEL7 −40°C to +125°C 8-Lead SOIC R-8
AD8608AR −40°C to +125°C 14-Lead SOIC R-14
AD8608AR-REEL −40°C to +125°C 14-Lead SOIC R-14
AD8608AR-REEL7 −40°C to +125°C 14-Lead SOIC R-14
AD8608ARU −40°C to +125°C 14-Lead TSSOP RU-14
AD8608ARU-REEL −40°C to +125°C 14-Lead TSSOP RU-14

1

Z = Pb-free part.

1

−40°C to +125°C 5-Lead SOT-23 RT-5 B3A

Rev. D | Page 19 of 20

AD8605/AD8606/AD8608

NOTES

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C02731-0-5/04(D)

Rev. D | Page 20 of 20