ANALOG DEVICES AD8597, AD8599 Service Manual

Single and Dual, Ultralow

FEATURES

Low noise: 1.1 nV/√Hz at 1 kHz
Low distortion: −120 dB THD @ 1 kHz
Input noise, 0.1 Hz to 10 Hz: <76 nV p-p
Slew rate: 14 V/μs
Wide bandwidth: 10 MHz
Supply current: 4.8 mA/amp typical
Low offset voltage: 10 μV typical
CMRR: 120 dB
Unity-gain stable
±15 V operation

APPLICATIONS

Professional audio preamplifiers
ATE/precision testers
Imaging systems
Medical/physiological measurements
Precision detectors/instruments
Precision data conversion

Distortion, Ultralow Noise Op Amps

AD8597/AD8599

PIN CONFIGURATIONS

1

NC

AD8597

–IN

2

+IN

3

TOP VIEW

(Not to S cale)

V–

4

NC = NO CONNECT

Figure 1. AD8597 8-Lead SOIC (R-8)

1

NC

2

–IN
+IN

V–

NOTES

1. NC = NO CONNECT.

2. IT I S RECOMMENDED T HAT THE
EXPOSED PAD BE CONNECTED
TO V–.

3
4

AD8597

TOP VIEW

Figure 2. AD8597 8-Lead LFCSP (CP-8-2)

PIN 1
INDICATOR

8
7
6
5

NC
V+
OUT
NC

8NC
7V+
6OUT
5NC

06274-060

06274-061

GENERAL DESCRIPTION

The AD8597/AD8599 are very low noise, low distortion opera­tional amplifiers ideal for use as preamplifiers. The low noise of

1.1 nV/√Hz and low harmonic distortion of −120 dB (or better)
at audio bandwidths give the AD8597/AD8599 the wide dynamic
range necessary for preamplifiers in audio, medical, and instru­mentation applications. The excellent slew rate of 14 V/μs and
10 MHz gain bandwidth make them highly suitable for medical
applications. The low distortion and fast settling time make
them ideal for buffering of high resolution data converters.

OUT A

–IN A
+IN A

–V

1

AD8599

2
3

TOP VIEW

(Not to S cale)

4

8
7
6
5

+V
OUT B
–IN B
+IN B

06274-054

Figure 3. AD8599 8-Lead SOIC (R-8)

The AD8597 is available in 8-lead SOIC and LFCSP packages,
while the AD8599 is available in an 8-lead SOIC package. They
are both specified over a −40°C to +125°C temperature range.
The AD8597 and AD8599 are members of a growing series of
low noise op amps offered by Analog Devices, Inc., (see Tabl e 1).

Table 1. Low Noise Op Amps

Package 0.9 nV 1.1 nV 1.8 nV 2.8 nV 3.8 nV

Single AD797 AD8597 ADA4004-1 AD8675 AD8671
Dual AD8599 ADA4004-2 AD8676 AD8672
Quad ADA4004-4 AD8674

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007–2009 Analog Devices, Inc. All rights reserved.

AD8597/AD8599

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Pin Configurations ........................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

Thermal Resistance ...................................................................... 5

Power Sequencing ........................................................................ 5

REVISION HISTORY

12/09—Rev. B to Rev. C

Changes to Table 1 ............................................................................ 1

10/08—Rev. A to Rev. B

Added AD8597 ................................................................... Universal

Added LFCSP_VD ............................................................. Universal

Added Table 1 .................................................................................... 1

Changes to Specifications Section .................................................. 3

Changes to Absolute Maximum Ratings Section ......................... 5

Changes to Typical Performance Characteristics Section ........... 6

Added Figure 12 and Figure 15....................................................... 7

Added Figure 18 and Figure 19....................................................... 8

Added Figure 30 and Figure 33..................................................... 10

Added Figure 34 to Figure 38 ........................................................ 11

Added Figure 42 and Figure 45..................................................... 12

Added Figure 52, Figure 55, Figure 57 ......................................... 14

Added Functional Operation Section .......................................... 15

Added Figure 58 .............................................................................. 15

Updated Outline Dimensions ....................................................... 17

Changes to Ordering Guide .......................................................... 17

ESD Caution...................................................................................5

Typical Performance Characteristics ..............................................6

Functional Operation..................................................................... 15

Input Voltage Range ................................................................... 15

Output Phase Reversal ............................................................... 15

Noise and Source Impedance Considerations ........................... 15

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 17

4/07—Rev. 0 to Rev. A

Updated Layout ................................................................................. 5

Changes to Figure 45 Caption ...................................................... 12

Added Figure 48 ............................................................................. 12

Changes to Figure 51 Caption ...................................................... 13

2/07—Revision 0: Initial Version

Rev. C | Page 2 of 20

AD8597/AD8599

SPECIFICATIONS

VSY = ±5 V, VCM = 0 V, VO = 0 V, TA = 25°C, unless otherwise specified.

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V

OS

−40°C ≤ TA ≤ +125°C 180 μV

Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +125°C 0.8 2.2 μV/°C
Input Bias Current I

B

−40°C ≤ TA ≤ +125°C 340 nA
Input Offset Current I

OS

−40°C ≤ TA ≤ +125°C 340 nA
Input Voltage Range IVR
Common-Mode Rejection Ratio CMRR −2.0 V ≤ VCM ≤ +2.0 V 120 135 dB

−40°C ≤ TA ≤ +125°C 105 dB
Large Signal Voltage Gain AVO R

−40°C ≤ TA ≤ +125°C 100 dB
Input Capacitance

Differential Capacitance C
Common-Mode Capacitance C

15.4 pF

DIFF

CM

OUTPUT CHARACTERISTICS

Output Voltage High V

OH

−40°C ≤ TA ≤ +125°C 3.3 V
R

−40°C ≤ TA ≤ +125°C 3.5 V
Output Voltage Low V

OL

−40°C ≤ TA ≤ +125°C −3.3 V
R

−40°C ≤ TA ≤ +125°C −3.4 V
Output Short-Circuit Current I
Closed-Loop Output Impedance Z

SC

At 1 MHz, AV = 1 5 Ω

OUT

POWER SUPPLY

Power Supply Rejection Ratio PSRR VSY = ±18 V to ±4.5 V 120 140 dB

−40°C ≤ TA ≤ +125°C 118 dB
Supply Current per Amplifier ISY 4.8 5.5 mA

−40°C ≤ TA ≤ +125°C 6.5 mA

DYNAMIC PERFORMANCE

Slew Rate SR AV = −1, RL = 2 kΩ 14 V/μs
A
Settling Time tS To 0.01%, step = 10 V 2 μs
Gain Bandwidth Product GBP 10 MHz
Phase Margin ΦM 60 Degrees

NOISE PERFORMANCE

Peak-to-Peak Noise en p-p 0.1 Hz to 10 Hz 76 nV p-p
Voltage Noise Density e

n

f = 10 Hz 1.5 nV/√Hz
Correlated Current Noise f = 1 kHz 2.0 pA/√Hz
f = 10 Hz 4.2 pA/√Hz
Uncorrelated Current Noise f = 1 kHz 2.4 pA/√Hz
f = 10 Hz 5.2 pA/√Hz
Total Harmonic Distortion + Noise THD + N G = 1, RL ≥ 1 kΩ, f = 1 kHz, V
Channel Separation CS f = 10 kHz −120 dB

15 120 μV

40 210 nA

65 250 nA

−2.0 +2.0 V

≥ 600 Ω, V

L

= −11 V to +11 V 105 110 dB

O

5.5 pF

RL = 600 Ω 3.5 3.7 V

= 2 kΩ 3.7 3.8 V

L

RL = 600 Ω −3.6 −3.4 V

= 2 kΩ −3.7 −3.5 V

L

±52 mA

= 1, RL = 2 kΩ 14 V/μs

V

f = 1 kHz 1.07 1.15 nV/√Hz

Rev. C | Page 3 of 20

RMS

= 1 V

−120 dB

AD8597/AD8599

VS = ±15 V, VCM = 0 V, VO = 0 V, TA = +25°C, unless otherwise specified.

Table 3.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V

OS

−40°C ≤ TA ≤ +125°C 180 μV

Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +125°C 0.8 2.2 μV/°C

Input Bias Current I

B

−40°C ≤ TA ≤ +125°C 300 nA
Input Offset Current I

OS

−40°C ≤ TA ≤ +125°C 300 nA
Input Voltage Range IVR
Common-Mode Rejection Ratio CMRR −12.5 V ≤ VCM ≤ +12.5 V 120 135 dB

−40°C ≤ TA ≤ +125°C 115 dB
Large Signal Voltage Gain AVO R

−40°C ≤ TA ≤ +125°C 106 dB
Input Capacitance

Differential Capacitance C
Common-Mode Capacitance C

12.1 pF

DIFF

CM

OUTPUT CHARACTERISTICS

Output Voltage High V

OH

−40°C ≤ TA ≤ +125°C 12.8 V
R

−40°C ≤ TA ≤ +125°C 13.2 V
Output Voltage Low V

OL

−40°C ≤ TA ≤ +125°C −12.8 V
R

−40°C ≤ TA ≤ +125°C −13.3 V
Output Short-Circuit Current I
Closed-Loop Output Impedance Z

SC

At 1 MHz, AV = 1 5 Ω

OUT

POWER SUPPLY

Power Supply Rejection Ratio PSRR VSY = ±18 V to ±4.5 V 120 140 dB

−40°C ≤ TA ≤ +125°C 118 dB
Supply Current per Amplifier ISY 5.0 5.7 mA

−40°C ≤ TA ≤ +125°C 6.75 mA

DYNAMIC PERFORMANCE

Slew Rate SR AV = −1, RL = 2 kΩ 16 V/μs
A
Settling Time ts To 0.01%, step = 10 V 2 μs
Gain Bandwidth Product GBP 10 MHz
Phase Margin ΦM 65 Degrees

NOISE PERFORMANCE

Peak-to-Peak Noise en p-p 0.1 Hz to 10 Hz 76
Voltage Noise Density e

n

f = 10 Hz 1.5 nV/√Hz
Correlated Current Noise f = 1 kHz 1.9 pA/√Hz
f = 10 Hz 4.3 pA/√Hz
Uncorrelated Current Noise f = 1 kHz 2.3 pA/√Hz
f = 10 Hz 5.3 pA/√Hz
Total Harmonic Distortion + Noise THD + N G = 1, R
Channel Separation CS f = 10 kHz −120 dB

10 120 μV

25 200 nA

50 200 nA

−12.5 +12.5 V

≥ 600 Ω, V

L

= −11 V to +11 V 110 116 dB

O

5.1 pF

RL = 600 Ω 13.1 13.4 V

= 2 kΩ 13.5 13.7 V

L

RL = 600 Ω −13.2 −12.9 V

= 2 kΩ −13.5 −13.4 V

L

±52 mA

= 1, RL = 2 kΩ 15 V/μs

V

nV p-p

f = 1 kHz 1.07 1.15 nV/√Hz

≥ 1 kΩ, f = 1 kHz, V

L

Rev. C | Page 4 of 20

RMS

= 3 V

−120 dB

AD8597/AD8599

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage ±18 V
Input Voltage −V ≤ VIN ≤ +V
Differential Input Voltage1 ±1 V
Output Short-Circuit to GND Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Lead Temperature Range (Soldering 60 sec) 300°C
Junction Temperature 150°C

1

If the differential input voltage exceeds 1 V, the current should be limited

to 5 mA.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified with the device soldered on a circuit board with
its exposed paddle soldered to a pad (if applicable) on a 4-layer
JEDEC standard PCB with zero air flow.

Table 5.

Package Type θJA θ

8-Lead LFCSP_VD (CP-8-2) 78 20 °C/W
8-Lead SOIC (R-8) (AD8597) 140 39 °C/W
8-Lead SOIC (R-8) (AD8599) 120 36 °C/W

Unit

JC

POWER SEQUENCING

The op amp supplies should be applied simultaneously. The
op amp supplies should be stable before any input signals are
applied. In any case, the input current must be limited to 5 mA.

ESD CAUTION

Rev. C | Page 5 of 20

AD8597/AD8599

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, unless otherwise noted.

70

60

50

40

30

20

NUMBER OF AMPLIFIERS

10

0

–75 –65 –55 –45 –35 –25 –15 –5 15 25 35 45 55 65 755

VOS (µV)

Figure 4. Input Offset Voltage Distribution

60

50

40

30

20

NUMBER OF AMPLIFIERS

10

0

0 0.2 1.6 1.8 2.0 2.41.41.21.00.4 0.6 0.8 2.2

TCVOS (µV)

Figure 5. TCVOS Distribution, −40°C ≤ TA ≤ +125°C

AD8599
MEAN = 8.23
STDEV = 24.47

MIN = –72.62
MAX = 62.09
V

= ±5V

SY

AD8599
MEAN = 0.346
STDEV = 0. 218

MIN = 0.010
MAX = 1.155
V

= ±5V

SY

70

60

50

40

30

20

NUMBER OF AMPL IFIE R S

10

0

–75 –65–55 –45 –35 –25 –15 –5 15 25 35 45 55 65 755

6274-001

VOS (µV)

AD8599
MEAN = 7.91
STDEV = 21. 89
MIN = –63.02
MAX = 57.5

= ±15V

V

SY

06274-002

Figure 7. Input Offset Voltage Distribution

45

40

35

30

25

20

15

NUMBER OF AMPLIFIERS

10

5

0

0 0.2 1.6 1.8 2.0 2.41.41.21.00.4 0.6 0.8 2.2

06274-004

TCVOS (µV)

AD8599
MEAN = 0.765
STDEV = 0.234

MIN = 0.338
MAX = 1.709

= ±15V

V

SY

6274-007

Figure 8. TCVOS Distribution, −40°C ≤ TA ≤ +125°C

60

50

40

30

20

NUMBER OF AMPLIFIERS

10

0

0 0.2 1.6 1.8 2.0 2.41.41.21.00.4 0.6 0.8 2.2

TCVOS (µV)

Figure 6. TCVOS Distribution, −40°C ≤ TA ≤ +85°C

AD8599
MEAN = 0.461
STDEV = 0. 245
MIN = 0.026
MAX = 1.26
V

= ±5V

SY

6274-006

Rev. C | Page 6 of 20

60

50

40

30

20

NUMBER OF AMPLIFIERS

10

0

0 0.2 1.6 1.8 2.0 2.41.41.21.00.4 0.6 0.8 2.2

TCVOS (µV)

Figure 9. TCVOS Distribution, −40°C ≤ TA ≤ +85°C

AD8599
MEAN = 0.342
STDEV = 0. 221

MIN = 0.013
MAX = 1.239

= ±15V

V

SY

06274-005

AD8597/AD8599

100

75

50

25

(µV)

0

OS

V

–25

–50

–75

–100

–5.0 –2.5 0 2.5 5.0

AD8599

V

SY

VCM (V)

= ±5V

Figure 10. Offset Voltage vs. VCM

350

AD8599

300

V

= ±5V

SY

= 0V

V

CM

250
200
150

100

(nA)

B

50

I

0

–50
–100
–150
–200

–50 –25 0 25 50

TEMPERATURE ( °C)

75 100

Figure 11. Input Bias Current vs. Temperature

6274-009

125

06274-011

100

75

50

25

(µV)

0

OS

V

–25

–50

–75

–100

–15 –10 –5 0 5

AD8599

V

SY

VCM (V)

= ±15V

Figure 13. Offset Voltage vs. VCM

350

AD8599

300

V

= ±15V

SY

V

= 0V

CM

250
200
150

100

(nA)

B

50

I

0

–50
–100
–150
–200

–50 –25 0 25 50

TEMPERATURE (°C)

Figure 14. Input Bias Current vs. Temperature

10 15

75 100

6274-010

125

06274-012

50

AD8597

40

30

20

10

(µV)

0

OS

V

±15V

–10

–20

–30

–40

–50

–50 –25 0 25 50 75 100 125 150

±5V

TEMPERATURE (°C)

Figure 12. Input Offset Voltage vs. Temperature

06274-062

Rev. C | Page 7 of 20

350

AD8597

300

V

= ±15V

SY

250
200
150
100

50

0

(nA)

B

I

–50
–100
–150
–200
–250
–300
–350

–12–10–8–6–4–2024681012

TA = –40°C

TA = +25°C

TA = +85°C

TA = +125°C

VCM (V)

Figure 15. Input Bias Current vs. Temperature

06274-063

AD8597/AD8599

80

AD8599

70

60

50

40

(nA)

OS

I

30

20

10

–50 –25 0 25 50

IOS @ VSY = ±5V

IOS @ VSY = ±15V

TEMPERATURE (°C)

Figure 16. Input Offset Current vs. Temperature

75 1000125

6274-013

150

AD8597

100

50

0

(nA)

B

I

–50

–100

–150

–50 –25 0 25 50 75 100 125

±15V

±5V

TEMPERATURE (°C)

Figure 19. Input Offset Current vs. Temperature

06274-065

114

AD8599
V

= ±5V

SY

112

110

108

(dB)

VO

106

A

104

102

100

RL = 600, VO = ±2V

RL = 2k, VO = ±2V

75 100

TEMPERATURE ( °C)

Figure 17. Large Signal Voltage Gain vs. Temperature

8

AD8597

7

6

5

4

(mA)

SY

I

3

2

1

0

0 2 4 6 8 1012141618202224262830323436

= +125°C

T

A

T

VSY (V)

= +85°C

A

TA = +25°C

Figure 18. Supply Current vs. Supply Voltage

= –40°C

T

A

120

AD8599
V

= ±15V

SY

118

116

(dB)

VO

A

114

112

150125–50 –25 0 25 50

6274-015

110

–50 –25 0 25 50

RL = 600, VO = ±11V

RL = 2k, VO = ±11V

75 100

TEMPERATURE (°C)

150125

6274-016

Figure 20. Large Signal Voltage Gain vs. Temperature

350

AD8599

300

= ±15V

V

SY

250
200
150
100

50

0

(nA)

B

I

–50
–100
–150
–200
–250

06274-064

–300
–350

–12 –10 –8 –6 –4

TA = –40°C

TA = +25°C

TA = +85°C

TA = +125°C

–2 0

VCM (V)

6

42

12

108

06274-014

Figure 21. Input Bias Current vs. VCM

Rev. C | Page 8 of 20

AD8597/AD8599

V

V

80

60

I

40

SINK

AD8599
V

= ±5V

SY

80

60

I

40

SINK

AD8599
V

= ±15V

SY

20

0

–20

OUTPUT CURRENT ( mA)

–40

I

SOURCE

–60

–80

–50 –25 0 25 50

75 100

TEMPERATURE ( °C)

Figure 22. ISC vs. Temperature

10k

AD8599
V

= ±5V

SY

I

SINK

1k

I

SOURCE

OUTPUT SATURATION VO LTAGE (mV)

100

0.001 0.01 0.1 1 10
IL (mA)

Figure 23. Output Saturation Voltage vs. Current Load

20

0

–20

OUTPUT CURRENT ( mA)

–40

I

SOURCE

–60

150125

06274-017

–80

–50 –25 0 25 50

TEMPERATURE ( °C)

75 100

150125

06274-018

Figure 25. ISC vs. Temperature

10k

AD8599
V

= ±15V

SY

I

SINK

1k

I

SOURCE

OUTPUT SATURATION VO LTAGE (mV)

100

100

06274-021

0.001 0.01 0.1 1 10
IL (mA)

100

06274-022

Figure 26. Output Saturation Voltage vs. Current Load

2.5
AD8599
V

= ±5V

SY

2.0

1.5

(V)

OH

–

CC

1.0

V

VCC – VOH@ RL = 600

VCC – VOH@ RL = 2k

0.5

0
–50 –25 0 25 50

75 100 125 150

TEMPERATURE (°C)

Figure 24. Output Saturation Voltage vs. Temperature

6274-027

Rev. C | Page 9 of 20

2.5
AD8599

V

= ±15V

SY

2.0

VCC – VOH@ RL = 600

1.5

(V)

OH

–

CC

1.0

V

VCC – VOH@ RL = 2k

0.5

0
–50 –25 0 25 50

75 100 125 150

TEMPERATURE (°C)

Figure 27. Output Saturation Voltage vs. Temperature

6274-029

AD8597/AD8599

V

–

V

–0.5

0

AD8599
V

= ±5V

SY

–0.5

0

AD8599
V

= ±15V

SY

–1.0

(V)

OL

–

EE

–1.5

V

VEE – VOL@ RL = 2k

VEE – VOL@ RL = 600

–2.0

–2.5

–50 –25 0 25 50

75 100 125 150

TEMPERATURE (°C)

Figure 28. Output Saturation Voltage vs. Temperature

13.0

–13.5

(V)

–14.0

OL

V

–14.5

AD8599

= ±15V

V

SY

–15.0

–50 0 50

VOL@ RL = 600

VOL@ RL = 2k

TEMPERATURE (°C)

Figure 29. Output Voltage Low vs. Temperature

100 150

–1.0

(V)

OL

–

EE

–1.5

V

–2.0

–2.5

–50 –25 0 25 50

06274-028

VEE – VOL@ RL = 2k

VEE – VOL@ RL = 600

75 100 125 150

TEMPERATURE (°C)

6274-030

Figure 31. Output Saturation Voltage vs. Temperature

15.0
AD8599

14.8

V

= ±15V

SY

14.6

14.4

14.2

(V)

14.0

OH

V

13.8

VOH@ RL = 2k

13.6

13.4

VOH@ RL = 600

13.2

13.0

–50 0 50

06274-032

TEMPERATURE (°C)

100 150

06274-031

Figure 32. Output Voltage High vs. Temperature

100

80

60

40

C

L

= 20pF

20

0

–20

–40

–60

GAIN (dB) AND P HASE (Degrees)

AD8597
V

= ±5V

SY

–80

R

= 2k

L

–100

10 100 1k 10k 50k

CL = 200pF

FREQUENCY (kHz)

Figure 30. Gain and Phase vs. Frequency

06274-066

Rev. C | Page 10 of 20

120

100

80

60

40

20

0

–20

–40

GAIN (dB) AND P HASE (Degrees)

AD8597
V

= ±15V

SY

–60

R

= 2k

L

–80

1 10 100 1k 50k10k

FREQUENCY (kHz)

Figure 33. Gain and Phase vs. Frequency

C

L

= 20pF

CL = 200pF

06274-067

AD8597/AD8599

50

40

AV = 100

30

20

AV = 10

10

0

GAIN (dB)

–10

–20

–30

–40

= 1

A

V

AD8597
V

= ±5V

SY

R

= 2k

L

1 10 100 1k 50k10k

FREQUENCY (kHz)

Figure 34. Closed-Loop Gain vs. Frequency

06274-068

50

40

AV = 100

30

20

AV = 10

10

0

GAIN (dB)

–10

–20

–30

–40

= 1

A

V

AD8597
V

= ±15V

SY

R

= 2k

L

1 10 100 1k 50k10k

FREQUENCY (kHz)

Figure 37. Closed-Loop Gain vs. Frequency

06274-071

100

AV = –100

10

AV = –10

()

1

OUT

Z

0.1

0.01
10 100 1k 10k 100k

AV = +1

FREQUENCY (kHz)

AD8597
V

Figure 35. Closed-Loop Output Impedance vs. Frequency

110

100

90

80

70

60

CMRR (dB)

AD8597
V

= ±5V, ±15V

50

40

30

20

SY

1 10 100 1k 10k

FREQUENCY (kHz)

Figure 36. Common-Mode Rejection Ratio vs. Frequency

SY

= ±5V

100

AV = –100

10

AV = –10

()

1

OUT

Z

0.1

06274-069

0.01
10 100 1k 10k 100k

AV = +1

FREQUENCY (kHz)

AD8597
V

= ±15V

SY

06274-072

Figure 38. Closed-Loop Output Impedance vs. Frequency

120

100

80

60

40

PSRR (dB)

20

0

06274-070

–20

100 1k 10k 100k 1M

FREQUENCY (Hz)

AD8599
±5V  V

 ±15V

SY

PSRR+ (dB)
PSRR– (dB)

10M

06274-038

Figure 39. Power Supply Rejection Ratio vs. Frequency

Rev. C | Page 11 of 20

AD8597/AD8599

90

80

70

60

50

40

30

NUMBER OF AMPLIFIERS

20

10

0

1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.9 2.01.8
VOLTAGE NOISE DENSITY (nV/ Hz)

Figure 40. Voltage Noise Density @ 10 Hz

100

AD8599
±5V  V

 ±15V

SY

10

AD8599
MEAN = 1.30
STDEV = 0. 09

MIN = 1.1
MAX = 1.5

 ±15V

±5V  V

SY

6274-039

600

500

400

300

200

NUMBER OF AMPL IFIERS

100

0

0.95 0.98 1.01 1.04 1.07 1.10 1.13 1.16 1.19
VOLTAGE NOISE DENSITY (nV/ Hz)

AD8599
MEAN = 1.07
STDEV = 0.02

MIN = 1.05
MAX = 1.15
±5V  V

Figure 43. Voltage Noise Density @ 1 kHz

100

AD8599

 ±15V

±5V  V

SY

10

SY

 ±15V

6274-040

1

VOLTAGE NOISE DENSITY (nV/ Hz)

0.1
1 10 100 1k

FREQUENCY (Hz)

Figure 41. Voltage Noise Density vs. Frequency

1

0.1

RL = 600

0.01
AD8597

THD + N (%)

V

= ±5V

SY

A

= +1

V

0.001

0.0001

0.001 0.01 0.1 1 10
V rms (V)

RL = 100k

Figure 42. THD + N vs. Amplitude

1

CURRTENT NOIS E DE NS ITY (pA/ Hz )

0.1
110100

06274-041

FREQUENCY (Hz)

1k

06274-042

Figure 44. Current Noise Density vs. Frequency

1

0.1

0.01
AD8597

THD + N (%)

V

= ±15V

SY

= +1

A

V

0.001

06274-073

0.0001

0.001 0.01 0.1 1 10
V rms (V)

RL = 600

RL = 100k

06274-074

Figure 45. THD + N vs. Amplitude

Rev. C | Page 12 of 20

AD8597/AD8599

0.1
AD8599

= ±15V

V

SY

VIN = 3V rms
V

= 5V rms

IN

V

= 7V rms

IN

0.1
AD8599
V

= ±15V

SY

= 3V rms

V

IN

0.01

THD + N (%)

0.001

0.0001
10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 46. THD + N vs. Frequency

20

AD8599

15

10

5

0

–5

AMPLITUDE (V)

–10

–15

–20

–8.6 –4.6 –0.6 3.4 7.4 11.4 15.4 19.4 23.4

VSY = ±15V
V

= 20V p-p

IN

A

= 1

V

R

= 1k

F

R

= 2k

L

VERTICAL AXIS = 5V/DIV
HORIZONTAL AXIS = 4µ s/DIV

TIME (µs)

Figure 47. Large Signal Response

27.4 31.4

0.01

THD + N (%)

0.001

RL = 600

RL = 2k

0.0001
10 100 1k 10k 100k

06274-044

FREQUENCY (Hz)

06274-043

Figure 49. THD + N vs. Frequency

20

AD8599

15

10

5

0

–5

AMPLITUDE (V)

–10

–15

–20

–8.6 –4.6 –0.6 3.4 7.4 11.4 15.4 19.4 23.4

06274-047

VSY = ±15V
V

= 20V p-p

IN

A

= –1

V

R

= 2k

F

R

= 2k

S

C

= 0pF

L

VERTICAL AXIS = 5V/DIV
HORIZONTAL AXIS = 4µs/DIV

TIME (µs)

27.4 31.4

06274-048

Figure 50. Large Signal Response

80

AD8599

60

40

20

0

–20

AMPLITUDE (mV)

–40

–60

VSY = ±15V, ±5V
V

= 100mV p-p

IN

A

= 1

V

EXTERNAL C
EXTERNAL R
VERTICAL AXIS = 20mV/DI V

= 100pF

L

= 10k

L

HORIZONTAL AXIS = 400ns/DIV

–80

–800 –400 0 400 800 1200 1600 2000 2400

TIME (ns)

Figure 48. Small Signal Response

2800 3200

06274-046

Rev. C | Page 13 of 20

45

AD8599

 ±15V

±5V  V
A

V

R

L

= 1
= 10k

SY

40

35

30

25

20

OVERSHOOT (%)

15

10

5

0

10 100 1k

CAPACITANCE (pF )

Figure 51. Overshoot vs. Capacitance

06274-049

AD8597/AD8599

45

AD8597
V

= ±5V

SY

40

35

30

25

20

OVERSHOOT (%)

15

10

5

0

10 100 1k

OS–

OS+

CAPACITANCE (pF)

Figure 52. Overshoot vs. Capacitive Load

06247-077

45

AD8597
V

= ±15V

SY

40

35

30

25

20

OVERSHOOT (%)

15

10

OS+

5

0

10 100 1k

CAPACITANCE (pF)

OS–

Figure 55. Overshoot vs. Capacitive Load

06247-078

0

–20

–40

–60

–80

–100

–120

CHANNEL SEPARATION (dB)

–140

–160

100 1k 10k 100k 1M

FREQUENCY (Hz)

AD8599
V

SY

A

V

R

L

VIN = 10V p-p
V

IN

Figure 53. Channel Separation vs. Frequency

800

AD8599

 ±15V

±5V  V

SY

AMPLITUDE (nV)

600

400

200

0

–200

–400

= ±15V
= 100
= 1k

= 20V p-p

15.0
AD8599

12.5

10.0

(mA)

SY

I

7.5

5.0

06274-050

–50 –25 0 25 50

VSY = ±15V

V

= ±5V

SY

TEMPERATURE ( °C)

75 100

125

06274-020

Figure 56. Supply Current vs. Temperature

6.0
AD8597

5.5

VSY = ±15V

5.0

(mA)

SY

I

4.5

VSY = ±5V

–600

–800

012345678

TIME (S eco n ds)

Figure 54. Peak-to-Peak Noise

910

4.0

–40 –25 –10 5 20 35 50 65 80 95 110 125

06274-053

TEMPERATURE (°C)

Figure 57. Supply Current vs. Temperature

06274-075

Rev. C | Page 14 of 20

AD8597/AD8599

FUNCTIONAL OPERATION

INPUT VOLTAGE RANGE

The AD8597/AD8599 are not rail-to-rail input amplifiers;
therefore, care is required to ensure that both inputs do not
exceed the input voltage range. Under normal negative feedback
operating conditions, the amplifier corrects its output to ensure
that the two inputs are at the same voltage. However, if either
input exceeds the input voltage range, the loop opens and large
currents begin to flow through the ESD protection diodes in the
amplifier.

These diodes are connected between the inputs and each supply
rail to protect the input transistors against an electrostatic discharge
event and they are normally reverse-biased. However, if the
input voltage exceeds the supply voltage, these ESD diodes
can become forward-biased. Without current limiting, excessive
amounts of current may flow through these diodes, causing
permanent damage to the device. If inputs are subject to over­voltage, insert appropriate series resistors to limit the diode
current to less than 5 mA maximum.

The input stage has two diodes between the input pins to
protect the differential pair. Under high slew rate conditions,
when the op amp is connected as a voltage follower, the diodes
may become forward-biased and the source may try to drive
the output. A small resistor should be placed in the feedback
loop and in the noninverting input. The noise of a 100 Ω
resistor at room temperature is ~1.25 nV/√Hz, which is higher
than the AD8597/AD8599. Thus, there is a tradeoff between
noise performance and protection. If possible, limiting should
be placed earlier in the signal path. For further details, see the
Amplifier Input Protection…Friend or Foe article at

http://www.analog.com/amplifier_input.

Because of the large transistors used to achieve low noise, the
input capacitance may seem rather high. To take advantage of
the low noise performance, impedance around the op amp should
be low, less than 500 Ω. Under these conditions, the pole from
the input capacitance should be greater than 50 MHz, which
does not affect the signal bandwidth.

The AD8597/AD8599 amplifiers have been carefully designed
to prevent any output phase reversal if both inputs are main­tained within the specified input voltage range. If one or both
inputs exceed the input voltage range but remain within the
supply rails, the op amp specifications, such as CMRR, are not
guaranteed, but the output remains close to the correct value.

NOISE AND SOURCE IMPEDANCE CONSIDERATIONS

The AD8597/AD8599 ultralow voltage noise of 1.1 nV/√Hz is
achieved with special input transistors running at high collector
current. Therefore, it is important to consider the total input­referred noise (e
voltage noise (e
(√4 kTR

where R

).

S

total = [e

e

N

is the total input source resistance.

S

This equation is plotted for the AD8597/AD8599 in Figure 58.
Because optimum dc performance is obtained with matched
source resistances, this case is considered even though it is clear
from Equation 1 that eliminating the balancing source resistance
lowers the total noise by reducing the total R

At a very low source resistance (R
amplifier dominates. As source resistance increases, the Johnson
noise of R
achieved; the current noise component is larger than the
resistor noise.

100

10

1

TOTAL NOISE (nV/ Hz)

total), which includes contributions from

N

), current noise (iN), and resistor noise

N

2

+ 4 kTRS + (iN × RS)2]

N

dominates until a higher resistance of RS > 2 kΩ is

S

TOTAL NOISE

1/2

(1)

by a factor of 2.

S

< 50 Ω), the voltage noise of the

S

RESISTOR NOIS E

ONLY

OUTPUT PHASE REVERSAL

Output phase reversal occurs in some amplifiers when the
input common-mode voltage range is exceeded. As the common­mode voltage is moved outside the input voltage range, the
outputs of these amplifiers can suddenly jump in the opposite
direction to the supply rail. This is the result of the differential
input pair shutting down that causes a radical shifting of
internal voltages that results in the erratic output behavior.

Rev. C | Page 15 of 20

0.1
10 100 1k 10k

SOURCE RESISTANCE ()

Figure 58. Noise vs. Source Resistance

06274-076

AD8597/AD8599

V

The AD8597/AD8599 are the optimum choice for low noise
performance if the source resistance is kept < 1 kΩ. At higher
values of source resistance, optimum performance with respect
to only noise is obtained with other amplifiers from Analog
Devices. Both voltage noise and current noise need to be consi­dered. For more information on avoiding noise from grounding
problems and inadequate bypassing, see the AN-345 Application
Note, Grounding for Low- and High-Frequency Circuits. For

+

7

R18 R19

Q18 Q19

D41
D42

Figure 59. Simplified Schematic

INVERTING

INPUT

NONINVERTING

INPUT

D1

2

–

D39
D40

3

+

D2

4

V–

V

B

Q19

Q27

general noise theory with extensive calculations, see the
AN-358 Application Note, Noise and Operational Amplifier
Circuits. A good selection table for low noise op amps can
be found in AN-940 Application Note, Low Noise Amplifier
Selection Guide for Optimal Noise Performance. An interesting
note on using one section of a monolithic dual to phase compen­sate the other section is in the AN-107 Application Note, Active
Feedback Improves Amplifier Phase Accuracy.

Q36

Q20

Q28

D31
D34

C1

R1

Q32

R31

R32

D2

6

OUTPUT

D3

06247-079

Rev. C | Page 16 of 20

AD8597/AD8599

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLL ING DIMENSIONS ARE IN MILLIME TERS; INCH DIM E NSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

Figure 60. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

INDICATOR

0.90 MAX

0.85 NOM

SEATING

PLANE

3.25

3.00 SQ

PIN 1

12° MAX

2.75

TOP

VIEW

0.70 MAX

0.65TYP

0.30

0.23

0.18

2.95

2.75 SQ

2.55

0.05 MAX

0.01 NOM

0.20 REF

0.60 MAX

Figure 61. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]

3 mm × 3 mm Body, Very Thin, Dual Lead

(CP-8-2)

Dimensions shown in millimeters

0.60 MAX

5

EXPOSED

PAD

(BOTTOM VIEW)

4

0.50

0.40

0.30

FOR PROPER CONNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO NS
SECTION OF THIS DATA SHEET.

1

0.50
BSC

8

1.60

1.45

1.30

PIN 1
INDICATOR

1.89

1.74

1.59

101708-B

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD8597ACPZ-R21 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 A22
AD8597ACPZ-REEL1 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 A22
AD8597ACPZ-REEL71 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 A22
AD8597ARZ1 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8597ARZ-REEL1 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8597ARZ-REEL71 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8599ARZ1 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8599ARZ-REEL1 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8599ARZ-REEL71 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8

1

Z = RoHS Complaint Part.

Rev. C | Page 17 of 20

AD8597/AD8599

NOTES

Rev. C | Page 18 of 20

AD8597/AD8599

NOTES

Rev. C | Page 19 of 20

AD8597/AD8599

NOTES

©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06274-0-12/09(C)

Rev. C | Page 20 of 20