16 V Rail-to-Rail
1
2
3
5
4
–IN
+IN
V–OUT
AD8565
V+
TOP VIEW
16
5
13
8
9
12
1
4
1415
2
3
76
11
10
–IN D
+IN D
V–
+IN C
–IN A
+IN A
V+
+IN B
NC
OUT A
OUT D
NC
–IN B
OUT B
OUT C
–IN C
AD8567
NC = NO CONNECT
a
FEATURES
Single-Supply Operation: 4.5 V to 16 V
Input Capability beyond the Rails
Rail-to-Rail Output Swing
Continuous Output Current: 35 mA
Peak Output Current: 250 mA
Offset Voltage: 10 mV
Slew Rate: 6 V/s
Unity Gain Stable with Large Capacitive Loads
Supply Current: 700 A per Amplifier
APPLICATIONS
LCD Reference Drivers
Portable Electronics
Communications Equipment
GENERAL DESCRIPTION
The AD8565, AD8566, and AD8567 are low cost, single-supply
rail-to-rail input and output operational amplifiers optimized for
LCD monitor applications. They are built on an advanced high
voltage CBCMOS process. The AD8565 contains a single
amplifier, the AD8566 has two amplifiers, and the AD8567 has
four amplifiers.
These LCD op amps have high slew rates, 35 mA continuous
output drive, 250 mA peak output drive, and high capacitive load
drive capability. They have a wide supply range and offset voltages below 10 mV. The AD8565, AD8566, and AD8567 are
ideal for LCD grayscale reference buffer and V
The AD8565, AD8566, and AD8567 are specified over the –40°C
to +85°C temperature range. The AD8565 single is available in a
5-lead SC70 package. The AD8566 dual is available in an 8-lead
MSOP package. The AD8567 quad is available in 14-lead TSSOP
and 16-lead LFCSP packages.
applications.
COM
AD8565/AD8566/AD8567
5-Lead SC70
(KS Suffix)
Operational Amplifiers
PIN CONFIGURATIONS
8-Lead MSOP
(RM Suffix)
AD8566
1
OUT A
–IN A
2
+IN A
36
V–
45
14-Lead TSSOP
(RU Suffix)
1
OUT A
213
–IN A
3
+IN A
4
V+
+IN B
–IN B
OUT B
AD8567
510
69
78
14
12
11
16-Lead LFCSP
(CP Suffix)
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
8
7
V+
OUT B
–IN B
+IN B
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
AD8565/AD8566/AD8567–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(4.5 V ≤ VS ≤ 16 V, VCM = VS/2, TA = 25C, unless otherwise noted.)
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage V
Offset Voltage Drift ∆V
Input Bias Current I
Input Offset Current I
OS
/∆T –40°C ≤ TA ≤ +85°C5 µV/°C
OS
B
OS
–40°C ≤ T
–40°C ≤ T
≤ +85°C 800 nA
A
≤ +85°C 130 nA
A
Input Voltage Range Common-Mode Input –0.5 V
Common-Mode Rejection Ratio CMRR V
Large Signal Voltage Gain AVO R
Input Impedance Z
Input Capacitance C
IN
IN
= 0 to VS,
CM
–40°C ≤ T
= 10 kΩ,
L
= 0.5 V to (VS – 0.5 V) 3 10 V/mV
V
O
≤ +85°C5495 dB
A
210 mV
80 600 nA
180 nA
+ 0.5 V
S
400 kΩ
1pF
OUTPUT CHARACTERISTICS
Output Voltage High V
Output Voltage Low V
Continuous Output Current I
Peak Output Current I
OH
OL
OUT
PK
IL = 100 µAV
= 16 V, IL = 5 mA 15.85 15.95 V
V
S
–40°C ≤ T
V
= 4.5 V, IL = 5 mA 4.2 4.38 V
S
–40°C ≤ T
≤ +85°C 15.75 V
A
≤ +85°C 4.1 V
A
– 0.005 V
S
IL = 100 µA5mV
V
= 16 V, IL = 5 mA 42 150 mV
S
–40°C ≤ T
= 4.5 V, IL = 5 mA 95 300 mV
V
S
–40°C ≤ T
≤ +85°C 250 mV
A
≤ +85°C 400 mV
A
35 mA
VS = 16 V 250 mA
POWER SUPPLY
Supply Voltage V
S
Power Supply Rejection Ratio PSRR V
Supply Current/Amplifier I
SY
= 4 V to 17 V,
S
–40°C ≤ T
≤ +85°C7090 dB
A
VO = VS/2, No Load 700 850 µA
4.5 16 V
–40°C ≤ TA ≤ +85°C1mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ, CL = 200 pF 4 6 V/µs
Gain Bandwidth Product GBP R
Phase Margin ØoR
= 10 kΩ, CL = 10 pF 5 MHz
L
= 10 kΩ, CL = 10 pF 65 Degrees
L
Channel Separation 75 dB
NOISE PERFORMANCE
Voltage Noise Density e
Current Noise Density i
Specifications subject to change without notice.
n
e
n
n
f = 1 kHz 26 nV/√Hz
f = 10 kHz 25 nV/√Hz
f = 10 kHz 0.8 pA/√Hz
–2–
REV. C
AD8565/AD8566/AD8567
ABSOLUTE MAXIMUM RATINGS
*
Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V
+ 0.5 V
S
S
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Package Type
5-Lead SC70 (KS) 376 126 °C/W
8-Lead MSOP (RM) 210 45 °C/W
14-Lead TSSOP (RU) 180 35 °C/W
16-Lead LFCSP (CP) 38
NOTES
1
θJA is specified for worst-case conditions, i.e., θ
onto a circuit board for surface-mount packages.
2
DAP is soldered down to PCB.
1
JA
2
JC
2
30
is specified for a device soldered
JA
Unit
°C/W
ORDERING GUIDE
Temperature Package
Model Range Package Description Option Branding
AD8565AKS-R2 –40°C to +85°C 5-Lead Thin Shrink Small Outline Transistor Package KS-5 ASA
AD8565AKS-REEL7 –40°C to +85°C 5-Lead Thin Shrink Small Outline Transistor Package KS-5 ASA
AD8565AKSZ-REEL7* –40°C to +85°C 5-Lead Thin Shrink Small Outline Transistor Package KS-5 ASA
AD8566ARM-R2 –40°C to +85°C 8-Lead Micro Small Outline Package RM-8 ATA
AD8566ARM-REEL –40°C to +85°C 8-Lead Micro Small Outline Package RM-8 ATA
AD8566ARMZ-REEL* –40°C to +85°C 8-Lead Micro Small Outline Package RM-8 ATA
AD8567ARU –40°C to +85°C 14-Lead Thin Shrink Small Outline Package RU-14
AD8567ARU-REEL –40°C to +85°C 14-Lead Thin Shrink Small Outline Package RU-14
AD8567ARUZ* –40°C to +85°C 14-Lead Thin Shrink Small Outline Package RU-14
AD8567ARUZ-REEL* –40°C to +85°C 14-Lead Thin Shrink Small Outline Package RU-14
AD8567ACP-R2 –40°C to +85°C 16-Lead Lead Frame Chip Scale Package CP-16
AD8567ACP-REEL –40°C to +85°C 16-Lead Lead Frame Chip Scale Package CP-16
AD8567ACP-REEL7 –40°C to +85°C 16-Lead Lead Frame Chip Scale Package CP-16
AD8567ACPZ-REEL* –40°C to +85°C 16-Lead Lead Frame Chip Scale Package CP-16
AD8567ACPZ-REEL7* –40°C to +85°C 16-Lead Lead Frame Chip Scale Package CP-16
*Z = Pb-free part.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8565/AD8566/AD8567 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. C
–3–
WARNING!
ESD SENSITIVE DEVICE
AD8565/AD8566/AD8567
–Typical Performance Characteristics
0
VCM = VS/2
0.25
0.50
0.75
VS = 4.5V
1.00
INPUT OFFSET VOLTAGE (mV)
1.25
1.50
40
VS = 16V
25 85
TEMPERATURE (C)
TPC 1. Input Offset Voltage vs. Temperature
10
4.5V VS 16V
T
= 25C
A
1
CURRENT NOISE DENSITY (pA Hz)
1000
4.5V VS 16V
= 25C
T
A
100
10
VOLTAGE NOISE DENSITY (nV Hz)
1
10 10k100 1k
FREQUENCY (Hz)
TPC 4. Voltage Noise Density vs. Frequency
1.0
VO = VS/2
= +1
A
V
T
= 25C
A
0.8
0.6
0.4
0.2
SUPPLY CURRENT/AMPLIFIER (mA)
0.1
10 10k100 1k
FREQUENCY (Hz)
TPC 2. Current Noise Density vs. Frequency
VS = 16V
= 10k
R
L
= 100pF
C
L
= +1
A
V
= 25C
T
A
TIME (50mV/DIV)
FREQUENCY (1s/DIV)
TPC 3. Small Signal Transient Response
0
0182
4681012 14 16
SUPPLY VOLTAGE (V)
TPC 5. Supply Current/Amplifier vs. Supply Voltage
0.80
VCM = VS/2
0.75
VS = 16V
0.70
0.65
0.60
0.55
SUPPLY CURRENT/AMPLIFIER (mA)
0.50
40
TEMPERATURE (C)
VS = 4.5V
25 85
TPC 6. Supply Current/Amplifier vs. Temperature
–4–
REV. C
100
1k 100M10k
GAIN (dB)
100k 1M 10M
100
80
60
40
20
FREQUENCY (Hz)
45
90
135
180
0
225
270
PHASE SHIFT (degrees)
VS = 16V
R
L
= 10k
C
L
= 40pF
T
A
= 25C
0
VS = 16V
90
= 100mV p-p
V
IN
= 10k
R
L
80
= +1
A
V
= 25C
T
A
70
60
50
40
OVERSHOOT (%)
30
20
10
0
10 1k100
LOAD CAPACITANCE (pF)
AD8565/AD8566/AD8567
–OS
+OS
TPC 7. Small Signal Overshoot vs. Load Capacitance
18
16
14
12
10
8
6
OUTPUT SWING (V p-p)
VS = 16V
A
= +1
4
V
= 10k
R
L
DISTORTION < 1%
2
= 25C
T
A
0
100
10 1k 10k 100k 1M 10M
FREQUENCY (Hz)
TPC 8. Closed-Loop Output Swing vs. Frequency
60
50
A
= –100
VCL
40
30
A
= –10
VCL
20
10
A
= +1
VCL
0
CLOSED-LOOP GAIN (dB)
10010 1k
TPC 9. Closed-Loop Gain vs. Frequency
10k
FREQUENCY (Hz)
4.5V VS 16V
= 10k
R
L
= 40pF
C
L
= 25C
T
A
100k 1M 10M
TPC 10. Open-Loop Gain and Phase Shift vs. Frequency
1k
TA = 25C
100
10
OUTPUT VOLTAGE (mV)
1
0.1
0.001 1000.01 0.1 1 10
LOAD CURRENT (mA)
VS = 4.5V
VS = 16V
TPC 11. Output Voltage to Supply Rail vs. Load Current
150
I
135
120
105
90
75
60
45
OUTPUT VOLTAGE (mV)
30
15
= 5mA
SINK
VS = 4.5V
VS = 16V
0
40
25 85
TEMPERATURE (C)
TPC 12. Output Voltage Swing to Rail vs. Temperature
REV. C
–5–
AD8565/AD8566/AD8567
150
I
= 5mA
SOURCE
135
120
105
90
75
60
45
OUTPUT VOLTAGE (mV)
30
15
0
40
TEMPERATURE (C)
VS = 4.5V
VS = 16V
25 85
TPC 13. Output Voltage Swing to Rail vs. Temperature
500
AV = +1
450
400
350
300
250
200
IMPEDANCE ()
150
100
= 25C
T
A
50
0
100 10M1k
VS = 4.5V
10k 100k 1M
FREQUENCY (Hz)
VS = 16V
TPC 14. Closed-Loop Output Impedance vs. Frequency
160
VS = 16V
140
= 25C
T
A
120
100
80
60
40
20
0
POWER SUPPLY REJECTION RATIO (dB)
20
40
100 10M1k
+PSRR
–PSRR
10k 100k 1M
FREQUENCY (Hz)
TPC 16. Power Supply Rejection Ratio vs. Frequency
VS = 16V
R
= 10k
L
= +1
A
V
= 25C
T
A
VOLTA GE (3V/DIV)
TIME (40s/DIV)
TPC 17. No Phase Reversal
VS = 16V
140
120
100
CMRR (dB)
= 25C
T
A
80
60
40
20
0
10010 1k
FREQUENCY (Hz)
100k 1M 10M
10k
TPC 15. Common-Mode Rejection Ratio vs. Frequency
–6–
1.8k
VS = 16V
1.6k
= 25C
T
A
1.4k
1.2k
1.0k
800
600
QUANTITY (Amplifiers)
400
200
0
10108 6 4 2
INPUT OFFSET VOLTAGE (mV)
02468
TPC 18. Input Offset Voltage Distribution
REV. C
5
COMMON-MODE VOLTAGE (V)
7
0
0162
BANDWIDTH (MHz)
4681012 14
6
4
3
2
1
5
VS = 16V
A
V
= +1
RL = x
T
A
= 25C
4
3
2
1
0
–1
–2
INPUT OFFSET CURRENT (nA)
–3
–4
–5
–40
VS = 4.5V
VS = 16V
25 85
TEMPERATURE (C)
TPC 19. Input Offset Current vs. Temperature
AD8565/AD8566/AD8567
TPC 22. Frequency vs. Common-Mode Voltage (VS = 16 V)
0
VCM = VS/2
–50
–40
VS = 16V
VS = 4.5V
25 85
TEMPERATURE (C)
–100
–150
–200
–250
INPUT BIAS CURRENT (nA)
–300
–350
TPC 20. Input Bias Current vs. Temperature
–20
–40
–60
–80
–100
–120
CROSSTALK (dB)
–140
4.5V
16V
6
VS = 5V
= +1
A
5
4
3
2
BANDWIDTH (MHz)
1
0
051
234
COMMON-MODE VOLTAGE (V)
V
R
L
T
A
= 10k
= 25C
TPC 23. Frequency vs. Common-Mode Voltage
(VS = 5.0 V)
–160
–180
50 1k 60k10k100
TPC 21. Channel A vs. Channel B Crosstalk
REV. C
FREQUENCY (Hz)
–7–
AD8565/AD8566/AD8567
APPLICATIONS
Theory of Operation
The AD856x family is designed to drive large capacitive loads in
LCD applications. It has high output current drive, rail-to-rail
input/output operation, and is powered from a single 16 V supply.
It is also intended for other applications where low distortion and
high output current drive are needed.
Figure 1 illustrates a simplified equivalent circuit for the AD856x.
The rail-to-rail bipolar input stage is composed of two PNP
differential pairs, Q4 to Q5 and Q10 to Q11, operating in series
with diode protection networks, D1 to D2. Diode network
D1 to D2 serves as protection against large transients for
Q4 to Q5 to accommodate rail-to-rail input swing. D5 to D6
protect Q10 to Q11 against Zenering. In normal operation,
Q10 to Q11 are off and their input stage is buffered from the
operational amplifier inputs by Q6 to D3 and Q8 to D4. Opera-
tion of the input stage is best understood as a function of applied
common-mode voltage: when the inputs of the AD856x are
biased midway between the supplies, the differential signal
path gain is controlled by resistive loads (via R9, R10) Q4 to Q5.
As the input common-mode level is reduced toward the negative
supply (V
or GND), the input transistor current sources, I1
NEG
and I2, are forced into saturation, thereby forcing the Q6 to D3
and Q8 to D4 networks into cutoff. However, Q4 to Q5 remain
active, providing input stage gain. Inversely, when common-mode
input voltage is increased toward the positive supply, Q4 to Q5
are driven into cutoff, Q3 is driven into saturation, and Q4
becomes active, providing bias to the Q10 to Q11 differential
pair. The point at which Q10 to Q11 differential pair becomes
active is approximately equal to (V
R1
Q3
D1 D2
R3 R4
Q6
V+
D3 D4
I1 I2
C1
Q4
R5 R6
Q10
R9 R10
– 1 V).
POS
V
POS
Q4
Q5
C2
Q11
D5
D6
V
NEG
BIAS LINE
Q8
V–
FOLDED
CASCADE
Figure 1. AD856x Equivalent Input Circuit
The benefit of this type of input stage is low bias current. The
input bias current is the sum of base currents of Q4 to Q5 and
Q6 to Q8 over the range from (V
+ 1 V) to (V
NEG
– 1 V). Out-
POS
side of this range, input bias current is dominated by the sum of
base currents of Q10 to Q11 for input signals close to V
Q6 to Q8 (Q10 to Q11) for signals close to V
. From this type
POS
NEG
and of
of design, the input bias current of AD856x not only exhibits
different amplitude but also exhibits different polarities. Figure 2
provides the characteristics of the input bias current versus the
common-mode voltage. It is important to keep in mind that the
source impedances driving the AD856x inputs are balanced for
optimum dc and ac performance.
1,000
VS = 16V
800
= 25C
T
A
600
400
200
0
–200
–400
INPUT BIAS CURRENT (nA)
–600
–800
–1,000
0162
468101214
INPUT COMMON-MODE VOLTAGE (V)
Figure 2. AD856x Input Bias Current vs. Common-Mode
Voltage
In order to achieve rail-to-rail output performance, the AD856x
design uses a complementary common-source (or gmRL) output.
This configuration allows output voltages to approach the power
supply rails, particularly if the output transistors are allowed to
enter the triode region on extremes of signal swing, which are
limited by V
, the transistor sizes, and output load current.
GS
Also, this type of output stage exhibits voltage gain in an open-loop
gain configuration. The amount of gain depends on the total
load resistance at the output of the AD856x.
Input Overvoltage Protection
As with any semiconductor device, whenever the input exceeds
either supply voltages, attention needs to be paid to the input
overvoltage characteristics. As an overvoltage occurs, the amplifier
could be damaged, depending on the voltage level and the magnitude
of the fault current. When the input voltage exceeds either supply
by more than 0.6 V, internal pn junctions allow current to flow
from the input to the supplies.
This input current is not inherently damaging to the device as
long as it is limited to 5 mA or less. If a condition exists using
the AD856x where the input exceeds the supply more than 0.6 V,
an external series resistor should be added. The size of the resistor can be calculated by using the maximum overvoltage divided
by 5 mA. This resistance should be placed in series with either
input exposed to an overvoltage.
–8–
REV. C
AD8565/AD8566/AD8567
FREQUENCY (Hz)
20 30k
THD+N (%)
100
1k 10k
10
1
0.01
0.1
VS = 2.5V
VS = 8V
Output Phase Reversal
The AD856x family is immune to phase reversal. Although
the device’s output will not change phase, large currents due
to input overvoltage could damage the device. In applications
where the possibility of an input voltage exceeding the supply
voltage exists, overvoltage protection should be used as described
in the previous section.
Total Harmonic Distortion + Noise (THD+N)
The AD856x family features low total harmonic distortion.
Figure 4 shows a graph of THD+N versus frequency. The THD+N
for the AD856x over the entire supply range is below 0.008%.
When the device is powered from a 16 V supply, the THD+N
stays below 0.003%. Figure 4 shows the AD8566 in a unity
noninverting configuration.
Power Dissipation
The maximum allowable internal junction temperature of 150°C
limits the AD856x family’s maximum power dissipation of
AD856x devices. As the ambient temperature increases, the
maximum power dissipated by AD856x devices must decrease
linearly to maintain the maximum junction temperature. If this
maximum junction temperature is exceeded momentarily, the
device will still operate properly once the junction temperature is
reduced below 150°C. If the maximum junction temperature is
exceeded for an extended period of time, overheating could lead
to permanent damage of the device.
The maximum safe junction temperature, T
, is 150°C. Using
J
MAX
the following formula, we can obtain the maximum power that
an AD856x device can safely dissipate as a function of temperature:
P
= T
DISS
where:
= the AD856x power dissipation.
P
DISS
T
= the AD856x maximum allowable junction
J
MAX
temperature (150°C).
= the ambient temperature of the circuit.
T
A
θ
= the AD856x package thermal resistance,
J
A
junction-to-ambient.
The power dissipated by the device can be calculated as
P
= (VS – V
DISS
where:
= the supply voltage.
V
S
V
= the output voltage.
OUT
= the output load current.
I
LOAD
Figure 3 shows the maximum power dissipation versus temperature.
To achieve proper operation, use the previous equation to calculate
P
for a specific package at any given temperature or use the
DISS
figure below.
1.25
14-LEAD SOIC
1.00
J
MAX
– TA/
OUT
) ⫻ I
θ
J
LOAD
A
Figure 4. THD+N vs. Frequency Graph
Short-Circuit Output Conditions
The AD856x family does not have internal short-circuit protection
circuitry. As a precautionary measure, it is recommended not to
short the output directly to the positive power supply or to ground.
It is not recommended to operate the AD856x with more than
35 mA of continuous output current. The output current can be
limited by placing a series resistor at the output of the amplifier
whose value can be derived using the following equation:
V
≥
35 mA
S
R
X
For a 5 V single-supply operation, RX should have a minimum
value of 143 Ω.
LCD Panel Applications
The AD856x amplifier is designed for LCD panel applications
or applications where large capacitive load drive is required. It
can instantaneously source/sink greater than 250 mA of current.
At unity gain, it can drive 1 µF without compensation. This
makes the AD856x ideal for LCD V
driver applications.
COM
To evaluate the performance of the AD856x family, a test circuit
was developed to simulate the V
driver application for an
COM
LCD panel.
0.75
0.50
14-LEAD TSSOP
8-LEAD MSOP
5-LEAD SOT-23
0.25
MAXIMUM POWER DISSIPATION ( W)
0
–35
–15 5 25 456585
AMBIENT TEMPERATURE (C)
Figure 3. Maximum Power Dissipation vs. Temperature
for 5-, 8-, and 14-Lead Packages
REV. C
–9–
AD8565/AD8566/AD8567
Figure 5 shows the test circuit. Series capacitors and resistors
connected to the output of the op amp represent the load of the
LCD panel. The 300 Ω and 3 kΩ feedback resistors are used to
improve settling time. This test circuit simulates the worst-case
scenario for a V
to a signal switched symmetrically around V
a scope photo of the instantaneous output peak current capability
of the AD856x family.
8V
Figure 5. V
. It drives a represented load that is connected
COM
300
3k
10 10 10 10
4V
MEASURE
CURRENT
Test Circuit with Supply Voltage at 16 V
COM
10nF 10nF 10nF
10nF
. Figure 6 displays
COM
INPUT 0V TO 8V
SQUARE WAVE WITH
15.6s PULSE WIDTH
10–20
100
90
10
0%
CH 1 = 5V/DIV
CH 2 =
100mA/DIV
TIME (2s/DIV)
Figure 6. Scope Photo of the V
Peak Current
Instantaneous
COM
–10–
REV. C
OUTLINE DIMENSIONS
AD8565/AD8566/AD8567
5-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-5)
Dimensions shown in millimeters
2.00 BSC
0.30
0.15
4
3
0.65 BSC
2.10 BSC
1.10 MAX
SEATING
PLANE
0.22
0.08
0.46
0.36
0.26
2
1.25 BSC
1.00
0.90
0.70
0.10 MAX
5
1
PIN 1
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203AA
14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
8-Lead Micro Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
BSC
85
3.00
BSC
1
PIN 1
0.65 BSC
0.15
0.00
0.38
0.22
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA
4
SEATING
PLANE
4.90
BSC
1.10 MAX
0.23
0.08
8
0
0.80
0.60
0.40
1.05
1.00
0.80
4.50
4.40
4.30
PIN 1
5.10
5.00
4.90
14
0.65
BSC
0.15
0.05
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
0.30
0.19
8
6.40
BSC
71
SEATING
PLANE
0.20
1.20
0.09
MAX
COPLANARITY
0.10
8
0
0.75
0.60
0.45
REV. C
–11–
AD8565/AD8566/AD8567
OUTLINE DIMENSIONS
16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body
(CP-16)
Dimensions shown in millimeters
PIN 1
INDICATOR
1.00
0.85
0.80
12 MAX
SEATING
PLANE
4.0
BSC SQ
TOP
VIEW
0.80 MAX
0.65 TYP
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
0.35
0.28
0.25
3.75
BSC SQ
0.20 REF
0.60 MAX
0.65 BSC
0.05 MAX
0.02 NOM
COPLANARITY
0.75
0.60
0.50
0.08
13
12
9
8
0.60 MAX
BOTTOM
VIEW
16
1
4
5
1.95 BSC
PIN 1
INDICATOR
2.25
SQ
2.10
1.95
0.25 MIN
Revision History
Location Page
3/04—Data Sheet changed from REV. B to REV. C.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to TPC 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to TPC 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to TPC 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Changes to TPC 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12/03—Data Sheet changed from REV. A to REV. B.
Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
10/01—Data Sheet changed from REV. 0 to REV. A.
Edit to 16-Lead CSP and 5-Lead SC70 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edit to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
C01909–0–3/04(C)
–12–
–12–
REV. C
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