Analog Devices AD8565, AD8566, AD8567 Service Manual

16 V Rail-to-Rail

FEATURES

Single-supply operation: 4.5 V to 16 V
Input capability beyond the rails
Rail-to-rail output swing
Continuous output current: 35 mA
Peak output current: 250 mA
Offset voltage: 10 mV
Slew rate: 6 V/μs
Unity gain stable with large capacitive loads
Supply current: 700 μA per amplifier

APPLICATIONS

LCD reference drivers
Portable electronics
Communications equipment

GENERAL DESCRIPTION

The AD8565, AD8566, and AD8567 are low cost, single-supply,
rail-to-rail input and output operational amplifiers optimized
for LCD monitor applications. They are built on an advanced
high voltage CBCMOS process. The AD8565 contains a single
amplifier, the AD8566 has two amplifiers, and the AD8567 has
four amplifiers.

These LCD op amps have high slew rates, 35 mA continuous
output drive, 250 mA peak output drive, and a high capacitive
load drive capability. They have a wide supply range and offset
voltages below 10 mV. The AD8565, AD8566, and AD8567 are
ideal for LCD grayscale reference buffer and V

The AD8565, AD8566, and AD8567 are specified over the

−40°C to +85°C temperature range. The AD8565 single is
available in a 5-lead SC70 package. The AD8566 dual is
available in an 8-lead MSOP package. The AD8567 quad is
available in a 14-lead TSSOP package and a 16-lead LFCSP
package.

applications.

COM

Operational Amplifiers

AD8565/AD8566/AD8567

PIN CONFIGURATIONS

AD8565

1

V+

2

3

+IN

TOP VIEW

(Not to Scale)

Figure 1. 5-Lead SC70 Pin Configuration

AD8566

1

OUT A

–IN A

2

+IN A

36

V–

45

TOP VIEW

(Not to Scale)

Figure 2. 8-Lead MSOP Pin Configuration

1

OUT A

–IN A

3

+IN A

AD8567

TOP VIEW

4

V+

(Not to Scale)

510

+IN B

–IN B

OUT B

Figure 3. 14-Lead TSSOP Pin Configuration

NC

16

1

–IN A

+IN A

V+

+IN B

AD8567

2

TOP VIEW

3

(Not to Scale)

4

5

OUT AOUT DNC

13

1415

8

76

5

4

12

11

10

8

7

14

12

11

9

V–OUT

–IN

V+

OUT B

–IN B

+IN B

312

96

87

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

–IN D

+IN D

V–

+IN C

01909-001

01909-002

01909-003

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

–IN B

NC = NO CONNECT

OUT B

OUT C

–IN C

01909-004

Figure 4. 16-Lead LFCSP Pin Configuration

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD8565/AD8566/AD8567

TABLE OF CONTENTS

Features .............................................................................................. 1

Input Overvoltage Protection......................................................9

Applications....................................................................................... 1

General Description......................................................................... 1

Pin Configurations ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Typical Performance Characteristics ............................................. 5

Theory of Operation ........................................................................ 9

REVISION HISTORY

2/06—Rev C to Rev. D

Updated Format..................................................................Universal

Changes to Figure 6 and Figure 8................................................... 5

Added the Thermal Pad—AD8567 Section................................ 10

Changes to Ordering Guide.......................................................... 13

Output Phase Reversal............................................................... 10

Power Dissipation....................................................................... 10

Thermal Pad—AD8567............................................................. 10

Total Harmonic Distortion + Noise (THD+N)...................... 11

Short-Circuit Output Conditions............................................. 11

LCD Panel Applications ............................................................ 11

Outline Dimensions ....................................................................... 12

Ordering Guide .......................................................................... 13

3/04—Rev B to Rev. C

Changes to Specifications................................................................ 2

Changes to TPC 4............................................................................. 4

Changes to TPC 10........................................................................... 5

Changes to TPC 14........................................................................... 6

Changes to TPC 20........................................................................... 7

12/03—Rev. A to Rev. B

Updated Ordering Guide................................................................. 3

Updated Outline Dimensions....................................................... 11

10/01—Rev. 0 to Rev. A

Edit to 16-Lead CSP and 5-Lead SC70 Pin Configuration......... 1

Edit to Ordering Guide.................................................................... 3

7/01—Revision 0: Initial Version

Rev. D | Page 2 of 16

AD8565/AD8566/AD8567

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

4.5 V ≤ VS ≤ 16 V, VCM = VS/2, TA = 25°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V

OS

Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +85°C 5 μV/°C
Input Bias Current I

B

−40°C ≤ TA ≤ +85°C 800 nA
Input Offset Current I

OS

−40°C ≤ TA ≤ +85°C 130 nA
Input Voltage Range Common-mode input −0.5 VS + 0.5 V
Common-Mode Rejection Ratio CMRR VCM = 0 to VS, −40°C ≤ TA ≤ +85°C 54 95 dB
Large Signal Voltage Gain AVO RL = 10 kΩ, VO = 0.5 V to (VS − 0.5 V) 3 10 V/mV
Input Impedance Z
Input Capacitance C

IN

IN

OUTPUT CHARACTERISTICS

Output Voltage High V

OH

V

−40°C ≤ TA ≤ +85°C 15.75 V
V

−40°C ≤ TA ≤ +85°C 4.1 V
Output Voltage Low V

OL

V

−40°C ≤ TA ≤ +85°C 250 mV
V

−40°C ≤ TA ≤ +85°C 400 mV
Continuous Output Current I
Peak Output Current I

OUT

PK

POWER SUPPLY

Supply Voltage V

S

Power Supply Rejection Ratio PSRR VS = 4 V to 17 V, −40°C ≤ TA ≤ +85°C 70 90 dB
Supply Current/Amplifier I

SY

−40°C ≤ TA ≤ +85°C 1 mA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 10 kΩ, CL = 200 pF 4 6 V/μs
Gain Bandwidth Product GBP RL = 10 kΩ, CL = 10 pF 5 MHz
Phase Margin Øo RL = 10 kΩ, CL = 10 pF 65 Degrees
Channel Separation 75 dB

NOISE PERFORMANCE

Voltage Noise Density e
e
Current Noise Density i

n

n

n

2 10 mV

80 600 nA

1 80 nA

400 kΩ
1 pF

IL = 100 μA VS − 0.005 V

= 16 V, IL = 5 mA 15.85 15.95 V

S

= 4.5 V, IL = 5 mA 4.2 4.38 V

S

IL = 100 μA 5 mV

= 16 V, IL = 5 mA 42 150 mV

S

= 4.5 V, IL = 5 mA 95 300 mV

S

35 mA
VS = 16 V 250 mA

4.5 16 V

VO = VS/2, no load 700 850 μA

f = 1 kHz 26 nV/√Hz
f = 10 kHz 25 nV/√Hz
f = 10 kHz 0.8 pA/√Hz

Rev. D | Page 3 of 16

AD8565/AD8566/AD8567

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Ratings

Supply Voltage (VS) 18 V
Input Voltage −0.5 V to VS + 0.5 V
Differential Input Voltage V

S

Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Table 3.

Package Type θ

1

JA

θ

JC

Unit

5-Lead SC70 (KS-5) 376 126 °C/W
8-Lead MSOP (RM-8) 210 45 °C/W
14-Lead TSSOP (RU-14) 180 35 °C/W
16-Lead LFCSP (CP-16-4) 38

1

θJA is specified for worst-case conditions, that is, θJA is specified for a device

soldered onto a circuit board for surface-mount packages.

2

DAP is soldered down to PCB.

2

30

2

°C/W

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. D | Page 4 of 16

AD8565/AD8566/AD8567

√

TYPICAL PERFORMANCE CHARACTERISTICS

0

VCM = VS/2

–0.25

1000

Hz)

4.5V ≤ VS ≤ 16V
T

= 25°C

A

–0.50

–0.75

–1.00

INPUT OFFSET VOLTAG E (mV)

–1.25

–1.50

CURRENT NOISE DENS ITY (pA/√Hz)

= 16V

V

S

VS = 4.5V

–40

25 85

TEMPERATURE (°C)

Figure 5. Input Offset Voltage vs. Temperature

10

4.5V ≤ VS ≤ 16V
T

= 25°C

A

1

100

10

VOLTAGE NOISE DENSITY (nV/

1

10 100 1k 10k

01909-005

FREQUENCY (Hz)

01909-008

Figure 8. Voltage Noise Density vs. Frequency

1.0

0.8

0.6

0.4

0.2

SUPPLY CURRENT/AMPLIF IER (mA)

V

O

A

V

T

A

= VS/2
= +1
= 25°C

0.1

10 100 1k 10k

FREQUENCY (Hz)

01909-006

Figure 6. Current Noise Density vs. Frequency

VS = 16V
R

= 10kΩ

L

C

= 100pF

L

A

= +1

V

T

= 25°C

A

TIME (50mV/DIV)

FREQUENCY (1µs/DIV)

01909-007

Figure 7. Small Signal Transient Response

0

SUPPLY VOLTAGE (V)

Figure 9. Supply Current/Amplifier vs. Supply Voltage

0.80

VCM = VS/2

0.75

V

= 16V

S

0.70

0.65

0.60

= 4.5V

V

0.55

SUPPLY CURRENT/AMPLIF IER (mA)

0.50

–40

TEMPERATURE (°C)

S

25 85

Figure 10. Supply Current/Amplifier vs. Temperature

181614121086420

01909-009

01909-010

Rev. D | Page 5 of 16

AD8565/AD8566/AD8567

100

VS = 16V

90

= 100mV p-p

V

IN

= 10kΩ

R

L

80

= +1

A

V

= 25°C

T

A

70

60

50

40

OVERSHOOT (%)

30

20

10

0

10 100 1k

LOAD CAPACITANCE ( pF)

–OS

+OS

Figure 11. Small Signal Overshoot vs. Load Capacitance

18

16

14

12

10

8

6

VS = 16V

OUTPUT SWING (V p-p)

= +1

A

V

4

= 10kΩ

R

L

DISTORTION < 1%

2

= 25°C

T

A

0

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 12. Closed-Loop Output Swing vs. Frequency

60

50

A

= –100

VCL

40

30

A

= –10

VCL

20

10

A

= +1

VCL

0

CLOSED-LOOP GAIN (dB)

10 100 1k 10k 100k 1M 10 M

FREQUENCY (Hz)

4.5V ≤ VS ≤ 16V
= 10kΩ

R

L

= 40pF

C

L

T

= 25°C

A

Figure 13. Closed-Loop Gain vs. Frequency

100

80

60

40

20

GAIN (dB)

0

1k 10k 100k 1M 10M 100M

01909-011

Figure 14. Open-Loop Gain and Phase Shift vs. Frequency

FREQUENCY (Hz)

1k

TA = 25°C

100

VS = 4.5V

10

∆OUTPUT VOLTAGE (mV)

1

0.1

0.001 0.01 0.1 1 10 100

01909-012

LOAD CURRENT (mA)

Figure 15. Output Voltage to Supply Rail vs. Load Current

150

I

= 5mA

SINK

135

120

105

90

75

60

45

OUTPUT VOLTAGE (mV)

30

15

0

01909-013

–40 25 85

V

= 4.5V

S

V

= 16V

S

TEMPERATURE (° C)

Figure 16. Output Voltage Swing to Rail vs. Temperature

VS = 16V

= 10kΩ

R

L

= 40pF

C

L

= 25°C

T

A

VS = 16V

0

45

90

135

180

225

270

PHASE SHIFT (Degrees)

1909-016

01909-014

01909-015

Rev. D | Page 6 of 16

AD8565/AD8566/AD8567

A

150

I

= 5mA

SOURCE

135

120

105

90

75

60

45

OUTPUT VO LTAGE (mV)

30

15

0

–40 25 85

TEMPERATURE ( °C)

V

V

S

S

= 4.5V

= 16V

Figure 17. Output Voltage Swing to Rail vs. Temperature

1909-017

160

VS = 16V

140

= 25°C

T

A

120

TIO (dB)

100

80

60

40

20

0

POWER SUPPLY REJECTION R

–20

–40

100 1k 10k 100k 1M 10M

+PSRR

–PSRR

FREQUENCY (Hz)

Figure 20. Power Supply Rejection Ratio vs. Frequency

01909-020

500

AV = +1

450

400

350

300

250

200

IMPEDANCE (Ω)

150

100

= 25°C

T

A

V

= 4.5V

S

50

0

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

V

= 16V

S

Figure 18. Closed-Loop Output Impedance vs. Frequency

VS = 16V

140

120

100

CMRR (dB)

= 25°C

T

A

80

60

40

20

0

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 19. Common-Mode Rejection Ratio (CMRR) vs. Frequency

VS = 16V
R

= 10kΩ

L

A

= +1

V

T

= 25°C

A

VOLTAGE (3V/DIV)

01909-018

TIME (40µs/DIV)

Figure 21. No Phase Reversal

01909-021

1.8k

VS = 16V

1.6k

T

= 25°C

A

1.4k

1.2k

1.0k

800

600

QUANTITY (Amplifiers)

400

200

0

–10 –8 –6 –4 –2 0 2 4 6 8 10

1909-019

INPUT OFFSETVOLTAGE (mV)

Figure 22. Input Offset Voltage Distribution

01909-022

Rev. D | Page 7 of 16

AD8565/AD8566/AD8567

R

–

5

4

3

2

1

0

–1

–2

INPUT OFFSET CURRENT (nA)

–3

–4

–5

–40 25 85

VS = 4.5V

TEMPERATURE ( °C)

Figure 23. Input Offset Current vs. Temperature

0

V

= VS/2

CM

–50

V

= 16V

S

VS = 4.5V

INPUT BIAS CURRENT (nA)

–100

–150

–200

–250

–300

V

= 16V

S

01909-023

7

6

5

4

3

BANDWIDTH (MHz)

2

VS = 16V
A

= +1

V

1

R

= x

L

T

= 25°C

A

0

0 2 4 6 8 10121416

Figure 26. Frequency vs. Common-Mode Voltage (V

COMMON-MODEVOLTAGE (V)

= 16 V)

S

6

5

4

3

2

BANDWIDTH (MHz)

1

VS = 5V
A

= +1

V

R

= 10kΩ

L

T

= 25°C

A

01909-026

–350

–40 25 85

TEMPERATURE (° C)

Figure 24. Input Bias Current vs. Temperature

20

–40

–60

–80

–100

OSSTALK (dB)

–120

C

–140

–160

–180

50 100 1k 10k 60k

4.5V

16V

FREQUENCY (Hz)

01909-024

1909-025

0

01234

COMMON-MODE VOLTAGE (V)

Figure 27. Frequency vs. Common-Mode Voltage (V

= 5 V)

S

5

01909-027

Figure 25. Channel A vs. Channel B Crosstalk

Rev. D | Page 8 of 16

AD8565/AD8566/AD8567

V

V

THEORY OF OPERATION

The AD856x family is designed to drive large capacitive loads in
LCD applications. It has high output current drive, rail-to-rail
input/output operation, and is powered from a single 16 V
supply. It is also intended for other applications where low
distortion and high output current drive are needed.

Figure 28 illustrates a simplified equivalent circuit for the
AD856x. The rail-to-rail bipolar input stage is composed of two
PNP differential pairs, Q4 to Q5 and Q10 to Q11, operating in
series with diode protection networks, D1 to D2. Diode network
D1 to D2 serves as protection against large transients for Q4 to
Q5 to accommodate rail-to-rail input swing. D5 to D6 protect
Q10 to Q11 against Zenering. In normal operation, Q10 to Q11
are off and their input stage is buffered from the operational
amplifier inputs by Q6 to D3 and Q8 to D4. Operation of the
input stage is best understood as a function of applied
common-mode voltage: when the inputs of the AD856x are
biased midway between the supplies, the differential signal path
gain is controlled by resistive loads (via R9, R10) Q4 to Q5. As
the input common-mode level is reduced toward the negative
supply (V

or GND), the input transistor current sources, I1

NEG

and I2, are forced into saturation, thereby forcing the Q6 to D3
and Q8 to D4 networks into cutoff. However, Q4 to Q5 remain
active, providing input stage gain. Inversely, when common­mode input voltage is increased toward the positive supply, Q4
to Q5 are driven into cutoff, Q3 is driven into saturation, and
Q4 becomes active, providing bias to the Q10 to Q11 differential
pair. The point at which Q10 to Q11 differential pair becomes
active is approximately equal to (V

POS

R1

Q3

Q6

+

C1

Q4

R5 R6

C2

Q10

D5

D6

Q11

POS

Q4

− 1 V).

D2D1

R4R3

Q5

R10R9

BIAS LINE

Q8

V–

D4D3

I2I1

FOLDED
CASCADE

The benefit of this type of input stage is low bias current. The
input bias current is the sum of base currents of Q4 to Q5 and
Q6 to Q8 over the range from (V

+ 1 V) to (V

NEG

− 1 V).

POS

Outside of this range, input bias current is dominated by the
sum of base currents of Q10 to Q11 for input signals close to
V

and of Q6 to Q8 (Q10 to Q11) for signals close to V

NEG

POS

.
From this type of design, the input bias current of AD856x not
only exhibits different amplitude but also exhibits different
polarities.

Figure 29 provides the characteristics of the input
bias current vs. the common-mode voltage. It is important to
keep in mind that the source impedances driving the AD856x
inputs are balanced for optimum dc and ac performance.

1000

V

= 16V

S

800

= 25°C

T

A

600

400

200

0

–200

–400

INPUT BIAS CURRENT (nA)

–600

–800

–1000

02

46810121416

INPUT COMMON-MODE VOLTAGE (V)

1909-029

Figure 29. AD856x Input Bias Current vs. Common-Mode Voltage

To achieve rail-to-rail output performance, the AD856x design
uses a complementary common-source (or gmRL) output. This
configuration allows output voltages to approach the power
supply rails, particularly if the output transistors are allowed to
enter the triode region on extremes of signal swing, which are
limited by V

, the transistor sizes, and output load current. In

GS

addition, this type of output stage exhibits voltage gain in an
open-loop gain configuration. The amount of gain depends on
the total load resistance at the output of the AD856x.

INPUT OVERVOLTAGE PROTECTION

As with any semiconductor device, whenever the input exceeds
either supply voltages, attention needs to be paid to the input
overvoltage characteristics. As an overvoltage occurs, the amplifier
could be damaged, depending on the voltage level and the
magnitude of the fault current. When the input voltage exceeds
either supply by more than 0.6 V, internal pn junctions allow
current to flow from the input to the supplies.

V

NEG

01909-028

Figure 28. AD856x Equivalent Input Circuit

Rev. D | Page 9 of 16

AD8565/AD8566/AD8567

A

This input current is not inherently damaging to the device as
long as it is limited to 5 mA or less. If a condition exists using
the AD856x where the input exceeds the supply more than

0.6 V, an external series resistor should be added. The size of the
resistor can be calculated by using the maximum overvoltage
divided by 5 mA. This resistance should be placed in series with
either input exposed to an overvoltage.

OUTPUT PHASE REVERSAL

The AD856x family is immune to phase reversal. Although the
device’s output does not change phase, large currents due to
input overvoltage could damage the device. In applications
where the possibility of an input voltage exceeding the supply
voltage exists, overvoltage protection should be used as
described in the

Input Overvoltage Protection section.

POWER DISSIPATION

The maximum allowable internal junction temperature of
150°C limits the AD856x family’s maximum power dissipation
of AD856x devices. As the ambient temperature increases, the
maximum power dissipated by AD856x devices must decrease
linearly to maintain the maximum junction temperature. If this
maximum junction temperature is exceeded momentarily, the
device still operates properly once the junction temperature is
reduced below 150°C. If the maximum junction temperature is
exceeded for an extended period, overheating could lead to
permanent damage of the device.

The maximum safe junction temperature, T
the following formula, the maximum power that an AD856x
device can safely dissipate as a function of temperature can be
obtained:

= T

P

DISS

JMAX

− TA/θ

JA

where:

is the AD856x power dissipation.

P

DISS

is the AD856x maximum allowable junction temperature

T

JMAX

(150°C).

is the ambient temperature of the circuit.

T

A

is the AD856x package thermal resistance, junction-to-ambient.

θ

JA

, is 150°C. Using

JMAX

The power dissipated by the device can be calculated as

P

= (VS − V

DISS

OUT

) × I

LOAD

where:

is the supply voltage.

V

S

is the output voltage.

V

OUT

is the output load current.

I

LOAD

Figure 30 shows the maximum power dissipation vs.
temperature. To achieve proper operation, use the previous
equation to calculate P
temperature or use

1.25

14-LEAD SOIC

1.00

TION (W)

0.75

0.50

0.25

MAXIMUM POWER DISSIP

for 5-Lead SC70, 8-Lead MSOP, and 14-Lead TSSOP/SOIC Packages

14-LEAD TSS OP

8-LEAD MSOP

5-LEAD SOT-23

0

–15 5 25 45 65 85

–35

Figure 30. Maximum Power Dissipation vs. Temperature

for a specific package at any given

DISS

Figure 30.

AMBIENTTEMPERATURE (°C)

01909-030

THERMAL PAD—AD8567

The AD8567 LFCSP comes with a thermal pad that is attached
to the substrate. This substrate is connected to V
electrically safe, the thermal pad should be soldered to an area
on the board that is electrically isolated or connected to V
Attaching the thermal pad to ground adversely affects the
performance of the part.

Soldering down this thermal pad dramatically improves the
heat dissipation of the package. It is necessar y to attach vias that
connect the soldered thermal pad to another layer on the board.
This provides an avenue to dissipate the heat away from the
part. Without vias, the heat is isolated directly under the part.

. To be

DD

DD

.

Rev. D | Page 10 of 16

AD8565/AD8566/AD8567

TOTAL HARMONIC DISTORTION + NOISE (THD+N) LCD PANEL APPLICATIONS

The AD856x family features low total harmonic distortion.
Figure 31 shows THD+N vs. frequency. The THD+N for the
AD856x over the entire supply range is below 0.008%. When
the device is powered from a 16 V supply, the THD+N stays
below 0.003%.

Figure 31 shows the AD8566 in a unity

noninverting configuration.

10

1

THD+N (%)

0.1
VS = ±2.5V

VS = ±8V

The AD856x amplifier is designed for LCD panel applications
or applications where large capacitive load drive is required. It
can instantaneously source/sink greater than 250 mA of current. At
unity gain, it can drive 1 μF without compensation. This makes
the AD856x ideal for LCD V

driver applications.

COM

To evaluate the performance of the AD856x family, a test circuit
was developed to simulate the V

driver application for an

COM

LCD panel.

Figure 32 shows the test circuit. Series capacitors and resistors
connected to the output of the op amp represent the load of the
LCD panel. The 300 Ω and 3 kΩ feedback resistors are used to
improve settling time. This test circuit simulates the worst-case
scenario for a V
a signal switched symmetrically around V

. It drives a represented load that is connected to

COM

. Figure 33 shows a

COM

scope photo of the instantaneous output peak current capability
of the AD856x family.

0.01
20

100

1k 10k 30k

FREQUENCY (Hz)

01909-031

Figure 31. THD+N vs. Frequency

SHORT-CIRCUIT OUTPUT CONDITIONS

The AD856x family does not have internal short-circuit
protection circuitry. As a precautionary measure, it is
recommended not to short the output directly to the
positive power supply or to ground.

It is not recommended to operate the AD856x with more than
35 mA of continuous output current. The output current can be
limited by placing a series resistor at the output of the amplifier
whose value can be derived using

V

S

R ≥

X

For a 5 V single-supply operation, R
value of 143 Ω.

mA35

should have a minimum

X

300Ω

8V

Figure 33. Scope Photo of the V

4V

Figure 32. V

100

90

CH 1 = 5V/DIV

10

0%

3kΩ

MEASURE
CURRENT

INPUT 0VTO 8V
SQUARE WAVEWITH

15.6µs PULSE WIDTH

10Ω 10Ω 10Ω 10Ω

10nF 10nF 10nF

10nF

10Ω TO 20Ω

Test Circuit with Supply Voltage at 16 V

COM

CH 2 = 100mA/DIV

TIME (2µs/DIV)

Instantaneous Peak Current

COM

01909-032

1909-033

Rev. D | Page 11 of 16

AD8565/AD8566/AD8567

OUTLINE DIMENSIONS

3.20

3.00

2.80

8

5

4

SEATING
PLANE

5.15

4.90

4.65

1.10 MAX

0.23

0.08

8°
0°

3.20

3.00

1

2.80

PIN 1

0.65 BSC

0.95

0.85

0.75

0.15

0.38

0.00

0.22

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 34. 8-Lead Micro Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

5.10

5.00

4.90

0.80

0.60

0.40

2.20

2.00

1.80

1.35

1.25

1.15

1.00

0.90

0.70

0

.

1

0

M

123

PIN 1

X

A

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-203-AA

0.30

0.15

45

Figure 35. 5-Lead Thin Shrink Small Outline Transistor Package [SC70]

Dimensions shown in millimeters

2.40

2.10

1.80

0.65 BSC

1.10

0.80

SEATING
PLANE

(KS-5)

0.40

0.10

0.22

0.08

0.46

0.36

0.26

1.05

1.00

0.80

4.50

4.40

4.30

PIN 1

14

0.65
BSC

0.15

0.05

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

0.30

0.19

8

6.40
BSC

71

1.20
MAX

SEATING
PLANE

0.20

0.09

COPLANARITY

0.10

8°
0°

Figure 36. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

0.75

0.60

0.45

Rev. D | Page 12 of 16

AD8565/AD8566/AD8567

R

4.00

PIN 1

INDICATO

1.00

0.85

0.80

12° MAX

SEATING
PLANE

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

COMPLIANT TO JEDEC STANDARDS MO-220-VGGC

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

0.60 MAX

0.65 BSC

0.05 MAX

0.02 NOM

COPLANARITY

0.75

0.60

0.50

0.08

Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-16-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description

AD8565AKS-R2 −40°C to +85°C 5-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-5 ASA
AD8565AKS-REEL7 −40°C to +85°C 5-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-5 ASA
AD8565AKSZ-REEL7
AD8566ARM-R2 −40°C to +85°C 8-Lead Micro Small Outline Package (MSOP) RM-8 ATA
AD8566ARM-REEL −40°C to +85°C 8-Lead Micro Small Outline Package (MSOP) RM-8 ATA
AD8566ARMZ-R2
AD8566ARMZ-REEL
AD8567ARU −40°C to +85°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14
AD8567ARU-REEL −40°C to +85°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14
AD8567ARUZ
AD8567ARUZ-REEL
AD8567ACP-R2 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4
AD8567ACP-REEL −40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4
AD8567ACP-REEL7 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4
AD8567ACPZ-R2
AD8567ACPZ-REEL
AD8567ACPZ-REEL71−40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4

1

Z = Pb-free part, # denotes lead-free product may be top or bottom marked.

1

−40°C to +85°C 5-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-5 A0N

1

1

1

−40°C to +85°C 8-Lead Micro Small Outline Package (MSOP) RM-8 ATA#

1

−40°C to +85°C 8-Lead Micro Small Outline Package (MSOP) RM-8 ATA#

−40°C to +85°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14

1

−40°C to +85°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14

−40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4

1

−40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4

0.60 MAX

13

12

EXPOSED

(BOTTOM VIEW)

9

8

PAD

16

1

4

5

1.95 BSC

PIN 1
INDICATOR

2.25

2.10 SQ

1.95

0.25 MIN

Package
Option

Branding

Rev. D | Page 13 of 16

AD8565/AD8566/AD8567

NOTES

Rev. D | Page 14 of 16

AD8565/AD8566/AD8567

NOTES

Rev. D | Page 15 of 16

AD8565/AD8566/AD8567

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01909-0-2/06(D)

Rev. D | Page 16 of 16