Analog Devices AD8557 Service Manual

Digitally Programmable Sensor Signal Amplifier

VPOS

VNEG

Preliminary Technical Data

FEATURES

Very low offset voltage: 10 μV max over temperature Very low input offset voltage drift: 50 nV/°C max High CMRR: 96 dB min Digitally programmable gain and output offset voltage Gain Range from 28 to 1300 Single-wire serial interface Stable with any capacitive load SOIC_N and LFCSP_VQ packages

2.7 V to 5.5 V operation

FUNCTIONAL BLOCK DIAGRAM

VSS

AD8557

APPLICATIONS

Automotive sensors Pressure and position sensors Precision current sensing Thermocouple amplifiers Industrial weigh scales Strain gages

LAMP

VDD

DD 2

VDD

DAC

VSS

Rev.PrC

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Figure 1.

OUT

AD8557 Preliminary Technical Data

TABLE OF CONTENTS

Specifications..................................................................................... 4

Absolute Maximum Ratings....... Error! Bookmark not defined.

Thermal Resistance ................. Error! Bookmark not defined.

ESD Caution............................. Error! Bookmark not defined.

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 10

REVISION HISTORY

XXXX—Revision 0: Initial Version

Gain Values ................................................................................. 11

Open Wire Fault Detection....................................................... 12

Shorted Wire Fault Detection................................................... 12

Floating VPOS, VNEG, or VCLAMP Fault Detection ......... 12

Device Programming................................................................. 12

Outline Dimensions....................................................................... 17

Ordering Guide .......................................................................... 17

Rev. PrC | Page 2 of 19

Preliminary Technical Data AD8557

GENERAL DESCRIPTION

The AD8557 is a zero-drift, sensor signal amplifier with digitally programmable gain and output offset. Designed to easily and accurately convert variable pressure sensor and strain bridge outputs to a well-defined output voltage range, the AD8557 accurately amplifies many other differential or singleended sensor outputs. The AD8557 uses the ADI patented low noise auto-zero and DigiTrim® technologies to create an incredibly accurate and flexible signal processing solution in a very compact footprint.

Gain is digitally programmable in a wide range from 28 to 1300 through a serial data interface. Gain adjustment can be fully simulated in-circuit and then permanently programmed with reliable polyfuse technology. Output offset voltage is also digitally programmable and is ratiometric to the supply voltage. When used in conjunction with an ADC referenced to the same supply, the system accuracy becomes immune to normal supply voltage variations. Output offset voltage can be adjusted with a resolution of better than 0.4% of the difference between VDD

and VSS. A lockout trim after gain and offset adjustment further ensures field reliability.

In addition to extremely low input offset voltage and input offset voltage drift and very high dc and ac CMRR, the AD8557 also includes a pull-up current source at the input pins and a pull-down current source at the VCLAMP pin. Output clamping set via an external reference voltage allows the AD8557 to drive lower voltage ADCs safely and accurately.

When used in conjunction with an ADC referenced to the same supply, the system accuracy becomes immune to normal supply voltage variations. Output offset voltage can be adjusted with a resolution of better than 0.4% of the difference between VDD and VSS. A lockout trim after gain and offset adjustment further ensures field reliability.

The AD8557 is fully specified from −40°C to +125°C. Operating from single-supply voltages of 2.7 V to 5.5 V, the AD8557 is offered in the 8-lead SOIC_N, and 4 mm × 4 mm 16-lead LFCSP_VQ.

Rev. PrC | Page 3 of 19

AD8557 Preliminary Technical Data

SPECIFICATIONS

VDD = 5.0 V, VSS = 0.0 V, VCM = 2.5 V, VO = 2.5 V, Gain = 28, TA = 25°C, unless otherwise specified.

Table 1. Electrical Specifications

Parameter Symbol Conditions Min Typ Max Unit

INPUT STAGE

Input Offset Voltage VOS −40°C ≤ TA ≤ +125°C 2 10 μV

Input Offset Voltage Drift TCVOS 50 nV/°C

Input Bias Current IB −40°C ≤ TA ≤ +125°C 8 18 28 nA

Input Offset Current IOS −40°C ≤ TA ≤ +125°C 1 8 nA

Input Voltage Range 0.8 3.6 V

Common-Mode Rejection Ratio CMRR VCM = 0.9 V to 3.6 V, AV = 28 70 82 dB

Linearity VO = 0.2 V to 3.4 V 20 ppm

Differential Gain Accuracy Second stage gain = 10 to 70 1.6 %

Differential Gain Accuracy Second stage gain = 100 to 250 2.5 %

Differential Gain Temperature

Coefficient

Second stage gain = 10 to 250 15 40 ppm/°C

DAC

Accuracy Offset codes = 8 to 248 0.7 0.8 %

Ratiometricity Offset codes = 8 to 248 50 ppm

Output Offset Offset codes = 8 to 248 5 35 mV

Temperature Coefficient 20 80 ppm FS/°C VCLAMP

Input Bias Current ICLAMP 100 166 330 nA

Input Voltage Range 1.25 2.64 V OUTPUT STAGE

Short-Circuit Current ISC Source -40 -25 mA

Sink 40 50 mA

Output Voltage, Low VOL R

Output Voltage, High VOH R POWER SUPPLY

Supply Current ISY

Power Supply Rejection Ratio PSRR 125 dB

−40°C ≤ TA ≤ +125°C 105

DYNAMIC PERFORMANCE

Gain Bandwidth Product GBP First gain stage 2 MHz

Second gain stage 8 MHz

Settling Time ts To 0.1%, 4 V output step 8 μs NOISE PERFORMANCE

Input Referred Noise f = 1 kHz 32 nV/√Hz

Low Frequency Noise en p-p f = 0.1 Hz to 10 Hz 0.5 μV p-p

Total Harmonic Distortion THD VIN = 16.75 mV rms, f = 1 kHz -100 dB DIGITAL INTERFACE

Input Current 2 μA

DIGIN Pulse Width to Load 0 tw0 0.05 10 μs

DIGIN Pulse Width to Load 1 tw1 50 μs

Time Between Pulses at DIGIN tws 10 μs

DIGIN Low 1 V

DIGIN High 4 V

DIGOUT Logic 0 1 V

= 0.9 V to 3.6 V, AV = 1300 96 112 dB

= 0.2 V to 4.8 V 1000 ppm

= 10 kΩ to 5 V 30 mV

= 10 kΩ to 0 V 4.94 V

= 2.5 V, VPOS = VNEG = 2.5 V, VDAC code

= XXXX

1.8 mA

Rev. PrC | Page 4 of 19

Preliminary Technical Data AD8557

Parameter Symbol Conditions Min Typ Max Unit

DIGOUT Logic 1 4 V

VDD = 2.7 V, VSS = 0.0 V, VCM = 1.35 V, VO = 1.35 V, Gain = 28, TA = 25°C, unless otherwise specified.

Table 2. Electrical Specifications

Parameter Symbol Conditions Min Typ Max Unit

INPUT STAGE

Input Offset Voltage VOS −40°C ≤ TA ≤ +125°C 2 10 μV Input Offset Voltage Drift TCVOS 50 nV/°C Input Bias Current IB −40°C ≤ TA ≤ +125°C 8 18 28 nA Input Offset Current IOS −40°C ≤ TA ≤ +125°C 0.2 1 nA Input Voltage Range 0.5 1.6 V Common-Mode Rejection Ratio CMRR VCM = 0.9 V to 3.6 V, AV = 28 70 82 dB V Linearity VO = 0.2 V to 3.4 V 20 ppm V Differential Gain Accuracy Second stage gain = 10 to 250 1.6 % Differential Gain Temperature

Coefficient

Second stage gain = 10 to 250 15 40 ppm/°C

DAC

Accuracy Offset codes = 8 to 248 0.7 0.8 % Ratiometricity Offset codes = 8 to 248 50 ppm Output Offset Offset codes = 8 to 248 5 35 mV Temperature Coefficient 20 80 ppm FS/°C

VCLAMP

Input Bias Current ICLAMP 100 166 330 nA Input Voltage Range 1.25 2.64 V

OUTPUT STAGE

Short-Circuit Current ISC Source -12 -7 mA Sink 15 20 mA Output Voltage, Low VOL R Output Voltage, High VOH R

POWER SUPPLY

Supply Current ISY

Power Supply Rejection Ratio PSRR 125 dB

−40°C ≤ TA ≤ +125°C 105

DYNAMIC PERFORMANCE

Gain Bandwidth Product GBP First gain stage 2 MHz Second gain stage 8 MHz Settling Time ts To 0.1%, 4 V output step 8 μs

NOISE PERFORMANCE

Input Referred Noise f = 1 kHz 32 nV/√Hz Low Frequency Noise en p-p f = 0.1 Hz to 10 Hz 0.5 μV p-p Total Harmonic Distortion THD VIN = 16.75 mV rms, f = 1 kHz -100 dB

DIGITAL INTERFACE

Input Current 2 μA DIGIN Pulse Width to Load 0 tw0 0.05 10 μs DIGIN Pulse Width to Load 1 tw1 50 μs Time Between Pulses at DIGIN tws 10 μs DIGIN Low 1 V DIGIN High 4 V DIGOUT Logic 0 1 V DIGOUT Logic 1 4 V

= 0.9 V to 3.6 V, AV = 1300 96 112 dB

= 0.2 V to 4.8 V 1000 ppm

= 10 kΩ to 5 V 30 mV

= 10 kΩ to 0 V 2.64 V

= 2.5 V, VPOS = VNEG = 2.5 V, VDAC code

= XXXX

Rev. PrC | Page 5 of 19

1.8 mA

AD8557 Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage 6 V Input Voltage VSS − 0.3 V to VDD + 0.3 V Differential Input Voltage1 ±5.0 V Output Short-Circuit Duration to

Indefinite

VSS or VDD ESD (Human Body Model) 2000 V Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +125°C Junction Temperature Range −65°C to +150°C Lead Temperature Range 300°C

Differential input voltage is limited to ±5.0 V or ± the supply voltage, which-

ever is less.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θ

8-Lead SOIC_N (R) 158 43 °C/W 16-Lead LFCSP_VQ (CP) 44 31.5 °C/W

θJA is specified for the worst-case conditions, that is, θJA is specified for device

soldered in circuit board for LFCSP_VQ package.

θJC Unit

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. PrC | Page 6 of 19

Preliminary Technical Data AD8557

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VDD

DIGOUT

DIGIN VNEG

3 4

AD8557

TOP VIEW

Figure 2. 8-Lead SOIC_N Pin Configuration

VSS

VOUT

VCLAMP

VPOS

05448-002

DIGOUT

DIGIN

Figure 3. 16-Lead LFCSP_VQ Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

SOIC_N LFCSP_VQ

Mnemonic Description

1 VDD Positive Supply Voltage. 2 2 DIGOUT In read mode this pin functions as a digital output. 3 4 DIGIN Digital Input. 4 6 VNEG Negative Amplifier Input (Inverting Input). 5 8 VPOS Positive Amplifier Input (Noninverting Input). 6 10 VCLAMP Set Clamp Voltage at Output. 7 12 VOUT Amplifier Output. 8 VSS Negative Supply Voltage. 13, 14 DVSS, AVSS Negative Supply Voltage. 15, 16 DVDD, AVDD Positive Supply Voltage. 1, 3, 5, 7, 9, 11 NC Do Not Connect.

14 AVSS

16 AVDD

15 DVDD

PIN 1

INDICATOR

AD8557

TOP VIEW

NC 7

NC 5

NEG 6

NC = NO CONNECT

13 DVSS

VOUT

VCLAMP

POS 8

Rev. PrC | Page 7 of 19

AD8557 Preliminary Technical Data

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. Input Offset Voltage Distribution

Figure 5. Input Offset Voltage vs. Common-Mode Voltage

Figure 6. Input Offset Voltage vs. Temperature

Figure 7. T

Figure 8. Output Buffer Offset vs. Temperature

at VSY = 5 V

CVOS

Figure 21. Low Frequency Input Voltage Noise (0.1 Hz to 10 Hz)

Figure 22. Low Frequency Input Voltage Noise (0.1 Hz to 10 Hz)

Figure 23. Closed-Loop Gain vs. Frequency Measured at Filter Pin

Figure 24. Closed-Loop Gain vs. Frequency Measured at Output Pin

Figure 25. Output Buffer Gain vs. Frequency

Figure 9. Input Bias Current at VPOS, VNEG vs. Temperature

Figure 10. Input Bias Current at VPOS, VNEG vs. Common-Mode Voltage

Figure 11. Input Offset Current vs. Temperature

Figure 12. Digital Input Current vs. Digital Input Voltage (Pin 4)

Figure 13. VCLAMP Current over Temperature at V

Figure 14. Supply Current (I

Figure 15. Supply Current (I

Figure 16. CMRR vs. Fre quency

Figure 17. CMRR vs. Fre quency

Figure 18. CMRR vs. Temperature at Different Gains

Figure 19. Input Voltage Noise Density vs. Frequency (0 Hz to 10 kHz)

Figure 20. Input Voltage Noise Density vs. Frequency (0 Hz to 500 kHz)

= 5 V vs. VCLAMP Voltage

) vs. Supply Voltage

) vs. Temperature

Figure 26. Output Buffer Positive Overshoot

Figure 27. Output Buffer Negative Overshoot

Figure 28. Output Voltage to Supply Rail vs. Load Current

Figure 29. Output Short-Circuit vs. Temperature

Figure 30. Power-On Response at 25°C

Figure 31. Power-On Response at 125°C

Figure 32. Power-On Response at −40°C

Figure 33. PSRR vs. Temperature

Figure 34. PSRR v s. Frequency

Figure 35. Small Signal Response

Figure 36. Small Signal Response

Rev. PrC | Page 8 of 19

Preliminary Technical Data AD8557

Figure 37. Large Signal Response

Figure 38. Large Signal Response

Figure 39. Output Impedance vs. Frequency

Figure 40. Negative Overload Recovery (Gain = 70)

Figure 41. Positive Overload Recovery (Gain = 70)

Figure 43. Positive Overload Recovery (Gain = 1280)

Figure 44. Settling Time 0.1%

Figure 45. Settling Time 0.01%

Figure 46. THD vs. Frequency

Figure 42. Negative Overload Recovery (Gain = 1280)

Rev. PrC | Page 9 of 19

AD8557 Preliminary Technical Data

(

−

THEORY OF OPERATION

A1, A2, R1, R2, R3, P1, and P2 form the first gain stage of the differential amplifier. A1 and A2 are auto-zeroed op amps that minimize input offset errors. P1 and P2 are digital potentiometers, guaranteed to be monotonic. Programming P1 and P2 allows the first stage gain to be varied from 2.8 to 5.2 with 7-bit resolution (see Table 5 and Equation 1), giving a fine gain adjustment resolution of 0.37%. R1, R2, R3, P1, and P2 each have a similar temperature coefficient, so the first stage gain temperature coefficient is lower than 100 ppm/°C.

Code

⎞

⎛

⎟

⎜

127

⎠

⎝

5.2

⎞

⎛

2.8

GAIN1 (1)

A3, R4, R5, R6, R7, P3, and P4 form the second gain stage of the differential amplifier. A3 is an auto-zeroed op amp that minimizes input offset errors and also includes an output buffer. P3 and P4 are digital potentiometers, which allow the second stage gain to be varied from 10 to 250 in eight steps (see Table

6). R4, R5, R6, R7, P3, and P4 each have a similar temperature coefficient, so the second stage gain temperature coefficient is lower than 100 ppm/°C. The output stage of A3 is supplied from a buffered version of VCLAMP instead of VDD, allowing the positive swing to be limited.

A4 implements a voltage buffer, which provides the positive supply to the output stage of A3. Its function is to limit VOUT to a maximum value, useful for driving analog-to-digital converters (ADC) operating on supply voltages lower than

×≈

⎜ ⎝

2.8

⎟ ⎠

VDD. The input to A4, VCLAMP, has a very high input resistance. It should be connected to a known voltage and not left floating. However, the high input impedance allows the clamp voltage to be set using a high impedance source, such as, a potential divider. If the maximum value of VOUT does not need to be limited, VCLAMP should be connected to VDD.

An 8-bit digital-to-analog converter (DAC) is used to generate a variable offset for the amplifier output. This DAC is guaranteed to be monotonic. To preserve the ratiometric nature of the input signal, the DAC references are driven from VSS and VDD, and the DAC output can swing from VSS (Code 0) to VDD (Code

255). The 8-bit resolution is equivalent to 0.39% of the difference between VDD and VSS, for example, 19.5 mV with a 5 V supply. The DAC output voltage (VDAC) is given approximately by

VDAC +−

Where the temperature coefficient of ppm/°C.

The amplifier output voltage (VOUT) is given by

where

⎜ ⎝

GAIN is the product of the first and second stage gains.

Code

⎛

≈

5.0

⎞

()

⎟

256

⎠

{insert picture}

Figure 47. Functional Schematic

VSSVSSVDD

VDAC is lower than 200

)

VDACVNEGVPOSGAINVOUT +

(2)

(3)

Rev. PrC | Page 10 of 19

Preliminary Technical Data AD8557

GAIN VALUES

Table 5. First Stage Gain vs. First Stage Gain Code

First Stage Gain Code First Stage Gain

0 32 64 96 1 33 65 97 2 34 66 98 3 35 67 99 4 36 68 100 5 37 69 101 6 38 70 102 7 39 71 103 8 40 72 104 9 41 73 105 10 42 74 106 11 43 75 107 12 44 76 108 13 45 77 109 14 46 78 110 15 47 79 111 16 48 80 112 17 49 81 113 18 50 82 114 19 51 83 115 20 52 84 116 21 53 85 117 22 54 86 118 23 55 87 119 24 56 88 120 25 57 89 121 26 58 90 122 27 59 91 123 28 60 92 124 29 61 93 125 30 62 94 126 31 63 95 127

First Stage Gain Code First Stage Gain

Table 6. Second Stage Gain and Gain Ranges vs. Second Stage Gain Code

Second Stage Gain Code Second Stage Gain Minimum Combined Gain Maximum Combined Gain

0 1 2 3 4 5 6 7

Rev. PrC | Page 11 of 19

AD8557 Preliminary Technical Data

OPEN WIRE FAULT DETECTION

The inputs to A1 and A2, VNEG and VPOS, each have a comparator to detect whether VNEG or VPOS exceeds a threshold voltage, nominally VDD − 2.0 V. If (VNEG > VDD − 2.0 V) or (VPOS > VDD − 2.0 V), VOUT is clamped to VSS. The output current limit circuit is disabled in this mode, but the maximum sink current is approximately 10 mA when VDD = 5 V. The inputs to A1 and A2, VNEG and VPOS, are also pulled up to VDD by currents IP1 and IP2. These are both nominally 49 nA and matched to within 3 nA. If the inputs to A1 or A2 are accidentally left floating, as with an open wire fault, IP1 and IP2 pull them to VDD which would cause VOUT to swing to VSS, allowing this fault to be detected. It is not possible to disable IP1 and IP2, nor the clamping of VOUT to VSS, when VNEG or VPOS approaches VDD.

SHORTED WIRE FAULT DETECTION

The AD8557 provides fault detection in the case where VPOS, VNEG, or VCLAMP shorts to VDD and VSS. Figure 48 shows the voltage regions at VPOS, VNEG, and VCLAMP that trigger an error condition. When an error condition occurs, the VOUT pin is shorted to VSS. Table 7 lists the voltage levels shown in Figure 48.

VPOS VNEG

ERROR

NORMAL

ERROR

VDD

VINH

VINL VSS

Figure 48. Voltage Regions at VPOS, VNEG, and VCLAMP

ERROR

NORMAL

ERROR

that Trigger a Fault Condition

VDD

VINH

VINL VSS

Table 7. Typical VINL, VINH, and VCLL Values (VDD = 5 V)

Voltage Min (V) Max (V) VOUT Condition

VINH 3.9 4.2

Short to VSS fault detection

VINL 0.195 0.55

Short to VSS fault detection

VCLL 1.0 1.2

Short to VSS fault detection

VCLAMP

VDD

NORMAL

VCLL

ERROR

VSS

05448-048

FLOATING VPOS, VNEG, OR VCLAMP FAULT DETECTION

A floating fault condition at the VPOS, VNEG, or VCLAMP pins is detected by using a low current to pull a floating input into an error voltage range, defined in the previous section. In this way, the VOUT pin is shorted to VSS when a floating input is detected. Table 8 lists the currents used.

Table 8. Floating Fault Detection at VPOS, VNEG, and VCLAMP

Pin Typical Current Goal of Current

VPOS 16 nA pull-up Pull VPOS above VINH VNEG 16 nA pull-up Pull VNEG above VINH VCLAMP 0.2 μA pull-down Pull VCLAMP below VCLL

DEVICE PROGRAMMING

Digital Interface

The digital interface allows the first stage gain, second stage gain, and output offset to be adjusted and allows desired values for these parameters to be permanently stored by selectively blowing polysilicon fuses. To minimize pin count and board space, a single-wire digital interface is used. The digital input pin, DIGIN, has hysteresis to minimize the possibility of inadvertent triggering with slow signals. It also has a pull-down current sink to allow it to be left floating when programming is not being performed. The pull-down ensures inactive status of the digital input by forcing a dc low voltage on DIGIN.

A short pulse at DIGIN from low to high and back to low again, such as between 50 ns and 10 μs long, loads a 0 into a shift register. A long pulse at DIGIN, such as 50 μs or longer, loads a 1 into the shift register. The time between pulses should be at least 10 μs. Assuming VSS = 0 V, voltages at DIGIN between VSS and 0.2 × VDD are recognized as a low, and voltages at DIGIN between 0.8 × VDD and VDD are recognized as a high. A timing diagram example, Figure 49, shows the waveform for entering code 010011 into the shift register.

Rev. PrC | Page 12 of 19

Preliminary Technical Data AD8557

AVEFORM

CODE

01001 1

Figure 49. Timing Diagram for Code 010011

Table 9. Timing Specifications

Timing Parameter Description Specification

tw0 Pulse Width for Loading 0 into Shift Register Between 50 ns and 10 μs tw1 Pulse Width for Loading 1 into Shift Register ≥50 μs tws Width Between Pulses ≥10 μs

Table 10. 38-Bit Serial Word Format

Field No. Bits Description

0 0 to 11 12-Bit Start of Packet 1000 0000 0001 1 12 to 13 2-Bit Function 00: Change Sense Current 01: Simulate Parameter Value 10: Program Parameter Value 11: Read Parameter Value 2 14 to 15 2-Bit Parameter 00: Second Stage Gain Code 01: First Stage Gain Code 10: Output Offset Code 11: Other Functions 3 16 to 17 2-Bit Dummy 10 4 18 to 25 8-Bit Value Parameter 00 (Second Stage Gain Code): 3 LSBs Used Parameter 01 (First Stage Gain Code): 7 LSBs Used Parameter 10 (Output Offset Code): All 8 Bits Used Parameter 11 (Other Functions) Bit 0 (LSB): Master Fuse Bit 1: Fuse for Production Test at Analog Devices 5 26 to 37 12-Bit End of Packet 0111 1111 1110

05448-049

A 38-bit serial word is used, divided into 6 fields. Assuming each bit can be loaded in 60 μs, the 38-bit serial word transfers in 2.3 ms. Table 10 summarizes the word format.

Within each field, the MSB must be written first and the LSB written last. The shift register features power-on reset to minimize the risk of inadvertent programming; power-on reset occurs when VDD is between 0.7 V and 2.2 V.

Field 0 and Field 5 are the start-of-packet field and end-ofpacket field, respectively. Matching the start-of-packet field with 1000 0000 0001 and the end-of-packet field with 0111 1111 1110 ensures that the serial word is valid and enables decoding of the other fields.

Field 3 breaks up the data and ensures that no data combination can inadvertently trigger the start-of-packet and end-of-packet fields. Field 0 should be written first and Field 5 written last.

Rev. PrC | Page 13 of 19

AD8557 Preliminary Technical Data

Initial State

Initially, all the polysilicon fuses are intact. Each parameter has the value 0 assigned (see Table 11).

Table 11. Initial State Before Programming

Second Stage Gain Code = 0 Second Stage Gain = 17.5

First stage gain code = 0 First stage gain = 4.0 Output offset code = 0 Output offset = VSS Master fuse = 0 Master fuse not blown

When power is applied to a device, parameter values are taken either from internal registers, if the master fuse is not blown, or from the polysilicon fuses, if the master fuse is blown. Programmed values have no effect until the master fuse is blown. The internal registers feature power-on reset, so the unprogrammed devices enter a known state after power-up. Power-on reset occurs when VDD is between 0.7 V and 2.2 V.

Simulation Mode

The simulation mode allows any parameter to be temporarily changed. These changes are retained until the simulated value is reprogrammed, the power is removed, or the master fuse is blown. Parameters are simulated by setting Field 1 to 01, selecting the desired parameter in Field 2, and the desired value for the parameter in Field 4. Note that a value of 11 for Field 2 is ignored during the simulation mode. Examples of temporary settings follow:

• Setting the second stage gain code (Parameter 00) to 011 and

the second stage gain to 50 produces:

1000 0000 0001 01 00 10 0000 0011 0111 1111 1110

• Setting the first stage gain code (Parameter 01) to 000 1011

and the first stage gain to 4.166 produces:

1000 0000 0001 01 01 10 0000 1011 0111 1111 1110

A first stage gain of 4.166 with a second stage gain of 50 gives a

total gain of 208.3. This gain has a maximum tolerance of 2.5%.

• Set the output offset code (Parameter 10) to 0100 0000 and

the output offset to 1.260 V when VDD = 5 V and VSS = 0 V.

This output offset has a maximum tolerance of 0.8%:

1000 0000 0001 01 10 10 0100 0000 0111 1111 1110

Programming Mode

Intact fuses give a bit value of 0. Bits with a desired value of 1 need to have the associated fuse blown. Since a relatively large current is needed to blow a fuse, only one fuse can be reliably blown at a time. Thus, a given parameter value may need several 38-bit words to allow reliable programming. A 5.25 V

±0.25 V) supply is required when blowing fuses to minimize

( the on resistance of the internal MOS switches that blow the fuse. The power supply voltage must not exceed the absolute maximum rating and must be able to deliver 250 mA of current.

At least 10 μF (tantalum type) of decoupling capacitance is needed across the power pins of the device during programming. The capacitance can be on the programming apparatus as long as it is within 2 inches of the device being programmed. An additional 0.1 recommended within ½ inch of the device being programmed. A minimum period of 1 ms should be allowed for each fuse to blow. There is no need to measure the supply current during programming.

The best way to verify correct programming is to use the read mode to read back the programmed values. Then, remeasure the gain and offset to verify these values. Programmed fuses have no effect on the gain and output offset until the master fuse is blown. After blowing the master fuse, the gain and output offset are determined solely by the blown fuses, and the simulation mode is permanently deactivated.

Parameters are programmed by setting Field 1 to 10, selecting the desired parameter in Field 2, and selecting a single bit with the value 1 in Field 4.

As an example, suppose the user wants to permanently set the second stage gain to 50. Parameter 00 needs to have the value 0000 0011 assigned. Two bits have the value 1, so two fuses need to be blown. Since only one fuse can be blown at a time, this code can be used to blow one fuse: 1000 0000 0001 10 00 10 0000 0010 0111 1111 1110

The MOS switch that blows the fuse closes when the complete packet is recognized, and opens when the start-of-packet, dummy, or end-of-packet fields are no longer valid. After 1 ms, this second code is entered to blow the second fuse: 1000 0000 0001 10 00 10 0000 0001 0111 1111 1110

To permanently set the first stage gain to a nominal value of

4.151, Parameter 01 needs to have the value 000 1011 assigned. Three fuses need to be blown, and the following codes are used, with a 1 ms delay after each code: 1000 0000 0001 10 01 10 0000 1000 0111 1111 1110 1000 0000 0001 10 01 10 0000 0010 0111 1111 1110 1000 0000 0001 10 01 10 0000 0001 0111 1111 1110

To permanently set the output offset to a nominal value of 1.260 V when VDD = 5 V and VSS = 0 V, Parameter 10 needs to have the value 0100 0000 assigned. If one fuse needs to be blown, use the following code: 1000 0000 0001 10 10 10 0100 0000 0111 1111 1110

Finally, to blow the master fuse to deactivate the simulation mode and prevent further programming, use code: 1000 0000 0001 10 11 10 0000 0001 0111 1111 1110

There are a total of 20 programmable fuses. Since each fuse requires 1 ms to blow, and each serial word can be loaded in 2.3

μF (ceramic type) in parallel with the 10 μF is

Rev. PrC | Page 14 of 19

Preliminary Technical Data AD8557

ms, the maximum time needed to program the fuses can be as low as 66 ms.

Read Mode

The values stored by the polysilicon fuses can be sent to the FILT/DIGOUT pin to verify correct programming. Normally, the FILT/DIGOUT pin is only connected to the second gain stage output via RF. During read mode, however, the FILT/DIGOUT pin is also connected to the output of a shift register to allow the polysilicon fuse contents to be read. Since VOUT is a buffered version of FILT/DIGOUT, VOUT also outputs a digital signal during read mode.

Read mode is entered by setting Field 1 to 11 and selecting the desired parameter in Field 2. Field 4 is ignored. The parameter value, stored in the polysilicon fuses, is loaded into an internal shift register, and the MSB of the shift register is connected to the FILT/DIGOUT pin. Pulses at DIGIN shift out the shift register contents to the FILT/DIGOUT pin, allowing the 8‒bit parameter value to be read after seven additional pulses; shifting occurs on the falling edge of DIGIN. An eighth pulse at DIGIN disconnects FILT/DIGOUT from the shift register and terminates the read mode. If a parameter value is less than eight bits long, the MSBs of the shift register are padded with 0s.

For example, to read the second stage gain, this code is used: 1000 0000 0001 11 00 10 0000 0000 0111 1111 1110 Since the second stage gain parameter value is only three bits long, the FILT/DIGOUT pin has a value of 0 when this code is entered, and remains 0 during four additional pulses at DIGIN. The fifth, sixth, and seventh pulses at DIGIN return the 3-bit value at FILT/DIGOUT, the seventh pulse returns the LSB. An eighth pulse at DIGIN terminates the read mode.

Sense Current

A sense current is sent across each polysilicon fuse to determine whether it has been blown. When the voltage across the fuse is less than approximately 1.5 V, the fuse is considered not blown, and Logic 0 is output from the OTP cell. When the voltage across the fuse is greater than approximately 1.5 V, the fuse is considered blown, and Logic 1 is output.

When the AD8557 is manufactured, all fuses have a low resistance. When a sense current is sent through the fuse, a voltage less than 0.1 V is developed across the fuse. This is much lower than 1.5 V, so Logic 0 is output from the OTP cell. When a fuse is electrically blown, it should have a very high resistance. When the sense current is applied to the blown fuse, the voltage across the fuse should be larger than 1.5 V, so Logic 1 is output from the OTP cell.

It is theoretically possible, though very unlikely, for a fuse to be incompletely blown during programming, assuming the required conditions are met. In this situation, the fuse could have a medium resistance, neither low nor high, and a voltage of

approximately 1.5 V could be developed across the fuse. Thus, the OTP cell could output Logic 0 or a Logic 1, depending on temperature, supply voltage, and other variables.

To detect this undesirable situation, the sense current can be lowered by a factor of 4 using a specific code. The voltage developed across the fuse would then change from 1.5 V to 0.38 V, and the output of the OTP would be a Logic 0 instead of the expected Logic 1 from a blown fuse. Correctly blown fuses would still output a Logic 1. In this way, incorrectly blown fuses can be detected. Another specific code would return the sense current to the normal (larger) value. The sense current cannot be permanently programmed to the low value. When the AD8557 is powered up, the sense current defaults to the high value.

The low sense current code is: 1000 0000 0001 00 00 10 XXXX XXX1 0111 1111 1110

The normal (high) sense current code is: 1000 0000 0001 00 00 10 XXXX XXX0 0111 1111 1110

Programming Procedure

For reliable fuse programming, it is imperative to follow the programming procedure requirements, especially the proper supply voltage during programming.

When programming the AD8557, the temperature of the

1. device must be between 10°C to 40°C.

Set VDD and VSS to the desired values in the application.

2. Use simulation mode to test and determine the desired codes for the second stage gain, first stage gain, and output offset. The nominal values for these parameters are shown in Table 5, Table 6, Equation 2, and Equation 3; use the codes corresponding to these values as a starting point. However, since actual parameter values for given codes vary from device to device, some fine tuning is necessary for the best possible accuracy.

One way to choose these values is to set the output offset to an approximate value, such as Code 128 for midsupply, to allow the required gain to be determined. Then set the second stage gain so the minimum first stage gain (Code 0) gives a lower gain than required, and the maximum first stage gain (Code 127) gives a higher gain than required. After choosing the second stage gain, the first stage gain can be chosen to fine tune the total gain. Finally, the output offset can be adjusted to give the desired value. After determining the desired codes for second stage gain, first stage gain, and output offset, the device is ready for permanent programming.

Important:

any fuse, there should be no further attempt to blow that fuse. If a fuse does not program to the expected state, discard

Once a programming attempt has been made for

Rev. PrC | Page 15 of 19

AD8557 Preliminary Technical Data

the unit. The expected incidence rate of attempted but unblown fuses is very small when following the proper programming procedure and conditions.

Set VSS to 0 V and VDD to 5.25 V (±0.25 V). Power supplies

3. should be capable of supplying 250 mA at the required voltage and properly bypassed as described in the Programming Mode section. Use program mode to permanently enter the desired codes for the first stage gain, second stage gain, and output offset. Blow the master fuse to allow the AD8557 to read data from the fuses and to prevent further programming.

Set VDD and VSS to the desired values in the application.

4. Use read mode with low sense current followed by high sense current to verify programmed codes.

Measure gain and offset to verify correct functionality.

Determining Optimal Gain and Offset Codes

First, determine the desired gain:

Determine the desired gain, G

(using the measurements

obtained from the simulation).

Use Table 6 to determine G

(4.00 × 1.04) < (G

A/G2

, the second stage gain, such that

) < (6.4/1.04). This ensures the first and last codes for the first stage gain are not used, thereby allowing enough first stage gain codes within each second stage gain range to adjust for the 3% accuracy.

Next, set the second stage gain:

Use the simulation mode to set the second stage gain to G

Set the output offset to allow the AD8557 gain to be

2. measured, for example, use Code 128 to set it to midsupply.

Use Table 5 or Equation 1 to set the first stage gain code

3. , so the first stage gain is nominally GA/G2.

Measure the resulting gain (G

3% of G

Calculate the first stage gain error (in relative terms)

5. E

Calculate the error (in the number of the first stage gain

6. codes) C

Set the first stage gain code to C

Measure the gain (G

Calculate the error (in relative terms) E

Calculate the error (in the number of the first stage gain

10. codes) C

Set the first stage gain code to C

11.

= GB/GA − 1.

EG1

EG2

= EG1/0.00370.

). GC should be closer to GA than to GB.

= EG2/0.00370.

resulting gain should be within one code of G

). GB should be within

− C

EG1

= GC/GA − 1.

− C

. The

EG2

Finally, determine the desired output offset:

Determine the desired output offset O

(using the

measurements obtained from the simulation).

Use Equation 2 to set the output offset code C

2. the output offset is nominally O

Measure the output offset (O

Calculate the error (in relative terms) E

Calculate the error (in the number of the output offset

5. codes) C

Set the output offset code to C

Measure the output offset (O

7. than to O

Calculate the error (in relative terms) E

Calculate the error (in the number of the output offset

9. codes) C

Set the output offset code to C

10.

= EO1/0.00392.

EO1

= EO2/0.00392.

EO2

). OB should be within 3% of

− C

EO1

− C

). OC should be closer to OA

resulting offset should be within one code of O

such that

= OB/OA − 1.

= OC/OA − 1.

. The

EO2

Rev. PrC | Page 16 of 19

Preliminary Technical Data AD8557

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

6.20 (0.2440)

5.80 (0.2284)

PIN 1

INDICATO

1.00

0.85

0.80

1.27 (0.0500) BSC

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

Figure 50. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

12° MAX

SEATING PLANE

4.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

COMPLIANT TO JEDEC STANDARDS MO-220-VGGC

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

0.60 MAX

0.65 BSC

0.05 MAX

0.02 NOM

COPLANARITY

0.75

0.60

0.50

0.08

0.60 MAX

EXPOSED

(BOTTOM VIEW)

PAD

1.95 BSC

Figure 51. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-16-4)

Dimensions shown in millimeters

× 45°

2.25

2.10 SQ

1.95

0.25 MIN

PIN 1 INDICATOR

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8557AR AD8557AR-REEL AD8557AR-REEL7

-40°C to +125°C

AD8557AR-EVAL Evaluation Board AD8557ACP-R2 AD8557ACP-REEL AD8557ACP-REEL7

-40°C to +125°C

8-Lead SOIC R-8 8-Lead SOIC R-8 8-Lead SOIC R-8

16-Lead LFCSP CP-16 16-Lead LFCSP CP-16 16-Lead LFCSP CP-16

Rev. PrC | Page 17 of 19

AD8557 Preliminary Technical Data

NOTES

Rev. PrC | Page 18 of 19

Preliminary Technical Data AD8557

NOTES

PR06013-0-5/06(PrC)

Rev. PrC | Page 19 of 19

Analog Devices AD8557 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual