Analog Devices AD8556 Service Manual

Digitally Programmable Sensor Signal

V

FEATURES

EMI filters at input pins
Specified from −40°C to +140°C
Low offset voltage: 10 µV max
Low input offset voltage drift: 65 nV/°C max
High CMRR: 94 dB min
Digitally programmable gain and output offset voltage
Programmable output clamp voltage
Open and short wire fault detection
Low-pass filtering
Single-wire serial interface
Stable with any capacitive load
SOIC_N and LFCSP_VQ packages

2.7 V to 5.5 V operation

FUNCTIONAL BLOCK DIAGRAM

LOGIC

VDD

A1

EMI

–IN

+IN

1

+IN

3

OUT

2

–IN

VSS

VDD

A2

1

+IN

3

OUT

2

–IN

VPOS

NEG

EMI

FILTER

EMI

FILTER

FILTER

R2

R3

R1

VDD

DAC

VSS

P2

P1

R4 R6

P3

Amplifier with EMI Filters

APPLICATIONS

Automotive sensors
Pressure and position sensors
Precision current sensing
Strain gages

VDDDIGIN VCLAMP

A5

1

EMI

FILTER

R7P4R5

VDD

A3

1

+IN

2

–IN

OUT

VSS

RF

3

+IN

2

–IN

EMI

FILTER

OUT

VSS

AD8556

3

VDD

A4

1

+IN

3

OUT

2

–IN

VSS

VOUT

VSS

VSS

AD8556

FILT/DIGOUT

05448-053

Figure 1.

Rev. 0

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infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.

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Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

www.analog.com

AD8556

TABLE OF CONTENTS

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics............................................. 8

Theory of Operation ...................................................................... 16

Gain Values.................................................................................. 17

REVISION HISTORY

5/05—Revision 0: Initial Version

Open Wire Fault Detection....................................................... 18

Shorted Wire Fault Detection ................................................... 18

Floating VPOS, VNEG, or VCLAMP Fault Detection ......... 18

Device Programming................................................................. 18

EMI/RFI Performance................................................................... 24

Outline Dimensions ....................................................................... 26

Ordering Guide .......................................................................... 26

Rev. 0 | Page 2 of 28

AD8556

GENERAL DESCRIPTION

The AD8556 is a zero-drift, sensor signal amplifier with
digitally programmable gain and output offset. Designed to
easily and accurately convert variable pressure sensor and
strain bridge outputs to a well-defined output voltage range,
the AD8556 accurately amplifies many other differential or
single-ended sensor outputs. The AD8556 uses the ADI
patented low noise auto-zero and DigiTrim® technologies to
create an incredibly accurate and flexible signal processing
solution in a very compact footprint.

Gain is digitally programmable in a wide range from 70 to
1,280 through a serial data interface. Gain adjustment can
be fully simulated in-circuit and then permanently pro­grammed with reliable polyfuse technology. Output offset
voltage is also digitally programmable and is ratiometric to the
supply voltage. AD8556 also features internal EMI filters on the
VNEG, VPOS, FILT and VCLAMP pins.

In addition to extremely low input offset voltage, low input
offset voltage drift, and very high dc and ac CMRR, the

AD8556 also includes a pull-up current source at the input pins
and a pull-down current source at the VCLAMP pin. This
allows open wire and shorted wire fault detection. A low-pass
filter function is implemented via a single low cost external
capacitor. Output clamping set via an external reference voltage
allows the AD8556 to drive lower voltage ADCs safely and
accurately.

When used in conjunction with an ADC referenced to the same
supply, the system accuracy becomes immune to normal supply
voltage variations. Output offset voltage can be adjusted with a
resolution of better than 0.4% of the difference between VDD
and VSS. A lockout trim after gain and offset adjustment
further ensures field reliability.

The AD8556 is fully specified from −40°C to +140°C.
Operating from single-supply voltages of 2.7 V to 5.5 V, the
AD8556 is offered in the 8-lead SOIC_N, and 4 mm × 4 mm
16-lead LFCSP_VQ.

Rev. 0 | Page 3 of 28

AD8556

SPECIFICATIONS

VDD = 5.0 V, VSS = 0.0 V, VCM = 2.5 V, VO = 2.5 V, −40°C ≤ TA ≤ +140°C, unless otherwise specified.

Table 1. Electrical Specifications

Parameter Symbol Conditions Min Typ Max Unit

INPUT STAGE

Input Offset Voltage VOS −40°C ≤ TA ≤ +125°C 2 10 µV

−40°C ≤ TA ≤ +140°C 3 12 µV
Input Offset Voltage Drift TCV
Input Bias Current I

OS

B

−40°C ≤ TA ≤ +125°C 58 nA

−40°C ≤ TA ≤ +140°C 60 nA
Input Offset Current I

OS

−40°C ≤ TA ≤ +125°C 3.0 nA

−40°C ≤ TA ≤ +140°C 4.0 nA
Input Voltage Range 2.1 2.9 V
Common-Mode Rejection Ratio CMRR VCM = 2.1 V to 2.9 V, AV = 70 80 92 dB
V
Linearity VO = 0.2 V to 3.4 V 20 ppm
V
Differential Gain Accuracy Second stage gain = 17.5 to 100 0.35 1.6 %
Second stage gain = 140 to 200 0.5 2.5 %
Differential Gain Temperature

Coefficient

Second stage gain = 17.5 to 100 7 20 ppm/°C

Second stage gain = 140 to 200 10 40 ppm/°C
RF 14 18 22 kΩ
RF Temperature Coefficient 600 ppm/°C

DAC

Accuracy AV = 70, offset codes = 8 to 248 0.2 0.6 %
Ratiometricity AV = 70, offset codes = 8 to 248 50 ppm
Output Offset AV = 70, offset codes = 8 to 248 5 35 mV
Temperature Coefficient −40°C ≤ TA ≤ +125°C 3.3 15 ppm FS/°C

−40°C ≤ TA ≤ +140°C 25 ppm FS/°C
VCLAMP

Input Bias Current TA = 25°C, VCLAMP = 5 V 200 nA

−40°C ≤ TA ≤ +125°C, VCLAMP = 5 V 500 nA

−40°C ≤ TA ≤ +140°C, VCLAMP = 5 V 550 nA
Input Voltage Range 1.2 4.94 V

OUTPUT BUFFER STAGE

Buffer Offset 3 7 mV
Short-Circuit Current I
Output Voltage, Low V
Output Voltage, High V

SC

OL

OH

POWER SUPPLY

Supply Current I

SY

Power Supply Rejection Ratio PSRR AV = 70 109 125 dB
Supply Voltage Required During

Programming

25 65 nV/°C
TA = 25°C 38 49 54 nA

TA = 25°C 0.2 2.5 nA

= 2.1 V to 2.9 V, AV = 1,280 94 112 dB

CM

= 0.2 V to 4.8 V 1,000 ppm

O

5 10 mA
RL = 10 kΩ to 5 V 20 mV
RL = 10 kΩ to 0 V 4.94 V

−40°C ≤ TA ≤ +125°C, VO = 2.5 V, VPOS = VNEG =

2.5 V, VDAC code = 128;

−40°C ≤ T

≤ +140°C, VO = 2.5 V, VPOS = VNEG =

A

2.5 V, VDAC Code = 128

10°C < T

< 40°C, supply capable of driving

PROG

250 mA

2.0 2.7 mA

2.78 mA

5.0 5.25 5.5 V

Rev. 0 | Page 4 of 28

AD8556

Parameter Symbol Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Gain Bandwidth Product GBP First gain stage, TA = 25°C 2 MHz
Second gain stage, TA = 25°C 8 MHz
Output buffer stage, TA = 25°C 1.5 MHz
Output Buffer Slew Rate SR AV = 70, RL = 10 kΩ, CL = 100 pF, TA = 25°C 1.2 V/µs
Settling Time t

s

NOISE PERFORMANCE

Input Referred Noise TA = 25°C, f = 1 kHz 32 nV/√Hz
Low Frequency Noise en p-p f = 0.1 Hz to 10 Hz, TA = 25°C 0.5 µV p-p
Total Harmonic Distortion THD VIN = 16.75 mV rms, f = 1 kHz, AV = 100, TA = 25°C −100 dB

DIGITAL INTERFACE

Input Current 2 µA
DIGIN Pulse Width to Load 0 tw
DIGIN Pulse Width to Load 1 tw
Time Between Pulses at DIGIN tw

0

1

s

DIGIN Low TA = 25°C 1 V
DIGIN High TA = 25°C 4 V
DIGOUT Logic 0 TA = 25°C 1 V
DIGOUT Logic 1 TA = 25°C 4 V

To 0.1%, AV = 70, 4 V output step, TA = 25°C 8 µs

TA = 25°C 0.05 10 µs
TA = 25°C 50 µs
TA = 25°C 10 µs

Rev. 0 | Page 5 of 28

AD8556

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage 6 V
Input Voltage VSS − 0.3 V to VDD + 0.3 V
Differential Input Voltage
Output Short-Circuit Duration to

VSS or VDD
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +150°C
Junction Temperature Range −65°C to +150°C
Lead Temperature Range 300°C

1

Differential input voltage is limited to ±5.0 V or ± the supply voltage, which-

ever is less.

1

±5.0 V
Indefinite

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θ

8-Lead SOIC_N (R) 158 43 °C/W
16-Lead LFCSP_VQ (CP) 44 31.5 °C/W

1

θJA is specified for the worst-case conditions, that is, θJA is specified for device

soldered in circuit board for LFCSP_VQ package.

1

JA

θ

JC

Unit

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 28

AD8556

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AVDD

DVDD

AVSS

VDD

FILT/DIGOUT

DIGIN

VNEG

1

AD8556

2

TOP VIEW

3

(Not to Scale)

4

VSS

8

7

VOUT

6

VCLAMP

VPOS

5

05448-002

FILT/DIGOUT

Figure 2. 8-Lead SOIC_N Pin Configuration

Figure 3.16-Lead LFCSP_VQ Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

SOIC_N LFCSP_VQ

Mnemonic Description

1 VDD Positive Supply Voltage.
2 2 FILT/DIGOUT

Unbuffered Amplifier Output in Series with a Resistor RF. Adding a capacitor between FILT and
VDD or VSS implements a low-pass filtering function. In read mode, this pin functions as a

digital output.
3 4 DIGIN Digital Input.
4 6 VNEG Negative Amplifier Input (Inverting Input).
5 8 VPOS Positive Amplifier Input (Noninverting Input).
6 10 VCLAMP Set Clamp Voltage at Output.
7 12 VOUT

Buffered Amplifier Output. Buffered version of the signal at the FILT/DIGOUT pin. In read

mode, VOUT is a buffered digital output.
8 VSS Negative Supply Voltage.
13, 14 DVSS, AVSS Negative Supply Voltage.
15, 16 DVDD, AVDD Positive Supply Voltage.
1, 3, 5, 7, 9, 11 NC Do Not Connect.

NC

NC

DIGIN

1

2

3

4

NC = NO CONNECT

161514

PIN 1
INDICATOR

AD8556

TOP VIEW

5

678

NC

NC

VNEG

DVSS

13

VPOS

VOUT

12

NC

11

VCLAMP

10

NC

9

05448-003

Rev. 0 | Page 7 of 28

AD8556

TYPICAL PERFORMANCE CHARACTERISTICS

100

80

N: 363,
MEAN: –0.389938,
SD: 1.65684

25

20

VSY = 5V

60

HITS

40

20

0

VOS5V (µV)

Figure 4. Input Offset Voltage Distribution

2.0

1.5

1.0

0.5

0

–0.5

(µV)

OSi

–1.0

V

–1.5

–2.0

–2.5

–3.0

VCM (V)

Figure 5. Input Offset Voltage vs. Common-Mode Voltage

T

A

10–10 –5 0 5

= 5V

V

S

= 25°C

15

10

NUMBER OF AMPLIFIERS

5

0

Figure 7. T

V

= 4.7V

OUT

TEMPERATURE (°C)

TCVOS (nV/°C)

at VSY = 5 V

CVOS

V

= 0.3V

OUT

05448-004

1.9

1.7

1.5

1.3

1.1

0.9

BUFFER OFFSET VOLTAGE (mV)

0.7

3.51.5 2.0 2.5 3.0

05448-005

0.5

MORE0 10203040

05448-007

= 5V

V

SY

150–50 –25 0 25 50 75 100 125

05448-009

Figure 8. Output Buffer Offset vs. Temperature

10

8

6

4

2

0

–2

–4

–6

INPUT OFFSET VOLTAGE (µV)

–8

–10

TEMPERATURE (°C)

VSY = 5V

150–50 –25 0 25 50 75 100 125

05448-006

Figure 6. Input Offset Voltage vs. Temperature

100

10

INPUT BIAS CURRENT (nA)

1

TEMPERATURE (°C)

Figure 9. Input Bias Current at VPOS, VNEG vs. Temperature

VSY = 5V

150–50 –25 0 25 50 75 100 125

05448-010

Rev. 0 | Page 8 of 28

AD8556

100

IB–

T

A

VSY= 5
= 25°C

1000

VS = 5V

I

+

B

10

(nA)

B

I

1

VCM (V)

6012345

Figure 10. Input Bias Current at VPOS, VNEG vs. Common-Mode Voltage

0.8

0.6

0.5

0.3

0.2

–0.2

–0.3

–0.5

INPUT OFFSET CURRENT (nA)

–0.6

–0.8

0

TEMPERATURE (°C)

VSY = 5V

150–50 –25 0 25 50 75 100 125

Figure 11. Input Offset Current vs. Temperature

05448-011

05448-012

100

VCLAMP CURRENT (nA)

10

VCLAMP VOLTAGE (V)

Figure 13. VCLAMP Current over Temperature at V

3.0

2.5

2.0

1.5

1.0

SUPPLY CURRENT (mA)

0.5

0

SUPPLY VOLTAGE (V)

Figure 14. Supply Current (I

) vs. Supply Voltage

SY

+125°C

+25°C

–40°C

6023145

= 5 V vs. VCLAMP Voltage

S

TA = 25°C

60123 54

05448-014

05448-015

2.5

2.0

1.5

1.0

0.5

DIGITAL INPUT CURRENT (µA)

0

DIGITAL INPUT VOLTAGE (V)

VS = 5.5V

Figure 12. Digital Input Current vs. Digital Input Voltage (Pin 4)

6012345

05448-013

Rev. 0 | Page 9 of 28

2.5

2.3

2.1

1.9

1.7

1.5

1.3

1.1

SUPPLY CURRENT (mA)

0.9

0.7

0.5

TEMPERATURE (°C)

Figure 15. Supply Current (I

) vs. Temperature

SY

VSY = 5V

150–50 –25 0 25 50 75 100 125

05448-016