Analog Devices AD8556 Service Manual

Digitally Programmable Sensor Signal

V

FEATURES

EMI filters at input pins
Specified from −40°C to +140°C
Low offset voltage: 10 µV max
Low input offset voltage drift: 65 nV/°C max
High CMRR: 94 dB min
Digitally programmable gain and output offset voltage
Programmable output clamp voltage
Open and short wire fault detection
Low-pass filtering
Single-wire serial interface
Stable with any capacitive load
SOIC_N and LFCSP_VQ packages

2.7 V to 5.5 V operation

FUNCTIONAL BLOCK DIAGRAM

LOGIC

VDD

A1

EMI

–IN

+IN

1

+IN

3

OUT

2

–IN

VSS

VDD

A2

1

+IN

3

OUT

2

–IN

VPOS

NEG

EMI

FILTER

EMI

FILTER

FILTER

R2

R3

R1

VDD

DAC

VSS

P2

P1

R4 R6

P3

Amplifier with EMI Filters

APPLICATIONS

Automotive sensors
Pressure and position sensors
Precision current sensing
Strain gages

VDDDIGIN VCLAMP

A5

1

EMI

FILTER

R7P4R5

VDD

A3

1

+IN

2

–IN

OUT

VSS

RF

3

+IN

2

–IN

EMI

FILTER

OUT

VSS

AD8556

3

VDD

A4

1

+IN

3

OUT

2

–IN

VSS

VOUT

VSS

VSS

AD8556

FILT/DIGOUT

05448-053

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

www.analog.com

AD8556

TABLE OF CONTENTS

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics............................................. 8

Theory of Operation ...................................................................... 16

Gain Values.................................................................................. 17

REVISION HISTORY

5/05—Revision 0: Initial Version

Open Wire Fault Detection....................................................... 18

Shorted Wire Fault Detection ................................................... 18

Floating VPOS, VNEG, or VCLAMP Fault Detection ......... 18

Device Programming................................................................. 18

EMI/RFI Performance................................................................... 24

Outline Dimensions ....................................................................... 26

Ordering Guide .......................................................................... 26

Rev. 0 | Page 2 of 28

AD8556

GENERAL DESCRIPTION

The AD8556 is a zero-drift, sensor signal amplifier with
digitally programmable gain and output offset. Designed to
easily and accurately convert variable pressure sensor and
strain bridge outputs to a well-defined output voltage range,
the AD8556 accurately amplifies many other differential or
single-ended sensor outputs. The AD8556 uses the ADI
patented low noise auto-zero and DigiTrim® technologies to
create an incredibly accurate and flexible signal processing
solution in a very compact footprint.

Gain is digitally programmable in a wide range from 70 to
1,280 through a serial data interface. Gain adjustment can
be fully simulated in-circuit and then permanently pro­grammed with reliable polyfuse technology. Output offset
voltage is also digitally programmable and is ratiometric to the
supply voltage. AD8556 also features internal EMI filters on the
VNEG, VPOS, FILT and VCLAMP pins.

In addition to extremely low input offset voltage, low input
offset voltage drift, and very high dc and ac CMRR, the

AD8556 also includes a pull-up current source at the input pins
and a pull-down current source at the VCLAMP pin. This
allows open wire and shorted wire fault detection. A low-pass
filter function is implemented via a single low cost external
capacitor. Output clamping set via an external reference voltage
allows the AD8556 to drive lower voltage ADCs safely and
accurately.

When used in conjunction with an ADC referenced to the same
supply, the system accuracy becomes immune to normal supply
voltage variations. Output offset voltage can be adjusted with a
resolution of better than 0.4% of the difference between VDD
and VSS. A lockout trim after gain and offset adjustment
further ensures field reliability.

The AD8556 is fully specified from −40°C to +140°C.
Operating from single-supply voltages of 2.7 V to 5.5 V, the
AD8556 is offered in the 8-lead SOIC_N, and 4 mm × 4 mm
16-lead LFCSP_VQ.

Rev. 0 | Page 3 of 28

AD8556

SPECIFICATIONS

VDD = 5.0 V, VSS = 0.0 V, VCM = 2.5 V, VO = 2.5 V, −40°C ≤ TA ≤ +140°C, unless otherwise specified.

Table 1. Electrical Specifications

Parameter Symbol Conditions Min Typ Max Unit

INPUT STAGE

Input Offset Voltage VOS −40°C ≤ TA ≤ +125°C 2 10 µV

−40°C ≤ TA ≤ +140°C 3 12 µV
Input Offset Voltage Drift TCV
Input Bias Current I

OS

B

−40°C ≤ TA ≤ +125°C 58 nA

−40°C ≤ TA ≤ +140°C 60 nA
Input Offset Current I

OS

−40°C ≤ TA ≤ +125°C 3.0 nA

−40°C ≤ TA ≤ +140°C 4.0 nA
Input Voltage Range 2.1 2.9 V
Common-Mode Rejection Ratio CMRR VCM = 2.1 V to 2.9 V, AV = 70 80 92 dB
V
Linearity VO = 0.2 V to 3.4 V 20 ppm
V
Differential Gain Accuracy Second stage gain = 17.5 to 100 0.35 1.6 %
Second stage gain = 140 to 200 0.5 2.5 %
Differential Gain Temperature

Coefficient

Second stage gain = 17.5 to 100 7 20 ppm/°C

Second stage gain = 140 to 200 10 40 ppm/°C
RF 14 18 22 kΩ
RF Temperature Coefficient 600 ppm/°C

DAC

Accuracy AV = 70, offset codes = 8 to 248 0.2 0.6 %
Ratiometricity AV = 70, offset codes = 8 to 248 50 ppm
Output Offset AV = 70, offset codes = 8 to 248 5 35 mV
Temperature Coefficient −40°C ≤ TA ≤ +125°C 3.3 15 ppm FS/°C

−40°C ≤ TA ≤ +140°C 25 ppm FS/°C
VCLAMP

Input Bias Current TA = 25°C, VCLAMP = 5 V 200 nA

−40°C ≤ TA ≤ +125°C, VCLAMP = 5 V 500 nA

−40°C ≤ TA ≤ +140°C, VCLAMP = 5 V 550 nA
Input Voltage Range 1.2 4.94 V

OUTPUT BUFFER STAGE

Buffer Offset 3 7 mV
Short-Circuit Current I
Output Voltage, Low V
Output Voltage, High V

SC

OL

OH

POWER SUPPLY

Supply Current I

SY

Power Supply Rejection Ratio PSRR AV = 70 109 125 dB
Supply Voltage Required During

Programming

25 65 nV/°C
TA = 25°C 38 49 54 nA

TA = 25°C 0.2 2.5 nA

= 2.1 V to 2.9 V, AV = 1,280 94 112 dB

CM

= 0.2 V to 4.8 V 1,000 ppm

O

5 10 mA
RL = 10 kΩ to 5 V 20 mV
RL = 10 kΩ to 0 V 4.94 V

−40°C ≤ TA ≤ +125°C, VO = 2.5 V, VPOS = VNEG =

2.5 V, VDAC code = 128;

−40°C ≤ T

≤ +140°C, VO = 2.5 V, VPOS = VNEG =

A

2.5 V, VDAC Code = 128

10°C < T

< 40°C, supply capable of driving

PROG

250 mA

2.0 2.7 mA

2.78 mA

5.0 5.25 5.5 V

Rev. 0 | Page 4 of 28

AD8556

Parameter Symbol Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Gain Bandwidth Product GBP First gain stage, TA = 25°C 2 MHz
Second gain stage, TA = 25°C 8 MHz
Output buffer stage, TA = 25°C 1.5 MHz
Output Buffer Slew Rate SR AV = 70, RL = 10 kΩ, CL = 100 pF, TA = 25°C 1.2 V/µs
Settling Time t

s

NOISE PERFORMANCE

Input Referred Noise TA = 25°C, f = 1 kHz 32 nV/√Hz
Low Frequency Noise en p-p f = 0.1 Hz to 10 Hz, TA = 25°C 0.5 µV p-p
Total Harmonic Distortion THD VIN = 16.75 mV rms, f = 1 kHz, AV = 100, TA = 25°C −100 dB

DIGITAL INTERFACE

Input Current 2 µA
DIGIN Pulse Width to Load 0 tw
DIGIN Pulse Width to Load 1 tw
Time Between Pulses at DIGIN tw

0

1

s

DIGIN Low TA = 25°C 1 V
DIGIN High TA = 25°C 4 V
DIGOUT Logic 0 TA = 25°C 1 V
DIGOUT Logic 1 TA = 25°C 4 V

To 0.1%, AV = 70, 4 V output step, TA = 25°C 8 µs

TA = 25°C 0.05 10 µs
TA = 25°C 50 µs
TA = 25°C 10 µs

Rev. 0 | Page 5 of 28

AD8556

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage 6 V
Input Voltage VSS − 0.3 V to VDD + 0.3 V
Differential Input Voltage
Output Short-Circuit Duration to

VSS or VDD
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +150°C
Junction Temperature Range −65°C to +150°C
Lead Temperature Range 300°C

1

Differential input voltage is limited to ±5.0 V or ± the supply voltage, which-

ever is less.

1

±5.0 V
Indefinite

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θ

8-Lead SOIC_N (R) 158 43 °C/W
16-Lead LFCSP_VQ (CP) 44 31.5 °C/W

1

θJA is specified for the worst-case conditions, that is, θJA is specified for device

soldered in circuit board for LFCSP_VQ package.

1

JA

θ

JC

Unit

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 28

AD8556

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AVDD

DVDD

AVSS

VDD

FILT/DIGOUT

DIGIN

VNEG

1

AD8556

2

TOP VIEW

3

(Not to Scale)

4

VSS

8

7

VOUT

6

VCLAMP

VPOS

5

05448-002

FILT/DIGOUT

Figure 2. 8-Lead SOIC_N Pin Configuration

Figure 3.16-Lead LFCSP_VQ Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

SOIC_N LFCSP_VQ

Mnemonic Description

1 VDD Positive Supply Voltage.
2 2 FILT/DIGOUT

Unbuffered Amplifier Output in Series with a Resistor RF. Adding a capacitor between FILT and
VDD or VSS implements a low-pass filtering function. In read mode, this pin functions as a

digital output.
3 4 DIGIN Digital Input.
4 6 VNEG Negative Amplifier Input (Inverting Input).
5 8 VPOS Positive Amplifier Input (Noninverting Input).
6 10 VCLAMP Set Clamp Voltage at Output.
7 12 VOUT

Buffered Amplifier Output. Buffered version of the signal at the FILT/DIGOUT pin. In read

mode, VOUT is a buffered digital output.
8 VSS Negative Supply Voltage.
13, 14 DVSS, AVSS Negative Supply Voltage.
15, 16 DVDD, AVDD Positive Supply Voltage.
1, 3, 5, 7, 9, 11 NC Do Not Connect.

NC

NC

DIGIN

1

2

3

4

NC = NO CONNECT

161514

PIN 1
INDICATOR

AD8556

TOP VIEW

5

678

NC

NC

VNEG

DVSS

13

VPOS

VOUT

12

NC

11

VCLAMP

10

NC

9

05448-003

Rev. 0 | Page 7 of 28

AD8556

TYPICAL PERFORMANCE CHARACTERISTICS

100

80

N: 363,
MEAN: –0.389938,
SD: 1.65684

25

20

VSY = 5V

60

HITS

40

20

0

VOS5V (µV)

Figure 4. Input Offset Voltage Distribution

2.0

1.5

1.0

0.5

0

–0.5

(µV)

OSi

–1.0

V

–1.5

–2.0

–2.5

–3.0

VCM (V)

Figure 5. Input Offset Voltage vs. Common-Mode Voltage

T

A

10–10 –5 0 5

= 5V

V

S

= 25°C

15

10

NUMBER OF AMPLIFIERS

5

0

Figure 7. T

V

= 4.7V

OUT

TEMPERATURE (°C)

TCVOS (nV/°C)

at VSY = 5 V

CVOS

V

= 0.3V

OUT

05448-004

1.9

1.7

1.5

1.3

1.1

0.9

BUFFER OFFSET VOLTAGE (mV)

0.7

3.51.5 2.0 2.5 3.0

05448-005

0.5

MORE0 10203040

05448-007

= 5V

V

SY

150–50 –25 0 25 50 75 100 125

05448-009

Figure 8. Output Buffer Offset vs. Temperature

10

8

6

4

2

0

–2

–4

–6

INPUT OFFSET VOLTAGE (µV)

–8

–10

TEMPERATURE (°C)

VSY = 5V

150–50 –25 0 25 50 75 100 125

05448-006

Figure 6. Input Offset Voltage vs. Temperature

100

10

INPUT BIAS CURRENT (nA)

1

TEMPERATURE (°C)

Figure 9. Input Bias Current at VPOS, VNEG vs. Temperature

VSY = 5V

150–50 –25 0 25 50 75 100 125

05448-010

Rev. 0 | Page 8 of 28

AD8556

100

IB–

T

A

VSY= 5
= 25°C

1000

VS = 5V

I

+

B

10

(nA)

B

I

1

VCM (V)

6012345

Figure 10. Input Bias Current at VPOS, VNEG vs. Common-Mode Voltage

0.8

0.6

0.5

0.3

0.2

–0.2

–0.3

–0.5

INPUT OFFSET CURRENT (nA)

–0.6

–0.8

0

TEMPERATURE (°C)

VSY = 5V

150–50 –25 0 25 50 75 100 125

Figure 11. Input Offset Current vs. Temperature

05448-011

05448-012

100

VCLAMP CURRENT (nA)

10

VCLAMP VOLTAGE (V)

Figure 13. VCLAMP Current over Temperature at V

3.0

2.5

2.0

1.5

1.0

SUPPLY CURRENT (mA)

0.5

0

SUPPLY VOLTAGE (V)

Figure 14. Supply Current (I

) vs. Supply Voltage

SY

+125°C

+25°C

–40°C

6023145

= 5 V vs. VCLAMP Voltage

S

TA = 25°C

60123 54

05448-014

05448-015

2.5

2.0

1.5

1.0

0.5

DIGITAL INPUT CURRENT (µA)

0

DIGITAL INPUT VOLTAGE (V)

VS = 5.5V

Figure 12. Digital Input Current vs. Digital Input Voltage (Pin 4)

6012345

05448-013

Rev. 0 | Page 9 of 28

2.5

2.3

2.1

1.9

1.7

1.5

1.3

1.1

SUPPLY CURRENT (mA)

0.9

0.7

0.5

TEMPERATURE (°C)

Figure 15. Supply Current (I

) vs. Temperature

SY

VSY = 5V

150–50 –25 0 25 50 75 100 125

05448-016

AD8556

120

80

CMRR (dB)

40

0

120

80

CMRR (dB)

0

4

0

145

135

125

FREQUENCY (Hz)

Figure 16. CMRR vs. Fre quency

FREQUENCY (Hz)

Figure 17. CMRR vs. Fre quency

GAIN = 1280

VS = ±2.5V
GAIN = 70

VS = ±2.5V
GAIN = 1280

VSY = 5V

GAIN = 800

GAIN = 400

VS = ±2.5V
GAIN = 70

60

50

40

30

20

VOLTAGE NOISE DENSITY (nV/ Hz)

10

1M100k100 1k 10k

05448-017

FREQUENCY (kHz)

1050

05448-020

Figure 19. Input Voltage Noise Density vs. Frequency (0 Hz to 10 kHz)

V

= ±2.5V

S

GAIN = 70

35

30

25

20

15

10

VOLTAGE NOISE DENSITY (nV/ Hz)

1M100 1k 10k 100k

05448-018

5

FREQUENCY (kHz)

5002500

05448-021

Figure 20. Input Voltage Noise Density vs. Frequency (0 Hz to 500 kHz)

VS = ±2.5V

0.6

0.4

GAIN = 1000

115

105

CMRR (dB)

95

85

75

GAIN = 70

TEMPERATURE (°C)

GAIN = 200

GAIN = 100

Figure 18. CMRR vs. Temperature at Different Gains

150–50 –25 0 25 50 75 100 125

05448-019

Rev. 0 | Page 10 of 28

0.2

0

NOISE (µV)

–0.2

–0.4

–0.6

TIME (1s/DIV)

Figure 21. Low Frequency Input Voltage Noise (0.1 Hz to 10 Hz)

05448-022

AD8556

8

4

0

GAIN (dB)

–4

–8

VS = ±2.5V

Figure 22. Low Frequency Input Voltage Noise (0.1 Hz to 10 Hz)

VS = ±2.5V

C

GAIN = 1280

60

40

GAIN = 70

20

CLOSED-LOOP GAIN (dB)

0

1k 100k10k 1M

FREQUENCY (Hz)

= 40PF

L

Figure 23. Closed-Loop Gain vs. Frequency Measured at Filter Pin

GAIN = 1280

60

VS = ±2.5V

05448-024

1k 100k10k 1M 10M

FREQUENCY (Hz)

Figure 25. Output Buffer Gain vs. Frequency

60

VS = ±2.5V

50

40

30

20

OVERSHOOT (%)

10

0

OUTPUT
BUFFER

R

S

C

L

= 100

R

S

LOAD CAPACITANCE (nF)

R

= 20

= 50

R

S

S

Figure 26. Output Buffer Positive Overshoot

60

VS = ±2.5V

50

R

S

C

L

RS = 0

R

S

= 10

RS = 0

05448-026

1000.1 1 10

05448-027

40

GAIN = 70

20

CLOSED-LOOP GAIN (dB)

0

1k 100k10k 1M

FREQUENCY (Hz)

Figure 24. Closed-Loop Gain vs. Frequency Measured at Output Pin

05448-025

Rev. 0 | Page 11 of 28

40

30

20

OVERSHOOT (%)

10

= 100

R

0

S

LOAD CAPACITANCE (nF)

R

= 10

S

= 20

R

S

R

= 50

S

100.00.1 1.0 10.0

05448-028

Figure 27. Output Buffer Negative Overshoot

AD8556

1.000

0.100

SOURCE

VS = ±2.5V

6

SUPPLY VOLTAGE

5

4

0.010

VDD – OUTPUT VOLTAGE (V)

0.001

LOAD CURRENT (mA)

SINK

Figure 28. Output Voltage to Supply Rail vs. Load Current

15

12

9

6

3

0

–3

–6

–9

OUTPUT SHORT CIRCUIT (mA)

–12

–15

SINK 5V

SOURCE 5V

TEMPERATURE (°C)

Figure 29. Output Short-Circuit vs. Temperature

3

VOLTAGE (1V/DIV)

2

1

V

10.00.01 0.10 1.00

05448-029

0

OUT

TIME (100µs/DIV)

05448-032

Figure 31. Power-On Response at 125°C

6

SUPPLY VOLTAGE

5

4

3

VOLTAGE (1V/DIV)

2

1

V

175–75 –50 –25 0 25 50 75 100 125 150

05448-030

0

OUT

TIME (100µs/DIV)

05448-033

Figure 32. Power-On Response at −40°C

4

2

0

VOLTAGE

3

2

1

0

SUPPLY VOLTAGE

V

OUT

TIME (100µs/DIV)

Figure 30. Power-On Response at 25°C

05448-031

Rev. 0 | Page 12 of 28

150

145

140

135

130

125

120

PSRR (dB)

115

110

105

100

VS = 2.7V TO 5.5V

TEMPERATURE (°C)

Figure 33. PSRR vs. Temperature

150–75 –50 –25 0 25 50 75 100 125

05448-034

AD8556

140

120

100

80

60

PSRR (dB)

40

20

VS = 2.7V TO 2.5V

2

VOUT (1V/DIV)

T

VS = ±2.5V
GAIN = 70

= 100pF

C

L

0

FREQUENCY (kHz)

Figure 34. PSRR v s. Frequency

T

2

VOUT (50mV/DIV)

TIME (100µs/DIV)

Figure 35. Small Signal Response

T

VS = ±2.5V
GAIN = 70
CL = 0.1µF

= 10kHz

F

IN

VS = ±2.5V
GAIN = 70
C

= 100pF

L

= 1kHz

F

IN

1000.01 0.1 1 10

05448-035

TIME (10µs/DIV)

05448-038

Figure 37. Large Signal Response

05448-036

T

2

VOUT (1V/DIV)

TIME (10µs/DIV)

VS = ±2.5V
GAIN = 70
CL = 0.05µF

05448-039

Figure 38. Large Signal Response

1k

VSY = ±2.5V
A

= 70

V

100

2

10

VOUT (50mV/DIV)

TIME (100µs/DIV)

05448-037

Figure 36. Small Signal Response

IMPEDANCE (Ω)

1

0.1 101 100 1M
FREQUENCY (kHz)

Figure 39. Output Impedance vs. Frequency

05448-040

Rev. 0 | Page 13 of 28

AD8556

1

0V

V

IN

V

IN

2

0V

V

OUT

CH1 50.0mV CH2 2.00V M 1.00µs A CH1 –21.0mV

Figure 40. Negative Overload Recovery (Gain = 70)

V

IN

1

0V

V

OUT

2

0V

CH1 50.0mV CH2 2.00V M 1.00µs A CH1 57.0mV

Figure 41. Positive Overload Recovery (Gain = 70)

05448-041

05448-042

1

0V

V

OUT

2

0V

CH1 10.0mV CH2 2.00V M 4.00µs A CH1 8.40mV

Figure 43. Positive Overload Recovery (Gain = 1280)

OFFSET = 128

1

+V

4V pp

2

5

.

0

Ω

2

4

9

Ω

10kΩ 1kΩ 10kΩ

2

0.1µF

1

4

6

7

5

DUT

8

0.1µF

–V

OUT

CH1 2.00mV CH2 2.00mV M 1.00µs A CH1 40.0mV

Figure 44. Settling Time 0.1%

GAIN = 70

= ±2.5V

V

S

05448-044

05448-045

1

0V

V

IN

2

0V

–2.5V

CH1 10.0mV CH2 2.00V M 4.00µs A CH1 –9.40mV

Figure 42. Negative Overload Recovery (Gain = 1280)

05448-043

1

0V

+V

4V pp

0

2

Ω

5

.

9

2

Ω

4

10kΩ 1kΩ 10kΩ

2

0V

0.1µF

1

4

6

7

5

DUT

8

0.1µF

–V

OUT

CH1 2.00mV CH2 2.00mV M 1.00µs A CH1 40.0mV

Figure 45. Settling Time 0.01%

GAIN = 70

OFFSET = 128

= ±2.5V

V

S

05448-046

Rev. 0 | Page 14 of 28

AD8556

1.00

0.50

0.20

0.10

THD (%)

0.05

VS=±2.5V

0.02

0.01
20 1k 2k20010050 500 5k 10k 20k

FREQUENCY (Hz)

05448-047

Figure 46. THD vs. Frequency

Rev. 0 | Page 15 of 28

AD8556

(

−

=

V

THEORY OF OPERATION

A1, A2, R1, R2, R3, P1, and P2 form the first gain stage of the
differential amplifier. A1 and A2 are auto-zeroed op amps that
minimize input offset errors. P1 and P2 are digital potentiome­ters, guaranteed to be monotonic. Programming P1 and P2
allows the first stage gain to be varied from 4.0 to 6.4 with 7-bit
resolution (see Table 5 and Equation 1), giving a fine gain
adjustment resolution of 0.37%. R1, R2, R3, P1, and P2 each
have a similar temperature coefficient, so the first stage gain
temperature coefficient is lower than 100 ppm/°C.

Code

⎞

⎛

⎟

⎜

127

6.4

⎛

GAIN1 (1)

4

×≈

⎜

4

⎝

⎠

⎝

⎞
⎟
⎠

A3, R4, R5, R6, R7, P3, and P4 form the second gain stage of
the differential amplifier. A3 is also an auto-zeroed op amp that
minimizes input offset errors. P3 and P4 are digital potenti­ometers, which allow the second stage gain to be varied from

17.5 to 200 in eight steps (see Table 6). R4, R5, R6, R7, P3, and
P4 each have a similar temperature coefficient, so the second
stage gain temperature coefficient is lower than 100 ppm/°C.

RF together with an external capacitor, connected between
FILT/DIGOUT and VSS or VDD, form a low-pass filter. The
filtered signal is buffered by A4 to give a low impedance output
at VOUT. RF is nominally 18 kΩ, allowing an 880 Hz low-pass
filter to be implemented by connecting a 10 nF external
capacitor between FILT/DIGOUT and VSS, or between
FILT/DIGOUT and VDD. If low-pass filtering is not needed,
the FILT/DIGOUT pin must be left floating.

A5 implements a voltage buffer, which provides the positive
supply to A4, the amplifier output buffer. Its function is to limit
VOUT to a maximum value, useful for driving analog-to-digital
converters (ADC) operating on supply voltages lower than
VDD. The input to A5, VCLAMP, has a very high input
resistance. It should be connected to a known voltage and not
left floating. However, the high input impedance allows the
clamp voltage to be set using a high impedance source, such as,
a potential divider. If the maximum value of VOUT does not
need to be limited, VCLAMP should be connected to VDD.

A4 implements a rail-to-rail input and output unity-gain
voltage buffer. The output stage of A4 is supplied from a
buffered version of VCLAMP instead of VDD, allowing the

positive swing to be limited. The maximum output current is
limited between 5 mA to 10 mA.

An 8-bit digital-to-analog converter (DAC) is used to generate
a variable offset for the amplifier output. This DAC is guaran­teed to be monotonic. To preserve the ratiometric nature of the
input signal, the DAC references are driven from VSS and VDD,
and the DAC output can swing from VSS (Code 0) to VDD
(Code 255). The 8-bit resolution is equivalent to 0.39% of the
difference between VDD and VSS, for example, 19.5 mV with
a 5 V supply. The DAC output voltage (VDAC) is given
approximately by

VDAC +−

Where the temperature coefficient of
200 ppm/°C.

The amplifier output voltage (VOUT) is given by

GAIN is the product of the first and second stage gains.

where

NEG

VPOS

VDD

A1

VSS

VDD

A2

VSS

Code

⎛

≈

⎜
⎝

R1

P1

R3

P2

R2

VDD

DAC

VSS

⎞

()

⎟

256

⎠

P3

R4

R5 R7

Figure 47. Functional Schematic

R6

VDD

A3

VSS

P4

5.0

+

VSSVSSVDD

(2)

VDAC is lower than

)

VCLAMP

(3)

VDACVNEGVPOSGAINVOUT +

VDD

A5

VSS

VDD

RF

A4

FILT/

DIGOUT

VSS

VOUT

05448-001

Rev. 0 | Page 16 of 28

AD8556

GAIN VALUES

Table 5. First Stage Gain vs. First Stage Gain Code

First Stage
Gain Code

0 4.000 32 4.503 64 5.069 96 5.706
1 4.015 33 4.520 65 5.088 97 5.727
2 4.030 34 4.536 66 5.107 98 5.749
3 4.045 35 4.553 67 5.126 99 5.770
4 4.060 36 4.570 68 5.145 100 5.791
5 4.075 37 4.587 69 5.164 101 5.813
6 4.090 38 4.604 70 5.183 102 5.834
7 4.105 39 4.621 71 5.202 103 5.856
8 4.120 40 4.638 72 5.221 104 5.878
9 4.135 41 4.655 73 5.241 105 5.900
10 4.151 42 4.673 74 5.260 106 5.921
11 4.166 43 4.690 75 5.280 107 5.943
12 4.182 44 4.707 76 5.299 108 5.965
13 4.197 45 4.725 77 5.319 109 5.988
14 4.213 46 4.742 78 5.339 110 6.010
15 4.228 47 4.760 79 5.358 111 6.032
16 4.244 48 4.778 80 5.378 112 6.054
17 4.260 49 4.795 81 5.398 113 6.077
18 4.276 50 4.813 82 5.418 114 6.099
19 4.291 51 4.831 83 5.438 115 6.122
20 4.307 52 4.849 84 5.458 116 6.145
21 4.323 53 4.867 85 5.479 117 6.167
22 4.339 54 4.885 86 5.499 118 6.190
23 4.355 55 4.903 87 5.519 119 6.213
24 4.372 56 4.921 88 5.540 120 6.236
25 4.388 57 4.939 89 5.560 121 6.259
26 4.404 58 4.958 90 5.581 122 6.283
27 4.420 59 4.976 91 5.602 123 6.306
28 4.437 60 4.995 92 5.622 124 6.329
29 4.453 61 5.013 93 5.643 125 6.353
30 4.470 62 5.032 94 5.664 126 6.376
31 4.486 63 5.050 95 5.685 127 6.400

First Stage Gain

First Stage
Gain Code

First Stage Gain

First Stage
Gain Code

First Stage Gain

First Stage
Gain Code

First Stage Gain

Table 6. Second Stage Gain and Gain Ranges vs. Second Stage Gain Code

Second Stage Gain Code Second Stage Gain Minimum Combined Gain Maximum Combined Gain

0 17.5 70 112
1 25 100 160
2 35 140 224
3 50 200 320
4 70 280 448
5 100 400 640
6 140 560 896
7 200 800 1280

Rev. 0 | Page 17 of 28

AD8556

OPEN WIRE FAULT DETECTION

The inputs to A1 and A2, VNEG and VPOS, each have a com­parator to detect whether VNEG or VPOS exceeds a threshold
voltage, nominally VDD − 2.0 V. If (VNEG > VDD − 2.0 V) or
(VPOS > VDD − 2.0 V), VOUT is clamped to VSS. The output
current limit circuit is disabled in this mode, but the maximum
sink current is approximately 10 mA when VDD = 5 V. The
inputs to A1 and A2, VNEG and VPOS, are also pulled up to
VDD by currents IP1 and IP2. These are both nominally 49 nA
and matched to within 3 nA. If the inputs to A1 or A2 are
accidentally left floating, as with an open wire fault, IP1 and IP2
pull them to VDD which would cause VOUT to swing to VSS,
allowing this fault to be detected. It is not possible to disable IP1
and IP2, nor the clamping of VOUT to VSS, when VNEG or
VPOS approaches VDD.

SHORTED WIRE FAULT DETECTION

The AD8556 provides fault detection in the case where VPOS,
VNEG, or VCLAMP shorts to VDD and VSS. Figure 48 shows
the voltage regions at VPOS, VNEG, and VCLAMP that trigger
an error condition. When an error condition occurs, the VOUT
pin is shorted to VSS. Table 7 lists the voltage levels shown in
Figure 48.

VPOS VNEG

ERROR

NORMAL

ERROR

VDD

VINH

VINL
VSS

Figure 48. Voltage Regions at VPOS, VNEG, and VCLAMP

ERROR

NORMAL

ERROR

that Trigger a Fault Condition

VDD

VINH

VINL
VSS

Table 7. Typical VINL, VINH, and VCLL Values (VDD = 5 V)

Voltage Min (V) Typ (V) Max (V) VOUT Condition

VINH 2.95 3.0 3.05

VINL 1.95 2.0 2.05

VCLL 1.05 1.1 1.15

VCLAMP

VDD

NORMAL

VCLL

ERROR

VSS

Short to VSS fault
detection

Short to VSS fault
detection

Short to VSS fault
detection

05448-048

FLOATING VPOS, VNEG, OR VCLAMP FAULT DETECTION

A floating fault condition at the VPOS, VNEG, or VCLAMP
pins is detected by using a low current to pull a floating input
into an error voltage range, defined in the previous section. In
this way, the VOUT pin is shorted to VSS when a floating input
is detected. Table 8 lists the currents used.

Table 8. Floating Fault Detection at VPOS, VNEG,
and VCLAMP

Pin Typical Current Goal of Current

VPOS 49 nA pull-up Pull VPOS above VINH
VNEG 49 nA pull-up Pull VNEG above VINH
VCLAMP 0.2 µA pull-down Pull VCLAMP below VCLL

DEVICE PROGRAMMING

Digital Interface

The digital interface allows the first stage gain, second stage
gain, and output offset to be adjusted and allows desired values
for these parameters to be permanently stored by selectively
blowing polysilicon fuses. To minimize pin count and board
space, a single-wire digital interface is used. The digital input
pin, DIGIN, has hysteresis to minimize the possibility of
inadvertent triggering with slow signals. It also has a pull-down
current sink to allow it to be left floating when programming is
not being performed. The pull-down ensures inactive status of
the digital input by forcing a dc low voltage on DIGIN.

A short pulse at DIGIN from low to high and back to low again,
such as between 50 ns and 10 µs long, loads a 0 into a shift
register. A long pulse at DIGIN, such as 50 µs or longer, loads a
1 into the shift register. The time between pulses should be at
least 10 µs. Assuming VSS = 0 V, voltages at DIGIN between
VSS and 0.2 × VDD are recognized as a low, and voltages at
DIGIN between 0.8 × VDD and VDD are recognized as a high.
A timing diagram example, Figure 49, shows the waveform for
entering code 010011 into the shift register.

Rev. 0 | Page 18 of 28

AD8556

W

t

WS

t

W0

t

W0

t

WS

t

W1

t

WS

t

W1

AVEFORM

t

W1

t

WS

t

W0

t

WS

CODE

01001 1

Figure 49. Timing Diagram for Code 010011

Table 9. Timing Specifications

Timing Parameter Description Specification

tw0 Pulse Width for Loading 0 into Shift Register Between 50 ns and 10 µs
tw1 Pulse Width for Loading 1 into Shift Register ≥50 µs
tws Width Between Pulses ≥10 µs

Table 10. 38-Bit Serial Word Format

Field No. Bits Description

0 0 to 11 12-Bit Start of Packet 1000 0000 0001
1 12 to 13 2-Bit Function
00: Change Sense Current
01: Simulate Parameter Value
10: Program Parameter Value
11: Read Parameter Value
2 14 to 15 2-Bit Parameter
00: Second Stage Gain Code
01: First Stage Gain Code
10: Output Offset Code
11: Other Functions
3 16 to 17 2-Bit Dummy 10
4 18 to 25 8-Bit Value
Parameter 00 (Second Stage Gain Code): 3 LSBs Used
Parameter 01 (First Stage Gain Code): 7 LSBs Used
Parameter 10 (Output Offset Code): All 8 Bits Used
Parameter 11 (Other Functions)
Bit 0 (LSB): Master Fuse
Bit 1: Fuse for Production Test at Analog Devices
Bit 2: Parity Fuse
5 26 to 37 12-Bit End of Packet 0111 1111 1110

05448-049

A 38-bit serial word is used, divided into 6 fields. Assuming
each bit can be loaded in 60 µs, the 38-bit serial word transfers
in 2.3 ms. Table 10 summarizes the word format.

Field 0 and Field 5 are the start-of-packet field and end-of­packet field, respectively. Matching the start-of-packet field with
1000 0000 0001 and the end-of-packet field with 0111 1111
1110 ensures that the serial word is valid and enables decoding

Field 3 breaks up the data and ensures that no data combination
can inadvertently trigger the start-of-packet and end-of-packet
fields. Field 0 should be written first and Field 5 written last.

Within each field, the MSB must be written first and the LSB
written last. The shift register features power-on reset to mini­mize the risk of inadvertent programming; power-on reset
occurs when VDD is between 0.7 V and 2.2 V.

of the other fields.

Rev. 0 | Page 19 of 28

AD8556

Initial State

Initially, all the polysilicon fuses are intact. Each parameter has
the value 0 assigned (see Table 11).

Table 11. Initial State Before Programming

Second Stage Gain Code = 0 Second Stage Gain = 17.5

First stage gain code = 0 First stage gain = 4.0
Output offset code = 0 Output offset = VSS
Master fuse = 0 Master fuse not blown

When power is applied to a device, parameter values are taken
either from internal registers, if the master fuse is not blown,
or from the polysilicon fuses, if the master fuse is blown.
Programmed values have no effect until the master fuse is
blown. The internal registers feature power-on reset, so the
unprogrammed devices enter a known state after power-up.
Power-on reset occurs when VDD is between 0.7 V and 2.2 V.

Simulation Mode

The simulation mode allows any parameter to be temporarily
changed. These changes are retained until the simulated value is
reprogrammed, the power is removed, or the master fuse is
blown. Parameters are simulated by setting Field 1 to 01,
selecting the desired parameter in Field 2, and the desired value
for the parameter in Field 4. Note that a value of 11 for Field 2 is
ignored during the simulation mode. Examples of temporary
settings follow:

Setting the second stage gain code (Parameter 00) to 011 and

•

the second stage gain to 50 produces:
1000 0000 0001 01 00 10 0000 0011 0111 1111 1110

Setting the first stage gain code (Parameter 01) to 000 1011

•

and the first stage gain to 4.166 produces:
1000 0000 0001 01 01 10 0000 1011 0111 1111 1110

A first stage gain of 4.166 with a second stage gain of 50 gives a
total gain of 208.3. This gain has a maximum tolerance of 2.5%.

•

Set the output offset code (Parameter 10) to 0100 0000 and

the output offset to 1.260 V when VDD = 5 V and VSS = 0 V.
This output offset has a maximum tolerance of 0.8%:
1000 0000 0001 01 10 10 0100 0000 0111 1111 1110

Programming Mode

Intact fuses give a bit value of 0. Bits with a desired value of 1
need to have the associated fuse blown. Since a relatively large
current is needed to blow a fuse, only one fuse can be reliably
blown at a time. Thus, a given parameter value may need
several 38-bit words to allow reliable programming. A 5.25 V
(±0.25 V) supply is required when blowing fuses to minimize
the on resistance of the internal MOS switches that blow the
fuse. The power supply voltage must not exceed the absolute
maximum rating and must be able to deliver 250 mA of current.

At least 10 µF (tantalum type) of decoupling capacitance is
needed across the power pins of the device during program­ming. The capacitance can be on the programming apparatus as
long as it is within 2 inches of the device being programmed.
An additional 0.1 µF (ceramic type) in parallel with the 10 µF is
recommended within ½ inch of the device being programmed.
A minimum period of 1 ms should be allowed for each fuse to
blow. There is no need to measure the supply current during
programming.

The best way to verify correct programming is to use the read
mode to read back the programmed values. Then, remeasure
the gain and offset to verify these values. Programmed fuses
have no effect on the gain and output offset until the master
fuse is blown. After blowing the master fuse, the gain and
output offset are determined solely by the blown fuses, and the
simulation mode is permanently deactivated.

Parameters are programmed by setting Field 1 to 10, selecting
the desired parameter in Field 2, and selecting a single bit with
the value 1 in Field 4.

As an example, suppose the user wants to permanently set the
second stage gain to 50. Parameter 00 needs to have the value
0000 0011 assigned. Two bits have the value 1, so two fuses need
to be blown. Since only one fuse can be blown at a time, this
code can be used to blow one fuse:
1000 0000 0001 10 00 10 0000 0010 0111 1111 1110

The MOS switch that blows the fuse closes when the complete
packet is recognized, and opens when the start-of-packet,
dummy, or end-of-packet fields are no longer valid. After 1 ms,
this second code is entered to blow the second fuse:
1000 0000 0001 10 00 10 0000 0001 0111 1111 1110

To permanently set the first stage gain to a nominal value of

4.151, Parameter 01 needs to have the value 000 1011 assigned.
Three fuses need to be blown, and the following codes are used,
with a 1 ms delay after each code:
1000 0000 0001 10 01 10 0000 1000 0111 1111 1110
1000 0000 0001 10 01 10 0000 0010 0111 1111 1110
1000 0000 0001 10 01 10 0000 0001 0111 1111 1110

To permanently set the output offset to a nominal value of

1.260 V when VDD = 5 V and VSS = 0 V, Parameter 10 needs to
have the value 0100 0000 assigned. If one fuse needs to be
blown, use the following code:
1000 0000 0001 10 10 10 0100 0000 0111 1111 1110

Finally, to blow the master fuse to deactivate the simulation
mode and prevent further programming, use code:
1000 0000 0001 10 11 10 0000 0001 0111 1111 1110

There are a total of 20 programmable fuses. Since each fuse
requires 1 ms to blow, and each serial word can be loaded in

Rev. 0 | Page 20 of 28

AD8556

2.3 ms, the maximum time needed to program the fuses can be
as low as 66 ms.

Parity Error Detection

A parity check is used to determine whether the programmed
data of an AD8556 is valid, or whether data corruption has
occurred in the nonvolatile memory. Figure 50 shows the
schematic implemented in the AD8556.

VA0 to VA2 is the 3-bit control signal for the second stage gain,
VB0 to VB6 is the 7-bit control signal for the first stage gain,
and VC0 to VC7 is the 8-bit control signal for the output offset.
PFUSE is the signal from the parity fuse, and MFUSE is the
signal from the master fuse.

The function of the 2-input AND gate (Cell AND2) is to ignore
the output of the parity circuit (PAR_SUM signal) when the
master fuse has not been blown. PARITY_ERROR is set to 0
when MFUSE = 0. In the simulation mode, for example, parity
check is disabled. After the master fuse has been blown, that is,
after the AD8556 has been programmed, the output from the
parity circuit (PAR_SUM signal) is fed to PARITY_ERROR.

I0

VA0

VA1

VA2

VB0

VB1

VB2

VB3

VB4

VB5

VB6

VC0

VC1

VC2

VC3

VC4

VC5

VC6

VC7

IN01

IN02

IN03

IN04

IN05

IN06

IN07

IN08

IN09

IN10

IN11

IN12

IN13

IN14

IN15

IN16

IN17

IN18

EOR18 OUT

DAT_SUM

PFUSE

Figure 50. Functional Circuit of AD8556 Parity Check

IN1

IN2

When PARITY_ERROR is 0, the AD8556 behaves as a
programmed amplifier. When PARITY_ERROR is 1, a parity
error has been detected, and VOUT is connected to VSS.

The 18-bit data signal (VA0 to VA2, VB0 to VB6, and VC0 to
VC7) is fed to an 18-input exclusive-OR gate (Cell EOR18). The
output of Cell EOR18 is the DAT_SUM signal. DAT_SUM = 0 if
there is an even number of 1s in the 18-bit word; DAT_SUM =
1 if there is an odd number of 1s in the 18-bit word. Refer to
Table 12 for examples.

After the second stage gain, first stage gain, and output offset
have been programmed, compute DAT_SUM and set the parity
bit equal to DAT_SUM. If DAT_SUM is 0, the parity fuse

be blown in order for the PFUSE signal to be 0. If

not

DAT_SUM is 1, the parity fuse should be blown to set the
PFUSE signal to 1. The code to blow the parity fuse is:
1000 0000 0001 10 11 10 0000 0100 01111111 1110.

After setting the parity bit, the master fuse can be blown to
prevent further programming, using the code:
1000 0000 0001 10 11 10 0000 0001 0111 1111 1110.

PAR_SUM

EOR2

I1

OUT

MFUSE

IN1

IN2

AND2

I2

OUT

PARITY_ERROR

05448-050

should

Table 12. Examples of DAT_SUM

Second Stage Gain Code First Stage Gain Code Output Offset Code Number of Bits with 1 DAT_SUM

000 000 0000 0000 0000 0 0
000 000 0000 1000 0000 1 1
000 000 0000 1000 0001 2 0
000 000 0001 0000 0000 1 1
000 100 0001 0000 0000 2 0
001 000 0000 0000 0000 1 1
001 000 0001 1000 0000 3 1
111 111 1111 1111 1111 18 0

Rev. 0 | Page 21 of 28

AD8556

Signal PAR_SUM is the output of the 2-input exclusive-OR
gate (Cell EOR2). After the master fuse is blown, set
PARITY_ERROR to PAR_SUM. As mentioned earlier, the
AD8556 behaves as a programmed amplifier when
PARITY_ERROR = 0 (no parity error). On the other hand,
VOUT is connected to VSS when a parity error has been
detected, that is, when PARITY_ERROR = 1.

It is theoretically possible, though very unlikely, for a fuse to be
incompletely blown during programming, assuming the
required conditions are met. In this situation, the fuse could
have a medium resistance, neither low nor high, and a voltage of
approximately 1.5 V could be developed across the fuse. Thus,
the OTP cell could output Logic 0 or a Logic 1, depending on
temperature, supply voltage, and other variables.

Read Mode

The values stored by the polysilicon fuses can be sent to the
FILT/DIGOUT pin to verify correct programming. Normally,
the FILT/DIGOUT pin is only connected to the second gain
stage output via RF. During read mode, however, the
FILT/DIGOUT pin is also connected to the output of a shift
register to allow the polysilicon fuse contents to be read. Since
VOUT is a buffered version of FILT/DIGOUT, VOUT also
outputs a digital signal during read mode.

Read mode is entered by setting Field 1 to 11 and selecting the
desired parameter in Field 2. Field 4 is ignored. The parameter
value, stored in the polysilicon fuses, is loaded into an internal
shift register, and the MSB of the shift register is connected to
the FILT/DIGOUT pin. Pulses at DIGIN shift out the shift
register contents to the FILT/DIGOUT pin, allowing the 8‒bit
parameter value to be read after seven additional pulses; shift­ing occurs on the falling edge of DIGIN. An eighth pulse at
DIGIN disconnects FILT/DIGOUT from the shift register and
terminates the read mode. If a parameter value is less than eight
bits long, the MSBs of the shift register are padded with 0s.

For example, to read the second stage gain, this code is used:
1000 0000 0001 11 00 10 0000 0000 0111 1111 1110
Since the second stage gain parameter value is only three bits
long, the FILT/DIGOUT pin has a value of 0 when this code is
entered, and remains 0 during four additional pulses at DIGIN.
The fifth, sixth, and seventh pulses at DIGIN return the 3-bit
value at FILT/DIGOUT, the seventh pulse returns the LSB. An
eighth pulse at DIGIN terminates the read mode.

Sense Current

A sense current is sent across each polysilicon fuse to determine
whether it has been blown. When the voltage across the fuse is
less than approximately 1.5 V, the fuse is considered not blown,
and Logic 0 is output from the OTP cell. When the voltage
across the fuse is greater than approximately 1.5 V, the fuse is
considered blown, and Logic 1 is output.

When the AD8556 is manufactured, all fuses have a low
resistance. When a sense current is sent through the fuse, a
voltage less than 0.1 V is developed across the fuse. This is
much lower than 1.5 V, so Logic 0 is output from the OTP cell.
When a fuse is electrically blown, it should have a very high
resistance. When the sense current is applied to the blown fuse,
the voltage across the fuse should be larger than 1.5 V, so
Logic 1 is output from the OTP cell.

To detect this undesirable situation, the sense current can be
lowered by a factor of 4 using a specific code. The voltage
developed across the fuse would then change from 1.5 V to

0.38 V, and the output of the OTP would be a Logic 0 instead of
the expected Logic 1 from a blown fuse. Correctly blown fuses
would still output a Logic 1. In this way, incorrectly blown fuses
can be detected. Another specific code would return the sense
current to the normal (larger) value. The sense current cannot
be permanently programmed to the low value. When the
AD8556 is powered up, the sense current defaults to the high
value.

The low sense current code is:
1000 0000 0001 00 00 10 XXXX XXX1 0111 1111 1110

The normal (high) sense current code is:
1000 0000 0001 00 00 10 XXXX XXX0 0111 1111 1110

Programming Procedure

For reliable fuse programming, it is imperative to follow the
programming procedure requirements, especially the proper
supply voltage during programming.

1.

When programming the AD8556, the temperature of the

device must be between 10°C to 40°C.

2.

Set VDD and VSS to the desired values in the application.

Use simulation mode to test and determine the desired
codes for the second stage gain, first stage gain, and output
offset. The nominal values for these parameters are shown in
Table 5, Table 6, Equation 2, and Equation 3; use the codes
corresponding to these values as a starting point. However,
since actual parameter values for given codes vary from
device to device, some fine tuning is necessary for the best
possible accuracy.

One way to choose these values is to set the output offset
to an approximate value, such as Code 128 for midsupply, to
allow the required gain to be determined. Then set the
second stage gain so the minimum first stage gain (Code 0)
gives a lower gain than required, and the maximum first
stage gain (Code 127) gives a higher gain than required.
After choosing the second stage gain, the first stage gain can
be chosen to fine tune the total gain. Finally, the output
offset can be adjusted to give the desired value. After
determining the desired codes for second stage gain, first
stage gain, and output offset, the device is ready for
permanent programming.

Rev. 0 | Page 22 of 28

AD8556

Important: Once a programming attempt has been made for

any fuse, there should be no further attempt to blow that
fuse. If a fuse does not program to the expected state, discard
the unit. The expected incidence rate of attempted but
unblown fuses is very small when following the proper
programming procedure and conditions.

3.

Set VSS to 0 V and VDD to 5.25 V (±0.25 V). Power supplies

should be capable of supplying 250 mA at the required
voltage and properly bypassed as described in the
Programming Mode section. Use program mode to
permanently enter the desired codes for the first stage gain,
second stage gain, and output offset. Blow the parity bit fuse
if necessary (see Parity Error Detection section). Blow the
master fuse to allow the AD8556 to read data from the fuses
and to prevent further programming.

4.

Set VDD and VSS to the desired values in the application.

Use read mode with low sense current followed by high
sense current to verify programmed codes.

5.

Measure gain and offset to verify correct functionality.

Determining Optimal Gain and Offset Codes

First, determine the desired gain:

1.

Determine the desired gain, G

(using the measurements

A

obtained from the simulation).

2.

Use Table 6 to determine G

(4.00 × 1.04) < (G

A/G2

, the second stage gain, such that

2

) < (6.4/1.04). This ensures the first and
last codes for the first stage gain are not used, thereby
allowing enough first stage gain codes within each second
stage gain range to adjust for the 3% accuracy.

Next, set the second stage gain:

1.

Use the simulation mode to set the second stage gain to G
Set the output offset to allow the AD8556 gain to be

2.
measured, for example, use Code 128 to set it to midsupply.

.

2

Use Table 5 or Equation 1 to set the first stage gain code

3.
C

, so the first stage gain is nominally GA/G2.

G1

Measure the resulting gain (G

4.
3% of G

5.

Calculate the first stage gain error (in relative terms)

E

.

A

= GB/GA − 1.

G1

). GB should be within

B

6. Calculate the error (in the number of the first stage gain
codes) C

7. Set the first stage gain code to CG1 − C

8.

Measure the gain (G

9.

Calculate the error (in relative terms) E

Calculate the error (in the number of the first stage gain

10.
codes) C

11. Set the first stage gain code to CG1 − C
resulting gain should be within one code of G

= EG1/0.00370.

EG1

C

= EG2/0.00370.

EG2

.

EG1

). GC should be closer to GA than to GB.

= GC/GA − 1.

G2

− C

EG2

A

. The

.

EG1

Finally, determine the desired output offset:

1.

Determine the desired output offset O

(using the

A

measurements obtained from the simulation).

2.

Use Equation 2 to set the output offset code C

the output offset is nominally O

3.

Measure the output offset (O

3% of O

.

A

.

A

). OB should be within

B

such that

O1

4. Calculate the error (in relative terms) EO1 = OB/OA − 1.

5. Calculate the error (in the number of the output offset
codes) C

6. Set the output offset code to CO1 − C

Measure the output offset (O

7.
than to O

= EO1/0.00392.

EO1

.

B

.

EO1

). OC should be closer to OA

C

8. Calculate the error (in relative terms) EO2 = OC/OA − 1.

9. Calculate the error (in the number of the output offset
codes) C

10. Set the output offset code to CO1 − C
resulting offset should be within one code of O

= EO2/0.00392.

EO2

EO1

− C

EO2

. The

.

A

Rev. 0 | Page 23 of 28

AD8556

V

EMI/RFI PERFORMANCE

Real world applications must work with ever increasing
radio/magnetic frequency interference (RFI and EMI). In
situations where signal strength is low and transmission lines
are long, instrumentation amplifiers such as AD8556 are
needed to extract weak, small differential signals riding on
common-mode noise and interference. Additionally, wires and
PCB traces act as antennas and pick up high frequency EMI
signals. The longer the wire, the larger the voltage it picks up.
The amount of voltages picked up is dependent on the
impedances at the wires, as well as the EMI frequency. These
high frequency voltages are then passed into the in-amp
through its pins. All instrumentation amplifiers can rectify high
frequency out-of-band signals. Unfortunately, the EMI/RFI
rectification occurs because amplifiers do not have any
significant common-mode rejection above 100 kHz. Once these
high frequency signals are rectified, they appear as dc offset
errors at the output.

AD8556 features internal EMI filters on the VNEG, VPOS,
FILT and VCLAMP pins. These built-in filters on the pins limit

the interference bandwidth, and provide good RFI suppression
without reducing performance within the pass-band of the
in-amp. A functional diagram of AD8556 along with its
EMI/RFI filters is shown in Figure 51.

AD8556 has built-in filters on its inputs, VCLAMP, and filter
pins. The first-order low-pass filters inside the AD8556 are
useful to reject high frequency EMI signals picked up by wires
and PCB traces outside the AD8556. The most sensitive pin of
any amplifier to RFI/EMI signal is the non-inverting pin. Signals
present at this pin appear as common-mode signals and create
problems.

The filters built at the input of the AD8556 have two different
bandwidths: common and differential mode. The common­mode bandwidth defines what a common-mode RF signal sees
between the two inputs tied together and ground. The EMI
filters placed on the input pins of the AD8556 reject EMI/RFI
suppressions that appear as common-mode signals.

VPOS

NEG

EMI

FILTER

EMI

FILTER

EMI

FILTER

VSS

LOGIC

–IN

+IN

VDD

DAC

VDD

A1

1

+IN

2

–IN

VSS

VDD

1

+IN

2

–IN

VSS

A2

OUT

OUT

3

3

R2

R3

R1

VSS

P2

P1

R4 R6

P3

AD8556

R7P4R5

VDD

A3

1

+IN

OUT

2

–IN

VSS

Figure 51. Block Diagram Showing EMI/RFI Built-In Filters

EMI

FILTER

RF

3

FILT/DIGOUT

1

+IN

2

–IN

EMI

FILTER

VDDDIGIN VCLAMP

A5

3

OUT

VSS

VDD

A4

1

+IN

2

–IN

VSS

OUT

3

VOUT

05448-053

Rev. 0 | Page 24 of 28

AD8556

In order to show the benefits that the AD8556 brings to new
applications where EMI/RFI signals are present, a part was
programmed with a gain of 70, dc offset = 2.5 V, to produce
V

= 0 V. A test circuit like that shown in Figure 52 was used.

OUT

Figure 52 simulates the presence of a noisy common-mode
signal, and Figure 53 shows the response dc values at V

+2.5V –2.5V

U3

1

VDD VSS

2

FILT/DIGOUT

3

DIGIN

405

VNEG VPOS

VCLAMP

AD8556

VOUT

8

7

6

2.5V

OUT

VOUT

.

inputs, VPOS (that is, +IN ) and VNEG (that is, –IN). Figure 54
shows the circuit used to test for AD8556 EMI/RFI
susceptibility. The part is programmed as stated previously
during the common-mode testing.

+2.5V –2.5V

U2

VOUT

8

7

6

5

200mV p-p

2.5V

V2

V

OUT

05448-052

1

VDD VSS

2

FILT/DIGOUT

3

0

0

DIGIN

4

VNEG VPOS

VCLAMP

AD8556

Figure 54. Test Circuit to Show AD8556 Performance Exposed to Differential

Mode RFI/EMI Signals

V3

VARIABLE

05448-051

Figure 52. Test Circuit to Show AD8556 Performance

Exposed to Common-Mode RFI/EMI Signals

100

80

60

40

20

0

DEVIATION FROM DC OUTPUT (mV)

–20

0 200 400 600 800 1000

NON-EMI PROTECTED SOLUTION

AD8556

FREQUENCY (MHz)

Figure 53. DC Offset Values at V

OUT

Caused by Frequency Seep of Input

The differential bandwidth defines the frequency response of
the filters with a differential signal applied between the two

05448-054

The response of AD8556 to EMI/RFI differential signals is
shown in Figure 55.

600

400

–200

–400

–600

DC OFFSET (mV)

–800

–1000

–1200

–1400

200

0

AD8556

NON-EMI PROTECTED SOLUTION

0 200 400 600 800 1000

FREQUENCY (MHz)

Figure 55. Response of AD8556 to EMI/RFI Differential Signals

To make a board robust against EMI, the leads at VPOS and
VNEG should be as similar as possible. In this way, any EMI
received by the VPOS and VNEG pins will be similar (that is, a
common-mode input), and rejected by the AD8556.
Furthermore, additional filtering at the VPOS and VNEG pins
should give a better reduction of unwanted behavior compared
with filtering at the other pins.

05448-055

Rev. 0 | Page 25 of 28

AD8556

R

OUTLINE DIMENSIONS

4.00 (0.1574)

3.80 (0.1497)

5.00 (0.1968)

4.80 (0.1890)

85

6.20 (0.2440)

5.80 (0.2284)

41

PIN 1

INDICATO

1.00

0.85

0.80

1.27 (0.0500)
BSC

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

Figure 56. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

12° MAX

SEATING
PLANE

4.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

COMPLIANT TO JEDEC STANDARDS MO-220-VGGC

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

0.60 MAX

0.65 BSC

0.05 MAX

0.02 NOM

COPLANARITY

0.75

0.60

0.50

0.08

0.60 MAX

13

12

EXPOSED

(BOTTOM VIEW)

9

8

PAD

16

1

4

5

1.95 BSC

Figure 57. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-16-4)

Dimensions shown in millimeters

× 45°

2.25

2.10 SQ

1.95

0.25 MIN

PIN 1
INDICATOR

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8556ARZ
AD8556ARZ-REEL1 −40°C to +140°C 8-Lead SOIC_N R-8
AD8556ARZ-REEL71 −40°C to +140°C 8-Lead SOIC_N R-8
AD8556ACPZ-R21 −40°C to +140°C 16-Lead LFCSP_VQ CP-16-4
AD8556ACPZ-REEL1 −40°C to +140°C 16-Lead LFCSP_VQ CP-16-4
AD8556ACPZ-REEL71 −40°C to +140°C 16-Lead LFCSP_VQ CP-16-4
AD8556ARZ-EVAL1 Evaluation Board

1

Z = Pb-free part.

1

−40°C to +140°C 8-Lead SOIC_N R-8

Rev. 0 | Page 26 of 28

AD8556

NOTES

Rev. 0 | Page 27 of 28

AD8556

NOTES

©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D05448–0–5/05(0)

Rev. 0 | Page 28 of 28