Analog Devices AD8555 Service Manual

Zero-Drift, Digitally Programmable

V

FEATURES

Very low offset voltage: 10 µV maximum over temperature Very low input offset voltage drift: 60 nV/°C maximum High CMRR: 96 dB minimum Digitally programmable gain and output offset voltage Single-wire serial interface Open and short wire fault detection Low-pass filtering Stable with any capacitive load Externally programmable output clamp voltage for driving

low voltage ADCs

LFCSP-16 and SOIC-8 packages

2.7 V to 5.5 V operation

−40°C to +125°C operation

APPLICATIONS

Automotive sensors Pressure and position sensors Thermocouple amplifiers Industrial weigh scales Precision current sensing Strain gages

NEG

VPOS

Sensor Signal Amplifier

AD8555

FUNCTIONAL BLOCK DIAGRAM

VDD

R6

VDD

A3

VSS

Figure 1.

VCLAMP

RF

FILT/

DIGOUT

A5

VSS

VDD

A1

VSS

VDD

A2

VSS

P3

R4

R1

P1

R3

P2

R2

R5 R7

P4

VDD

DAC

VSS

VDD

A4

VSS

VOUT

04598-0-001

GENERAL DESCRIPTION

The AD8555 is a zero-drift, sensor signal amplifier with digitally programmable gain and output offset. Designed to easily and accurately convert variable pressure sensor and strain bridge outputs to a well-defined output voltage range, the AD8555 also accurately amplifies many other differential or single-ended sensor outputs. The AD8555 uses the ADI patented low noise auto-zero and DigiTrim® technologies to create an incredibly accurate and flexible signal processing solution in a very compact footprint.

Gain is digitally programmable in a wide range from 70 to 1,280 through a serial data interface. Gain adjustment can be fully simulated in-circuit and then permanently programmed with proven and reliable poly-fuse technology. Output offset voltage is also digitally programmable and is ratiometric to the supply voltage.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

In addition to extremely low input offset voltage and input offset voltage drift and very high dc and ac CMRR, the AD8555 also includes a pull-up current source at the input pins and a pull-down current source at the VCLAMP pin. This allows open wire and shorted wire fault detection. A low-pass filter function is implemented via a single low cost external capacitor. Output clamping set via an external reference voltage allows the AD8555 to drive lower voltage ADCs safely and accurately.

When used in conjunction with an ADC referenced to the same supply, the system accuracy becomes immune to normal supply voltage variations. Output offset voltage can be adjusted with a resolution of better than 0.4% of the difference between VDD and VSS. A lockout trim after gain and offset adjustment further ensures field reliability.

The AD8555AR is fully specified over the extended industrial temperature range of −40°C to +125°C. Operating from single-supply voltages of 2.7 V to 5.5 V, the AD8555 is offered in the narrow 8-lead SOIC package and the 4 mm × 4 mm 16-lead LFCSP.

AD8555

ELECTRICAL SPECIFICATIONS

At VDD = 5.0 V, VSS = 0.0 V, VCM = 2.5 V, VO = 2.5 V, −40°C ≤ TA ≤ +125°C, unless otherwise specified.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

INPUT STAGE

Input Offset Voltage VOS 2 10 µV Input Offset Voltage Drift TCVOS 25 65 nV/°C Input Bias Current IB T 25 nA Input Offset Current IOS T

1.5 nA Input Voltage Range 0.6 3.8 V Common-Mode Rejection Ratio CMRR VCM = 0.9 V to 3.6 V, AV = 70 80 92 dB V Linearity VO = 0.2 V to 3.4 V 20 ppm V Differential Gain Accuracy Second Stage Gain = 17.5 to 100 0.35 1.6 % Second Stage Gain = 140 to 200 0.5 2.5 % Differential Gain Temperature Coefficient Second Stage Gain = 17.5 to 100 15 40 ppm/°C Second Stage Gain = 140 to 200 40 100 ppm/°C

RF 14 18 22 kΩ RF Temperature Coefficient 700 ppm/°C

DAC

Accuracy AV = 70, Offset Codes = 8 to 248 0.7 0.8 % Ratiometricity AV = 70, Offset Codes = 8 to 248 50 ppm Output Offset AV = 70, Offset Codes = 8 to 248 5 35 mV Temperature Coefficient 3.3 15 ppm FS/°C

VCLAMP

Input Bias Current TA = 25°C, VCLAMP = 5 V 200 nA 500 nA Input Voltage Range 1.25 4.94 V

OUTPUT BUFFER STAGE

Buffer Offset 7 15 mV Short-Circuit Current ISC 5 10 mA Output Voltage, Low VOL R Output Voltage, High VOH R

POWER SUPPLY

Supply Current ISY

Power Supply Rejection Ratio PSRR AV = 70 109 125 dB

DYNAMIC PERFORMANCE

Gain Bandwidth Product GBP First Gain Stage, TA = 25°C 2 MHz Second Gain Stage, TA = 25°C 8 MHz Output Buffer Stage 1.5 MHz Output Buffer Slew Rate SR AV = 70, RL = 10 kΩ, C L = 100 pF 1.2 V/µs Settling Time ts To 0.1%, AV = 70, 4 V Output Step 8 µs

NOISE PERFORMANCE

Input Referred Noise TA = 25°C, f = 1 kHz 32 nV/√Hz Low Frequency Noise e

f = 0.1 Hz to 10 Hz 0.5 µV p-p

n p-p

Total Harmonic Distortion THD VIN = 16.75 mV rms, f = 1 kHz, AV = 100 −100 dB

= 25°C 12 16 22 nA

A

= 25°C 0.2 1 nA

A

= 0.9 V to 3.6 V, AV = 1,280 96 112 dB

CM

= 0.2 V to 4.8 V 1000 ppm

O

= 10 kΩ to 5 V 30 mV

L

= 10 kΩ to 0 V 4.94 V

L

= 2.5 V, VPOS = VNEG = 2.5V,

V

O

2.0 2.5 mA

VDAC Code = 128

Rev. 0 | Page 3 of 28

AD8555

Parameter Symbol Conditions Min Typ Max Unit

DIGITAL INTERFACE

Input Current 2 µA DIGIN Pulse Width to Load 0 tw0 T DIGIN Pulse Width to Load 1 tw1 T Time between Pulses at DIGIN tws T DIGIN Low TA = 25°C 1 V DIGIN High TA = 25°C 4 V DIGOUT Logic 0 TA = 25°C 1 V DIGOUT Logic 1 TA = 25°C 4 V

= 25°C 0.05 10 µs

A

= 25°C 50 µs

A

= 25°C 10 µs

A

Rev. 0 | Page 4 of 28

AD8555

At VDD = 2.7 V, VSS = 0.0 V, VCM = 1.35 V, VO = 1.35 V, −40°C ≤ TA ≤ +125°C, unless otherwise specified.

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

INPUT STAGE

Input Offset Voltage VOS 2 10 µV Input Offset Voltage Drift TCVOS 25 60 nV/°C Input Bias Current IB T Input Offset Current IOS T

1.5 nA Input Voltage Range 0.5 1.6 V Common-Mode Rejection Ratio CMRR VCM = 0.9 V to 1.3 V, AV = 70 80 92 dB V Linearity VO = 0.2 V to 3.4 V 20 ppm V Differential Gain Accuracy Second Stage Gain = 17.5 to 100 0.35 % Second Stage Gain = 140 to 200 0.5 % Differential Gain Temperature Coefficient Second Stage Gain = 17.5 to 100 15 ppm/°C Second Stage Gain = 140 to 200 40

RF 14 18 22 kΩ RF Temperature Coefficient 700 ppm/°C

DAC

Accuracy AV = 70, Offset Codes = 8 to 248 0.7 % Ratiometricity AV = 70, Offset Codes = 8 to 248 50 ppm Output Offset AV = 70, Offset Codes = 8 to 248 5 35 mV Temperature Coefficient 3.3 ppm FS/°C

VCLAMP

Input Bias Current TA = 25°C, VCLAMP = 2.7 V 200 nA 500 nA Input Voltage Range 1.25 2.64 V

OUTPUT BUFFER STAGE

Buffer Offset 7 15 mV Short-Circuit Current ISC 4.5 9.5 mA Output Voltage, Low VOL R Output Voltage, High VOH R

POWER SUPPLY

Supply Current ISY

Power Supply Rejection Ratio PSRR AV = 70 109 125 dB

DYNAMIC PERFORMANCE

Gain Bandwidth Product GBP First Gain Stage, TA = 25°C 2 MHz Second Gain Stage, TA = 25°C 8 MHz Output Buffer Stage 1.5 MHz Output Buffer Slew Rate SR AV = 70, RL = 10 kΩ, CL = 100 pF 1.2 V/µs Settling Time ts To 0.1%, AV = 70, 4 V Output Step 8 µs

NOISE PERFORMANCE

Input Referred Noise TA = 25°C, f = 1 kHz 32 nV/√Hz Low Frequency Noise en

f = 0.1 Hz to 10 Hz 0.3 µV p-p

p-p

Total Harmonic Distortion THD VIN = 16.75 mV rms, f = 1 kHz, AV = 100 −100 dB

= 25°C 12 16 nA

A

= 25°C 0.2 1 nA

A

= 0.9 V to 1.3 V, AV = 1,280 96 112 dB

CM

= 0.2 V to 4.8 V 1000 ppm

O

ppm/°C

= 10 kΩ to 5 V 30 mV

L

= 10 kΩ to 0 V 2.64 V

L

= 1.35 V, VPOS = VNEG = 1.35 V,

V

O

2.0 mA

VDAC Code = 128

Rev. 0 | Page 5 of 28

AD8555

Parameter Symbol Conditions Min Typ Max Unit

DIGITAL INTERFACE

Input Current 2 µA DIGIN Pulse Width to Load 0 tw0 T DIGIN Pulse Width to Load 1 tw1 T Time between Pulses at DIGIN tws T

= 25°C 0.05 10 µs

A

= 25°C 50 µs

A

= 25°C 10 µs

A

Rev. 0 | Page 6 of 28

AD8555

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage 6 V Input Voltage VSS − 0.3 V to VDD + 0.3 V Differential Input Voltage1 ±5.0 V Output Short-Circuit

Indefinite

Duration to VSS or VDD Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +125°C Junction Temperature Range −65°C to +150°C Lead Temperature Range

300°C

(Soldering, 10 sec)

Table 4.

Package Type θ

2

θJC Unit

JA

8-Lead SOIC (R) 158 43 °C/W 16-Lead LFCSP (CP) 44 31.5 °C/W

1

Differential input voltage is limited to ±5.0 V or ± the supply voltage, which-

ever is less.

2

θJA is specified for the worst-case conditions, i.e., θJA is specified for device

soldered in circuit board for SOIC and LFCSP packages.

Rev. 0 | Page 7 of 28

AD8555

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VSS

VDD

1

FILT/DIGOUT

DIGIN VNEG

AD8555

2

TOP VIEW

3

(Not to Scale)

4

Figure 2. 8-Lead SOIC (Not Drawn to Scale)

Table 5. Pin Configuration

SOIC LFCSP

Pin No. Mnemonic Pin No. Mnemonic Description

1 VDD N/A N/A Positive Supply Voltage. 2 FILT/DIGOUT 2 FILTDIGOUT

3 DIGIN 4 DIGIN Digital Input. 4 VNEG 6 VNEG Negative Amplifier Input (Inverting Input). 5 VPOS 8 VPOS Positive Amplifier Input (Noninverting Input). 6 VCLAMP 10 VCLAMP Set Clamp Voltage at Output. 7 VOUT 12 VOUT

8 VSS N/A N/A Negative Supply Voltage. N/A N/A 13, 14 DVSS, AVSS Negative Supply Voltage. N/A N/A 15, 16 DVDD, AVDD Positive Supply Voltage. N/A N/A 1, 3, 5, 7, 9, 11 NC Do Not Connect.

8

VOUT

7

VCLAMP

6 5

VPOS

04598-0-049

NC

FILT/DIGOUT

NC

DIGIN

AVDD

161514

1

PIN 1 INDICATOR

2

AD8555

3

TOP VIEW

4

5

NC

NC = NO CONNECT

Figure 3. 16-Lead LFCSP (Not Drawn to Scale)

Unbuffered Amplifier Output In Series with a Resistor RF. Adding a capacitor between FILT and VDD or VSS implements a low-pass filtering function. In read mode, this pin functions as a digital output.

Buffered Amplifier Output. Buffered version of the signal at the FILT/DIGOUT pin. In read mode, VOUT is a buffered digital output.

DVDD

AVSS

678

NC

VNEG

DVSS

13

VPOS

VOUT

12

NC

11

VCLAMP

10

NC

9

04598-0-050

Rev. 0 | Page 8 of 28

AD8555

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5V

40

30

40

35

30

25

VS = 5V

20

NUMBER OF AMPLIFIERS

10

0

VOS (µV)

Figure 4. Input Offset Voltage Distribution

1.0

0.5

0

–0.5

–1.0

–1.5

(µV)

OS

V

–2.0

–2.5

–3.0

–3.5

–4.0

VCM (V)

Figure 5. Input Offset Voltage vs. Common-Mode Voltage

10

8

6

4

2

0

–2

–4

–6

INPUT OFFSET VOLTAGE (µV)

–8

–10

TEMPERATURE (°C)

Figure 6. Input Offset Voltage vs. Temperature

20

15

10

NUMBER OF AMPLIFIERS

5

9–9 –6 –3 3 60

04598-0-005

4.50 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

04598-0-061

150–50 –25 0 25 50 75 100 125

04598-0-062

0

TCVOS (nV/°C)

Figure 7. T

50

45

40

35

30

25

20

15

NUMBER OF AMPLIFIERS

10

5

0

0 12.5 25.0 37.5 50.0 62.5 75.0

Figure 8. T

10.0

7.5

5.0

(mV)

OS

–2.5

BUF V

–5.0

–7.5

–10.0

2.5

0

VOUT = 0.3V

TEMPERATURE (°C)

@ VS = 5 V

CVOS

TCVOS (nV/°C)

@ VS = 2.7 V

CVOS

VOUT = 4.7V

75.050.0 62.537.525.012.50

VS = 5V

04598-0-006

04598-0-007

150–50 –25 0 25 50 75 100 125

04598-0-008

Figure 9. Output Buffer Offset vs. Temperature

Rev. 0 | Page 9 of 28

Analog Devices AD8555 Service Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS