Analog Devices AD8510, AD8512, AD8513 Service Manual

Precision, Very Low Noise, Low Input Bias Current,

A

A

A

O

A

FEATURES

Fast settling time: 500 ns to 0.1%
Low offset voltage: 400 μV maximum
Low TCVOS: 1 μV/°C typical
Low input bias current: 25 pA typical
Dual-supply operation: ±5 V to ±15 V
Low noise: 8 nV/√Hz
Low distortion: 0.0005%
No phase reversal
Unity gain stable

APPLICATIONS

Instrumentation
Multipole filters
Precision current measurement
Photodiode amplifiers
Sensors
Audio

Wide Bandwidth JFET Operational Amplifiers

AD8510/AD8512/AD8513

PIN CONFIGURATIONS

NC

AD8510

–IN

TOP VIEW

+IN

(Not to Scale)

V–

Figure 1. 8-Lead MSOP (RM Suffix) Figure 2. 8-Lead SOIC_N (R Suffix)

–IN A

+IN A

V–

1

AD8512

TOP VIEW

(Not to Scale)

4

OUT

Figure 3. 8-Lead MSOP (RM Suffix) Figure 4. 8-Lead SOIC_N (R Suffix)

1

OUT

–IN A

2

+IN A

3

AD8513

V+

4

TOP VIEW

(Not to Scale)

+IN B

5

–IN B

6

UT B

7

Figure 5. 14-Lead SOIC_N (R Suffix) Figure 6. 14-Lead TSSOP (RU Suffix)

NC

V+

OUT

NC

02729-D-003

8

V+

OUT B

–IN B

+IN B

5

14

OUT D

–IN D

13

+IN D

12

V–

11

+IN C

10

–IN C

9

OUT C

8

02729-D-001

02729-D-005

NC

–IN

+IN

V–

OUT

–IN A

+IN A

OUT

–IN A

+IN A

+IN B

–IN B

OUT B

V–

V+

AD8510

TOP VIEW

(Not to Scale)

AD8512

TOP VIEW

(Not to Scale)

1

AD8513

TOP VIEW

(Not to Scale)

7

NC

V+

OUT

NC

02729-D-004

V+

OUT B

–IN B

+IN B

02729-D-002

14

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

8

02729-D-006

GENERAL DESCRIPTION

The AD8510/AD8512/AD8513 are single-, dual-, and quad­precision JFET amplifiers that feature low offset voltage, input
bias current, input voltage noise, and input current noise.

The combination of low offsets, low noise, and very low input
bias currents makes these amplifiers especially suitable for high
impedance sensor amplification and precise current measurements
using shunts. The combination of dc precision, low noise, and
fast settling time results in superior accuracy in medical
instruments, electronic measurement, and automated test
equipment. Unlike many competitive amplifiers, the AD8510/
AD8512/AD8513 maintain their fast settling performance even
with substantial capacitive loads. Unlike many older JFET
amplifiers, the AD8510/AD8512/AD8513 does not suffer from
output phase reversal when input voltages exceed the maximum
common-mode voltage range.

Fast slew rate and great stability with capacitive loads make the
AD8510/AD8512/AD8513 a perfect fit for high performance
filters. Low input bias currents, low offset, and low noise result
in a wide dynamic range of photodiode amplifier circuits. Low
noise and distortion, high output current, and excellent speed
make the AD8510/AD8512/AD8513 a great choice for audio
applications.

The AD8510/AD8512 are both available in 8-lead narrow SOIC_N
and 8-lead MSOP packages. MSOP packaged parts are only
available in tape and reel. The AD8513 is available in 14-lead
SOIC_N and TSSOP packages.

The AD8510/AD8512/AD8513 are specified over the –40°C to
+125°C extended industrial temperature range.

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD8510/AD8512/AD8513

TABLE OF CONTENTS

Features .............................................................................................. 1

Output Phase Reversal............................................................... 13

Applications....................................................................................... 1

Pin Configurations ........................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 4

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Typical Performance Characteristics ............................................. 7

General Application Information................................................. 13

Input Overvoltage Protection................................................... 13

REVISION HISTORY

6/06—Rev. E to Rev. F

Changes to Figure 23 ....................................................................... 9

Updated Outline Dimensions....................................................... 19

Changes to Ordering Guide.......................................................... 20

6/04—Rev. D to Rev. E

Changes to Format ............................................................. Universal

Changes to Specifications................................................................ 3

Updated Outline Dimensions....................................................... 19

10/03—Rev. C to Rev. D

Added AD8513 Model.......................................................Universal

Changes to Specifications................................................................ 3

Added Figures 36 through 40........................................................ 10

Added new Figures 55 and 57....................................................... 17

Changes to Ordering Guide.......................................................... 20

9/03—Rev. B to Rev. C

Changes to Ordering Guide ........................................................... 4

Updated Figure 2 ............................................................................ 10

Changes to Input Overvoltage Protection Section .................... 10

Changes to Figures 10 and 11 ....................................................... 12

Changes to Photodiode Circuits Section..................................... 13

Changes to Figures 13 and 14 ....................................................... 13

Deleted Precision Current Monitoring Section.......................... 14

Updated Outline Dimensions....................................................... 15

THD + Noise............................................................................... 13

Total Noise Including Source Resistors................................... 13

Settling Time............................................................................... 14

Overload Recovery Time .......................................................... 14

Capacitive Load Drive ............................................................... 14

Open-Loop Gain and Phase Response.................................... 15

Precision Rectifiers..................................................................... 16

I-V Conversion Applications.................................................... 17

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 20

3/03—Rev. A to Rev. B

Updated Figure 5............................................................................ 11

Updated Outline Dimensions....................................................... 15

8/02—Rev. 0 to Rev. A

Added AD8510 Model....................................................... Universal

Added Pin Configurations ...............................................................1

Changes to Specifications.................................................................2

Changes to Ordering Guide.............................................................4

Changes to TPCs 2 and 3..................................................................5

Added new TPCs 10 and 12.............................................................6

Replaced TPC 20 ...............................................................................8

Replaced TPC 27 ...............................................................................9

Changes to General Application Information Section.............. 10

Changes to Figure 5........................................................................ 11

Changes to I-V Conversion Applications Section ..................... 13

Changes to Figures 13 and 14....................................................... 13

Changes to Figure 17...................................................................... 14

Rev. F | Page 2 of 20

AD8510/AD8512/AD8513

SPECIFICATIONS

@ VS = ±5 V, VCM = 0 V, TA = 25°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage (B Grade)

−40°C < TA < +125°C 0.8 mV
Offset Voltage (A Grade) V

−40°C < TA < +125°C 1.8 mV
Input Bias Current I

−40°C < TA < +85°C 0.7 nA

−40°C < TA < +125°C 7.5 nA
Input Offset Current I

−40°C < TA < +85°C 0.3 nA

−40°C < TA < +125°C 0.5 nA
Input Capacitance

Differential 12.5 pF

Common-Mode 11.5 pF
Input Voltage Range −2.0 +2.5 V
Common-Mode Rejection Ratio CMRR VCM = −2.0 V to +2.5 V 86 100 dB
Large Signal Voltage Gain A
Offset Voltage Drift (B Grade)1 ΔVOS/ΔT 0.9 5 μV/°C
Offset Voltage Drift (A Grade) ΔVOS/ΔT 1.7 12 μV/°C

OUTPUT CHARACTERISTICS

Output Voltage High VOH RL = 10 kΩ +4.1 +4.3 V
Output Voltage Low VOL −40°C < TA < +125°C −4.9 −4.7 V
Output Voltage High VOH RL = 2 kΩ +3.9 +4.2 V
Output Voltage Low VOL −40°C < TA < +125°C −4.9 −4.5 V
Output Voltage High VOH RL = 600 Ω +3.7 +4.1 V
Output Voltage Low VOL −40°C < TA < +125°C −4.8 −4.2 V
Output Current I

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V 86 130 dB
Supply Current/Amplifier I

AD8510/AD8512/AD8513 VO = 0 V 2.0 2.3 mA

AD8510/AD8512 −40°C < TA < +125°C 2.5 mA

AD8513 −40°C < TA < +125°C 2.75 mA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 2 kΩ 20 V/μs
Gain Bandwidth Product GBP 8 MHz
Settling Time tS To 0.1%, 0 V to 4 V step, G = +1 0.4 μs
THD + Noise THD + N 1 kHz, G = +1, RL = 2 kΩ 0.0005 %
Phase Margin Φ

NOISE PERFORMANCE

Voltage Noise Density en f = 10 Hz 34 nV/√Hz

f = 100 Hz 12 nV/√Hz
f = 1 kHz 8.0 10 nV/√Hz
f = 10 kHz 7.6 nV/√Hz

Peak-to-Peak Voltage Noise en p-p 0.1 Hz to 10 Hz bandwidth 2.4 5.2 μV p-p

1

AD8510/AD8512 only.

1

V

OS

OS

B

OS

VO

OUT

SY

0.08 0.4 mV

0.1 0.9 mV

21 75 pA

5 50 pA

RL = 2 kΩ, VO = −3 V to +3 V 65 107 V/mV

±40 ±54 mA

O

44.5 Degrees

Rev. F | Page 3 of 20

AD8510/AD8512/AD8513

ELECTRICAL CHARACTERISTICS

@ VS = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage (B Grade)1 VOS 0.08 0.4 mV

−40°C < TA < +125°C 0.8 mV

Offset Voltage (A Grade) VOS 0.1 1.0 mV

−40°C < TA < +125°C 1.8 mV
Input Bias Current IB 25 80 pA

−40°C < TA < +85°C 0.7 nA

−40°C < TA < +125°C 10 nA
Input Offset Current I

OS

−40°C < TA < +85°C 0.3 nA

−40°C < TA < +125°C 0.5 nA
Input Capacitance

Differential 12.5 pF

Common-Mode 11.5 pF
Input Voltage Range −13.5 +13.0 V
Common-Mode Rejection Ratio CMRR VCM = −12.5 V to +12.5 V 86 108 dB
Large Signal Voltage Gain AVO VO = −13.5 V to +13.5 V 115 196 V/mV

R

Offset Voltage Drift (B Grade)1 ΔVOS/ΔT 1.0 5 μV/°C
Offset Voltage Drift (A Grade) ΔVOS/ΔT 1.7 12 μV/°C

OUTPUT CHARACTERISTICS

Output Voltage High VOH RL = 10 kΩ +14.0 +14.2 V
Output Voltage Low VOL −40°C < TA < +125°C −14.9 −14.6 V
Output Voltage High VOH RL = 2 kΩ +13.8 +14.1 V
Output Voltage Low VOL −40°C < TA < +125°C –14.8 −14.5 V
Output Voltage High VOH RL = 600 Ω, TA = 25°C +13.5 +13.9 V

−40°C < TA < +125°C +11.4 V
Output Voltage Low VOL RL = 600 Ω, TA = 25°C −14.3 −13.8 V

−40°C < TA < +125°C −12.1 V
Output Current I

±70 mA

OUT

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V 86 dB
Supply Current/Amplifier ISY

AD8510/AD8512/AD8513 VO = 0 V 2.2 2.5 mA
AD8510/AD8512 −40°C < TA < +125°C 2.6 mA
AD8513 −40°C < TA < +125°C 3.0 mA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 2 kΩ 20 V/μs
Gain Bandwidth Product GBP 8 MHz
Settling Time t

S

To 0.01%, 0 V to 10 V step, G = +1 0.9 μs

THD + Noise THD + N 1 kHz, G = +1, RL = 2 kΩ 0.0005 %
Phase Margin ΦO 52 Degrees

6 75 pA

= 2 kΩ, VCM = 0 V

L

To 0.1%, 0 V to 10 V step, G = +1 0.5 μs

Rev. F | Page 4 of 20

AD8510/AD8512/AD8513

Parameter Symbol Conditions Min Typ Max Unit

NOISE PERFORMANCE

Voltage Noise Density en f = 10 Hz 34 nV/√Hz
f = 100 Hz 12 nV/√Hz
f = 1 kHz 8.0 10 nV/√Hz
f = 10 kHz 7.6 nV/√Hz

Peak-to-Peak Voltage Noise en p-p 0.1 Hz to 10 Hz bandwidth 2.4 5.2 μV p-p

1

AD8510/AD8512 only.

Rev. F | Page 5 of 20

AD8510/AD8512/AD8513

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage ±18 V
Input Voltage ±V
Output Short-Circuit Duration to GND

S

Observe
Derating Curves

Storage Temperature Range

R, RM Packages −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range

R, RM Packages −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Electrostatic Discharge (HBM) 2000 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Table 4. Thermal Resistance

Package Type θ

1

JA

θ

Unit

JC

8-Lead MSOP (RM) 210 45 °C/W
8-Lead SOIC_N (R) 158 43 °C/W
14-Lead SOIC_N (R) 120 36 °C/W
14-Lead TSSOP (RU) 180 35 °C/W

1

θJA is specified for worst-case conditions, that is, θJA is specified for device

soldered in circuit board for surface-mount packages.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. F | Page 6 of 20

AD8510/AD8512/AD8513

TYPICAL PERFORMANCE CHARACTERISTICS

120

100

VSY = ±15V

TA = 25°C

100k

10k

VSY = ±5V, ±15V

80

60

40

NUMBER OF AMPLIFIERS

20

0

–0.5

–0.4 –0.3

Figure 7. Input Offset Voltage Distribution

30

25

20

15

10

NUMBER OF AMPLIFIERS

5

0

0

1

Figure 8. AD8510/AD8512 T

30

25

20

–0.2 –0.1 0 0.1

INPUT OFFSET VOLTAGE (mV)

0.2 0.3 0.4

VSY = ±15V
B GRADE

2345 6

TCVOS (μV/

°C)

Distribution

CVOS

VSY = ±15V
A GRADE

0.5

02729-D-007

02729-D-008

1k

100

INPUT BIAS CURRENT (pA)

10

1

–25

–40

–10 5 20 35 50

TEMPERATURE (

Figure 10. Input Bias Current vs. Temperature

1000

100

10

1

INPUT OFFSET CURRENT (pA)

0.1
–40

–10 5 20 35 50

–25

TEMPERATURE (

Figure 11. Input Offset Current vs. Temperature

40

TA = 25

35

30

25

°C

80 95 110 125

65
°C)

±15V

±5V

65 80 95 110 125
°C)

02729-D-010

02729-D-011

15

10

NUMBER OF AMPLIFIERS

5

0

0

1

Figure 9. AD8510/AD8512 T

2345 6

TCVOS (μV/

°C)

Distribution

CVOS

02729-D-009

Rev. F | Page 7 of 20

20

15

10

INPUT BIAS CURRENT (pA)

5

0

8

13

18 23

SUPPLY VOLTAGE (V+ – V– )

Figure 12. Input Bias Current vs. Supply Voltage

28 30

02729-D-012

AD8510/AD8512/AD8513

2.0

TA = 25

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

SUPPLY CURRENT PER AMPLIFIER (mA)

1.1

1.0

°C

8

13

18 23 28 30

SUPPLY VOLTAGE (V+ – V–)

Figure 13. AD8512 Supply Current per Amplifier vs. Supply Voltage

16

14

12

10

8

6

OUTPUT VOLTAGE (V)

4

2

0

0

10

V

OL

V

OH

V

OL

V

=±5V

SY

V

OH

20 30 40 50

LOAD CURRENT (mA)

VSY = ±15

V

60 70 80

Figure 14. AD8510/AD8512 Output Voltage vs. Load Current

2.50

02729-D-013

02729-D-014

2.8

TA = 25

2.6

2.4

2.2

2.0

1.8

1.6

SUPPLY CURRENT (mA)

1.4

1.2

1.0

°C

8

13

18 23 28 33

SUPPLY VOLTAGE (V+ – V–)

Figure 16. AD8510 Supply Current vs. Supply Voltage

70

VSY = ±15

R

= 2.5k

L

C

SCOPE

φ

= 52 DEGREES

M

1M 10M

GAIN (dB)

–10

–20

–30

60

50

40

30

20

10

0

10k

100k

FREQUENCY (Hz)

Figure 17. Open-Loop Gain and Phase vs. Frequency

2.50

V

Ω

= 20pF

50M

315

270

225

180

135

90

45

0

–45

–90

–135

02729-D-016

PHASE (Degrees)

02729-D-017

2.25

2.00

1.75

1.50

1.25

SUPPLY CURRENT AMPLIFIER (mA)

1.00
–40

–10

–25 35 50 95 125

±15V

±5V

5 20 65 80 110

TEMPERATURE (

°C)

Figure 15. AD8512 Supply Current per Amplifier vs. Temperature

02729-D-015

Rev. F | Page 8 of 20

2.25

2.00

1.75

1.50

1.25

SUPPLY CURRENT AMPLIFIER (mA)

1.00
–40

–10

–25 35 50 95 125

5 20 65 80 110

TEMPERATURE (

±15V

°C)

Figure 18. AD8510 Supply Current vs. Temperature

±5V

02729-D-018

AD8510/AD8512/AD8513

70

60

50

40

AV = 100

30

20

AV = 10

10

0

CLOSED-LOOP GAIN (dB)

AV = 1

–10

–20

–30

1k

10k

100k

FREQUENCY (Hz)

VSY = ±15V, ±5V

1M 10M

02729-D-019

50M

Figure 19. Closed-Loop Gain vs. Frequency

120

VSY = ±15V

100

300

270

240

)

Ω

210

180

150

120

90

OUTPUT IMPEDANCE (

60

30

0

100

1k

AV = 100

AV = 10

10k 10M

100k

FREQUENCY (Hz)

1M

VSY = ±15V

= 50mV

V

IN

AV = 1

100M

02729-D-022

Figure 22. Output Impedance vs. Frequency

1k

VSY = ±5V TO ±15V

80

60

CMRR (dB)

40

20

0

100

120

100

80

60

40

PSRR (dB)

20

0

–20

100

10k 10M 100M

1k

100k 1M

FREQUENCY (Hz)

Figure 20. CMRR vs. Frequency

–PSRR

+PSRR

1k

100k 1M

10k 10M

FREQUENCY (Hz)

Figure 21. PSRR vs. Frequency

VSY = ±5V, ±15V

100M

02729-D-020

02729-D-021

100

10

VOLTAGE NOISE DENSI TY (nV/ √Hz)

1

1 10 100 1k

FREQUENCY (Hz)

Figure 23. Voltage Noise Density

VSY = ±15V

VOLTAGE (1μV/DIV)

TIME (1s/DIV)

Figure 24. 0.1 Hz to 10 Hz Input Voltage Noise

02729-023

10k

02729-D-024

Rev. F | Page 9 of 20

AD8510/AD8512/AD8513

280

245

210

175

140

105

70

VOLTAGE NOISE DENSITY (nV Hz)

35

0

10

0

30

20 70 90

40

50

FREQUENCY (Hz)

Figure 25. Voltage Noise Density vs. Frequency

VSY = ±15V

= 2kΩ

R

L

= 100pF

C

L

= 1

A

V

VOLTAGE (5V/DIV)

TIME (1μs/DIV)

Figure 26. Large Signal Transient Response

VSY = ±5V TO ±15V

60

02729-D-025

80

100

02729-D-026

90

VSY = ±15

80

70

60

50

40

OVERSHOOT (%)

30

20

10

0

1

V

R

= 2k

Ω

L

+OS

–OS

10

100 1k

CAPACITANCE (pF)

Figure 28. Small Signal Overshoot vs. Load Capacitance

70

60

50

40

30

20

GAIN (dB)

10

0

–10

–20

–30

10k

100k

FREQUENCY (Hz)

VSY =±5

= 2.5k

R

L

C

SCOPE

φ

= 44.5 DEGREES

M

1M 10M

Figure 29. Open-Loop Gain and Phase vs. Frequency

V

Ω

= 20pF

50M

10k

315

270

225

180

135

90

45

0

–45

–90

–135

02729-D-028

PHASE (Degrees)

02729-D-029

VSY = ±15V
R

= 2kΩ

L

C

= 100pF

L

A

= 1

V

VOLTAGE (50mV/DIV)

TIME (100ns/DIV)

Figure 27. Small Signal Transient Response

02729-D-027

Rev. F | Page 10 of 20

120

100

80

60

CMRR (dB)

40

20

0

100

1k

100k

10k 10M

FREQUENCY (Hz)

Figure 30. CMRR vs. Frequency

1M

VSY =±5V

100M

02729-D-030

AD8510/AD8512/AD8513

300

270

240

)

Ω

210

180

150

120

90

OUTPUT IMPEDANCE (

60

30

0

100

1k

AV= 100

AV= 10

10k 10M

100k 1M

FREQUENCY (Hz)

Figure 31. Output Impedance vs. Frequency

VSY =±5V

V/DIV)

μ

VOLTAGE (1

TIME (1s/DIV)

Figure 32. 0.1 Hz to 10 Hz Input Voltage Noise

VSY = ±5V
R

= 2k

Ω

L

CL = 100pF
A

= 1

V

VOLTAGE (2V/DIV)

TIME (1μs/DIV)

Figure 33. Large Signal Transient Response

VSY =±5

V

= 50mV

IN

AV= 1

V

100M

02729-D-031

02729-D-032

02729-D-033

VSY = ±5V
R

= 2kΩ

L

C

= 100pF

L

A

= 1

V

VOLTAGE (50mV/DIV)

TIME (100ns/DIV)

Figure 34. Small Signal Transient Response

100

90

80

70

60

50

40

OVERSHOOT (%)

30

20

10

0

1

10

+OS

–OS

100 1k

CAPACITANCE (pF)

Figure 35. Small Signal Overshoot vs. Load Capacitance

NUMBER OF AMPLI FIERS

100

90

80

70

60

50

40

30

20

10

0

0

1

Figure 36. AD8513 T

34

25

TCVOS (µV/°C)

Distribution

CVOS

VS = ±15V

VSY =±5V

= 2k

Ω

R

L

10k

6

02729-D-034

02729-D-035

02729-036

Rev. F | Page 11 of 20

AD8510/AD8512/AD8513

120

VS = ±5V

100

80

16

14

12

10

V

OL

V

OH

VSY = ±15V

60

40

NUMBER OF AMPL IFIERS

20

0

0

1

Figure 37. AD8513 T

34

25

TCVOS (µV/°C)

Distribution

CVOS

2.5
TA= 25°C

2.4

2.3

2.2

2.1

2.0

1.9

1.8

SUPPLY CURRENT (mA)

1.7

1.6

1.5
8

13

18 33

SUPPLY VOLTAGE (V+ – V–)

23 28

Figure 38. AD8513 Supply Current vs. Supply Voltage

8

6

OUTPUT VOLTAGE (V)

4

2

02729-037

6

0

0

10

V

OL

V

OH

30 40

20 50

LOAD CURRENT (mA)

VSY = ±5V

02729-D-039

60 70 80

Figure 39. AD8513 Output Voltage vs. Load Current

3.0

02729-D-038

2.5

2.0

1.5

1.0

0.5

SUPPLY CURRENT PER AMPLIFIER (mA)

0

–40 –25 –10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

±15V

±5V

02729-D-040

Figure 40. AD8513 Supply Current vs. Temperature

Rev. F | Page 12 of 20

AD8510/AD8512/AD8513

(

GENERAL APPLICATION INFORMATION

DISTORTION (%)

0.01

0.001

VSY = ±5V

= 100k

R

L

BW = 22kHz

Ω

INPUT OVERVOLTAGE PROTECTION

The AD8510/AD8512/AD8513 have internal protective
circuitry that allows voltages as high as 0.7 V beyond the
supplies to be applied at the input of either terminal without
causing damage. For higher input voltages, a series resistor is
necessary to limit the input current. The resistor value can be
determined from the formula

VV

−

IN

S

R

S

mA5≤

With a very low offset current of <0.5 nA up to 125°C, higher
resistor values can be used in series with the inputs. A 5 kΩ
resistor protects the inputs to voltages as high as 25 V beyond
the supplies and adds less than 10 μV to the offset.

OUTPUT PHASE REVERSAL

Phase reversal is a change of polarity in the transfer function of
the amplifier. This can occur when the voltage applied at the
input of an amplifier exceeds the maximum common-mode
voltage.

Phase reversal can cause permanent damage to the device and
can result in system lockups. The AD8510/AD8512/AD8513 do
not exhibit phase reversal when input voltages are beyond the
supplies.

VSY = ±5V

= 1

A

V

= 10k

Ω

R

L

V

OUT

V

IN

VOLTAGE (2V/DIV)

02729-D-057

TIME (20μs/DIV)

Figure 41. No Phase Reversal

THD + NOISE

The AD8510/AD8512/AD8513 have low total harmonic distortion
and excellent gain linearity, making these amplifiers a great
choice for precision circuits with high closed-loop gain and for
audio application circuits.
AD8512/AD8513 have approximately 0.0005% of total distortion
when configured in positive unity gain (the worst case) and
driving a 100 kΩ load.

Figure 42 shows that the AD8510/

0.0001
20 100 1k

Figure 42. THD + N vs. Frequency

FREQUENCY (Hz)

02729-D-056

20k

TOTAL NOISE INCLUDING SOURCE RESISTORS

The low input current noise and input bias current of the
AD8510/AD8512/AD8513 make them the ideal amplifiers for
circuits with substantial input source resistance. Input offset
voltage increases by less than 15 nV per 500 Ω of source
resistance at room temperature. The total noise density of the
circuit is

nn

BWee

2

)

kTRRiee 4

++=

–23

nTOTA L

SS

J/K).

≈ e

.

n

nTOTAL

2

where:

e

is the input voltage noise density of the parts.

n

i

is the input current noise density of the parts.

n

R

is the source resistance at the noninverting terminal.

S

k is Boltzman’s constant (1.38 × 10

T is the ambient temperature in Kelvin (T = 273 + °C).

For RS < 3.9 kΩ, en dominates and e

The current noise of the AD8510/AD8512/AD8513 is so low
that its total density does not become a significant term unless
R

is greater than 165 MΩ, an impractical value for most

S

applications.

The total equivalent rms noise over a specific bandwidth is
expressed as

=

nTOTALnTOTAL

where

BW is the bandwidth in Hertz.

Note that the previous analysis is valid for frequencies larger
than 150 Hz and assumes flat noise above 10 kHz. For lower
frequencies, flicker noise (1/f) must be considered.

Rev. F | Page 13 of 20

AD8510/AD8512/AD8513

2

SETTLING TIME

Settling time is the time it takes the output of the amplifier to
reach and remain within a percentage of its final value after a
pulse is applied at the input. The AD8510/AD8512/AD8513
settle to within 0.01% in less than 900 ns with a step of 0 V to
10 V in unity gain. This makes each of these parts an excellent
choice as a buffer at the output of DACs whose settling time is
typically less than 1 μs.

In addition to their fast settling time and fast slew rate, their low
offset voltage drift and input offset current maintain full accuracy
of 12-bit converters over the entire operating temperature range.

OVERLOAD RECOVERY TIME

Overload recovery, also known as overdrive recovery, is the
time it takes the output of an amplifier to recover from a
saturated condition to its linear region. This recovery time is
particularly important in applications where the amplifier must
amplify small signals in the presence of large transient voltages.

Figure 43 shows the positive overload recovery of the
AD8510/AD8512/AD8513. The output recovers in approximately
200 ns from a saturated condition.

VSY = ±15V

= 200mV

V

IN

= –100

A

V

0V

RL = 10kΩ

–15V

+15V

0V

VOLTAGE

0V

INPUT OUTPUT

–200mV

TIME (2μs/DIV)

Figure 44. Negative Overload Recovery

CAPACITIVE LOAD DRIVE

The AD8510/AD8512/AD8513 are unconditionally stable at all
gains in inverting and noninverting configurations. They are
capable of driving up to 1000 pF of capacitive loads without
oscillation in unity gain, the worst-case configuration.

However, as with most amplifiers, driving larger capacitive
loads in a unity gain configuration can cause excessive
overshoot and ringing or even oscillation. A simple snubber
network reduces the amount of overshoot and ringing
significantly. The advantage of this configuration is that the
output swing of the amplifier is not reduced, because R
outside the feedback loop.

VSY = ±15V
A

= –100

V

R

= 10kΩ

L

S

02729-D-054

is

VOLTAGE

200mV

INPUT OUTPUT

0V

TIME (2μs/DIV)

02729-D-053

Figure 43. Positive Overload Recovery

The negative overdrive recovery time shown in Figure 44 is less
than 200 ns.

In addition to the fast recovery time, the AD8510/AD8512/
AD8513 show excellent symmetry of the positive and negative
recovery times. This is an important feature for transient signal
rectification because the output signal is kept equally undistorted
throughout any given period.

V+

7

AD8510

00mV

6

4

V–

R

S

C

S

V

OUT

C

L

02729-D-055

Figure 45. Snubber Network Configuration

Rev. F | Page 14 of 20

AD8510/AD8512/AD8513

Figure 46 shows a scope photograph of the output of the
AD8510/AD8512/AD8513 in response to a 400 mV pulse. The
circuit is configured in positive unity gain (worst-case) with a
load experience of 500 pF.

VSY = ±15V

= 500pF

C

L

=10kΩ

R

L

VOLTAGE (200mV/DIV)

TIME (1μs/DIV)

02729-D-041

Figure 46. Capacitive Load Drive without Snubber

When the snubber circuit is used, the overshoot is reduced from
55% to less than 3% with the same load capacitance. Ringing is
virtually eliminated, as shown in

VSY = ±15V

=10kΩ

R

L

= 500pF

C

L

=100Ω

R

S

=1nF

C

S

VOLTAGE (200mV/DIV)

Figure 47. Capacitive Load with Snubber Network

Figure 47.

TIME (1μs/DIV)

02729-D-042

Optimum values for RS and CS depend on the load capacitance
and input stray capacitance and are determined empirically.
Tabl e 5 shows a few values that can be used as starting points.

Table 5. Optimum Values for Capacitive Loads

C

RS (Ω) C

LOAD

S

500 pF 100 1 nF
2 nF 70 100 pF
5 nF 60 300 pF

OPEN-LOOP GAIN AND PHASE RESPONSE

In addition to their impressive low noise, low offset voltage, and
offset current, the AD8510/AD8512/AD8513 have excellent
loop gain and phase response even when driving large resistive
and capacitive loads. They were compared to the OPA2132
under the same conditions. With a 2.5 kΩ load at the output,
the AD8510/AD8512/AD8513 have more than 8 MHz of
bandwidth and a phase margin of more than 52°.

The OPA2132, on the other hand, has only 4.5 MHz of band­width and 28° of phase margin under the same test conditions.
Even with a 1 nF capacitive load in parallel with the 2 kΩ load
at the output, the AD8510/AD8512/AD8513 show much better
response than the OPA2132, whose phase margin is degraded to
less than 0, indicating oscillation.

GAIN (dB)

–10

–20

–30

70

60

50

40

30

20

10

0

10k

100k

1M 10M

FREQUENCY (Hz)

VSY = ±15

= 2.5k

R

L

CL = 0

Figure 48. Frequency Response of the AD8510/AD8512/AD8513

GAIN (dB)

–10

–20

–30

70

60

50

40

30

20

10

0

10k

100k

1M 10M

FREQUENCY (Hz)

VSY = ±15

= 2.5k

R

L

CL = 0

Figure 49. Frequency Response of the OPA2132

V

Ω

50M

V

Ω

50M

315

270

225

190

135

90

45

0

–45

–90

–135

315

270

225

190

135

90

45

0

–45

–90

–135

PHASE (Degrees)

02729-D-043

PHASE (Degrees)

02729-D-044

Rev. F | Page 15 of 20

AD8510/AD8512/AD8513

PRECISION RECTIFIERS

Rectifying circuits are used in a multitude of applications. One
of the most popular uses is in the design of regulated power
supplies, where a rectifier circuit is used to convert an input
sinusoid to a unipolar output voltage. There are some potential
problems with amplifiers used in this manner.

When the input voltage (V
magnitude of V

is doubled at the inputs of the op amp. This

IN

voltage can exceed the power supply voltage, which would damage
some amplifiers permanently. The op amp must come out of
saturation when V

is negative. This delays the output signal

IN

because the amplifier requires time to enter its linear region.

The AD8510/AD8512/AD8513 have a very fast overdrive
recovery time, which makes them great choices for the rectification
of transient signals. The symmetry of the positive and negative
recovery times is also important in keeping the output signal
undistorted.

Figure 50 shows the test circuit of the rectifier. The first stage of
the circuit is a half-wave rectifier. When the sine wave applied at
the input is positive, the output follows the input response.
During the negative cycle of the input, the output tries to swing
negative to follow the input, but the power supply restrains it to
zero. In a similar fashion, the second stage is a follower during
the positive cycle of the sine wave and an inverter during the
negative cycle.

10kΩ

V

IN

3V p-p

R1

1kΩ

3

AD8512

2

) is negative, the output is zero. The

IN

1/2

R2

5V

8

1

4

R3

10kΩ

6

AD8512

5

2/2

4

8

7

OUT B
(HALF WAVE)

VOLTAGE (1V/DIV)

TIME (1ms/DIV)

02729-D-046

Figure 51. Half-Wave Rectifier Signal (Out A)

VOLTAGE (1V/DIV)

TIME (1ms/DIV)

02729-D-047

Figure 52. Full-Wave Rectifier Signal (Out B)

5V

OUT A
(HALF WAVE)

02729-D-045

Figure 50. Half-Wave and Full-Wave Rectifier

Rev. F | Page 16 of 20

AD8510/AD8512/AD8513

I-V CONVERSION APPLICATIONS

Photodiode Circuits

Common applications for I-V conversion include photodiode
circuits where the amplifier is used to convert a current emitted
by a diode placed at the positive input terminal into an output
voltage.

The AD8510/AD8512/AD8513’s low input bias current, wide
bandwidth, and low noise make them each an excellent choice
for various photodiode applications, including fax machines,
fiber optic controls, motion sensors, and bar code readers.

The circuit shown in

Figure 53 uses a silicon diode with zero
bias voltage. This is known as a photovoltaic mode; this
configuration limits the overall noise and is suitable for
instrumentation applications.

Cf

R2

V

EE

4

2

AD8510

Rd Ct

Figure 53. Equivalent Preamplifier Photodiode Circuit

3

6

7

V

CC

02729-D-048

A larger signal bandwidth can be attained at the expense of
additional output noise. The total input capacitance (Ct)
consists of the sum of the diode capacitance (typically 3 pF to
4 pF) and the amplifier’s input capacitance (12 pF), which
includes external parasitic capacitance. Ct creates a pole in the
frequency response that can lead to an unstable system. To
ensure stability and optimize the bandwidth of the signal, a
capacitor is placed in the feedback loop of the circuit shown in
Figure 53. It creates a zero and yields a bandwidth whose corner
frequency is 1/(2π(R2Cf)).

The value of R2 can be determined by the ratio

V/I

D

where:

V is the desired output voltage of the op amp.

I

is the diode current.

D

For example, if ID is 100 μA and a 10 V output voltage is desired,
R2 should be 100 kΩ. Rd is a junction resistance that drops
typically by a factor of 2 for every 10°C increase in temperature.
A typical value for Rd is 1000 MΩ. Since Rd >> R2, the circuit
behavior is not impacted by the effect of the junction resistance.
The maximum signal bandwidth is

f

MAX

ft is the unity gain frequency of the amplifier.

where

ft

=

CtR

22π

Using t he previous parameters, Cf ≈ 1 pF, which yields a signal
bandwidth of about 2.6 MHz.

Ct

Cf

=

ftR

22π

where ft is the unity gain frequency of the op amp, and achieves
a phase margin, Φ

, of approximately 45°.

m

A higher phase margin can be obtained by increasing the value
of Cf. Setting Cf to twice the previous value yields approximately

= 65° and a maximally flat frequency response but reduces

Φ

m

the maximum signal bandwidth by 50%.

Rev. F | Page 17 of 20

AD8510/AD8512/AD8513

V

Signal Transmission Applications

One popular signal transmission method uses pulse-width
modulation. High data rates can require a fast comparator
rather than an op amp. However, the need for sharp and
undistorted signals can favor using a linear amplifier.

The AD8510/AD8512/AD8513 make excellent voltage
comparators. In addition to a high slew rate, the AD8510/
AD8512/AD8513 have a very fast saturation recovery time. In
the absence of feedback, the amplifiers are in open-loop mode
(very high gain). In this mode of operation, they spend much of
their time in saturation.

The circuit in

Figure 54 compares two signals of different

frequencies, namely a 100 Hz sine wave and a 1 kHz triangular

Figure 56 shows a scope photograph of the output waveform.

wave.
A pull-up resistor (typically 5 kΩ) can be connected from the
output to V

if the output voltage needs to reach the positive

CC

rail. The trade-off is that power consumption is higher.

+15V

3

7

Figure 54. Pulse-Width Modulator

2

18V p-p

3

V

IN

CROSSTALK = 20 LOG

Figure 55. Crosstalk Test Circuit

6

2

4

V1

–15V

V2

OUT

+V

S

8

1

V

OUT

10V

IN

V

OUT

02729-D-049

20kΩ

7

4

5kΩ5kΩ

–V

S

2.2kΩ

6

5

02729-D-052

VOLTAGE (5V/DIV)

TIME (2ms/DIV)

02729-D-050

Figure 56. Pulse-Width Modulation

Crosstalk

Crosstalk, also known as channel separation, is a measure of
signal feedthrough from one channel to the other on the same
IC. The AD8512/AD8513 have a channel separation better than

−90 dB for frequencies up to 10 kHz and better than −50 dB for
frequencies up to 10 MHz.

Figure 57 shows the typical channel
separation behavior between Amplifier A (driving amplifier),
with respect to Amplifier B, Amplifier C, and Amplifier D.

0

–20

–40

–60

–80

–100

–120

CHANNEL SEPARATION (dB)

–140

–160

100

CH-D

1k

10k

FREQUENCY (Hz)

CH-B

100k

1M

CH-C

02729-D-051

10M

Figure 57. Channel Separation

Rev. F | Page 18 of 20

AD8510/AD8512/AD8513

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARI TY

0.10

CONTROL LING DIMENSI ONS ARE IN MIL LIMET ERS; IN CH DIMENSI ONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDE C STANDARDS MS-012-A A

BSC

6.20 (0. 2440)

5.80 (0. 2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

Figure 58. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

3.20

3.00

2.80

8

5

4

SEATING
PLANE

5.15

4.90

4.65

1.10 MAX

0.23

0.08

8°
0°

3.20

3.00

1

2.80

PIN 1

0.95

0.85

0.75

0.65 BSC

0.15

0.38

0.00

0.22

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 59. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

0.50 (0. 0196)

0.25 (0. 0099)

1.27 (0. 0500)

0.40 (0. 0157)

0.80

0.60

0.40

4.50

4.40

1.05

1.00

0.80

4.30

PIN 1

45°

060506-A

Figure 60. 14-Lead Thin Shrink Small Outline Package [TSSOP]

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARIT Y

0.10

CONTROLL ING DIMENS IONS ARE IN MILLIM ETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED- OFF MIL LIMET ER EQUIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE IN DES IGN.

Figure 61. 14-Lead Standard Small Outline Package [SOIC_N]

5.10

5.00

4.90

14

0.65
BSC

0.15

0.05

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

0.30

0.19

8

6.40

BSC

71

SEATING

PLANE

0.20

1.20

0.09

MAX

COPLANARITY

0.10

8°
0°

(RU-14)

Dimensions shown in millimeters

8.75 (0.3445)

8.55 (0.3366)

BSC

8

7

6.20 (0.2441)

5.80 (0.2283)

1.75 (0.0689)

1.35 (0.0531)

SEATING
PLANE

8°
0°

0.25 (0.0098)

0.17 (0.0067)

14

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-012-AB

Narrow Body (R-14)

Dimensions shown in millimeters and (inches)

0.50 (0.0197)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

0.75

0.60

0.45

45°

060606-A

Rev. F | Page 19 of 20

AD8510/AD8512/AD8513

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD8510ARM-REEL −40°C to +125°C 8-Lead MSOP RM-8 B7A
AD8510ARM-R2 −40°C to +125°C 8-Lead MSOP RM-8 B7A
AD8510ARMZ-REEL
AD8510ARMZ-R2
AD8510AR −40°C to +125°C 8-Lead SOIC_N R-8
AD8510AR-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8510AR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
AD8510ARZ
AD8510ARZ-REEL
AD8510ARZ-REEL7
AD8510BR −40°C to +125°C 8-Lead SOIC_N R-8
AD8510BR-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8510BR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
AD8510BRZ
AD8510BRZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8510BRZ-REEL7
AD8512ARM-REEL −40°C to +125°C 8-Lead MSOP RM-8 B8A
AD8512ARM-R2 −40°C to +125°C 8-Lead MSOP RM-8 B8A
AD8512ARMZ-REEL
AD8512ARMZ-R2
AD8512AR −40°C to +125°C 8-Lead SOIC_N R-8
AD8512AR-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8512AR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
AD8512ARZ
AD8512ARZ-REEL
AD8512ARZ-REEL7
AD8512BR −40°C to +125°C 8-Lead SOIC_N R-8
AD8512BR-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8512BR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
AD8512BRZ
AD8512BRZ-REEL
AD8512BRZ-REEL7
AD8513AR −40°C to +125°C 14-Lead SOIC_N R-14
AD8513AR-REEL −40°C to +125°C 14-Lead SOIC_N R-14
AD8513AR-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14
AD8513ARZ
AD8513ARZ-REEL
AD8513ARZ-REEL7
AD8513ARU −40°C to +125°C 14-Lead TSSOP RU-14
AD8513ARU-REEL −40°C to +125°C 14-Lead TSSOP RU-14
AD8513ARUZ
AD8513ARUZ-REEL

1

Z = Pb-free part, # denotes lead-free product may be top or bottom marked.

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

−40°C to +125°C 8-Lead MSOP RM-8 B7A#

−40°C to +125°C 8-Lead MSOP RM-8 B7A #

−40°C to +125°C 8-Lead SOIC_N R-8

−40°C to +125°C 8-Lead SOIC_N R-8

−40°C to +125°C 8-Lead SOIC_N R-8

−40°C to +125°C 8-Lead SOIC_N R-8

−40°C to +125°C 8-Lead SOIC_N R-8

−40°C to +125°C 8-Lead MSOP RM-8 B8A#

−40°C to +125°C 8-Lead MSOP RM-8 B8A#

−40°C to +125°C 8-Lead SOIC_N R-8

−40°C to +125°C 8-Lead SOIC_N R-8

−40°C to +125°C 8-Lead SOIC_N R-8

−40°C to +125°C 8-Lead SOIC_N R-8

−40°C to +125°C 8-Lead SOIC_N R-8

−40°C to +125°C 8-Lead SOIC_N R-8

−40°C to +125°C 14-Lead SOIC_N R-14

−40°C to +125°C 14-Lead SOIC_N R-14

−40°C to +125°C 14-Lead SOIC_N R-14

−40°C to +125°C 14-Lead TSSOP RU-14

−40°C to +125°C 14-Lead TSSOP RU-14

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02729-0-6/06(F)

Rev. F | Page 20 of 20