ANALOG DEVICES AD8488 Service Manual

Digital X-Ray Analog Front End

AD8488

Rev. A

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CHARGE CONVERS ION AMPLIFIER

128 CHANNELS

LPF

INT

IN0:127

VREF

TIMING SIGNALS

ANALOG

INPUTS

GAINAMPLIFIER

CONTROL REGISTER

PWR

IRST

GRST

HOLD

CSB_a, CSB_b

CF1SEL0, CF1SEL1

GNSEL0 TO GNSEL3

FSEL0, FSEL1

TST0 TO TST6

WRB

TST

CK_ENa

CLK

CK_ENb

RSTB

MUX SELECTOR

TIMINGAND CONTROL

CONTROL SIGNALS

2 4 2 7

DIFFERENTIAL

OUTPUT

MULTIPLEXER

128:1

OUTPUT
BUFFER

OUTHI

OUTLO

128

7

09801-001

INT

Data Sheet

FEATURES

128 integrator channels
Correlated double sample error correction (CDS)

Corrects for V

Power consumption per channel

Normal: 11 mW

Low power: 4 mW
Low input leakage current: −1.5 pA typical
Low input referred noise (QNI): 993 e
Linearity error: 0.03% typical
Compact 17 mm × 17 mm BGA
Selectable filter time constants
4 selectable input charge ranges
10 selectable gain ranges

APPLICATION

High performance digital X-ray systems
Medical X-ray
Security (baggage scanner) systems

and LF noise

OS

−

rms typical

GENERAL DESCRIPTION

The AD8488 is a 128-channel, analog front end (AFE) designed for
use in high performance digital X-ray systems. The analog channels
consist of an integrator followed by a gain selectable single-ended
to low impedance differential output. The analog channel converts
the charge acquired by X-ray or photodiode detectors to a voltage.
The channels are composed of CMOS transistors, using typical
high input impedance CMOS gates. The integrators generate charge
dependent voltages using a range of selectable capacitance values that
accommodate a broad range of input charge values. The integrators
are followed by single-ended input to differential output voltage
amplifiers where offset and low frequency noise voltages are
subtracted from the input voltages. A 128:1 channel differential
MUX follows the buffers and drives the analog output buffer.
Switch drivers and certain digital timing functions are included, and
all are mounted on a 255-lead BGA substrate. Charge conversion
for all 128 channels is simultaneous followed by a sequential voltage
output read of the channels using a 7-bit address code. The sequence
occurs twice, sampling all 128 channels. Logic control inputs,

CS_B

and

, select the lower and upper 64 blocks of the channel

addresses.

The AD8488 is packaged in a 17 mm × 17 mm, 255-lead, RoHS­compliant ball grid array (BGA). The operating temperature range
is 0°C to 85°C ambient.

FUNCTIONAL BLOCK DIAGRAM

128-Channel

CS_A

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No

Figure 1.

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AD8488 Data Sheet

TABLE OF CONTENTS

Features ...................................................................................................1

Application .............................................................................................1

General Description ..............................................................................1

Functional Block Diagram ...................................................................1

Table of Contents ...................................................................................2

Revision History ....................................................................................2

Specifications ..........................................................................................3

Absolute Maximum Ratings .................................................................5

Thermal Data .....................................................................................5

Thermal Characterization ................................................................5

ESD Caution .......................................................................................5

Pin Configuration and Function Descriptions ..................................6

Signal Mnemonics .................................................................................9

REVISION HISTORY

6/12—Revision A: Initial Version

Typical Performance Characteristics ................................................ 11

Theory of Operation ........................................................................... 13

Overview .......................................................................................... 13

Analog Amplifier ........................................................................ 13

Troubleshooting Channels ......................................................... 13

Timing Signals ................................................................................. 14

Timing Notes ............................................................................... 14

Applications Information ................................................................... 15

Control Register Bit Maps .............................................................. 15

Timing Diagrams ............................................................................ 17

Outline Dimensions ............................................................................ 18

Ordering Guide ............................................................................... 18

Rev. A| Page 2 of 20

Data Sheet AD8488

INPUT LEAKAGE CURRENT

−10

−1.5

+10

pA/channel

G = 4

3.92 4 4.08

V/V

Power Consumption

Normal

Pin PWR logic low

11 mW/channel

SPECIFICATIONS

Default test conditions, unless otherwise specified: VDD = 5 V, VCC = 5 V, LPF resistor (R1) = 130 kΩ, base panel temperature = 30°C, Pin PWR = logic
low, G = 1 V/ V, C

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

CHARGE CONVERSION RATE1 See Figure 16
CF1 = 0.45 pF 1.7 2.3 2.9 V/pC
CF1 = 0.9 pF 0.85 1.1 1.4 V/pC
CF1 = 3.5 pF 0.21 0.28 0.36 V/pC
CF1 = 7 pF 0.10 0.14 0.18 V/pC
GAIN CHARACTERISTICS

Accuracy2

CF1 = 7 pF G = 1 0.98 1 1.02 V/V
G = 2 1.96 2 2.04 V/V

G = 3 2.94 3 3.06 V/V

G = 5 4.9 5 5.1 V/V
G = 6 5.88 6 6.12 V/V
G = 7 6.86 7 7.14 V/V
G = 8 7.84 8 8.16 V/V
G = 9 8.82 9 9.18 V/V
G = 10 9.8 10 10.2 V/V

Gain Step Linear to 7 pC input charge 1 V/V

Error vs. Temperature3 0.003 %/°C
MAXIMUM INPUT CHARGE
CF1 = 0.45 pF 0.45 pC
CF1 = 0.9 pF 0.9 pC
CF1 = 3.5 pF 3.5 pC
CF1 = 7 pF 7 pC
CLOCK

Frequency 1 15 MHz
Rise and Fall Time 6 ns

LOGIC INTERFACE

Input High 3.25 V
Input Low 1.15 V
Leakage Current 14.5e−6 1 µA

POWER SUPPLY

Analog Supply

Voltage (AVDD) 4.75 5 5.25 V
Quiescent Current (AIDD) Pin PWR logic low 230 285 350 mA
Current in Low Power Mode Pin PWR logic high 65 90 100 mA

= 0.5 pF, and C

H

PAN EL

= 38 pF.

, CF1SELx, FSELx, GNSELx, HOLD, GRST, IRST,

WR
TSTx, CK_ENx, PWR,

CS_A, CS_B

Low Power Pin PWR logic high 4 mW/channel
Digital Supply
Voltage (DVDD) 4.75 5 5.25 V
Quiescent Current (DIDD) 2 10 mA

REFERENCE VOLTAGE

VREF 2.048 V

Rev. A | Page 3 of 20

AD8488 Data Sheet

Parameter Test Conditions/Comments Min Typ Max Unit

OUTPUT VOLTAGE

OUTHIGH 2.0 V
OUTLO W 2.0 V

INPUT REFERRED NOISE4

Normal C
Low Power C

PANEL CAPACITANCE 0 80 pF
LINEARITY ERROR5 CF1 = 0.9 pF, G = 5

Normal 0.03 + 1 % + LSB
Low Power 0.2 + 8.2 % + LSB

OPERATING TEMPERATURE Ambient, normal and low power 0 85 °C

1

Defined as the output voltage divided by the input charge (number of electrons in this case) with the gain amp setting (G = 1). This includes the gain error of the gain amp.

2

Each gain at G = 2, G = 4, G = 8, and G = 10 is calculated as the ratio of each output voltage to that at G = 1. Each measurement corresponds to the selection of each gain

setting capacitor.

3

Gain deviation over temperature.

4

The output noise voltage is measured and converted into the input referred noise electrons.

5

It is defined as the deviation from a best fit line, including the origin. The output voltage is measured with five different input conditions.

CF1 = 0.9 pF, G = 10

= 38 pF 993 e−rms

PAN EL

= 61 pF 2000 e−rms

PAN EL

Rev. A | Page 4 of 20

Data Sheet AD8488

Supply (AVDD, DVDD)

5.5 V

50°C

14.0

0.53

7.7

4.4

°C/W

25°C

21.2

0.15

8.3

4.4

°C/W

50°C

16.2

0.29

8.1

4.4

°C/W

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Voltage

Charge Input IN0 to IN127 −0.3 V to VREF + 0.3 V
Reference (VREF, VREF_ESD) 5.5 V
Logic Inputs −0.3 V to +5.5 V

Maximum Junction Temperature 125°C
Storage Temperature Range −30°C to +150°C
Input Charge to Integrator Channels 20 pC

Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions
above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

THERMAL DATA

ΨJB is the junction-to-board thermal characterization parameter
with a unit of °C/W. The Ψ
and calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as thermal
resistances. Ψ

measures the component power flowing through

JB

multiple thermal paths rather than a single path, as in thermal
resistance, θ

. Therefore, ΨJB thermal paths include convection

JB

from the top of the package as well as radiation from the package,
factors that make Ψ

JB

Maximum junction temperature (T
temperature (T

T

= TB + (PD × ΨJB)

J

) and power dissipation (PD) using the formula

B

Refer to JESD51-8 and JESD51-12 for more detailed information
about Ψ

.

JB

of the package is based on modeling

JB

more useful in real-world applications.

) is calculated from the board

J

THERMAL CHARACTERIZATION

Table 3. Thermal Resistance—Normal Operation (1.4 W)

Airflow Velocity
(m/sec) Ambient θ

0 85°C 18.6 0.20 8.3 4.4 °C/W
50°C 19.7 0.17 8.3 4.4 °C/W
25°C 20.6 0.16 8.3 4.4 °C/W
1 85°C 15.8 0.32 8.2 4.4 °C/W
50°C 16.1 0.30 8.2 4.4 °C/W
25°C 16.4 0.29 8.2 4.4 °C/W
3 85°C 13.8 0.54 7.7 4.4 °C/W

25°C 14.2 0.52 7.7 4.4 °C/W

ΨJT ΨJB θJC Unit

JA

Table 4. Thermal Resistance—Low Power Operation (0.5 W)

Airflow Velocity
(m/sec) Ambient θ

0 85°C 19.0 0.19 8.3 4.4 °C/W
50°C 20.2 0.16 8.3 4.4 °C/W

1 85°C 15.7 0.31 8.1 4.4 °C/W

25°C 16.4 0.28 8.1 4.4 °C/W
3 85°C 13.8 0.54 7.8 4.4 °C/W
50°C 14.1 0.52 7.8 4.4 °C/W
25°C 14.2 0.51 7.8 4.4 °C/W

ΨJT ΨJB θJC Unit

JA

Note that the thermal numbers are simulated per JEDEC JESD51-9
on a 4-layer printed circuit board size = 101.5 mm × 114.5 mm.

ESD CAUTION

Rev. A | Page 5 of 20

AD8488 Data Sheet

A

B

KEY

AVDD

C

D

E

F

G

H

J

K

L

M

N

P

R

T

AGND

DGND

DVDD

I/O

DIG I/O

NC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

TOP VIEW

A1 BALL PAD CO RNE R

NOTE: E 12 AND M 12 ARE NC ON THE BGA BUT

MUST BE CO NNE CTED TO GROUND ON T HE P CB

09801-002

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 2. 255-Ball CSP_BGA Ball Configuration (Top View)

Rev. A | Page 6 of 20