Digital X-Ray Analog Front End
AD8488
Rev. A
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CHARGE CONVERS ION AMPLIFIER
128 CHANNELS
LPF
INT
IN0:127
VREF
TIMING SIGNALS
ANALOG
INPUTS
GAINAMPLIFIER
CONTROL REGISTER
PWR
IRST
GRST
HOLD
CSB_a, CSB_b
CF1SEL0, CF1SEL1
GNSEL0 TO GNSEL3
FSEL0, FSEL1
TST0 TO TST6
WRB
TST
CK_ENa
CLK
CK_ENb
RSTB
MUX SELECTOR
TIMINGAND CONTROL
CONTROL SIGNALS
2 4 2 7
DIFFERENTIAL
OUTPUT
MULTIPLEXER
128:1
OUTPUT
BUFFER
OUTHI
OUTLO
128
7
09801-001
INT
Data Sheet
FEATURES
128 integrator channels
Correlated double sample error correction (CDS)
Corrects for V
Power consumption per channel
Normal: 11 mW
Low power: 4 mW
Low input leakage current: −1.5 pA typical
Low input referred noise (QNI): 993 e
Linearity error: 0.03% typical
Compact 17 mm × 17 mm BGA
Selectable filter time constants
4 selectable input charge ranges
10 selectable gain ranges
APPLICATION
High performance digital X-ray systems
Medical X-ray
Security (baggage scanner) systems
and LF noise
OS
−
rms typical
GENERAL DESCRIPTION
The AD8488 is a 128-channel, analog front end (AFE) designed for
use in high performance digital X-ray systems. The analog channels
consist of an integrator followed by a gain selectable single-ended
to low impedance differential output. The analog channel converts
the charge acquired by X-ray or photodiode detectors to a voltage.
The channels are composed of CMOS transistors, using typical
high input impedance CMOS gates. The integrators generate charge
dependent voltages using a range of selectable capacitance values that
accommodate a broad range of input charge values. The integrators
are followed by single-ended input to differential output voltage
amplifiers where offset and low frequency noise voltages are
subtracted from the input voltages. A 128:1 channel differential
MUX follows the buffers and drives the analog output buffer.
Switch drivers and certain digital timing functions are included, and
all are mounted on a 255-lead BGA substrate. Charge conversion
for all 128 channels is simultaneous followed by a sequential voltage
output read of the channels using a 7-bit address code. The sequence
occurs twice, sampling all 128 channels. Logic control inputs,
CS_B
and
, select the lower and upper 64 blocks of the channel
addresses.
The AD8488 is packaged in a 17 mm × 17 mm, 255-lead, RoHScompliant ball grid array (BGA). The operating temperature range
is 0°C to 85°C ambient.
FUNCTIONAL BLOCK DIAGRAM
128-Channel
CS_A
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
AD8488 Data Sheet
TABLE OF CONTENTS
Features ...................................................................................................1
Application .............................................................................................1
General Description ..............................................................................1
Functional Block Diagram ...................................................................1
Table of Contents ...................................................................................2
Revision History ....................................................................................2
Specifications ..........................................................................................3
Absolute Maximum Ratings .................................................................5
Thermal Data .....................................................................................5
Thermal Characterization ................................................................5
ESD Caution .......................................................................................5
Pin Configuration and Function Descriptions ..................................6
Signal Mnemonics .................................................................................9
REVISION HISTORY
6/12—Revision A: Initial Version
Typical Performance Characteristics ................................................ 11
Theory of Operation ........................................................................... 13
Overview .......................................................................................... 13
Analog Amplifier ........................................................................ 13
Troubleshooting Channels ......................................................... 13
Timing Signals ................................................................................. 14
Timing Notes ............................................................................... 14
Applications Information ................................................................... 15
Control Register Bit Maps .............................................................. 15
Timing Diagrams ............................................................................ 17
Outline Dimensions ............................................................................ 18
Ordering Guide ............................................................................... 18
Rev. A| Page 2 of 20
Data Sheet AD8488
INPUT LEAKAGE CURRENT
−10
−1.5
+10
pA/channel
G = 4
3.92 4 4.08
V/V
Power Consumption
Normal
Pin PWR logic low
11 mW/channel
SPECIFICATIONS
Default test conditions, unless otherwise specified: VDD = 5 V, VCC = 5 V, LPF resistor (R1) = 130 kΩ, base panel temperature = 30°C, Pin PWR = logic
low, G = 1 V/ V, C
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
CHARGE CONVERSION RATE1 See Figure 16
CF1 = 0.45 pF 1.7 2.3 2.9 V/pC
CF1 = 0.9 pF 0.85 1.1 1.4 V/pC
CF1 = 3.5 pF 0.21 0.28 0.36 V/pC
CF1 = 7 pF 0.10 0.14 0.18 V/pC
GAIN CHARACTERISTICS
Accuracy2
CF1 = 7 pF G = 1 0.98 1 1.02 V/V
G = 2 1.96 2 2.04 V/V
G = 3 2.94 3 3.06 V/V
G = 5 4.9 5 5.1 V/V
G = 6 5.88 6 6.12 V/V
G = 7 6.86 7 7.14 V/V
G = 8 7.84 8 8.16 V/V
G = 9 8.82 9 9.18 V/V
G = 10 9.8 10 10.2 V/V
Gain Step Linear to 7 pC input charge 1 V/V
Error vs. Temperature3 0.003 %/°C
MAXIMUM INPUT CHARGE
CF1 = 0.45 pF 0.45 pC
CF1 = 0.9 pF 0.9 pC
CF1 = 3.5 pF 3.5 pC
CF1 = 7 pF 7 pC
CLOCK
Frequency 1 15 MHz
Rise and Fall Time 6 ns
LOGIC INTERFACE
Input High 3.25 V
Input Low 1.15 V
Leakage Current 14.5e−6 1 µA
POWER SUPPLY
Analog Supply
Voltage (AVDD) 4.75 5 5.25 V
Quiescent Current (AIDD) Pin PWR logic low 230 285 350 mA
Current in Low Power Mode Pin PWR logic high 65 90 100 mA
= 0.5 pF, and C
H
PAN EL
= 38 pF.
, CF1SELx, FSELx, GNSELx, HOLD, GRST, IRST,
WR
TSTx, CK_ENx, PWR,
CS_A, CS_B
Low Power Pin PWR logic high 4 mW/channel
Digital Supply
Voltage (DVDD) 4.75 5 5.25 V
Quiescent Current (DIDD) 2 10 mA
REFERENCE VOLTAGE
VREF 2.048 V
Rev. A | Page 3 of 20
AD8488 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
OUTPUT VOLTAGE
OUTHIGH 2.0 V
OUTLO W 2.0 V
INPUT REFERRED NOISE4
Normal C
Low Power C
PANEL CAPACITANCE 0 80 pF
LINEARITY ERROR5 CF1 = 0.9 pF, G = 5
Normal 0.03 + 1 % + LSB
Low Power 0.2 + 8.2 % + LSB
OPERATING TEMPERATURE Ambient, normal and low power 0 85 °C
1
Defined as the output voltage divided by the input charge (number of electrons in this case) with the gain amp setting (G = 1). This includes the gain error of the gain amp.
2
Each gain at G = 2, G = 4, G = 8, and G = 10 is calculated as the ratio of each output voltage to that at G = 1. Each measurement corresponds to the selection of each gain
setting capacitor.
3
Gain deviation over temperature.
4
The output noise voltage is measured and converted into the input referred noise electrons.
5
It is defined as the deviation from a best fit line, including the origin. The output voltage is measured with five different input conditions.
CF1 = 0.9 pF, G = 10
= 38 pF 993 e−rms
PAN EL
= 61 pF 2000 e−rms
PAN EL
Rev. A | Page 4 of 20
Data Sheet AD8488
Supply (AVDD, DVDD)
5.5 V
50°C
14.0
0.53
7.7
4.4
°C/W
25°C
21.2
0.15
8.3
4.4
°C/W
50°C
16.2
0.29
8.1
4.4
°C/W
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Voltage
Charge Input IN0 to IN127 −0.3 V to VREF + 0.3 V
Reference (VREF, VREF_ESD) 5.5 V
Logic Inputs −0.3 V to +5.5 V
Maximum Junction Temperature 125°C
Storage Temperature Range −30°C to +150°C
Input Charge to Integrator Channels 20 pC
Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions
above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
THERMAL DATA
ΨJB is the junction-to-board thermal characterization parameter
with a unit of °C/W. The Ψ
and calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as thermal
resistances. Ψ
measures the component power flowing through
JB
multiple thermal paths rather than a single path, as in thermal
resistance, θ
. Therefore, ΨJB thermal paths include convection
JB
from the top of the package as well as radiation from the package,
factors that make Ψ
JB
Maximum junction temperature (T
temperature (T
T
= TB + (PD × ΨJB)
J
) and power dissipation (PD) using the formula
B
Refer to JESD51-8 and JESD51-12 for more detailed information
about Ψ
.
JB
of the package is based on modeling
JB
more useful in real-world applications.
) is calculated from the board
J
THERMAL CHARACTERIZATION
Table 3. Thermal Resistance—Normal Operation (1.4 W)
Airflow Velocity
(m/sec) Ambient θ
0 85°C 18.6 0.20 8.3 4.4 °C/W
50°C 19.7 0.17 8.3 4.4 °C/W
25°C 20.6 0.16 8.3 4.4 °C/W
1 85°C 15.8 0.32 8.2 4.4 °C/W
50°C 16.1 0.30 8.2 4.4 °C/W
25°C 16.4 0.29 8.2 4.4 °C/W
3 85°C 13.8 0.54 7.7 4.4 °C/W
25°C 14.2 0.52 7.7 4.4 °C/W
ΨJT ΨJB θJC Unit
JA
Table 4. Thermal Resistance—Low Power Operation (0.5 W)
Airflow Velocity
(m/sec) Ambient θ
0 85°C 19.0 0.19 8.3 4.4 °C/W
50°C 20.2 0.16 8.3 4.4 °C/W
1 85°C 15.7 0.31 8.1 4.4 °C/W
25°C 16.4 0.28 8.1 4.4 °C/W
3 85°C 13.8 0.54 7.8 4.4 °C/W
50°C 14.1 0.52 7.8 4.4 °C/W
25°C 14.2 0.51 7.8 4.4 °C/W
ΨJT ΨJB θJC Unit
JA
Note that the thermal numbers are simulated per JEDEC JESD51-9
on a 4-layer printed circuit board size = 101.5 mm × 114.5 mm.
ESD CAUTION
Rev. A | Page 5 of 20
AD8488 Data Sheet
A
B
KEY
AVDD
C
D
E
F
G
H
J
K
L
M
N
P
R
T
AGND
DGND
DVDD
I/O
DIG I/O
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TOP VIEW
A1 BALL PAD CO RNE R
NOTE: E 12 AND M 12 ARE NC ON THE BGA BUT
MUST BE CO NNE CTED TO GROUND ON T HE P CB
09801-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. 255-Ball CSP_BGA Ball Configuration (Top View)
Rev. A | Page 6 of 20
Data Sheet AD8488
KEY
AVDD
AGND
DGND
DVDD
I/O
DIG I/O
NC
A1 BALL PAD CO RNE R
NOTE: E 12 AND M 12 ARE NC ON THE BGA BUT
MUST BE CO NNE CTED TO GROUND ON T HE P CB
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
BOTTOM VIEW
12345678910111213141516
09801-003
CF1SEL1
Capacitor CF1 (see Table 9).
DGND
F16, G15, G16, H15, H16, J15, J16, K15, K16, L16
O
Digital Ground (0 V).
Table 5. Pin Function Descriptions
Mnemonic Pin No. I/O Description
AGND See Table 6 and Table 7 O Analog Power Ground (0 V).
AVDD F6, F7, F8, F9, F10, G6, G11, H6, H11, H12, J6,
J11, K6, K11, L6, L8, L9, L10, L11
CLK D15 I Clock for Mux Operation.
CK_ENa E14 I Clock Gate for Channel 0 to Channel 63.
CK_ENb F14 I Clock Gate for Channel 64 to Channel 127.
N14 I Logic Level to Enable Channel 0 to Channel 63.
CS_A
M15 I Logic Level to Enable Channel 64 to Channel 127.
CS_B
CF1SEL0,
B15, C15 I Binary Coded Logic Pins to Select One of Four Values of Integrator
DVDD B16, C16, D16, E16, F15, L15, M16, N16, P16, R16 I Power Supply for Digital Circuit (5 V).
FSEL0, FSEL1 R14, T14 I Filter Time Constant Select (see Table 10).
GNSEL0 to
A14, B14, C14, D14 I Gain Select for the Gain Amp. Select one of four hold capacitors. The
GNSEL3
GRST H14 I Gain Amp Reset. Closes the switch across Integrator Capacitor CF2
HOLD T16 I Gain Amp Hold. Connect the hold capacitor to the signal chain.
Figure 3. 255-Ball CSP_BGA Ball Configuration (Bottom View)
I Analog Supply Voltage (5 V).
four values are arranged in one of ten parallel options to establish ten
gain values (see Table 11).
setting the output of the gain amplifier to zero.
Rev. A | Page 7 of 20
AD8488 Data Sheet
A16 I Reset Gray Mode Counter for Mux.
Mnemonic Pin No. I/O Description
IN0 to IN127 See Table 6 and Table 7 I Analog Inputs.
IRST E15 I Integrator Reset. Closes a switch across the integration capacitor, CF1,
to set the output to zero.
NC A13, A15, B13, C13, D13, E10, E12, E13, F11,
F13, G13, H13, J12, J13, K13, L13, M12, M13,
N13, P13, R13, T13
OUTLO W F12 O Inverting Analog Output (Negative) of the Differential Output.
OUTHIGH G12 O Noninverting Analog Output (Positive) of the Differential Output.
PWR P14 I Normal state is logic low; reduces analog bias current by approximately
RST
TST_MODE J14 I Test Mode Enable. This control line is used together with the TST0 to
TST0 to TST6 T15, R15, P15, N15, M14, L14, K14 I Channel Address Select Bits When in Test Mode (see Table 8).
VREF L12 I Reference Input for Analog Circuit (2.048 V).
VREF_ESD K12 I ESD Reference. Connect to VREF (2.048 V).
G14 I Write Digital Instruction Word to the AFE.
WR
No connect. Connect these pins to GND on the PCB.
80% when high.
TST6 address bits to test or debug a system by continuously selecting a
channel.
Rev. A | Page 8 of 20
Data Sheet AD8488
A7
IN110
A11
IN119
B3
IN101
B11
IN120
C7
IN81
C11
IN121
D3
IN89
D7
IN85
D15
CLK
E11
IN122
E15
IRST
F7
AVDD
F15
DVDD
G3
IN71
G11
AVDD
H3
IN65
H15
DGND
J3
IN61
J11
AVDD
J15
DGND
K7
AGND
L3
IN53
L7
AGND
L15
DVDD
M7
AGND
M11
AGND
N3
IN45
N11
IN0
R3
IN27
R7
IN23
R15
TST1
T11
IN2
T15
TST0
SIGNAL MNEMONICS
Table 6. 255-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)
Ball Signal
A2 IN108
A3 IN107
A4 IN106
A5 IN80
A6 IN84
Ball Signal
C14 GNSEL1
C15 CF1SEL0
C16 DVDD
D1 IN91
D2 IN90
Ball Signal
F10 AV DD
F11 NC
F12 OUTLO W
F13 NC
F14 CK_ENb
Ball Signal
J6 AVDD
J7 AGND
J8 AGND
J9 AGND
J10 AGND
Ball Signal
M2 IN50
M3 IN49
M4 IN48
M5 AGND
M6 AGND
Ball Signal
P14 PWR
P15 TST2
P16 DVDD
R1 IN25
R2 IN26
A8 IN111
A9 IN112
A10 IN115
A12 IN124
A13 NC
A14 GNSEL3
A15 NC
A16
B1 IN103
B2 IN102
B4 IN100
B5 IN99
B6 IN98
B7 IN105
B8 IN104
B9 IN113
B10 IN116
B12 IN125
B13 NC
B14 GNSEL2
B15 CF1SEL1
B16 DVDD
C1 IN97
C2 IN96
C3 IN95
C4 IN94
C5 IN93
C6 IN92
C8 IN74
C9 IN114
C10 IN117
C12 IN127
C13 NC
RST
D4 IN88
D5 IN87
D6 IN86
D8 IN83
D9 IN118
D10 IN109
D11 IN123
D12 IN126
D13 NC
D14 GNSEL0
D16 DVDD
E1 IN75
E2 IN69
E3 IN68
E4 IN82
E5 AGND
E6 AGND
E7 AGND
E8 AGND
E9 AGND
E10 NC
E12 NC
E13 NC
E14 CK_ENa
E16 DVDD
F1 IN79
F2 IN78
F3 IN77
F4 IN76
F5 AGND
F6 AVDD
F8 AVDD
F9 AVDD
F16 DGND
G1 IN73
G2 IN72
G4 IN70
G5 AGND
G6 AVDD
G7 AGND
G8 AGND
G9 AGND
G10 AGND
G12 OUTHIGH
G13 NC
G14
G15 DGND
G16 DGND
H1 IN67
H2 IN66
H4 IN64
H5 AGND
H6 AVDD
H7 AGND
H8 AGND
H9 AGND
H10 AGND
H11 AVDD
H12 AVDD
H13 NC
H14 GRST
H16 DGND
J1 IN63
J2 IN62
J4 IN60
J5 AGND
WR
J12 NC
J13 NC
J14 TST_MODE
J16 DGND
K1 IN59
K2 IN58
K3 IN57
K4 IN56
K5 AGND
K6 AVDD
K8 AGND
K9 AGND
K10 AGND
K11 AVD D
K12 VREF_ESD
K13 NC
K14 TST6
K15 DGND
K16 DGND
L1 IN55
L2 IN54
L4 IN52
L5 AGND
L6 AVDD
L8 AVDD
L9 AVDD
L10 AVDD
L11 AVDD
L12 VREF
L13 NC
L14 TST5
L16 DGND
M1 IN47
M8 AGND
M9 AGND
M10 AGND
M12 NC
M13 NC
M14 TST4
M15
CS_B
M16 DVDD
N1 IN41
N2 IN46
N4 IN44
N5 IN43
N6 IN42
N7 IN51
N8 IN32
N9 IN40
N10 IN33
N12 IN9
N13 NC
N14
CS_A
N15 TST3
N16 DVDD
P1 IN31
P2 IN39
P3 IN37
P4 IN38
P5 IN36
P6 IN35
P7 IN34
P8 IN24
P9 IN14
P10 IN12
P11 IN1
P12 IN7
P13 NC
R4 IN28
R5 IN29
R6 IN30
R8 IN22
R9 IN15
R10 IN11
R11 IN5
R12 IN6
R13 NC
R14 FSEL0
R16 DVDD
T1 IN19
T2 IN18
T3 IN17
T4 IN8
T5 IN16
T6 IN20
T7 IN21
T8 IN13
T9 IN10
T10 IN4
T12 IN3
T13 NC
T14 FSEL1
T16 HOLD
Rev. A | Page 9 of 20
AD8488 Data Sheet
CF1SEL0
C15
DGND
G16
DVDD
B16
DVDD
F15
GRST
H14
TST6
K14
Table 7. 255-Ball CSP_BGA Ball Assignment (Alphabetically by Signal)
Signal Ball
AGND E5
AGND E6
AGND E7
AGND E8
AGND E9
AGND F5
AGND G5
AGND G7
AGND G8
AGND G9
AGND G10
AGND H5
AGND H7
AGND H8
AGND H9
AGND H10
AGND J5
AGND J7
AGND J8
AGND J9
AGND J10
AGND K5
AGND K7
AGND K8
AGND K9
AGND K10
AGND L5
AGND L7
AGND M5
AGND M6
AGND M7
AGND M8
AGND M9
AGND M10
AGND M11
AVDD F6
AVDD F7
AVDD F8
AVDD F9
AVDD F10
AVDD G6
AVDD G11
AVDD H6
AVDD H11
Signal Ball
AVDD H12
AVDD J6
AVDD J11
AVDD K6
AVDD K11
AVDD L6
AVDD L8
AVDD L9
AVDD L10
AVDD L11
CLK D15
CK_ENa E14
CK_ENb F14
N14
CS_A
M15
CS_B
CF1SEL1 B15
DGND F16
DGND G15
DGND H15
DGND H16
DGND J15
DGND J16
DGND K15
DGND K16
DGND L16
DVDD C16
DVDD D16
DVDD E16
DVDD L15
DVDD M16
DVDD N16
DVDD P16
DVDD R16
FSEL0 R14
FSEL1 T14
GNSEL0 D14
GNSEL1 C14
GNSEL2 B14
GNSEL3 A14
Signal Ball
HOLD T16
IN0 N11
IN1 P11
IN2 T11
IN3 T12
IN4 T10
IN5 R11
IN6 R12
IN7 P12
IN8 T4
IN9 N12
IN10 T9
IN11 R10
IN12 P10
IN13 T8
IN14 P9
IN15 R9
IN16 T5
IN17 T3
IN18 T2
IN19 T1
IN20 T6
IN21 T7
IN22 R8
IN23 R7
IN24 P8
IN25 R1
IN26 R2
IN27 R3
IN28 R4
IN29 R5
IN30 R6
IN31 P1
IN32 N8
IN33 N10
IN34 P7
IN35 P6
IN36 P5
IN37 P3
IN38 P4
IN39 P2
IN40 N9
IN41 N1
IN42 N6
Signal Ball
IN43 N5
IN44 N4
IN45 N3
IN46 N2
IN47 M1
IN48 M4
IN49 M3
IN50 M2
IN51 N7
IN52 L4
IN53 L3
IN54 L2
IN55 L1
IN56 K4
IN57 K3
IN58 K2
IN59 K1
IN60 J4
IN61 J3
IN62 J2
IN63 J1
IN64 H4
IN65 H3
IN66 H2
IN67 H1
IN68 E3
IN69 E2
IN70 G4
IN71 G3
IN72 G2
IN73 G1
IN74 C8
IN75 E1
IN76 F4
IN77 F3
IN78 F2
IN79 F1
IN80 A5
IN81 C7
IN82 E4
IN83 D8
IN84 A6
IN85 D7
IN86 D6
Signal Ball
IN87 D5
IN88 D4
IN89 D3
IN90 D2
IN91 D1
IN92 C6
IN93 C5
IN94 C4
IN95 C3
IN96 C2
IN97 C1
IN98 B6
IN99 B5
IN100 B4
IN101 B3
IN102 B2
IN103 B1
IN104 B8
IN105 B7
IN106 A4
IN107 A3
IN108 A2
IN109 D10
IN110 A7
IN111 A8
IN112 A9
IN113 B9
IN114 C9
IN115 A10
IN116 B10
IN117 C10
IN118 D9
IN119 A11
IN120 B11
IN121 C11
IN122 E11
IN123 D11
IN124 A12
IN125 B12
IN126 D12
IN127 C12
IRST E15
NC A13
NC A15
Signal Ball
NC B13
NC C13
NC D13
NC E10
NC E12
NC E13
NC F11
NC F13
NC G13
NC H13
NC J12
NC J13
NC K13
NC L13
NC M12
NC M13
NC N13
NC P13
NC R13
NC T13
OUTLO W F12
OUTHIGH G12
PWR P14
A16
RST
TST_MODE J14
TST0 T15
TST1 R15
TST2 P15
TST3 N15
TST4 M14
TST5 L14
VREF L12
VREF_ESD K12
G14
WR
Rev. A | Page 10 of 20
Data Sheet AD8488
0
0.05
CHANNEL NUMBER
100908070605010 403020 130120110
G = 5V/V
CF1 = 0.9pF
T
CASE
= 30°C
C
PANEL
= 38pF
0.04
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
LINEARITY ERROR (%)
09801-004
0
CHANNEL NUMBER
100908070605010 403020 130120110
G = 10
CF1 = 0.9pF
T
CASE
= 40°C
C
PANEL
= 38pF
1100
900
1000
1200
1300
1400
1500
800
INPUT REF E RRE D NOISE – Q NI (e
–
rms)
09801-005
0
CHANNEL NUMBER
100908070605010 403020 130120110
7
2
3
4
5
6
8
9
10
11
12
1
GAIN = 10
GAIN = 2
GAIN = 4
GAIN = 8
GAIN (V/V)
CF1 = 0.9pF
T
CASE
= 30°C
C
PANEL
= 38pF
V
OUT
= –104mV
09801-006
300
0
50
100
150
200
250
350
400
450
500
0
CHANNEL NUMBER
100908070605010 403020 130120110
CCR (nV/e–)
G = 1V/V
T
CASE
= 30°C
C
PANEL
= 38pF
V
OUT
= –104mV
CF1 = 0.45pF
CF1 = 0.9pF
CF1 = 3.5pF
CF1 = 7pF
09801-007
1100
0
850
900
950
1000
1050
1150
1200
1250
1300
800
TEMPERATURE (°C)
605010 403020
TYPICAL NOISE:
AVERAGE OF 128
CHANNELS
INPUT REF E RRE D NOISE [Q NI] (e–rms)
G = 10
CF1 = 0.9pF
C
PANEL
= 38pF
09801-008
0
0.004
CHANNEL NUMBER
100908070605010 403020 130120110
TEMPERATURE
SPAN
GAIN DRIF T (%/°C)
0.003
0.002
0.001
0
–0.001
–0.002
–0.003
–0.004
G = 10V/V
CF1 = 0.9 pF
T
CASE
= 0°C TO 60°C
C
PANEL
= 38pF
V
OUT
= –104mV
0°C TO 20°C
0°C TO 40°C
0°C TO 60°C
09801-009
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. Linearity Error vs. Channel
Figure 7. CCR vs. Channel for Four Values of CF1
Figure 5. Input Referred Noise (QNI) vs. Channel, C
Figure 6. Gain vs. Channel for Four Values of Gain
PANEL
= 38 pF, T
CASE
= 40°C
Rev. A | Page 11 of 20
Figure 8. Input Referred Noise (QNI) vs. Temperature
Figure 9. Gain Drift vs. Channel for Various Temperature Spans
AD8488 Data Sheet
0
0.12
CHANNEL NUMBER
100908070605010 403020 130120110
PERCENTAGE OF OUTPUT STEP (%)
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
G = 5V/V
CF1 = 0.9pF
T
CASE
= 30°C
F
SEL
= 160k
V
IN
= 0 TO –4.16mV
09801-010
0 100908070605010 403020 130120110
1
0
2
3
4
5
–5
CHANNEL NUMBER
–1
–2
–3
–4
ANALOG INPUT LE AKAGE (pA)
G = 10V/V
CF1 = 0.9pF
T
CASE
= 30°C
C
PANEL
= 38pF
09801-011
2
0
–2
0
4
6
8
10
CHANNEL NUMBER
100908070605010 403020 130120110
–10
–8
–6
–4
CF1 = 0.45p F
CF1 = 7.0p F
CF1 = 3.5p F
CF1 = 0.9p F
G = 1V/V
T
CASE
= 30°C
C
PANEL
= 38pF
V
IN
= 0V
V
OS
(mV)
09801-012
0
0.10
CHANNEL NUMBER
100908070605010 403020 130120110
PERCENT OF OUTPUT STEP (%)
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
G = 5V/V
CF1 = 0.9pF
T
CASE
= 30°C
F
SEL
= 160k
V
IN
= 0 TO –4.16mV
09801-013
180
0
140
160
200
220
240
260
T
CASE
(°C)
320
300
280
605010 403020
340
60
80
100
120
IAVDD
NORMAL PO WER
LOW POWER
65
SUPPLY CURRENT (mA)
09801-014
0
TEMPERATURE (°C)
605010 403020
–5.5
G = 10V/V
CF1 = 7 pF
T
CASE
= 30°C
C
PANEL
= 38pF
V
IN
= 0V
DIFFERENTIAL OFFSET VOLTAGE (mV)
–5.6
–5.7
–5.8
–5.9
–6.0
–6.1
–6.2
–6.3
–6.4
–6.5
09801-015
Figure 10. Adjacent Channel Crosstalk as Measured by the Percent of Output
Step for Each Channel
Figure 13. Crosstalk from All Nonadjacent Channels as Measured by the
Percent of Output Step for Each Channel
Figure 11. Input Leakage vs. Channel
Figure 12. Differential Offset Voltage vs. Channel for Four Values of CF1
Figure 14. Supply Current vs. Temperature (T
CASE
)
Figure 15. Differential Offset Voltage vs. Temperature
Rev. A | Page 12 of 20
Data Sheet AD8488
IN0 TO IN127
+
–
+
–
SWIRST
SWHOLD
TO
MUX
VREF
INTEGRATOR
GAIN
AMPLIFIER
CM
SWHOLD
SWGRST
SWGRST
CFx: FEE DBACK CAP ACITOR
C
H
: HOLD CAPACITOR
GNSEL0
TO
GNSEL3
GNSEL0
TO
GNSEL3
R1 (×4)
R1 (×4)
CF1 (×4)
CF2 = 0.5p F
CF2 = 0.5p F
09801-017
CH (×4)
C
H
(×4)
THEORY OF OPERATION
OVERVIEW
The AD8488 is a 128-channel AFE intended for interfacing thin film
transistor (TFT) detector panel arrays in various digital X-ray
applications (see Figure 1). The device includes a 128 dual stage,
charge conversion amplifiers, internal timing, and control circuitry,
a 128:1 differential output multiplexer, and an analog output buffer.
Only the detector panel and a minimal amount of analog circuitry are
required to complete a 128-channel analog X-ray interface. The
AD8488 AFE is packaged in a compact, 17 mm × 17 mm,
255-lead BGA.
Analog Amplifier
The AD8488 analog inputs are suitable for ac or dc connection to
128 X-ray detector panel outputs. The analog amplifier consists of
two stages: an integrator followed by a correlated double sampling
gain amplifier. Figure 16 is a simplified block diagram showing the
basic elements of an analog channel.
The characteristic CMOS high gate impedance of the integrator
minimizes source loading. Prior to sampling a gate line, all 128 mux
analog channels are initialized with
During the 6.1 µs GRST period, the gain amplifier acquires the
reference level (2.048 V) and any low frequency ambient noise.
Just prior to gate sampling, both op amps are unlocked and the
feedback capacitors, CF1 and CF2, are connected. When a TFT gate
line is activated (reference the bottom signal, TFT_GATE, in
Figure 17), the charge of each detector cell is applied simultaneously
RST
, as shown in Figure 17.
to all 128 MOSFET integrator circuits, which begin to ramp over a
12 µs interval. As seen in Figure 16, the op amps are biased at the
reference voltage, plus offset and low frequency noise error voltages.
Together, the resultant differential output voltage comprises the
CDS or correlated double sampled composite. Following the sampling
period, the pixel charges are stored, and the charge is held for the
next 133 clock cycles while the 128 channels are muxed and sampled
sequentially. As the channels are selected in sequence, their outputs
are applied to a dual channel, high precision, current feedback, high
frequency op amp. The AD8488 was designed to drive an ADC such
as the AD9244 differential input high speed converter.
The mux channels are enabled and selected by the timing inputs,
CK_ENa and CK_ENb. These two signals gate the clock and internal
counter that actually selects the mux channel. The multiplexers must
be read sequentially as one interprets from the CK_ENa and CK_ENb
lines in Figure 17. The read time for each channel is 1 clock cycle. The
timing signals, GATED CLKa and GATED CLKb, are developed
internally and are shown in Figure 17 for reference only.
Troubleshooting Channels
Using the TST_MODE enable pin, individual channels are accessible
for troubleshooting. Referring to Ta ble 8 , the channel address follows
two initialization words, 0x01 and 0x02, while the enable pin,
TST_MODE, is asserted high.
Figure 16. Block Diagram of an Integrator Channel
Rev. A | Page 13 of 20
AD8488 Data Sheet
RST
t
DELAY3 (SEE NOTE 3)
t
DELAY3 (SEE NOTE 3)
67 CLKS
t
DELAY2
(SEE NOTE2)
67 CLKS
t
CLK (SEE NOTE 1)
t
DELAY2 (SEE NOTE 2)
NOTES
1. IN THIS EXAMPLE
t
CLK
= 67ns (15MHz) .
2. ¼ CLK <
t
DELAY2
< ½ CLK.
3. 0 CLK <
t
DELAY3
< ¼ CLK.
4.
t
GATE
=
t
GRST
+
t
INT
+
t
READ
= 27µs.
5. ALL LOGIC LEVELS EXCEPT RST ARE ACTIVE HIGH.
6. SHOW N AS ACTIVE HI GH – CHARGE IS TRANSFERRED TO ALL CHANNELS DURI NG THIS INTERVAL .
IRST
GRST
HOLD
CLK
CK_ENa
GATED CL Ka
CK_ENb
GATED CL Kb
TFT_GATE
(SEE NOTE 5)
t
INT
(12µs)
≥6µs
t
CLK (SEE NOTE 1)
≥ 67ns
1 GATE LINE:
t
GATE
(27ms) (WI TH 15MHz CLO CK; S E E NOTE 4)
18.1µs
t
READ
(133 CLKS)
t
IRST
(130 CLKS)
09801-018
t
GRST
≥ 6.1µs
TIMING SIGNALS
Figure 17 is the gate line timing diagram. The gate line sequence
requires 405 clock cycles for channel integration and the sequential
transfer to an ADC. The timing signals, IRST, GRST, and HOLD,
control the integration, gain, and hold switches, respectively, and
define the timing intervals required by each of the integrator
channels. These signals may be generated by an FPGA, ROM,
or similar device.
The balance of the signals shown in Figure 16 are user discretionary
and encoded according to Table 8 through Ta b l e 11 for select gain,
hold capacitor values, low-pass filter values, and mux output channels
for troubleshooting.
Timing Notes
Refer to Figure 17 and the following timing notes:
1. The CLK frequency can range from 1 MHz to 15 MHz.
RST
2.
must be low (active) for the first half clock of the gate
line cycle.
3. t
4. t
must be ≥ 6.1 µs.
GRST
must be ≥ 12 µs.
INT
5. The CK_ENa and CK_ENb intervals must be exactly 67
clocks. The time can be longer if t
6. The t
interval must be exactly 130 CLKs.
IRST
exceeds 67 ns.
CLK
Figure 17. Gate Line Timing Diagram
Rev. A | Page 14 of 20
Data Sheet AD8488
0 0 0 1 1 0 0
5
0 0 1 1 1 1 0
17
0 1 1 0 1 1 1
34
APPLICATIONS INFORMATION
CONTROL REGISTER BIT MAPS
Table 8. Mux Switch Test Register Address Bits, Addresses Valid When TST = High
TST6 TST5 TST4 TST3 TST2 TST1 TST0 Selects Channel
0 0 0 0 0 0 0 None
0 0 0 0 0 0 1 −2
0 0 0 0 0 1 1 −1
0 0 0 0 0 1 0 0
0 0 0 0 1 1 0 1
0 0 0 0 1 1 1 2
0 0 0 0 1 0 1 3
0 0 0 0 1 0 0 4
0 0 0 1 1 0 1 6
0 0 0 1 1 1 1 7
0 0 0 1 1 1 0 8
0 0 0 1 0 1 0 9
0 0 0 1 0 1 1 10
0 0 0 1 0 0 1 11
0 0 0 1 0 0 0 12
0 0 1 1 0 0 0 13
0 0 1 1 0 0 1 14
0 0 1 1 0 1 1 15
0 0 1 1 0 1 0 16
0 0 1 1 1 1 1 18
0 0 1 1 1 0 71 19
0 0 1 1 1 0 0 20
0 0 1 0 1 0 0 21
0 0 1 0 1 0 1 22
0 0 1 0 1 1 1 23
0 0 1 0 1 1 0 24
0 0 1 0 0 1 0 25
0 0 1 0 0 1 1 26
0 0 1 0 0 0 1 27
0 0 1 0 0 0 0 28
0 1 1 0 0 0 0 29
0 1 1 0 0 0 1 30
0 1 1 0 0 1 1 31
0 1 1 0 0 1 0 32
0 1 1 0 1 1 0 33
0 1 1 0 1 0 1 35
0 1 1 0 1 0 0 36
0 1 1 1 1 0 0 37
0 1 1 1 1 0 1 38
0 1 1 1 1 1 1 39
0 1 1 1 1 1 0 40
0 1 1 1 0 1 0 41
0 1 1 1 0 1 1 42
0 1 1 1 0 0 1 43
0 1 1 1 0 0 0 44
0 1 0 1 0 0 0 45
Rev. A | Page 15 of 20
AD8488 Data Sheet
0 1 0 1 1 1 1
50
0 0 0 0 0
0
0 1 0 1 2.5
5
TST6 TST5 TST4 TST3 TST2 TST1 TST0 Selects Channel
0 1 0 1 0 0 1 46
0 1 0 1 0 1 1 47
0 1 0 1 0 1 0 48
0 1 0 1 1 1 0 49
0 1 0 1 1 0 1 51
0 1 0 1 1 0 0 52
0 1 0 0 1 0 0 53
0 1 0 0 1 0 1 54
0 1 0 0 1 1 1 55
0 1 0 0 1 1 0 56
0 1 0 0 0 1 0 57
0 1 0 0 0 1 1 58
0 1 0 0 0 0 1 59
0 1 0 0 0 0 0 60
1 1 0 0 0 0 0 61
1 1 0 0 0 0 1 62
1 1 0 0 0 1 1 63
Table 9. Integrator Capacitor Content (CSEL0 and CSEL1)
CF1SEL1 CF1SEL0 CF1 (pF)
0 0 0.45
0 1 0.9
1 0 3.5
1 1 7.0
Table 10. Low-Pass Filter Time Constant—Resistor Selection Address Bits (FSEL0 and FSEL1)
FSEL1 FSEL0 R1 (kΩ) Time Constant (µs)
0 0 195 1.5
0 1 130 1.0
1 0 65 0.5
1 1 0 0
Table 11. Gain Selection (Gain Amp/GNSEL0 to GNSEL3; CF2 = 0.5 pF)
GNSEL3 (CH3 = 1.5 pF) GNSEL2 (CH2 = 2 pF) GNSEL1 (CH = 1 pF) GNSEL0 (CH = 0.5 pF) Total CH (pF) Gain
0 0 0 1 0.5 1
0 0 1 0 1 2
0 0 1 1 1.5 3
0 1 0 0 2 4
0 1 1 0 3 6
0 1 1 1 3.5 7
1 1 0 1 4 8
1 1 1 0 4.5 9
1 1 1 1 5 10
Rev. A | Page 16 of 20
Data Sheet AD8488
t
1
DATA
WR
t
3
t
2
t
4
t
5
t
6
NOTES
1. TIMING DIAGRAM TO WRITE A STATIC SIGNAL TO CHANNEL 0 TO CHANNEL 63
OR CHANNEL 64 T O CHANNEL127.
2. CS_A LO W OR CS_B LOW SEL E CTS CHANNEL 0 T O
CHANNEL
63 OR
CHANNEL
64
TO
CHANNEL
127.
WRITE DATA BY SEQUENCING WR LOW, THEN HIGH.
09801-019
CS_A, CS_B
CLK
t
CLK
ADC INPUT
001
t
DELAY7
t
DELAY8
SAMPLE
SETTLES
NOTES
1. ADC SAMPL E S OCCUR WHEN MUX- CH001 TO MUX-CH003 IS HIGH, JUST PRIOR TO THE FALLING EDGE.
SAMPLE MUST BE COMPLETE BEFORE HIGH TO LOW TRANSITION.
2. TIME DELAY SAMPLES (REFERENCE, INTERNAL ONLY):
MIN. TYP. MAX.
t
DELAY
7: 5.3ns 6.6ns 7.8ns
t
DELAY
8: 1.2ns 1.4ns 1.7ns
3.
t
A
IS SYNCHRO NOUS WITH ADC TIMING.
ADC SAMPLE
MUX-CH001
ADC SAMPLE
MUX-CH002
ADC SAMPLE
MUX-CH003
002
003
MUX-CH001
TO
MUX-CH003
09801-020
TIMING DIAGRAMS
Figure 18. Input Register Timing Diagram
Figure 19. Timing Diagram—AD8488 to ADC
Rev. A | Page 17 of 20
AD8488 Data Sheet
*
COMPLIANT TO JEDEC
STANDARDS MS-034-AAF-1
WITH EXCEPTION TOPACKAGE
HEIGHT AND THICKNESS.
092409-A
1.00
BSC
1.0
0
REF
A
B
C
D
E
F
G
9
10 8
111213
1
4
7 5
6 4 2
3 1
BOTTOM VIEW
15
.00
BSC SQ
H
J
K
L
M
N
P
0.40 MIN
DETAIL A
TOP VIEW
DETAIL A
COPLANARITY
0.20
0.70
0.6
0
0.50
BALL DIAMETER
SEATING
PLANE
17.20
17.00 SQ
1
6.80
A1 BALL
CORNER
A1 BALL
CORNER
*
2.20
2.00
1.80
*
1.60
1.50
1.40
15
16
R
T
OUTLINE DIMENSIONS
Figure 20. 255-Ball Chip-Scale Package Ball Grid Array [CSP_BGA]
(BC-255-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD8488KBCZ 0°C to +85°C 255-Ball CSP_BGA BC-255-1
1
Z = RoHS Compliant Part.
Rev. A | Page 18 of 20
Data Sheet AD8488
NOTES
Rev. A | Page 19 of 20
AD8488 Data Sheet
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
NOTES
registered trademarks are the property of their respective owners.
D09801-0-6/12(A)
Rev. A | Page 20 of 20
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