ANALOG DEVICES AD844 Service Manual

60 MHz 2000 V/μs

FEATURES

Wide bandwidth

60 MHz at gain of −1

33 MHz at gain of −10
Slew rate: 2000 V/μs
20 MHz full power bandwidth, 20 V p-p, R
Fast settling: 100 ns to 0.1% (10 V step)
Differential gain error: 0.03% at 4.4 MHz
Differential phase error: 0.16° at 4.4 MHz
Low offset voltage: 150 μV maximum (B Grade)
Low quiescent current: 6.5 mA
Available in tape and reel in accordance with

EIA-481-A standard

APPLICATIONS

Flash ADC input amplifiers
High speed current DAC interfaces
Video buffers and cable drivers
Pulse amplifiers

= 500 Ω

L

Monolithic Op Amp

AD844

FUNCTIONAL BLOCK DIAGRAMS

1

NULL

–IN

+IN

–V

Figure 1. 8-Lead PDIP (N) and 8-Lead CERDIP (Q) Packages

OFFSETNULL

Figure 2. 16-Lead SOIC (R) Package

AD844

2

3

4

S

TOP VIEW

(Not to Scale)

NC

1

2

3

–IN

4

NC

5 12

+IN

NC

6 11

AD844

7 10

V–

TOP VIEW

8 9

NC

(Not to Scale)

NC = NO CO NNECT

8

NULL

7

+V

S

OUTPUT

6

TZ

5

16

NC

15

OFFSETNULL

14

V+

13

NC

OUTPUT

TZ

NC

NC

00897-001

00897-002

GENERAL DESCRIPTION

The AD844 is a high speed monolithic operational amplifier
fabricated using the Analog Devices, Inc., junction isolated
complementary bipolar (CB) process. It combines high band­width and very fast large signal response with excellent dc
performance. Although optimized for use in current-to-voltage
applications and as an inverting mode amplifier, it is also suitable
for use in many noninverting applications.

The AD844 can be used in place of traditional op amps, but its
current feedback architecture results in much better ac perfor­mance, high linearity, and an exceptionally clean pulse response.

This type of op amp provides a closed-loop bandwidth that is
determined primarily by the feedback resistor and is almost
independent of the closed-loop gain. The AD844 is free from
the slew rate limitations inherent in traditional op amps and
other current-feedback op amps. Peak output rate of change can
be over 2000 V/μs for a full 20 V output step. Settling time is
typically 100 ns to 0.1%, and essentially independent of gain.
The AD844 can drive 50 Ω loads to ±2.5 V with low distortion
and is short-circuit protected to 80 mA.

The AD844 is available in four performance grades and three
package options. In the 16-lead SOIC (RW) package, the AD844J
is specified for the commercial temperature range of 0°C to 70°C.

The AD844A and AD844B are specified for the industrial
temperature range of −40°C to +85°C and are available in the
CERDIP (Q) package. The AD844A is also available in an 8-lead
PDIP (N). The AD844S is specified over the military temperature
range of −55°C to +125°C. It is available in the 8-lead CERDIP
(Q) package. A and S grade chips and devices processed to
MIL-STD-883B, Rev. C are also available.

PRODUCT HIGHLIGHTS

1. The AD844 is a versatile, low cost component providing an

excellent combination of ac and dc performance.

2. It is essentially free from slew rate limitations. Rise and fall

times are essentially independent of output level.

3. The AD844 can be operated from ±4.5 V to ±18 V power

supplies and is capable of driving loads down to 50 Ω, as
well as driving very large capacitive loads using an external
network.

4. The offset voltage and input bias currents of the AD844 are

laser trimmed to minimize dc errors; V
μV/°C and bias current drift is typically 9 nA/°C.

5. The AD844 exhibits excellent differential gain and

differential phase characteristics, making it suitable for a
variety of video applications with bandwidths up to 60 MHz.

6. The AD844 combines low distortion, low noise, and low

drift with wide bandwidth, making it outstanding as an
input amplifier for flash analog-to-digital converters (ADCs).

drift is typically 1

OS

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©1989–2009 Analog Devices, Inc. All rights reserved.

AD844

TABLE OF CONTENTS

Features .............................................................................................. 1

Response as an Inverting Amplifier ......................................... 12

Applications ....................................................................................... 1 

Functional Block Diagrams ............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

Metallization Photograph ............................................................ 5

ESD Caution .................................................................................. 5

Typical Performance Characteristics ............................................. 6

Inverting Gain-of-1 AC Characteristics .................................... 8

Inverting Gain-of-10 AC Characteristics .................................. 9

Inverting Gain-of-10 Pulse Response ...................................... 10

Noninverting Gain-of-10 AC Characteristics ........................ 11

Understanding the AD844 ............................................................ 12

Response as an I-V Converter .................................................. 13

Circuit Description of the AD844 ............................................ 13

Response as a Noninverting Amplifier .................................... 14

Noninverting Gain of 100 ......................................................... 14

Using the AD844 ............................................................................ 15

Board Layout ............................................................................... 15

Input Impedance ........................................................................ 15

Driving Large Capacitive Loads ............................................... 15

Settling Time ............................................................................... 15

DC Error Calculation ................................................................ 16

Noise ............................................................................................ 16

Video Cable Driver Using ±5 V Supplies ................................ 16

High Speed DAC Buffer ............................................................ 17

20 MHz Variable Gain Amplifier ............................................. 17

Outline Dimensions ....................................................................... 19

Open-Loop Behavior ................................................................. 12

REVISION HISTORY

2/09—Rev. E to Rev F

Updated Format .................................................................. Universal

Changes to Features Section............................................................ 1

Changes to Differential Phase Error Parameter, Table 1 ............. 3

Changes to Figure 13 ........................................................................ 8

Changes to Figure 18 ........................................................................ 9

Changes to Figure 23 and Figure 24 ............................................. 11

Changes to Figure 42 and High Speed DAC Buffer Section ..... 17

Updated Outline Dimensions ....................................................... 19

Changes to Ordering Guide .......................................................... 20

Ordering Guide .......................................................................... 20

1/03 Data Sheet changed from REV. D to REV. E.

Updated Features ............................................................................... 1

Edit to TPC 18 ................................................................................... 7

Edits to Figure 13 and Figure 14 ................................................... 13

Updated Outline Dimensions ....................................................... 15

11/01 Data Sheet changed from REV. C to REV. D.

Edits to Specifications ...................................................................... 2

Edits to Absolute Maximum Ratings .............................................. 3

Edits to Ordering Guide ................................................................... 3

Rev. F | Page 2 of 20

AD844

SPECIFICATIONS

TA = 25°C and VS = ±15 V dc, unless otherwise noted.

Table 1.

AD844J/AD844A AD844B AD844S
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit

INPUT OFFSET VOLTAGE1

T

to T

MIN

75 500

MAX

vs. Temperature

vs. Supply 5 V to 18 V

Initial
T

to T

MIN

MAX

vs. Common Mode VCM = ±10 V

Initial
T

to T

MIN

MAX

INPUT BIAS CURRENT

Negative Input Bias Current1

T

to T

MIN

800 1500

MAX

vs. Temperature

vs. Supply 5 V to 18 V

Initial
T

to T

MIN

MAX

vs. Common Mode VCM = ±10 V

Initial
T

to T

MIN

MAX

Positive Input Bias Current1

T

to T

MIN

350 700

MAX

vs. Temperature

vs. Supply 5 V to 18 V

Initial
T

to T

MIN

MAX

vs. Common Mode VCM = ±10 V

Initial
T

to T

MIN

MAX

INPUT CHARACTERISTICS

Input Resistance

Negative Input
Positive Input 7 10

Input Capacitance

Negative Input
Positive Input

Input Common-Mode Voltage

±10 ±10 ±10 V

Range
INPUT VOLTAGE NOISE f ≥ 1 kHz 2
INPUT CURRENT NOISE

Negative Input f ≥ 1 kHz 10

Positive Input f ≥ 1 kHz 12
OPEN-LOOP TRANSRESISTANCE V
R

T

to T

MIN

1.3 2.0

MAX

= ±10 V

OUT

= 500 Ω 2.2 3.0

L

Transcapacitance 4.5
DIFFERENTIAL GAIN ERROR2 f = 4.4 MHz 0.03
DIFFERENTIAL PHASE ERROR2 f = 4.4 MHz 0.16

50 300

50 150
75 200

1 1 5

4 20

4 10

4 4 10

10 35

10 20

10 10 20

200 450

150 250
750 1100

9 9 15

175 250

175 200

220 220 240

90 160
110
150 400

90 110
110 150
100 200
300 500

3 3 7

80 150

80 100

100 100 120

90 150

90 120

130 130 190

50 65

2
2

Rev. F | Page 3 of 20

7 10 7 10

2
2 2 pF

10
12

2.8 3.0 2.2 3.0 MΩ

1.6 2.0

50 65

2 2 nV/√Hz

4.5

0.03

0.16 0.16 Degree

50 300 V
125 500 V
1 5 V/°C

4 20 V/V
4 20 V/V

10 35 V/V
10 35 V/V

200 450 nA
1900 2500 nA
20 30 nA/°C

175 250 nA/V
220 300 nA/V

90 160 nA/V
120 200 nA/V
100 400 nA
800 1300 nA
7 15 nA/°C

80 150 nA/V
120 200 nA/V

90 150 nA/V
140 200 nA/V

50 65 Ω

MΩ

2 pF

10 pV/√Hz
12 pV/√Hz

1.3 1.6 MΩ

4.5 pF

0.03 %

AD844

AD844J/AD844A AD844B AD844S
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit

FREQUENCY RESPONSE

Small Signal Bandwidth

Gain = −1 60
Gain = −10 33

TOTAL HARMONIC DISTORTION

SETTLING TIME

10 V Output Step ±15 V supplies

Gain = −1, to 0.1%5 100
Gain = −10, to 0.1%6 100

2 V Output Step ±5 V supplies

Gain = −1, to 0.1%
Gain = −10, to 0.1%6 100

OUTPUT SLEW RATE

FULL POWER BANDWIDTH THD = 3%

V

= 20 V p-p

OUT

V

= 2 V p-p

OUT

5

V

5

V

OUTPUT CHARACTERISTICS

Voltage RL = 500 Ω ±10 ±11
Short-Circuit Current 80
T

to T

MIN

60

MAX

Output Resistance Open loop 15

POWER SUPPLY

Operating Range ±4.5 ±18 ±4.5 ±18 ±4.5 ±18 V
Quiescent Current 6.5 7.5
T

to T

MIN

1

Rated performance after a 5 minute warm-up at TA = 25°C.

2

Input signal 285 mV p-p carrier (40 IRE) riding on 0 mV to 642 mV (90 IRE) ramp. RL = 100 Ω; R1, R2 = 300 Ω.

3

For gain = −1, input signal = 0 dBm, CL = 10 pF, RL = 500 Ω, R1 = 500 Ω, and R2 = 500 Ω in . Figure 29

4

For gain = −10, input signal = 0 dBm, CL =10 pF, RL = 500 Ω, R1 = 500 Ω, and R2 = 50 Ω in .

5

CL = 10 pF, RL = 500 Ω, R1 = 1 kΩ, R2 = 1 kΩ in .

6

CL = 10 pF, RL = 500 Ω, R1 = 500 Ω, R2 = 50 Ω in

7.5 8.5

MAX

3, 4

f = 100 kHz,

5

2 V rms

0.005

5

110

Overdriven

1200 2000

110
100
1200 2000

60
33

0.005

100
100

0.005 %

100 ns
100 ns

110 ns
100 ns
1200 2000 V/µs

60 MHz
33 MHz

input

= ±15 V 20

S

= ±5 V 20

S

Figure 29

Figure 29.

20 20 MHz

±10 ±11

Figure 29

20 20 MHz

80
60
15

6.5 7.5

7.5 8.5

±10 ±11
80 mA
60 mA
15 Ω

6.5 7.5 mA

7.5 8.5 mA

V

Rev. F | Page 4 of 20

AD844

–

V

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Ratings

Supply Voltage
Power Dissipation

1

1.1 W

±18 V

Output Short-Circuit Duration Indefinite
Input Common-Mode Voltage

±V

S

Differential Input Voltage 6 V
Inverting Input Current

Continuous 5 mA

Transient 10 mA
Storage Temperature Range (Q)

Storage Temperature Range (N, RW)
Lead Temperature (Soldering, 60 sec)

−65°C to +150°C

−65°C to +125°C
300°C

ESD Rating 1000 V

1

28-lead PDIP package: θJA = 90°C/W.

8-lead CERDIP package: θJA = 110°C/W.
16-lead SOIC package: θJA = 100°C/W.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

METALLIZATION PHOTOGRAPH

Contact factory for latest dimensions.

Dimensions shown in inches and (millimeters).

IN NULL NULL +

0.076
(1.9)

+IN –V

SUBSTRAT E CONNECTED T O +V

Figure 3. Die Photograph

S

0.095
(2.4)

TZ OUTPUT

ESD CAUTION

S

S

00897-003

Rev. F | Page 5 of 20

AD844

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C and VS = ±15 V, unless otherwise noted.

70

20

= 25°C

T

A

60

50

–3dB BANDWIDTH ( MHz)

40

30

SUPPLY VOLTAGE (±V)

Figure 4. −3 dB Bandwidth vs. Supply Voltage, R1 = R2 = 500 Ω

–60

1V rms

–70

–80

–90

–100

–110

SECOND HARMONIC

HARMONIC DISTORTION (dB)

–120

–130

100 1k 10k 100k

INPUT FREQUENCY (Hz)

THIRD HARMONIC

Figure 5. Harmonic Distortion vs. Input Frequency, R1 = R2 = 1 kΩ

5

RL =

∞

4

RL = 500Ω

3

2

R

= 50Ω

TRANSRESISTANCE (MΩ)

1

L

15

10

INPUT VOLTAGE (V)

5

200 5 10 15

00897-004

0

SUPPLY VOLTAGE (±V)

200 5 10 15

00897-007

Figure 7. Noninverting Input Voltage Swing vs. Supply Voltage

20

= 500Ω

R

L

T

= 25°C

A

15

10

OUTPUT VOLTAGE (V)

5

0

00897-005

SUPPLY VOLTAGE (±V)

200 5 10 15

00897-008

Figure 8. Output Voltage Swing vs. Supply Voltage

10

9

8

7

6

SUPPLY CURRENT (mA)

5

VS = ±15V

VS = ±5V

0

–50 0 50 100 150

TEMPERATURE (° C)

Figure 6. Transresistance vs. Temperature

00897-006

Rev. F | Page 6 of 20

4

TEMPERATURE ( -°C)

140–60 –40 –20 0 20 40 60 80 10 0 120

Figure 9. Quiescent Supply Current vs. Temperature and Supply Voltage

00897-009

AD844

2

1

0

–1

INPUT BIAS CURRENT (µA)

–2

–50 0 50 100 150

TEMPERATURE (° C)

I

BP

I

BN

Figure 10. Inverting Input Bias Current (IBN) and Noninverting Input Bias

Current (I

100

10

1

) vs. Temperature

BP

±5V SUPPLIES

40

35

30

25

20

–3dB BANDWIDTH ( MHz)

15

10

00897-010

VS = ±15V

VS = ±5V

TEMPERATURE (-°C)

140–60 –40 –20 0 20 40 60 80 100 120

0897-012

Figure 12. –3 dB Bandwidth vs. Temperature, Gain = −1, R1 = R2 = 1 kΩ

OUTPUT IMPEDANCE (Ω)

0.1

0.01
10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 11. Output Impedance vs. Frequency, Gain = −1, R1 = R2 = 1 kΩ

00897-011

Rev. F | Page 7 of 20

AD844

V

–

INVERTING GAIN-OF-1 AC CHARACTERISTICS

+

0.22µF

S

4.7Ω

R1

5V

100

90

–IN

R2

–

AD844

+

0.22µF

–V

OUTPUT

R

L

4.7Ω

S

C

L

00897-013

Figure 13. Inverting Amplifier, Gain of −1 (R1 = R2)

6

R1 = R2 = 500Ω

0

–6

GAIN (dB)

–12

–18

–24

FREQUENCY (Hz)

R1 = R2 = 1kΩ

100M1M100k 10M

Figure 14. Gain vs. Frequency for Gain = −1, RL = 500 Ω, CL = 0 pF

180

10

0

20ns

0897-016

Figure 16. Large Signal Pulse Response, Gain = −1, R1 = R2 = 1 kΩ

500nV

100

90

10

0

20ns

00897-014

Figure 17. Small Signal Pulse Response, Gain = −1, R1 = R2 = 1 kΩ

0897-017

–210

–240

–270

PHASE (Degrees)

–300

–330

R1 = R2 = 1kΩ

FREQUENCY (MHz )

R1 = R2 = 500Ω

25

Figure 15. Phase vs. Frequency for Gain = −1, RL = 500 Ω, CL = 0 pF

500

00897-015

Rev. F | Page 8 of 20

AD844

V

–

INVERTING GAIN-OF-10 AC CHARACTERISTICS

180

–210

R

= 50Ω

L

RL = 500Ω

0.22µF

+

4.7Ω

500Ω

S

–IN

50Ω

–

AD844

+

0.22µF

–V

OUTPUT

R

L

4.7Ω

S

C

L

00897-018

Figure 18. Gain of −10 Amplifier

26

RL = 500Ω

20

= 50Ω

R

14

L

PHASE (Degrees)

–240

–270

–300

–330

25

FREQUENCY (MHz)

Figure 20. Phase vs. Frequency, Gain = −10

500

00897-020

GAIN (dB)

8

2

–4

FREQUENCY (Hz)

100M1M100k 10M

00897-019

Figure 19. Gain vs. Frequency, Gain = −10

Rev. F | Page 9 of 20

AD844

INVERTING GAIN-OF-10 PULSE RESPONSE

5V

100

90

10

0

20ns

Figure 21. Large Signal Pulse Response, Gain = –10, RL = 500 Ω

500nV

100

90

10

0

0897-021

20ns

0897-022

Figure 22. Small Signal Pulse Response, Gain = −10, RL = 500 Ω

Rev. F | Page 10 of 20

AD844

–

NONINVERTING GAIN-OF-10 AC CHARACTERISTICS

4.7Ω

+V

50Ω

–IN

S

–V

S

–

AD844

+

4.7Ω

0.22µF

450Ω

0.22µF

100

90

OUTPUT

R

L

C

L

10

00897-023

0

2V

100ns

GAIN (dB)

Figure 23. Noninverting Gain of +10 Amplifier

26

20

14

8

2

–4

FREQUENCY (Hz)

Figure 24. Gain vs. Frequency, Gain = +10

180

–210

–240

R

= 50Ω

L

RL = 500Ω

Figure 26. Noninverting Amplifier Large Signal Pulse Response, Gain = +10,

00897-026

= 500 Ω

R

L

200nV 50ns

RL = 500ΩRL = 50Ω

100M1M100k 10M

00897-024

100

90

10

0

Figure 27. Small Signal Pulse Response, Gain = +10, R

= 500 Ω

L

00897-027

–270

PHASE (Degrees)

–300

–330

25

FREQUENCY (MHz)

500

00897-025

Figure 25. Phase vs. Frequency, Gain = +10

Rev. F | Page 11 of 20

AD844

UNDERSTANDING THE AD844

The AD844 can be used in ways similar to a conventional op
amp while providing performance advantages in wideband
applications. However, there are important differences in the
internal structure that need to be understood to optimize the
performance of the AD844 op amp.

OPEN-LOOP BEHAVIOR

Figure 28 shows a current feedback amplifier reduced to essen­tials. Sources of fixed dc errors, such as the inverting node bias
current and the offset voltage, are excluded from this model.
The most important parameter limiting the dc gain is the
transresistance, R
is analogous to the finite open-loop voltage gain in a conven­tional op amp.

, which is ideally infinite. A finite value of Rt

t

RESPONSE AS AN INVERTING AMPLIFIER

Figure 29 shows the connections for an inverting amplifier.
Unlike a conventional amplifier, the transient response and the
small signal bandwidth are determined primarily by the value of
the external feedback resistor, R1, rather than by the ratio of
R1/R2 as is customarily the case in an op amp application. This
is a direct result of the low impedance at the inverting input. As
with conventional op amps, the closed-loop gain is −R1/R2.

The closed-loop transresistance is the parallel sum of R1 and R
Because R1 is generally in the range of 500 Ω to 2 kΩ and R
about 3 MΩ, the closed-loop transresistance is only 0.02% to

0.07% lower than R1. This small error is often less than the
resistor tolerance.

t

is

t

.

The current applied to the inverting input node is replicated by
the current conveyor to flow in Resistor R
across R
gain is the ratio R
R

is buffered by the unity gain voltage follower. Voltage

t

. With typical values of Rt = 3 MΩ and

t/RIN

= 50 Ω, the voltage gain is about 60,000. The open-loop

IN

. The voltage developed

t

current gain, another measure of gain that is determined by the
beta product of the transistors in the voltage follower stage (see
Figure 31), is typically 40,000.

+1

I

IN

R

IN

I

IN

Figure 28. Equivalent Schematic

R

t

C

t

+1

The important parameters defining ac behavior are the
transcapacitance, C

, and the external feedback resistor (not

t

shown). The time constant formed by these components is
analogous to the dominant pole of a conventional op amp and
thus cannot be reduced below a critical value if the closed-loop
system is to be stable. In practice, C

is held to as low a value as

t

possible (typically 4.5 pF) so that the feedback resistor can be
maximized while maintaining a fast response. The finite R

IN

also affects the closed-loop response in some applications.

The open-loop ac gain is also best understood in terms of the
transimpedance rather than as an open-loop voltage gain. The
open-loop pole is formed by R

in parallel with Ct. Because Ct is

t

typically 4.5 pF, the open-loop corner frequency occurs at about
12 kHz. However, this parameter is of little value in determining
the closed-loop response.

When R1 is fairly large (above 5 kΩ) but still much less than R

,

t

the closed-loop HF response is dominated by the time constant
R1 C

. Under such conditions, the AD844 is overdamped and

t

provides only a fraction of its bandwidth potential. Because of
the absence of slew rate limitations under these conditions, the
circuit exhibits a simple single-pole response even under large
signal conditions.

In Figure 29, R3 is used to properly terminate the input if desired.
R3 in parallel with R2 gives the terminated resistance. As R1 is
lowered, the signal bandwidth increases, but the time constant
R1 C

becomes comparable to higher order poles in the closed-

t

loop response. Therefore, the closed-loop response becomes
complex, and the pulse response shows overshoot. When R2

00897-028

is much larger than the input resistance, R
the feedback current in R1 is delivered to this input, but as R2
becomes comparable to R

, less of the feedback is absorbed at

IN

, at Pin 2, most of

IN

Pin 2, resulting in a more heavily damped response. Consequently,
for low values of R2, it is possible to lower R1 without causing
instability in the closed-loop response. Tabl e 3 lists combinations
of R1 and R2 and the resulting frequency response for the circuit
of Figure 29. Figure 16 shows the very clean and fast ±10 V
pulse response of the AD844.

R1

V

IN

OPTIONAL

R2

R3

Figure 29. Inverting Amplifier

AD844

R

L

V

OUT

C

L

0897-029

Rev. F | Page 12 of 20

AD844

K

+

Table 3. Gain vs. Bandwidth

Gain R1 R2 BW (MHz) GBW (MHz)

−1 1 kΩ 1 kΩ 35 35

−1 500 Ω 500 Ω 60 60

−2 2 kΩ 1 kΩ 15 30

−2 1 kΩ 500 Ω 30 60

−5 5 kΩ 1 kΩ 5.2 26

−5 500 Ω 100 Ω 49 245

−10 1 kΩ 100 Ω 23 230

−10 500 Ω 50 Ω 33 330

−20 1 kΩ 50 Ω 21 420

−100 5 kΩ 50 Ω 3.2 320

RESPONSE AS AN I-V CONVERTER

The AD844 works well as the active element in an operational
current-to-voltage converter, used in conjunction with an exter­nal scaling resistor, R1, in Figure 30. This analysis includes the
stray capacitance, C
high speed DAC. Using a conventional op amp, this capacitance
forms a nuisance pole with R1 that destabilizes the closed-loop
response of the system. Most op amps are internally compensated
for the fastest response at unity gain, so the pole due to R1 and
C

reduces the already narrow phase margin of the system. For

S

example, if R1 is 2.5 kΩ, a C
quency of about 4 MHz, well within the response range of even a
medium speed operational amplifier. In a current feedback amp,
this nuisance pole is no longer determined by R1 but by the
input resistance, R
the same 15 pF forms a pole at 212 MHz and causes little
trouble. It can be shown that the response of this system is:

OUT

where:

K is a factor very close to unity and represents the finite dc gain

of the amplifier.

Td is the dominant pole.
Tn is the nuisance pole.

K

=

t

Td = KR1C
Tn = RINCS (assuming RIN << R1)

, of the current source, which may be a

S

of 15 pF places this pole at a fre-

S

. Because this is about 50 Ω for the AD844,

IN

IV++=

sig

R

t

1RR

+

t

R1

()

()

Td

ss

11

Tn

R1

I

SIG

C

S

Figure 30. Current-to-Voltage Converter

AD844

R

L

V

OUT

C

L

0897-030

CIRCUIT DESCRIPTION OF THE AD844

A simplified schematic is shown in Figure 31. The AD844 differs
from a conventional op amp in that the signal inputs have
radically different impedance. The noninverting input (Pin 3)
presents the usual high impedance. The voltage on this input is
transferred to the inverting input (Pin 2) with a low offset voltage,
ensured by the close matching of like polarity transistors operating
under essentially identical bias conditions. Laser trimming nulls
the residual offset voltage, down to a few tens of microvolts. The
inverting input is the common emitter node of a complementary
pair of grounded base stages and behaves as a current summing
node. In an ideal current feedback op amp, the input resistance
is zero. In the AD844, it is about 50 Ω.

A current applied to the inverting input is transferred to a
complementary pair of unity-gain current mirrors that deliver
the same current to an internal node (Pin 5) at which the full
output voltage is generated. The unity-gain complementary
voltage follower then buffers this voltage and provides the load
driving power. This buffer is designed to drive low impedance
loads, such as terminated cables, and can deliver ±50 mA into a
50 Ω load while maintaining low distortion, even when operating
at supply voltages of only ±6 V. Current limiting (not shown)
ensures safe operation under short-circuited conditions.

+V

7

S

I

B

IN OUTPUT

I

B

–IN

TZ

6523

–V

Using typical values of R1 = 1 kΩ and R

= 3 MΩ, K = 0.9997; in

t

other words, the gain error is only 0.03%. This is much less than

Figure 31. Simplified Schematic

4

S

0897-031

the scaling error of virtually all DACs and can be absorbed, if
necessary, by the trim needed in a precise system.

In the AD844, R

is fairly stable with temperature and supply

t

voltages, and consequently the effect of finite gain is negligible
unless high value feedback resistors are used. Because that
results in slower response times than are possible, the relatively
low value of R

in the AD844 is rarely a significant source of error.

t

Rev. F | Page 13 of 20

AD844

V

It is important to understand that the low input impedance at
the inverting input is locally generated and does not depend on
feedback. This is very different from the virtual ground of a
conventional operational amplifier used in the current summing
mode, which is essentially an open circuit until the loop settles.
In the AD844, transient current at the input does not cause
voltage spikes at the summing node while the amplifier is
settling. Furthermore, all of the transient current is delivered
to the slewing (TZ) node (Pin 5) via a short signal path (the
grounded base stages and the wideband current mirrors).

NONINVERTING GAIN OF 100

The AD844 provides very clean pulse response at high
noninverting gains. Figure 32 shows a typical configuration
providing a gain of 100 with high input resistance. The feedback
resistor is kept as low as practicable to maximize bandwidth,
and a peaking capacitor (C
further extend the bandwidth. Figure 33 shows the small signal
response with C

= 3 nF, RL = 500 Ω, and supply voltages of

PK

either ±5 V or ±15 V. Gain bandwidth products of up to
900 MHz can be achieved in this way.

) can optionally be added to

PK

The current available to charge the capacitance (about 4.5 pF) at
the TZ node is always proportional to the input error current,
and the slew rate limitations associated with the large signal
response of the op amps do not occur. For this reason, the rise
and fall times are almost independent of signal level. In practice,
the input current eventually causes the mirrors to saturate.
When using ±15 V supplies, this occurs at about 10 mA (or
±2200 V/μs). Because signal currents are rarely this large,
classical slew rate limitations are absent.

This inherent advantage is lost if the voltage follower used
to buffer the output has slew rate limitations. The AD844 is
designed to avoid this problem, and as a result, the output
buffer exhibits a clean large signal transient response, free
from anomalous effects arising from internal saturation.

RESPONSE AS A NONINVERTING AMPLIFIER

Because current feedback amplifiers are asymmetrical with
regard to their two inputs, performance differs markedly in
noninverting and inverting modes. In noninverting modes, the
large signal high speed behavior of the AD844 deteriorates at
low gains because the biasing circuitry for the input system (not
shown in Figure 31) is not designed to provide high input
voltage slew rates.

However, good results can be obtained with some care. The
noninverting input does not tolerate a large transient input; it
must be kept below ±1 V for best results. Consequently, this
mode is better suited to high gain applications (greater than
×10). Figure 23 shows a noninverting amplifier with a gain of 10
and a bandwidth of 30 MHz. The transient response is shown in
Figure 26 and Figure 27. To increase the bandwidth at higher
gains, a capacitor can be added across R2 whose value is
approximately (R1/R2) × C

.

t

The offset voltage of the AD844 is laser trimmed to the 50 μV
level and exhibits very low drift. In practice, there is an
additional offset term due to the bias current at the inverting
input (I

), which flows in the feedback resistor (R1). This can

BN

optionally be nulled by the trimming potentiometer shown in
Figure 32.

+

S

4.7Ω

OFFSET

TRIM

C

3nF

R2

4.99Ω

PK

20Ω

1

2

8

AD844

V

IN

3

4

4.7Ω

–V

S

Figure 32. Noninverting Amplifier Gain = 100, Optional Offset Trim Is Shown

46

40

34

GAIN (dB)

28

22

7

0.22µF

R1

499Ω

0.22µF

6

VS = ±15V

VS = ±5V

R

L

00897-032

16

100k 1M 20M10M

FREQUENCY (Hz)

00897-040

Figure 33. AC Response for Gain = 100, Configuration Shown in Figure 32

Rev. F | Page 14 of 20

AD844

USING THE AD844

BOARD LAYOUT

As with all high frequency circuits considerable care must be
used in the layout of the components surrounding the AD844.
A ground plane, to which the power supply decoupling capaci­tors are connected by the shortest possible leads, is essential to
achieving clean pulse response. Even a continuous ground plane
exhibits finite voltage drops between points on the plane, and
this must be kept in mind when selecting the grounding points.
In general, decoupling capacitors should be taken to a point
close to the load (or output connector) because the load
currents flow in these capacitors at high frequencies. The +IN
and −IN circuits (for example, a termination resistor and Pin 3)
must be taken to a common point on the ground plane close to
the amplifier package.

Use low impedance 0.22 μF capacitors (AVX SR305C224KAA
or equivalent) wherever ac coupling is required. Include either
ferrite beads and/or a small series resistance (approximately

4.7 Ω) in each supply line.

INPUT IMPEDANCE

At low frequencies, negative feedback keeps the resistance at the
inverting input close to zero. As the frequency increases, the
impedance looking into this input increases from near zero to
the open-loop input resistance, due to bandwidth limitations,
making the input seem inductive. If it is desired to keep the
input impedance flatter, a series RC network can be inserted
across the input. The resistor is chosen so that the parallel sum
of it and R2 equals the desired termination resistance. The capacit­ance is set so that the pole determined by this RC network is
about half the bandwidth of the op amp. This network is not
important if the input resistor is much larger than the termination
used, or if frequencies are relatively low. In some cases, the
small peaking that occurs without the network can be of use in
extending the −3 dB bandwidth.

AD844

Figure 34. Feedforward Network for Large Capacitive Loads

100

90

10

0

Figure 35. Driving 1000 pF C

6

5

750Ω

5V

22pF

500ns

with Feedforward Network of Figure 34

L

SETTLING TIME

Settling time is measured with the circuit of Figure 36. This
circuit employs a false summing node, clamped by the two
Schottky diodes, to create the error signal and limit the input
signal to the oscilloscope. For measuring settling time, the ratio
of R6/R5 is equal to R1/R2. For unity gain, R6 = R5 = 1 kΩ, and

= 500 Ω. For the gain of −10, R5 = 50 Ω, R6 = 500 Ω, and RL

R

L

was not used because the summing network loads the output
with approximately 275 Ω. Using this network in a unity-gain
configuration, settling time is 100 ns to 0.1% for a –5 V to +5 V
step with C

= 10 pF.

L

TO SCOPE
(TEK 7A11 FET PROBE)

V

OUT

C

L

00897-034

00897-035

DRIVING LARGE CAPACITIVE LOADS

Capacitive drive capability is 100 pF without an external net­work. With the addition of the network shown in Figure 34,
the capacitive drive can be extended to over 10,000 pF, limited
by internal power dissipation. With capacitive loads, the output
speed becomes a function of the overdriven output current limit.
Because this is roughly ±100 mA, under these conditions, the
maximum slew rate into a 1000 pF load is ±100 V/μs. Figure 35
shows the transient response of an inverting amplifier (R1 =
R2 = 1 kΩ) using the feedforward network shown in Figure 34,
driving a load of 1000 pF.

Rev. F | Page 15 of 20

R5

D1 D2

V

IN

R3

NOTES

1. D1, D2 IN6263 O R EQUIVALENT SCHOTT KY DIODE.

R2

Figure 36. Settling Time Test Fixture

R6

AD844

R1

V

OUT

R

L

C

L

00897-036

AD844

V

V

DC ERROR CALCULATION

Figure 37 shows a model of the dc error and noise sources for
the AD844. The inverting input bias current, I
feedback resistor. I
in the resistance at Pin 3 (R

, the noninverting input bias current, flows

BP

), and the resulting voltage (plus

P

any offset voltage) appears at the inverting input. The total
error, V

Because I

, at the output is:

O

R1

()

PBP

O

and IBP are unrelated both in sign and magnitude,

BN

OS

⎛

RIVRIV

+++= 1

⎜

R2

⎝

inserting a resistor in series with the noninverting input does
not necessarily reduce dc error and may actually increase it.

V

R2

N

I

NN

I

NP

R

IN

I

BN

I

BP

V

⎞
⎟
⎠

R1

OS

, flows in the

BN

R1I

+

BNINBN

IN

50Ω

HP8753A
NETWORK
ANALYZER

EXT
TRIG
SYNC OUT

HP3314A

STAIRCASE

GENERATOR

0.3

0.2

+5

2.2µF

3

7

6

2

4

2.2µF

–5V

50Ω

300Ω

300Ω

Z

= 50Ω

O

Figure 38. The AD844 as a Cable Driver

OUT

V

V

IN

IN

470Ω

RF IN

OUT

INRF OUT

HP11850C
SPLITTER

OUT

(TERMINATO R)

50Ω

OUT

Figure 39. Differential Gain/Phase Test Setup

IRE = 7.14mV

V

OUT

R

L

50Ω

CIRCUIT

UNDER

TEST

0897-038

V

OUT

0897-039

R

P

AD844

Figure 37. Offset Voltage and Noise Model for the AD844

NOISE

Noise sources can be modeled in a manner similar to the dc bias
currents, but the noise sources are I
induced noise at the output, V

2

()()()

ON

2

VRIV

, INP, VN, and the amplifier

NN

, is:

ON

2

R1

⎛
⎜
⎝

⎞

1 R1I

++=

R2

+

⎟

NNNPNP

⎠

2

Overall noise can be reduced by keeping all resistor values to a
minimum. With typical numbers, R1 = R2 = 1 kΩ, R

= 2 nV/√Hz, INP = 10 pA/√Hz, INN = 12 pA/√Hz, and VON

V

N

= 0 Ω,

P

calculates to 12 nV/√Hz. The current noise is dominant in this
case, because it is in most low gain applications.

VIDEO CABLE DRIVER USING ±5 V SUPPLIES

The AD844 can be used to drive low impedance cables. Using
±5 V supplies, a 100 Ω load can be driven to ±2.5 V with low
distortion. Figure 38 shows an illustrative application that
provides a noninverting gain of +2, allowing the cable to be
reverse-terminated while delivering an overall gain of +1 to the
load. The −3 dB bandwidth of this circuit is typically 30 MHz.
Figure 39 shows a differential gain and phase test setup. In video
applications, differential-phase and differential-gain characteris­tics are often important. Figure 40 shows the variation in phase as
the load voltage varies. Figure 41 shows the gain variation.

0.1

DIFFERENTIAL PHASE (Degrees)

–0.1

–0.2

–0.3

0

36 54 72

V

(IRE)

OUT

90180

00897-040

00897-037

Figure 40. Differential Phase for the Circuit of Figure 38

0.06
IRE = 7.14mV

0.04

0.02

0

–0.02

DIFFERENTIAL GAIN (%)

–0.04

–0.06

018 936 54 72

V

(IRE)

OUT

0

00897-041

Figure 41. Differential Gain for the Circuit of Figure 38

Rev. F | Page 16 of 20

AD844

V

V

1

+15V

MSB

2

3

–15V

4

5

6

DIGITAL

INPUTS

*POWER SUPPLY BYPASS CAPACITORS.

AD568

7

8

9

10

11

LSB

12

TOP VIEW

(Not to Scale)

(VCC)

REFCOM

(VEE)

I

BPO

I

OUT

ACOM

LCOM

SPAN

SPAN

THCOM

V

24

23

22

21

20

19

R

L

18

17

16

15

14

13

TH

0.22µF*

0.22µF*

7

2

AD844

3

100pF

6

4

Figure 42. High Speed DAC Amplifier

GROUND

–5V

0.22µF*

0.22µF*

R

I

+15V

–15V

V

OUT

ANALOG
SUPPLY
GROUND

DIGITAL
SUPPLY

0897-042

HIGH SPEED DAC BUFFER

The AD844 performs very well in applications requiring current­to-voltage conversion. Figure 42 shows connections for use with
the AD568 current output DAC. In this application, the bipolar
offset is used so that the full-scale current is ±5.12 mA, which
generates an output of ±5.12 V using the 1 kΩ application resistor
on the AD568. Figure 43 shows the full-scale transient response.
Care is needed in power supply decoupling and grounding
techniques to achieve the full 12-bit accuracy and realize the
fast settling capabilities of the system. The AD568 data sheet
should be consulted for more complete details about its use.

2V

100

90

10

0

50ns

Figure 43. DAC Amplifier Full-Scale Transient Response

0897-043

20 MHZ VARIABLE GAIN AMPLIFIER

The AD844 is an excellent choice as an output amplifier for the

AD539 multiplier, in all of its connection modes. (See the

AD539 data sheet for full details.) Figure 44 shows a simple
multiplier providing the output:

VV

V

W

where V

X

to 3.2 V (maximum), and V
±2 V full scale but capable of operation up to ±4.2 V.

The peak output in this configuration is thus ±6.7 V. Using all
four of the internal application resistors provided on the AD539
in parallel results in a feedback resistance of 1.5 kΩ, at which
value the bandwidth of the AD844 is about 22 MHz, and is
essentially independent of V

INPUTS

V

*

X

0V TO 3

*

V

Y

±2V FS

3nF

INPUT

GND

0.22µF

*VX AND VY INPUTS MAY O PTIONAL LY BE TERMI NATED;
TYPICALL Y BY USING A 50Ω OR 75Ω RESISTOR TO GROUND.

YX

−= (1)

V

2

is the gain control input, a positive voltage from 0 V

is the signal voltage, nominally

Y

. The gain at VX = 3.16 V is 4 dB.

X

+

S

AD844

7

4

10Ω

TYP +6V
AT 15µA

6

=

V

W

–V
TYP –6V
AT 15µA

OUTPUT
V

W

–V

XVY

2V

S

10Ω 10Ω

0.22µF 0.22µF

1

2

3

AD539

4

TOP VIEW

5

(Not to Scale)

6

7

8

10Ω

16

15

14

13

12

11

10

9

2

3

0.22µF

Figure 44. 20 MHz VGA Using the AD539

00897-044

Rev. F | Page 17 of 20

AD844

Figure 45 shows the small signal response for a 50 dB gain control
range (V

= 10 mV to 3.16 V). At small values of VX, capacitive

X

feedthrough on the PC board becomes troublesome and very
careful layout techniques are needed to minimize this problem.
A ground strip between the pins of the AD539 is helpful in this
regard. Figure 46 shows the response to a 2 V pulse on V
V

= 1 V, 2 V, and 3 V. For these results, a load resistor of 500 Ω

X

for

Y

was used and the supplies were ±9 V. The multiplier operates
from supplies between ±4.5 V and ±16.5 V.

Disconnecting Pin 9 and Pin 16 on the AD539 alters the
denominator in Equation 1 to 1 V, and the bandwidth is
approximately 10 MHz, with a maximum gain of 10 dB.
Using only Pin 9 or Pin 16 results in a denominator of 0.5 V,
a bandwidth of 5 MHz, and a maximum gain of 16 dB.

4

VX = 3.15V

–6

= 1.0V

V

X

–16

= 0.316V

V

X

–26

GAIN (dB)

–36

–46

–56

= 0.10V

V

X

= 0.032V

V

X

FREQUENCY (Hz)

60M1M100k 10M

00897-045

Figure 45. VGA AC Response

1V 1V 50ns

100

90

10

0

00897-046

Figure 46. VGA Transient Response with V

= 1 V, 2 V, and 3 V

X

Rev. F | Page 18 of 20

AD844

OUTLINE DIMENSIONS

0.400 (10.16)

0.365 (9.27)

0.355 (9.02)

0.210 (5.33)

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

MAX

8

1

0.100 (2.54)

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

BSC

5

4

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

0.015
(0.38)
MIN

SEATING
PLANE

0.005 (0.13)
MIN

0.060 (1.52)
MAX

0.015 (0.38)
GAUGE

PLANE

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.430 (10.92)
MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

CONTROLL ING DIMENS IONS ARE IN INCHES; MILLIMETER DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-OF F INCH EQUI VALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOL E OR HALF LEADS.

COMPLIANT TO JEDEC STANDARDS MS-001

070606-A

Figure 47. 8-Lead Plastic Dual-in-Line Package [PDIP]

(N-8)

Dimensions shown in inches and (millimeters)

0.005 (0.13)

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 48. 8-Lead Ceramic Dual In-Line Package [CERDIP]

Dimensions shown in inches and (millimeters)

0.055 (1.40)

MIN

14

0.100 (2.54) BSC

0.405 (10.29) MAX

MAX

58

0.070 (1.78)

0.030 (0.76)

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

0.150 (3.81)
MIN

SEATING
PLANE

(Q-8)

0.320 (8.13)

0.290 (7.37)

15°

0°

0.015 (0.38)

0.008 (0.20)

Rev. F | Page 19 of 20

AD844

C

0.30 (0.0 118)

0.10 (0.0039)

OPLANARITY

0.10

10.50 (0.4134)

10.10 (0.3976)

BSC

9

7.60 (0.2992)

7.40 (0.2913)

8

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

8°
0°

0.33 (0.0130)

0.20 (0.0079)

5

(

0

.

7

0

.

2

5

(

16

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

CONTROLL ING DIMENS IONS ARE IN MILLIM ETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-O FF MIL LIMETE R EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013- AA

0

.

0

2

9

5

0

0

9

8

0

.

1.27 (0.0500)

0.40 (0.0157)

)

45°

)

032707-B

Figure 49. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD844AN −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
AD844ANZ
AD844ACHIPS −40°C to +85°C Die
AD844AQ −40°C to +85°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8
AD844BQ −40°C to +85°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8
AD844JR-16 0°C to 70°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
AD844JR-16-REEL 0°C to 70°C 16-Lead SOIC_W, 13” Tape and Reel RW-16
AD844JR-16-REEL7 0°C to 70°C 16-Lead SOIC_W, 7” Tape and Reel RW-16
AD844JRZ-16
AD844JRZ-16-REEL
AD844JRZ-16-REEL7
AD844SCHIPS −55°C to +125°C Die
AD844SQ −55°C to +125°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8
AD844SQ/883B −55°C to +125°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8
5962-8964401PA

1

Z = RoHS Compliant Part.

2

Refer to the DESC drawing for tested specifications.

1

−40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8

1

0°C to 70°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16

1

0°C to 70°C 16-Lead SOIC_W, 13” Tape and Reel RW-16

1

0°C to 70°C 16-Lead SOIC_W, 7” Tape and Reel RW-16

2

−55°C to +125°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8

©1989–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00897-0-2/09(F)

Rev. F | Page 20 of 20