Low Noise, Low Gain Drift, G = 2000
+IN–
–FIL
V
Data Sheet
FEATURES
Fixed gain of 2000
Access to internal nodes provides flexibility
Low noise: 1.5 nV/√Hz input voltage noise
High accuracy dc performance
Gain drift: 10 ppm/°C
Offset drift: 1 μV/°C
Gain accuracy: 0.2%
CMRR: 130 dB min
Excellent ac specifications
Bandwidth: 3.5 MHz
Slew rate: 40 V/μs
Power supply range: ±4 V to ±18 V
8-pin SOIC package
ESD protection >5000 V (HBM)
Temperature range for specified performance:
−40°C to +85°C
Operational up to 125°C
APPLICATIONS
Sensor interface
Medical instrumentation
Patient monitoring
GENERAL DESCRIPTION
The AD8428 is an ultralow noise instrumentation amplifier
designed to accurately measure tiny, high speed signals. It
delivers industry-leading gain accuracy, noise, and bandwidth.
All gain setting resistors for the AD8428 are internal to the part
and are precisely matched. Care is taken in both the chip pinout
and layout. This results in excellent gain drift and quick settling
to the final gain value after the part is powered on.
The high CMRR of the AD8428 prevents unwanted signals
from corrupting the signal of interest. The pinout of the AD8428
is designed to avoid parasitic capacitance mismatches that can
degrade CMRR at high frequencies.
Instrumentation Amplifier
AD8428
FUNCTIONAL BLOCK DIAGRAM
+
S
IN
6kΩ 6kΩ
3kΩ
30.15Ω
3kΩ
6kΩ 6kΩ
–V
+FIL
S
Figure 1.
Table 1. Instrumentation Amplifiers by Category1
GeneralPurpose
Zero
Drift
Military
Grade
AD8220 AD8231 AD620 AD627 AD8428
AD8221 AD8290 AD621 AD623 AD8429
AD8222 AD8293 AD524 AD8235
AD8224 AD8553 AD526 AD8236
AD8228 AD8556 AD624 AD8426
AD8295 AD8557 AD8226
AD8227
1
See www.analog.com for the latest instrumentation amplifiers.
The AD8428 is one of the fastest instrumentation amplifiers
available. The circuit architecture is designed for high bandwidth
at high gain. The AD8428 uses a current feedback topology for
the initial preamplifier gain stage of 200, followed by a difference
amplifier stage of 10. This architecture results in a 3.5 MHz
bandwidth at a gain of 2000 for an equivalent gain bandwidth
product of 7 GHz.
The AD8428 pinout allows access to internal nodes between the
first and second stages. This feature can be useful for modifying
the frequency response between the two amplification stages,
thereby preventing unwanted signals from contaminating the
output results.
The performance of the AD8428 is specified over the industrial
temperature range of −40°C to +85°C. It is available in an 8-lead
plastic SOIC package.
120kΩ
120kΩ
AD8428
Low
Power
OUT
REF
Low
Noise
09731-001
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
AD8428 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
10/11—Revision 0: Initial Version
Theory of Operation ...................................................................... 13
Architecture ................................................................................ 13
Filter Terminals ........................................................................... 13
Reference Terminal .................................................................... 13
Input Voltage Range ................................................................... 14
Layout .......................................................................................... 14
Input Bias Current Return Path ............................................... 15
Input Protection ......................................................................... 15
Radio Frequency Interference (RFI) ........................................ 16
Calculating the Noise of the Input Stage ................................. 16
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
Rev. 0 | Page 2 of 20
Data Sheet AD8428
SPECIFICATIONS
VS = ±15 V, V
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
COMMON-MODE REJECTION RATIO (RTI) VCM = ±10 V
CMRR, DC to 60 Hz 130 dB
CMRR at 50 kHz 110 dB
NOISE (RTI) VIN+, VIN− = 0 V
Voltage Noise f = 1 kHz 1.3 1.5 nV/√Hz
f = 0.1 Hz to 10 Hz 40 50 nV p-p
Current Noise f = 1 kHz 1.5 pA/√Hz
f = 0.1 Hz to 10 Hz 150 pA p-p
VOLTAGE OFFSET
Input Offset, V
Average TC TA = −40°C to +85°C 1 μV/°C
Offset RTI vs. Supply (PSRR) 120 dB
INPUT CURRENT
Input Bias Current 200 nA
Over Temperature TA = −40°C to +85°C 250 pA/°C
Input Offset Current 50 nA
Over Temperature TA = −40°C to +85°C 20 pA/°C
DYNAMIC RESPONSE
−3 dB Small Signal Bandwidth 3.5 MHz
Settling Time to 0.01% 10 V step 0.75 μs
Settling Time to 0.001% 10 V step 1.4 μs
Slew Rate 40 50 V/μs
GAIN
First Stage Gain 200 V/V
Subtractor Stage Gain 10 V/V
Total Gain Error V
Tot al G ain Nonlinearity V
Total Gain vs. Temperature 10 ppm/°C
INPUT
Impedance (Pin to Ground)
Input Operating Voltage Range VS = ±4 V to ±18 V −VS + 2.5 +VS − 2.5 V
Over Temperature TA = −40°C to +85°C −VS + 2.5 +VS − 2.5 V
OUTPUT
Output Swing RL = 2 kΩ −VS + 1.7 +VS − 1.2 V
Over Temperature TA = −40°C −VS + 2.0 +VS − 1.3 V
T
Output Swing RL = 10 kΩ −VS + 1.7 +VS − 1.0 V
Over Temperature TA = −40°C −VS + 1.8 +VS − 1.2 V
T
Short-Circuit Current 30 mA
REFERENCE INPUT
RIN 132 kΩ
IIN V
Voltage Range −VS +VS V
Reference Gain to Output 1 V/V
Reference Gain Error 0.01 %
= 0 V, TA = 25°C, G = 2000, RL = 10 k, unless otherwise noted.
REF
100 μV
OSI
= −10 V to +10 V 0.2 %
OUT
= −10 V to +10 V 5 ppm
OUT
1
1||2 GΩ||pF
= +85°C −VS + 1.6 +VS − 1.1 V
A
= +85°C −VS + 1.4 +VS − 0.9 V
A
+, VIN− = 0 V 6.5 μA
IN
Rev. 0 | Page 3 of 20
AD8428 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
FILTER TERMINALS
2
R
6 kΩ
IN
Voltage Range −VS +VS V
POWER SUPPLY
Operating Range ±4 ±18 V
Quiescent Current 6.5 6.8 mA
Over Temperature TA = −40°C to +85°C 8 mA
1
The differential and common-mode input impedances can be calculated from the pin impedance: Z
2
To calculate the actual impedance, see Figure 1.
DIFF
= 2(Z
); ZCM = Z
PIN
/2.
PIN
Rev. 0 | Page 4 of 20
Data Sheet AD8428
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage ±18 V
Output Short-Circuit Current Duration Indefinite
Maximum Voltage at −IN, +IN1 ±VS
Maximum Voltage at −FIL, +FIL ±VS
Differential Input Voltage1 ±1 V
Maximum Voltage at REF ±VS
Storage Temperature Range −65°C to +150°C
Specified Temperature Range −40°C to +85°C
Maximum Junction Temperature 140°C
ESD
Human Body Model 5000 V
Charged Device Model 1250 V
Machine Model 400 V
1
For voltages beyond these limits, use input protection resistors. See the
Input Protection section for more information.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package θJA Unit
8-Lead SOIC_N 121 °C/W
ESD CAUTION
Rev. 0 | Page 5 of 20
AD8428 Data Sheet
A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
D8428
–IN
1
–FIL
2
+FIL
3
+IN
4
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN Negative Input Terminal.
2 −FIL Negative Filter Terminal.
3 +FIL Positive Filter Terminal.
4 +IN Positive Input Terminal.
5 −VS Negative Power Supply Terminal.
6 REF Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level-shift the output.
7 OUT Output Terminal.
8 +VS Positive Power Supply Terminal.
+V
8
S
OUT
7
REF
6
–V
5
S
09731-002
Rev. 0 | Page 6 of 20
Data Sheet AD8428
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15 V, V
1200
1000
800
600
HITS
400
200
= 0 V, RL = 10 kΩ, unless otherwise noted.
REF
N = 5170
MEAN = 2.12
SD = 7.332
1600
1400
1200
1000
800
HITS
600
400
200
NONINVERTING I
INVERTING I
BIAS
N = +5171
MEAN = –10.8
SD = +6.67496
N = +5171
MEAN = –10.2
SD = +6.52901
BIAS
0
–40 –20 40200
V
(µV)
OSI
Figure 3. Typical Distribution of Input Offset Voltage, VS = ±5 V
1400
N = +5169
1200
1000
800
HITS
600
400
200
0
–40 –20 40200
V
(µV)
OSI
MEAN = –2.57
SD = +7.31066
Figure 4. Typical Distribution of Input Offset Voltage, VS = ±15 V
1400
1200
1000
800
HITS
600
400
200
N = 5166
MEAN = 0.398
SD = 0.42707
0
–60 –40 –20 40200
09731-003
I
BIAS
(nA)
09731-006
Figure 6. Typical Distribution of Input Bias Current
1000
800
600
HITS
400
200
0
–8 –6 –4 6042–2
09731-004
I
OFFSET (nA)
BIAS
N = +5171
MEAN = –0.53
SD = +1.41655
09731-007
Figure 7. Typical Distribution of Input Bias Current Offset
1200
N = +3487
MEAN = –53.9
1000
800
600
HITS
400
200
SD = +86.7774
0
–3 –2 –1 3120
V
OSI
DRIFT (µV)
Figure 5. Typical Distribution of Input Offset Voltage Drift
09731-005
Rev. 0 | Page 7 of 20
0
–600 –400 200 4000–200
GAIN ERROR (µV/V)
Figure 8. Typical Distribution of Gain Error, Gain = 2000,
V
= ±15 V, RL = 10 kΩ
S
09731-008
AD8428 Data Sheet
15
VS = ±15V
10
5
0
–5
–10
INPUT COMMON-MODE VOLTAGE (V)
–15
–15 –10 –5 0 5 10 15
VS = ±12V
VS = ±5V
OUTPUT VO LTAGE (V )
Figure 9. Input Common-Mode Voltage vs. Output Voltage,
= ±5 V, VS = ±12 V, VS = ±15 V
V
S
09731-009
72
66
60
54
48
42
36
30
24
GAIN (dB)
18
12
6
0
–6
–12
100 1k 10k 100k 100M1M 10M
FREQUENCY (Hz)
Figure 12. Gain vs. Frequency
09731-014
18
16
14
12
10
8
6
INPUT BIAS CURRENT (nA)
4
2
0
–14 14
–11.8V
+12V
–12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12
COMMON-MODE VOLTAGE (V)
Figure 10. Input Bias Current vs. Common-Mode Voltage,
= ±15 V
V
S
140
120
100
80
60
PSRR (dB)
40
20
0
0.1 1 1M100k10k1k10010
FREQUENCY (Hz)
+PSRR
–PSRR
Figure 11. PSRR vs. Frequency
170
160
150
140
130
120
CMRR (dB)
110
100
90
80
09731-010
1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
GAIN = 2000
09731-015
Figure 13. CMRR vs. Frequency
120
GAIN = 2000
110
100
90
80
70
60
50
CMRR (dB)
40
30
20
10
0
09731-011
1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
09731-016
Figure 14. CMRR vs. Frequency, 1 kΩ Source Imbalance
Rev. 0 | Page 8 of 20
Data Sheet AD8428
5
4
3
2
1
0
–1
CHANGE IN INPUT OFFSET VOLTAGE (µV)
–2
0 120
10 20 30 40 50 60 70 80 90 100 110
Figure 15. Change in Input Offset Voltage (V
WARM-UP TIME (Seconds)
OSI
) vs. Warm-Up Time
09731-017
70
REPRESENTATIVE DATA NORMALI ZED AT 25°C
60
50
40
30
20
10
CMRR (nV/V)
0
–10
–20
–30
–25–105 203550658095110
–40 125
TEMPERATURE ( °C)
Figure 18. CMRR vs. Temperature, Normalized at 25°C
09731-020
15
10
5
0
–5
–10
–15
INPUT BIAS CURRENT (nA)
–20
–25
–30
–40 125
IOS
IB+
IB–
NORMALIZ ED AT 25°C
–25–105 203550658095110
TEMPERATURE ( °C)
1.2
0.8
0.4
0
–0.4
–0.8
–1.2
–1.6
–2.0
–2.4
Figure 16. Input Bias Current and Input Offset Current vs. Temperature
250
200
150
100
50
0
–50
GAIN ERROR (µV/V)
–100
–150
REPRESENTATI VE DATA NORMALIZED AT 25°C
–200
–25–105 203550658095110
–40 125
TEMPERATURE ( °C)
Figure 17. Gain Error vs. Temperature, Normalized at 25°C
9.0
8.5
8.0
7.5
7.0
6.5
SUPPLY CURRENT (mA)
INPUT OFFSET CURRENT ( nA)
09731-018
6.0
5.5
5.0
–25–105 203550658095110
–40 125
TEMPERATURE ( °C)
09731-021
Figure 19. Supply Current vs. Temperature
50
40
30
20
10
0
–10
–20
–30
SHORT-CIRCUIT CURRENT (mA)
–40
–50
09731-019
–40 125
I
SHORT+
I
SHORT–
–25–105 203550658095110
TEMPERATURE ( °C)
09731-022
Figure 20. Short-Circuit Current vs. Temperature
Rev. 0 | Page 9 of 20
AD8428 Data Sheet
V
V
V
100
90
80
70
60
50
40
SLEW RATE (V/µ s)
30
20
10
0
–40 125
–25–105 203550658095110
TEMPERATURE ( °C)
Figure 21. Slew Rate vs. Temperature, VS = ±15 V
+SR
–SR
09731-023
+
S
–0.4
–40°C +25°C +85°C +125°C
–0.8
–1.2
+2.0
+1.6
+1.2
OUTPUT VO LTAGE SWING (V)
+0.8
REFERRED TO SUPPLY VOLTAGES
+0.4
–V
S
56789101112131415 1716
4
SUPPLY VOLTAGE (±V
)
S
Figure 24. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ
09731-026
100
90
80
70
60
–SR
50
40
SLEW RATE (V/µ s)
30
+SR
20
10
0
–40 125
–25–105 203550658095110
TEMPERATURE ( °C)
Figure 22. Slew Rate vs. Temperature, VS = ±5 V
+
S
–0.5
–1.0
–1.5
–2.0
–2.5
+2.5
+2.0
INPUT VOLTAGE (V)
+1.5
+1.0
REFERRED TO SUPPLY VOLTAGES
+0.5
–V
S
46810 18161412
SUPPLY VOLTAGE (±VS)
Figure 23. Input Voltage Limit vs. Supply Voltage
–40°C
+25°C
+85°C
+125°C
+
S
–0.4
–40°C +25°C +85°C +125°C
–0.8
–1.2
+2.0
+1.6
+1.2
OUTPUT VOLT AGE SWING (V)
+0.8
REFERRED TO SUPPLY VOLTAGES
+0.4
–V
S
5 6 7 8 9 10 11 12 13 14 15 1716
4
09731-024
SUPPLY VOLTAGE (±V
)
S
09731-027
Figure 25. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ
15
–40°C
10
+25°C
+85°C
+125°C
5
0
–5
OUTPUT VOLTAGE SWING (V)
–10
–15
100 1k 10k 100k
09731-025
LOAD (Ω)
09731-028
Figure 26. Output Voltage Swing vs. Load Resistance, VS = ±15 V
Rev. 0 | Page 10 of 20
Data Sheet AD8428
V
+
S
–0.5
–1.0
–1.5
+1.5
+1.0
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
+0.5
–V
S
0.01 0.1 1 10
Figure 27. Output Voltage Swing vs. Output Current, VS = ±15 V
–40°C +25°C +85°C +125° C
OUTPUT CURRENT (mA)
20nV/DIV 1s/DIV
09731-029
09731-032
Figure 30. 0.1 Hz to 10 Hz RTI Voltage Noise
20
15
10
5
0
–5
–10
GAIN NONLINEARITY (5 ppm/DIV)
–15
–20
–10–8–6–4–2 0 2 4 6 108
OUTPUT VO LTAGE (V)
Figure 28. Gain Nonlinearity, RL = 10 kΩ
100
10
GAIN = 2000
GAIN = 2000
16
15
14
13
12
11
10
9
8
7
NOISE (pA/√Hz)
6
5
4
3
2
1
09731-030
1 10 100 1k 10k 100k
FREQUENCY (Hz)
09731-033
Figure 31. Current Noise Spectral Density vs. Frequency
NOISE (nV/√Hz)
1
0.1
0.1 1 10 100 1k 10k 100k
FREQUENCY (Hz)
Figure 29. RTI Voltage Noise Spectral Density vs. Frequency
50pA/DI V 1s/DIV
09731-031
Figure 32. 0.1 Hz to 10 Hz Current Noise
09731-034
Rev. 0 | Page 11 of 20
AD8428 Data Sheet
5V/DIV
752ns TO 0.01%
1408ns TO 0. 001%
0.002%/DIV
1µs/DIV
TIME (µs)
Figure 33. Large Signal Pulse Response and Settling Time,
10 V Step, V
20mV/DIV 1µs/DIV
= ±15 V
S
GAIN = 2000
Figure 34. Small Signal Pulse Response, RL = 10 kΩ, CL = 100 pF
NO LOAD
CL = 500pF
CL = 770pF
09731-035
50mV/DIV 1µ s/DIV
09731-037
Figure 35. Small Signal Pulse Response with Various Capacitive Loads,
No Resistive Load
1800
1600
1400
1200
SETTL ED TO 0.001%
1000
800
600
SETTLING TIME (ns)
400
200
09731-036
0
SETTLED TO 0.01%
2 4 6 8 101214161820
STEP SIZE (V)
09731-038
Figure 36. Settling Time vs. Step Size
Rev. 0 | Page 12 of 20
Data Sheet AD8428
C
THEORY OF OPERATION
OMPENSATION
+V
S
1
–IN
–V
S
II
I
B
A1 A2
C1 C2
NODE 1
R1
3kΩ
–RG
30.15Ω
R
G
V
B
NODE 2
R2
3kΩ
+RG
Figure 37. Simplified Schematic
ARCHITECTURE
The AD8428 is based on the classic 3-op-amp topology. This
topology has two stages: a gain stage (preamplifier) to provide
differential amplification by a factor of 200, followed by a difference amplifier stage to remove the common-mode voltage and
provide additional amplification by a factor of 10. Figure 37
shows a simplified schematic of the AD8428.
The first stage works as follows. To keep its two inputs matched,
Amplifier A1 must keep the collector of Q1 at a constant voltage.
It does this by forcing −RG to be a precise diode drop from −IN.
Similarly, A2 forces +RG to be a constant diode drop from +IN.
Therefore, a replica of the differential input voltage is placed across
the gain setting resistor, R
. The current that flows across this
G
resistance must also flow through the R1 and R2 resistors, creating a gained differential signal between the A2 and A1 outputs.
The second stage is a G = 10 difference amplifier, composed of
Amplifier A3 and Resistors R3 through R8. This stage removes
the common-mode signal from the amplified differential signal.
The transfer function of the AD8428 is
V
= 2000 × (V
OUT
IN+
− V
IN−
) + V
REF
FILTER TERMINALS
The −FIL and +FIL terminals allow access between R3 and R4,
and between R5 and R6, respectively. Adding a filter between
these two terminals modifies the signal gain vs. frequency before
it reaches the second amplifier stage.
Q2Q1
+V
R3
6kΩ
R5
6kΩ
+V
–FIL
2
+FIL
–V
R4
6kΩ
R6
6kΩ
–V
3
S
S
120kΩ
A3
120kΩ
R8
R7
+V
S
7
OUT
+V
S
–V
S
6
REF
–V
S
09731-042
S
S
I
B
COMPENSATION
+V
S
4
+IN
–V
S
REFERENCE TERMINAL
The output voltage of the AD8428 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal must be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF pin to levelshift the output so that the AD8428 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +V
For best performance, the source impedance to the REF
terminal should be kept well below 1 Ω. As shown in Figure 37,
the reference terminal, REF, is at one end of a 120 k resistor.
Additional impedance at the REF terminal adds to this 120 k
resistor and results in amplification of the signal connected to
the positive input. The amplification from the additional R
can be calculated as follows:
2 × (120 k + R
Only the positive signal path is amplified; the negative path is
unaffected. This uneven amplification degrades the CMRR of
the amplifier.
V
or −VS.
S
)/(240 k + R
REF
INCORRECT
REF
CORRECT
AD8428
REF
V
+
OP1177
–
Figure 38. Driving the Reference Pin
)
AD8428
REF
REF
09731-043
Rev. 0 | Page 13 of 20
AD8428 Data Sheet
V
INPUT VOLTAGE RANGE
The 3-op-amp architecture of the AD8428 applies gain in the
first stage before removing the common-mode voltage in the
difference amplifier stage. Internal nodes between the first and
second stages (Node 1 and Node 2 in Figure 37) experience a
combination of an amplified differential signal, a common-mode
signal, and a diode drop. This combined signal can be limited by
the voltage supplies even when the individual input and output
signals are not limited. Figure 9 shows the allowable input
common-mode voltage ranges for various output voltages and
supply voltages.
LAYOUT
To ensure optimum performance of the AD8428 at the PCB
level, care must be taken in the design of the board layout. The
pins of the AD8428 are especially arranged to simplify board
layout and to help minimize parasitic imbalance between the
inputs.
AD8428
–IN
1
–FIL
2
+FIL
3
+IN
4
TOP VIEW
(Not to Scale)
Figure 39. Pinout Diagram
Common-Mode Rejection Ratio over Frequency
Poor layout can cause some of the common-mode signals to be
converted to differential signals before reaching the in-amp. Such
conversions occur when one input path has a frequency response
that is different from the other. To maintain high CMRR over
frequency, the input source impedance and capacitance of each
path should be closely matched. Additional source resistance in
the input paths (for example, for input protection) should be
placed close to the in-amp inputs to minimize the interaction
of the inputs with parasitic capacitance from the PCB traces.
Parasitic capacitance at the filter pins can also affect CMRR over
frequency. If the board design has a component at the filter pins,
the component should be chosen so that the parasitic capacitance
is as small as possible.
+V
8
S
OUT
7
REF
6
–V
5
S
09731-044
Power Supplies and Grounding
Use a stable dc voltage to power the instrumentation amplifier.
Noise on the supply pins can adversely affect performance. See
the PSRR performance curves in Figure 11 for more information.
Place a 0.1 µF capacitor as close as possible to each supply pin.
Because the length of the bypass capacitor leads is critical at
high frequency, surface-mount capacitors are recommended. A
parasitic inductance in the bypass ground trace works against
the low impedance created by the bypass capacitor.
As shown in Figure 40, a 10 µF capacitor can be used farther
away from the device. For larger value capacitors, which are
intended to be effective at lower frequencies, the current return
path distance is less critical. In most cases, the 10 µF capacitor
can be shared by other precision integrated circuits.
+
S
REF
10µF
LOAD
V
OUT
09731-045
0.1µF
+IN
AD8428
–IN
0.1µF 10µF
–V
S
Figure 40. Supply Decoupling, REF, and Output Referred to Local Ground
A ground plane layer is helpful to reduce undesired parasitic
inductances and to minimize voltage drops with changes in
current. The area of the current path is directly proportional
to the magnitude of parasitic inductances and, therefore, the
impedance of the path at high frequency. Large changes in
currents in an inductive decoupling path or ground return
create unwanted effects due to the coupling of such changes
into the amplifier inputs.
Because load currents flow from the supplies, the load should
be connected at the same physical location as the bypass capacitor grounds.
Reference Pin
The output voltage of the AD8428 is developed with respect to
the potential on the reference terminal. Ensure that REF is tied
to the appropriate local ground.
Rev. 0 | Page 14 of 20
Data Sheet AD8428
V
V
INPUT BIAS CURRENT RETURN PATH
The input bias current of the AD8428 must have a return path
to ground. When the source, such as a thermocouple, cannot
provide a current return path, one should be created, as shown
in Figure 41.
INCORRECT
+V
S
AD8428
REF
–V
S
TRANSFORMER
+V
S
AD8428
REF
–V
S
THERMOCOUPL E
+V
S
C
f
=
AD8428
C
CAPACITIVEL Y COUPLED
REF
–V
S
HIGH- PASS
2πRC
CAPACITIVEL Y COUPLED
Figure 41. Creating an Input Bias Current Return Path
10MΩ
1
CORRECT
TRANSFORMER
THERMOCOUPL E
C
R
C
R
+V
S
AD8428
–V
S
+V
S
AD8428
–V
S
+V
S
AD8428
–V
S
REF
REF
REF
INPUT PROTECTION
Do not allow the inputs of the AD8428 to exceed the ratings
stated in the Absolute Maximum Ratings section. If these ratings
cannot be adhered to, add protection circuitry in front of the
AD8428 to limit the maximum current into the inputs (see the
I
section).
MAX
I
MAX
The maximum current into the AD8428 inputs, I
on time and temperature. At room temperature, the device can
withstand a current of 10 mA for at least one day. This time is
cumulative over the life of the device.
, depends
MAX
Input Voltages Beyond the Rails
If voltages beyond the rails are expected, use an external resistor
in series with each input to limit current during overload conditions. The limiting resistor at each input can be computed using
the following equation:
VVR−
IN
PROTECT
≥
I
MAX
SUPPLY
Noise sensitive applications may require a lower protection
resistance. Low leakage diode clamps, such as the BAV199, can
be used at the inputs to shunt current away from the AD8428
inputs and, therefore, allow smaller protection resistor values.
To ensure that current flows primarily through the external
protection diodes, place a small value resistor, such as a 33
resistor, between the diodes and the AD8428.
+
+V
R
PROTECT
+
V
V
I
IN+
–
R
PROTECT
+
IN–
–
SIMPLE METHOD LOW NOISE METHOD
S
AD8428
–V
S
R
+
V
IN+
–
R
+
V
IN–
–
PROTECT
PROTECT
S
33Ω
I
–V
S
+V
S
33Ω
–V
S
Figure 42. Protection for Voltages Beyond the Rails
Large Differential Input Voltage at High Gain
If large differential voltages at high gain are expected, use an
external resistor in series with each input to limit current
during overload conditions. The limiting resistor at each input
can be computed using the following equation:
⎛
V
R
PROTECT
Noise sensitive applications may require a lower protection
09731-046
1
2
DIFF
⎜
×≥
⎜
⎝
I
MAX
V1
−
⎞
⎟
R
−
G
⎟
⎠
resistance. Low leakage diode clamps, such as the BAV199,
can be used across the AD8428 inputs to shunt current away
from the inputs and, therefore, allow smaller protection resistor
values.
R
PROTECT
I
+
DIFF
–
R
PROTECT
AD8428
Figure 43. Protection for Large Differential Voltages
+V
S
AD8428
–V
S
09731-048
09731-047
Rev. 0 | Page 15 of 20
AD8428 Data Sheet
V
R
()(
RADIO FREQUENCY INTERFERENCE (RFI)
Because of its high gain and low noise properties, the AD8428 is
a highly sensitive amplifier. Therefore, RF rectification can be a
problem if the AD8428 is used in applications that have strong
RF signal sources present. The problem is intensified if long
leads or PCB traces are required to connect the amplifier to the
signal source. The disturbance can appear as a dc offset voltage
or a train of pulses.
High frequency signals can be filtered with a low-pass filter
network at the input of the instrumentation amplifier, as shown
in Figure 44.
+
S
0.1µF
C
C
L*
33Ω
L*
33Ω
*CHIP FERRIT E BEAD.
1nF
R
C
D
R
10nF
C
C
1nF
0.1µF
Figure 44. RFI Suppression
+IN
AD8428
–IN
–V
The filter limits both the differential and common-mode bandwidth, as shown in the following equations:
DIFF
CM
=
=
uencyFilterFreq
uencyFilterFreq
where C
C
≥ 10 CC.
D
affects the differential signal, and CC affects the common-
D
mode signal. Choose values of R and C
mismatch between R × C
at the positive input and R × CC at
C
1
CCR
+
D
1
RC
π2
C
that minimize RFI. A
C
the negative input degrades the CMRR of the AD8428. By using
a value of C
one order of magnitude larger than CC, the effect
D
of the mismatch is reduced, and performance is improved.
Resistors add noise; therefore, the choice of resistor and capac-
itor values depends on the desired trade-off between noise, input
impedance at high frequencies, and RFI immunity. To achieve
low noise and sufficient RFI filtering, the use of inductive ferrite
beads is recommended (see Figure 44). Using inductive ferrite
beads allows the value of the resistors to be reduced, which helps
to minimize the noise at the input.
10µF
V
OUT
REF
10µF
S
09731-049
)2(π2
C
For best results, place the RFI filter network as close as possible
to the amplifier. Layout is critical to ensure that RF signals are
not picked up on the traces after the filter. If RF interference is
too strong to be filtered, shielding is recommended.
Note that the resistors used for the RFI filter can be the same
as those used for input protection (see the Input Protection
section).
CALCULATING THE NOISE OF THE INPUT STAGE
The total noise of the amplifier front end depends on much
more than the specifications in this data sheet. The three main
contributors to noise are as follows: the source resistance, the
voltage noise of the instrumentation amplifier, and the current
noise of the instrumentation amplifier.
In the following calculations, noise is referred to the input (RTI);
that is, all sources of noise are calculated as if the source appeared
at the amplifier input. To calculate the noise referred to the amplifier output (RTO), simply multiply the RTI noise by the gain of
the instrumentation amplifier.
Source Resistance Noise
Any sensor connected to the AD8428 has some output resistance.
There may also be resistance placed in series with the inputs for
protection from either overvoltage or radio frequency interference.
This combined resistance is labeled R1 and R2 in Figure 45. Any
resistor, no matter how well made, has an intrinsic level of noise.
This noise is proportional to the square root of the resistor value.
At room temperature, the value is approximately equal to
4 nV/√Hz × √(resistor value in k).
SENSO
R1
R2
Figure 45. Source Resistance from Sensor and Protection Resistors
For example, assuming that the combined sensor and protection resistance is 4 k on the positive input and 1 k on the
negative input, the total noise from the input resistance is
22
)
AD8428
=+=×+×
09731-050
HznV/9.816641444
Rev. 0 | Page 16 of 20
Data Sheet AD8428
Voltage Noise of the Instrumentation Amplifier Total Noise Density Calculation
Unlike other instrumentation amplifiers in which an external
resistor is used to set the gain, the voltage noise specification
of the AD8428 already includes the input noise, output noise,
and the R
resistor noise.
G
Current Noise of the Instrumentation Amplifier
The contribution of current noise to the input stage in nV/√Hz
is calculated by multiplying the source resistance in k by the
specified current noise of the instrumentation amplifier in
pA/√Hz.
For example, if the R1 source resistance in Figure 45 is 4 k
and the R2 source resistance is 1 k, the total effect from the
current noise is calculated as follows:
()()
22
=×+×
HznV/2.65.115.14
To determine the total noise of the in-amp, referred to input,
combine the source resistance noise, voltage noise, and current
noise contribution by the sum of squares method.
For example, if the R1 source resistance in Figure 45 is 4 k
and the R2 source resistance is 1 k, the total noise, referred
to input, is
222
=++
HznV/0.112.65.19.8
Rev. 0 | Page 17 of 20
AD8428 Data Sheet
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
85
1
1.27 (0.0500)
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
BSC
6.20 (0.2441)
5.80 (0.2284)
4
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
8°
0°
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
0.40 (0.0157)
45°
012407-A
Figure 46. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
1
Model
AD8428ARZ −40°C to +125°C 8-Lead SOIC_N R-8
AD8428ARZ-RL −40°C to +125°C 8-Lead SOIC_N, 13” Tape and Reel R-8
1
Z = RoHS Compliant Part.
Temperature Range Package Description Package Option
Rev. 0 | Page 18 of 20
Data Sheet AD8428
NOTES
Rev. 0 | Page 19 of 20
AD8428 Data Sheet
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09731-0-10/11(0)
Rev. 0 | Page 20 of 20
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