Datasheet AD8426 Datasheet (ANALOG DEVICES)

Wide Supply Range, Rail-to-Rail

FEATURES

2 channels in a small, 4 mm × 4 mm LFCSP LFCSP package has no metal pad

More routing room No current leakage to pad

Gain set with 1 external resistor

Gain range: 1 to 1000 Input voltage goes below ground Inputs protected beyond supplies Very wide power supply range

Single supply: 2.2 V to 36 V

Dual supply: ±1.35 V to ±18 V Bandwidth (G = 1): 1 MHz CMRR (G = 1): 80 dB minimum Input noise: 24 nV/√Hz Typical supply current (per amplifier): 350 μA Specified temperature range: −40°C to +125°C

APPLICATIONS

Industrial process controls Bridge amplifiers Medical instrumentation Portable data acquisition Multichannel systems

GENERAL DESCRIPTION

The AD8426 is a dual-channel, low cost, wide supply range instrumentation amplifier that requires only one external resistor to set any gain from 1 to 1000.

The AD8426 is designed to work with a variety of signal voltages. A wide input range and rail-to-rail output allow the signal to make full use of the supply rails. Because the input range can also go below the negative supply, small signals near ground can be amplified without requiring dual supplies. The

AD8426 operates on supplies ranging from ±1.35 V to ±18 V

for dual supplies and 2.2 V to 36 V for a single supply.

The robust AD8426 inputs are designed to connect to realworld sensors. In addition to its wide operating range, the

AD8426 can handle voltages beyond the rails. For example,

with a ±5 V supply, the part is guaranteed to withstand ±35 V at the input with no damage. Minimum and maximum input bias currents are specified to facilitate open-wire detection.

Output Instrumentation Amplifier

AD8426

CONNECTION DIAGRAM

S

OUT2

13141516

REF1

REF2

Figure 1.

–V

S

–V

12

11

10

9

Low Power

–IN2

RG2

+IN2

09490-001

High Speed PGA

+VSOUT1

AD8426

1

–IN1

2

RG1

3

RG1

4

+IN1

5678

S

+V

Table 1. Instrumentation Amplifiers by Category1

GeneralPurpose

Zero Drift

Military Grade

AD8220 AD8231 AD620 AD627 AD8250 AD8221 AD8290 AD621 AD623 AD8251 AD8222 AD8293 AD524 AD8235 AD8253 AD8224 AD8553 AD526 AD8236 AD8228 AD8556 AD624 AD8426 AD8295 AD8557 AD8226

AD8227

1

See www.analog.com for the latest instrumentation amplifiers.

The AD8426 is designed to make PCB routing easy and efficient. The two amplifiers are arranged in a logical way so that typical application circuits have short routes and few vias. Unlike most chip scale packages, the AD8426 does not have an exposed metal pad on the bottom of the part, which frees additional space for routing and vias. The AD8426 offers two in-amps in the equivalent board space of a typical MSOP package.

The AD8426 is ideal for multichannel, space-constrained industrial applications. Unlike other low cost, low power instrumentation amplifiers, the AD8426 is designed with a minimum gain of 1 and can easily handle ±10 V signals. With its space-saving LFCSP package and 125°C temperature rating, the AD8426 thrives in tightly packed, zero airflow designs.

The AD8226 is the single-channel version of the AD8426.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD8426

REVISION HISTORY

7/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

AD8426

SPECIFICATIONS

DUAL-SUPPLY OPERATION

+VS = +15 V, −VS = −15 V, V

Table 2.

Parameter Min Typ Max Min Typ Max Unit

COMMON-MODE REJECTION

RATIO (CMRR)

CMRR, DC to 60 Hz

G = 1 80 90 dB G = 10 100 105 dB G = 100 105 110 dB G = 1000 105 110 dB

CMRR at 5 kHz

G = 1 80 80 dB G = 10 90 90 dB G = 100 90 90 dB G = 1000 100 100 dB

NOISE

Voltage Noise f = 1 kHz

Input Voltage Noise, eNI 24 27 24 27 nV/√Hz Output Voltage Noise, eNO 120 125 120 125 nV/√Hz

RTI Noise f = 0.1 Hz to 10 Hz

G = 1 2 2 μV p-p G = 10 0.5 0.5 μV p-p G = 100 to 1000 0.4 0.4 μV p-p

Current Noise f = 1 kHz 100 100 fA/√Hz

f = 0.1 Hz to 10 Hz 3 3 pA p-p VOLTAGE OFFSET

Input Offset, V

V

OSI

Average Temperature

Coefficient

Output Offset, V

V

OSO

Average Temperature

Coefficient

Offset RTI vs. Supply (PSR) VS = ±5 V to ±15 V

G = 1 80 90 dB G = 10 100 105 dB G = 100 105 110 dB G = 1000 105 110 dB

INPUT CURRENT

Input Bias Current

1

T

T T

Average Temperature

Coefficient

Input Offset Current TA = +25°C 1.5 0.5 nA

T T

Average Temperature

Coefficient

= 0 V, TA = 25°C, G = 1, RL = 10 k, specifications referred to input, unless otherwise noted.

REF

Test Conditions/

A Grade B Grade

Comments

= −10 V to +10 V

V

CM

Tot al noise: e

= √(e

N

2

+ (eNO/G)2)

NI

Total offset voltage: VOS = V

T

+ (V

OSO

/G)

OSI

= ±5 V to ±15 V 200 100 μV

S

= −40°C to +125°C 0.5 2 0.5 1 μV/°C

A

= ±5 V to ±15 V 1000 500 μV

S

= −40°C to +125°C 2 10 1 5 μV/°C

A

= +25°C 5 20 27 5 20 27 nA

A

= +125°C 5 15 25 5 15 25 nA

A

= −40°C 5 30 35 5 30 35 nA

A

= −40°C to +125°C 70 70 pA/°C

A

= +125°C 1.5 0.5 nA

A

= −40°C 2 0.5 nA

A

= −40°C to +125°C 5 5 pA/°C

A

Rev. 0 | Page 3 of 28

AD8426

Parameter Min Typ Max Min Typ Max Unit

Test Conditions/ Comments

REFERENCE INPUT

RIN 100 100 kΩ IIN 7 7 μA Voltage Range −VS +VS −VS +VS V Reference Gain to Output 1 1 V/V Reference Gain Error 0.01 0.01 %

GAIN G = 1 + (49.4 kΩ/RG)

Gain Range 1 1000 1 1000 V/V Gain Error V

± 10 V

OUT

G = 1 0.04 0.01 % G = 5 to 1000 0.3 0.1 %

Gain Nonlinearity V

= −10 V to +10 V

OUT

G = 1 to 10 RL ≥ 2 kΩ 20 20 ppm G = 100 RL ≥ 2 kΩ 75 75 ppm G = 1000 RL ≥ 2 kΩ 750 750 ppm

Gain vs. Temperature

2

G = 1 TA = −40°C to +85°C 5 1 ppm/°C T

= +85°C to +125°C 5 2 ppm/°C

A

G > 1 TA = −40°C to +125°C −100 −100 ppm/°C

INPUT VS = ±1.35 V to +36 V

Input Impedance

Differential 0.8||2 0.8||2 GΩ||pF Common Mode 0.4||2 0.4||2 GΩ||pF

Input Operating Voltage

Range

3

T T

TA = +25°C −VS − 0.1 +VS − 0.8 −VS − 0.1 +VS − 0.8 V

= +125°C −VS − 0.05 +VS − 0.6 −VS − 0.05 +VS − 0.6 V

A

= −40°C −VS − 0.15 +VS − 0.9 −VS − 0.15 +VS − 0.9 V

A

Input Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40 V

OUTPUT

Output Swing

RL = 2 kΩ to Ground TA = +25°C −VS + 0.4 +VS − 0.7 −VS + 0.4 +VS − 0.7 V T T

= +125°C −VS + 0.4 +VS − 1.0 −VS + 0.4 +VS − 1.0 V

A

= −40°C −VS + 1.2 +VS − 1.1 −VS + 1.2 +VS − 1.1 V

A

RL = 10 kΩ to Ground TA = +25°C −VS + 0.2 +VS − 0.2 −VS + 0.2 +VS − 0.2 V T T

= +125°C −VS + 0.3 +VS − 0.3 −VS + 0.3 +VS − 0.3 V

A

= −40°C −VS + 0.2 +VS − 0.2 −VS + 0.2 +VS − 0.2 V

A

RL = 100 kΩ to Ground TA = −40°C to +125°C −VS + 0.1 +VS − 0.1 −VS + 0.1 +VS − 0.1 V

Short-Circuit Current 13 13 mA

POWER SUPPLY

Operating Range Dual-supply operation ±1.35 ±18 ±1.35 ±18 V

= +25°C 350 425 350 425 μA

Quiescent Current

T

A

(Per Amplifier) T T T

= −40°C 250 325 250 325 μA

A

= +85°C 450 525 450 525 μA

A

= +125°C 525 600 525 600 μA

A

TEMPERATURE RANGE −40 +125 −40 +125 °C

1

The input stage uses PNP transistors; therefore, input bias current always flows into the part.

2

The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.

3

Input voltage range of the AD8426 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.

See the section for more information. Input Voltage Range

A Grade B Grade

Rev. 0 | Page 4 of 28

AD8426

Dynamic Performance Specifications

+VS = +15 V, −VS = −15 V, V

Table 3. Single-Ended Output Configuration (Both Amplifiers)

Parameter Min Typ Max Min Typ Max Unit

DYNAMIC RESPONSE

Small Signal −3 dB Bandwidth

G = 1 1000 1000 kHz G = 10 160 160 kHz G = 100 20 20 kHz G = 1000 2 2 kHz

Settling Time 0.01% 10 V step

G = 1 25 25 μs G = 10 15 15 μs G = 100 40 40 μs G = 1000 750 750 μs

Slew Rate

G = 1 0.4 0.4 V/μs G = 5 to 100 0.6 0.6 V/μs

= 0 V, TA = 25°C, G = 1, RL = 10 k, specifications referred to input, unless otherwise noted.

REF

Test Conditions/ Comments

A Grade B Grade

Table 4. Differential Output Configuration

Parameter Min Typ Max Min Typ Max Unit

DYNAMIC RESPONSE

Small Signal −3 dB Bandwidth

G = 1 850 850 kHz G = 10 300 300 kHz G = 100 30 30 kHz G = 1000 2 2 kHz

Settling Time 0.01% 10 V step

G = 1 25 25 μs G = 10 15 15 μs G = 100 80 80 μs G = 1000 300 300 μs

Slew Rate

G = 1 0.4 0.4 V/μs G = 5 to 100 0.6 0.6 V/μs

Test Conditions/ Comments

A Grade B Grade

Rev. 0 | Page 5 of 28

AD8426

SINGLE-SUPPLY OPERATION

+VS = 2.7 V, −VS = 0 V, V

Table 5.

Parameter Min Typ Max Min Typ Max Unit

COMMON-MODE REJECTION

RATIO (CMRR) CMRR, DC to 60 Hz

G = 1 80 90 dB G = 10 100 105 dB G = 100 105 110 dB G = 1000 105 110 dB

CMRR at 5 kHz

G = 1 80 80 dB G = 10 90 90 dB G = 100 90 90 dB G = 1000 100 100 dB

NOISE

Voltage Noise f = 1 kHz

Input Voltage Noise, eNI 24 27 24 27 nV/√Hz Output Voltage Noise, eNO 120 125 120 125 nV/√Hz

RTI Noise f = 0.1 Hz to 10 Hz

G = 1 2 2 μV p-p G = 10 0.5 0.5 μV p-p G = 100 to 1000 0.4 0.4 μV p-p

Current Noise f = 1 kHz 100 100 fA/√Hz f = 0.1 Hz to 10 Hz 3 3 pA p-p VOLTAGE OFFSET

Input Offset, V

300 150 μV

OSI

Average Temperature

Coefficient

Output Offset, V

OSO

Average Temperature

Coefficient

Offset RTI vs. Supply (PSR) VS = 2.7 V to 36 V

G = 1 80 90 dB G = 10 100 105 dB G = 100 105 110 dB G = 1000 105 110 dB

INPUT CURRENT

Input Bias Current

1

T T

Average Temperature

Coefficient

Input Offset Current TA = +25°C 2 1 nA T T

Average Temperature

Coefficient

= 0 V, TA = 25°C, G = 1, RL = 10 k, specifications referred to input, unless otherwise noted.

REF

Test Conditions/

A Grade B Grade

Comments

V

= 0 V to 1.7 V

CM

Tot al noise: e

N

= √(e

2

+ (eNO/G)2)

NI

Total offset voltage:

= V

+ (V

V

OS

OSI

T

= −40°C to +125°C 0.5 3 0.5 1.5 μV/°C

A

OSO

/G)

1000 500 μV

= −40°C to +125°C 2 12 1 8 μV/°C

T

A

T

= +25°C 5 20 30 5 20 30 nA

A

= +125°C 5 15 28 5 15 28 nA

A

= −40°C 5 30 38 5 30 38 nA

A

= −40°C to +125°C 70 70 pA/°C

T

A

= +125°C 2 1 nA

A

= −40°C 3 1 nA

A

T

= −40°C to +125°C 5 5 pA/°C

A

Rev. 0 | Page 6 of 28

AD8426

Parameter Min Typ Max Min Typ Max Unit

Test Conditions/ Comments

REFERENCE INPUT

RIN 100 100 kΩ IIN 7 7 μA Voltage Range −VS +VS −VS +VS V Reference Gain to Output 1 1 V/V Reference Gain Error 0.01 0.01 %

GAIN G = 1 + (49.4 kΩ/RG)

Gain Range 1 1000 1 1000 V/V Gain Error

G = 1 V G = 5 to 1000 V

Gain vs. Temperature

2

= 0.8 V to 1.8 V 0.05 0.05 %

OUT

= 0.2 V to 2.5 V 0.3 0.1 %

OUT

G = 1 TA = −40°C to +85°C 5 1 ppm/°C T

= +85°C to +125°C 5 2 ppm/°C

A

G > 1 TA = −40°C to +125°C −100 −100 ppm/°C

INPUT

= 0 V, +VS = 2.7 V

−V

S

to 36 V

Input Impedance

Differential 0.8||2 0.8||2 GΩ||pF Common Mode 0.4||2 0.4||2 GΩ||pF

Input Operating Voltage

Range

3

T T

TA = +25°C −0.1 +VS − 0.7 −0.1 +VS − 0.7 V

= +125°C −0.05 +VS − 0.6 −0.05 +VS − 0.6 V

A

= −40°C −0.15 +VS − 0.9 −0.15 +VS − 0.9 V

A

Input Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40 V

OUTPUT

Output Swing

RL = 10 kΩ to 1.35 V TA = −40°C to +125°C 0.1 +VS − 0.1 0.1 +VS − 0.1 V

Short-Circuit Current 13 13 mA

POWER SUPPLY

Operating Range Single-supply operation 2.2 36 2.2 36 V

= 0 V, +VS = 2.7 V

Quiescent Current

−V

S

(Per Amplifier) T T T T

= +25°C 325 400 325 400 μA

A

= −40°C 250 325 250 325 μA

A

= +85°C 425 500 425 500 μA

A

= +125°C 475 550 475 550 μA

A

TEMPERATURE RANGE −40 +125 −40 +125 °C

1

The input stage uses PNP transistors; therefore, input bias current always flows into the part.

2

The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.

3

Input voltage range of the AD8426 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.

See the section for more information. Input Voltage Range

A Grade B Grade

Rev. 0 | Page 7 of 28

AD8426

Dynamic Performance Specifications

+VS = 2.7 V, −VS = 0 V, V

Table 6. Single-Ended Output Configuration (Both Amplifiers)

Parameter Min Typ Max Min Typ Max Unit

DYNAMIC RESPONSE

Small Signal −3 dB Bandwidth

G = 1 1000 1000 kHz G = 10 160 160 kHz G = 100 20 20 kHz G = 1000 2 2 kHz

Settling Time 0.01% 2 V step

G = 1 6 6 μs G = 10 6 6 μs G = 100 35 35 μs G = 1000 750 750 μs

Slew Rate

G = 1 0.4 0.4 V/μs G = 5 to 100 0.6 0.6 V/μs

= 0 V, TA = 25°C, G = 1, RL = 10 k, specifications referred to input, unless otherwise noted.

REF

Test Conditions/ Comments

A Grade B Grade

Table 7. Differential Output Configuration

Parameter Min Typ Max Min Typ Max Unit

DYNAMIC RESPONSE

Small Signal −3 dB Bandwidth

G = 1 850 850 kHz G = 10 300 300 kHz G = 100 30 30 kHz G = 1000 2 2 kHz

Settling Time 0.01% 2 V step

G = 1 25 25 μs G = 10 15 15 μs G = 100 80 80 μs G = 1000 300 300 μs

Slew Rate

G = 1 0.4 0.4 V/μs G = 5 to 100 0.6 0.6 V/μs

Test Conditions/ Comments

A Grade B Grade

Rev. 0 | Page 8 of 28

AD8426

ABSOLUTE MAXIMUM RATINGS

Table 8.

Parameter Rating

Supply Voltage ±18 V Output Short-Circuit Current Indefinite Maximum Voltage at −INx or +INx −VS + 40 V Minimum Voltage at −INx or +INx +VS − 40 V REFx Voltage ±VS Storage Temperature Range −65°C to +150°C Specified Temperature Range −40°C to +125°C Maximum Junction Temperature 130°C ESD

Human Body Model 1.5 kV Charged Device Model 1.5 kV Machine Model 100 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

The θJA value in Tabl e 9 assumes a 4-layer JEDEC standard board with zero airflow.

Table 9.

Package θJA Unit

16-Lead LFCSP (CP-16-19) 86 °C/W

ESD CAUTION

Rev. 0 | Page 9 of 28

AD8426

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

S

+VSOUT1

AD8426

1

–IN1

2

RG1

3

RG1

4

+IN1

5678

S

+V

Figure 2. Pin Configuration

Table 10. Pin Function Descriptions

Pin No. Mnemonic Description

1 −IN1 Negative Input, In-Amp 1 2 RG1 Gain-Setting Resistor Terminal, In-Amp 1 3 RG1 Gain-Setting Resistor Terminal, In-Amp 1 4 +IN1 Positive Input, In-Amp 1 5 +VS Positive Supply 6 REF1 Reference Adjust, In-Amp 1 7 REF2 Reference Adjust, In-Amp 2 8 −VS Negative Supply 9 +IN2 Positive Input, In-Amp 2 10 RG2 Gain-Setting Resistor Terminal, In-Amp 2 11 RG2 Gain-Setting Resistor Terminal, In-Amp 2 12 −IN2 Negative Input, In-Amp 2 13 −VS Negative Supply 14 OUT2 Output, In-Amp 2 15 OUT1 Output, In-Amp 1 16 +VS Positive Supply

–V

OUT2

13141516

–IN2

12

RG2

11

RG2

10

+IN2

9

S

–V

REF1

REF2

09490-002

Rev. 0 | Page 10 of 28

AD8426

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted.

60

50

40

HITS

30

20

10

0

50

40

30

HITS

20

IN-AMP 1 IN-AMP 2

–100 100500–50

CMRR (µV /V)

Figure 3. Typical Distribution for CMRR (G = 1)

IN-AMP 1 IN-AMP 2

40

30

HITS

20

10

0

–21 –20 –19 –18 –17

09490-303

I

BIAS

(nA)

09490-306

Figure 6. Typical Distribution of Input Bias Current, Inverting Input

IN-AMP 1

50

IN-AMP 2

40

30

HITS

20

10

0

–100 100500–50

V

(µV)

OSI

Figure 4. Typical Distribution of Input Offset Voltage

60

IN-AMP 1 IN-AMP 2

50

40

30

HITS

20

10

0

–600 600200 4000–200–400

V

(µV)

OSO

Figure 5. Typical Distribution of Output Offset Voltage

10

0

–21 –20 –19 –18 –17

09490-304

I

BIAS

(nA)

09490-307

Figure 7. Typical Distribution of Input Bias Current, Noninverting Input

IN-AMP 1

70

IN-AMP 2

60

50

40

HITS

30

20

10

0

–0.010 –0.005 0 0.005 0.010

09490-305

GAIN ERROR (%)

09490-308

Figure 8. Typical Distribution of Gain Error (G = 1)

Rev. 0 | Page 11 of 28

AD8426

2.5

2.0

+0.01V, +1.90V

+1.35V, +1.95V

V

REF

= +1.35V

2.5

2.0

+0.01V, +1.90V

+1.35V, +1.94V

V

REF

= +1.35V

1.5

1.0

0.5

+0.01V, +1.28V

V

+0.01V, +0.31V

REF

= 0V

+2.17V, +0.90V

+2.61V, +1.13V

+2.61V, +0.37V

0

INPUT COMMON-MODE VOLTAGE (V)

–0.5

0.00V, –0.45V

–1.0

–0.5 0 0.5 1.0 1.5

+1.35V, –0.41V

2.0

2.5 3.0

OUTPUT VOLTAGE (V)

Figure 9. Input Common-Mode Voltage vs. Output Voltage,

+2.50V, +4.25V

= 0V

REF

+2.50V, –0.40V

= 2.7 V, G = 1

S

+4.64V, +2.03V

V

= +2.5V

REF

+4.90V, +3.03V

+4.90V, +0.82V

Single Supply, V

5

+0.02V, +4.25V

4

3

+0.02V, +2.95V

2

+0.01V, +0.87V

1

0

INPUT COMMON-MODE VOLTAGE (V)

+0.01V, –0.30V

–1

–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 6.05.55.0

V

OUTPUT VOLTAGE (V)

Figure 10. Input Common-Mode Voltage vs. Output Voltage,

Single Supply, V

= 5 V, G = 1

S

1.5

1.0

+0.01V, +1.19V

V

REF

= 0V

+2.46V, +0.72V

+2.60V, +1.11V

0.5

0

–0.5

INPUT COMMON-MODE VOLTAGE (V)

–1.0

09490-103

–0.5 0 0.5 1.0 1.5

+0.01V, +0.05V

+0.01V, –0.40V

+1.35V, –0.55V

OUTPUT VOLTAGE (V)

2.0

+2.61V, +0.08V

2.5 3.0

09490-106

Figure 12. Input Common-Mode Voltage vs. Output Voltage,

Single Supply, V

5

+0.02V, +4.20V

4

3

+0.02V, +2.89V

2

1

+0.01V, +0.69V

0

INPUT COMMON-MODE VOLTAGE (V)

+0.01V, –0.40V

–1

09490-104

–0.5 0 0.5 1.0 2.0 3.0 4.0 5.55.01.52.53.54.5

= 2.7 V, G = 100

S

+2.49V, +4.25V

V

= 0V

REF

+2.49V, –0.30V

+4.77V, +1.71V

OUTPUT VOLTAGE (V)

= +2.50V

V

REF

+4.90V, +3.02V

+4.90V, +0.54V

09490-107

Figure 13. Input Common-Mode Voltage vs. Output Voltage,

Single Supply, V

= 5 V, G = 100

S

6

0V, +4.25V

4

2

–4.93V, +1.77V

+4.87V, +1.79V

0

–2

–4

INPUT COMMON-MODE VOLTAGE (V)

–6

–4.93V, –2.83V

0V, –5.30V

–6 –4 –2 0 2

+4.90V, –2.84V

4

OUTPUT VOLTAGE (V)

Figure 11. Input Common-Mode Voltage vs. Output Voltage,

Dual Supply, V

= ±5 V, G = 1

S

6

09490-105

Rev. 0 | Page 12 of 28

6

0V, +4.24V

4

2

–4.93V, +1.74V

+4.90V, +1.76V

0

–2

–4.93V, –3.15V

–4

INPUT COMMON-MODE VOLTAGE (V)

–6

–6 –4 –2 0 2 4 6

–0.01V, –5.30V

+4.90V, –3.18V

OUTPUT VO LTAGE (V)

Figure 14. Input Common-Mode Voltage vs. Output Voltage,

Dual Supply, V

= ±5 V, G = 100

S

09490-108

AD8426

20

15

10

–14.9V, +6.7V

5

–11.9V, +5.2V

0

–5

–10

–14.9V, –7.6V

INPUT COMMON-MODE VOLTAGE (V)

–15

–20

–20 –1 5 –10 –5 0 5 10 15 20

–11.9V, –6.0V

0V, +14.2V

0V, +11. 2V

V

= ±12V

S

0V, –12.3V

0V, –15.3V

VS = ±15V

+14.8V, +6.8V

+11.9V, +5.3V

+11.8V, –6.5V

+14.8V, –7.9V

OUTPUT VOLTAGE (V)

Figure 15. Input Common-Mode Voltage vs. Output Voltage,

Dual Supply, V

= ±15 V and VS = ±12 V, G = 1

S

09490-109

20

15

10

–14.9V, +6.61V

5

–11.9V, +5.22V

0

–5

–10

INPUT COMMON-MODE VOLTAGE (V)

–14.9V, –8.09V

–15

–20

–20 –1 5 –10 –5 0 5 10 15 20

–11.9V, –6.71V

0V, +14.1V

0V, +11. 2V

V

= ±12V

S

–0.01V, –12.3V

–0.01V, –15.3V

VS = ±15V

+14.8V, +6.64V

+11.8V, +5.25V

+11.8V, –6.63V

+14.8V, –8.18V

OUTPUT VOLTAGE (V)

Figure 18. Input Common-Mode Voltage vs. Output Voltage,

Dual Supply, V

= ±15 V and VS = ±12 V, G = 100

S

09490-112

2.75 VS = 2.7V

2.50

G = 1 –V

= 0V

IN

2.25

2.00

V

OUT

1.75

1.50

1.25

1.00

0.75

OUTPUT VOLTAGE (V)

0.50

I

IN

0.25

0

–0.25

–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40

INPUT VOLTAGE (V)

Figure 16. Input Overvoltage Performance,

Single Supply, V

16

VS = ±15V

14

G = 1

12

–V

= 0V

IN

10

8

6

4

2

0

–2

–4

–6

OUTPUT VOLTAGE (V)

–8

–10

–12

–14

–16

–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40

I

IN

INPUT VOLTAGE (V)

= 2.7 V, G = 1

S

V

OUT

Figure 17. Input Overvoltage Performance,

Dual Supply, V

= ±15 V, G = 1

S

0.6

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

2.75 VS = 2.7V

2.50

G = 100 –V

= 0V

IN

2.25

2.00

V

OUT

1.75

1.50

1.25

1.00

INPUT CURRENT (mA)

0.75

OUTPUT VOLTAGE (V)

0.50

I

IN

0.25

0

–0.25

–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40

09490-110

INPUT VOLTAGE (V)

0.6

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

INPUT CURRENT (mA)

09490-113

Figure 19. Input Overvoltage Performance,

V

OUT

I

IN

= 2.7 V, G = 100

S

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

INPUT CURRENT (mA)

09490-114

Single Supply, V

16

VS = ±15V

14

G = 100

12

–V

= 0V

IN

10

8

6

4

2

0

–2

–4

INPUT CURRENT (mA)

09490-111

–6

OUTPUT VOLTAGE (V)

–8

–10

–12

–14

–16

–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40

INPUT VOLTAGE (V)

Figure 20. Input Overvoltage Performance,

Dual Supply, V

= ±15 V, G = 100

S

Rev. 0 | Page 13 of 28

AD8426

G A

30

28

26

–0.12V

24

22

20

INPUT BIAS CURRENT (nA)

18

16

–0.5 0 0.5 1.0 1.5 2. 0 2.5 3.0 3.5 4. 0 4.5

COMMON-MODE VOLTAGE (V)

Figure 21. Input Bias Current vs. Common-Mode Voltage,

Single Supply, V

= 5 V

S

+4.22V

09490-115

50

45

40

35

–15.1V

30

25

20

15

10

INPUT BIAS CURRENT (nA)

5

0

–5

–16 – 12 –8 –4 0 4 8 12 16

COMMON-MODE VOLTAGE (V)

Figure 24. Input Bias Current vs. Common-Mode Voltage,

Dual Supply, V

= ±15 V

S

+14.1V

09490-118

160

GAIN = 1000

140

GAIN = 100

120

GAIN = 10

GAIN = 1

100

80

60

POSITIVE PSRR (dB)

40

20

0

0.1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz)

Figure 22. Positive PSRR vs. Frequency, RTI

70

GAIN = 1000

60

50

GAIN = 100

40

30

GAIN = 10

20

GAIN (dB)

10

GAIN = 1

0

–10

–20

–30

100 1k 10k 100k 1M 10M

FREQUENCY ( Hz)

VS = ±15V

Figure 23. Gain vs. Frequency, Dual Supply, VS = ±15 V

160

140

GAIN = 1000

120

GAIN = 100 GAIN = 10

100

GAIN = 1

80

TIVE PSRR (dB)

60

NE

40

20

0

09490-322

0.1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz)

09490-325

Figure 25. Negative PSRR vs. Frequency

70

GAIN = 1000

60

50

GAIN = 100

40

30

GAIN = 10

20

GAIN (dB)

10

GAIN = 1

0

–10

–20

09490-323

100 1k 10k 100k 1M 10M

FREQUENCY ( Hz)

09490-326

Figure 26. Gain vs. Frequency, Single Supply, VS = 2.7 V

Rev. 0 | Page 14 of 28

AD8426

160

GAIN = 1000

140

GAIN = 100

GAIN = 10

120

GAIN = 1

100

80

CMRR (dB)

60

40

20

0

0.1 1 10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 27. CMRR vs. Frequency, RTI

120

GAIN = 1000

100

GAIN = 1

80

GAIN = 100

GAIN = 10

BANDWIDTH

LIMITED

BANDWIDTH

LIMITED

30

25

±I

20

15

10

INPUT BIAS CURRENT (nA)

5

0

–45 –25 –5 15 35 55 75 95 115 135

09490-327

TEMPERATURE (°C)

B

I

OS

250

200

150

100

50

0

–50

INPUT OFF SET CURRENT (p A)

09490-330

Figure 30. Input Bias Current and Input Offset Current vs. Temperature

40

20

0

60

CMRR (dB)

40

20

0

0.1 1 10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 28. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance

6

5

4

3

2

1

0

–1

–2

–3

–4

–5

CHANGE IN INPUT OFFSET VOLTAGE (µV)

–6

0 20 40 60 80 10010 30 50 70 90 110 120

WARM-UP TIME (Seconds)

Figure 29. Change in Input Offset Voltage vs. Warm-Up Time

–20

–40

GAIN ERROR (µV/V)

–60

NORMALIZE D AT 25°C

–80

09490-328

–60 –40 –20 0 20 40 60 100 14080 120

TEMPERATURE (°C)

09490-125

Figure 31. Gain Error vs. Temperature, G = 1

10

5

0

–5

CMRR (µV/V)

–10

–15

REPRESENTATI VE DATA NORMALIZE D AT 25°C

–20

09490-329

–60 –40 –20 0 20 40 60 100 14080 120

TEMPERATURE (°C)

09490-126

Figure 32. CMRR vs. Temperature, G = 1

Rev. 0 | Page 15 of 28

AD8426

V

+

S

–0.2

–40°C +25° C +85°C +105°C +125° C

–0.4

–0.6

–0.8

–V

S

INPUT VOLTAGE (V)

–0.2

–0.4

REFERRED TO SUPPLY VOLTAGES

–0.6

–0.8

2 4 6 8 10 12 14 16 18

SUPPLY VOLTAGE (±V

)

S

Figure 33. Input Voltage Limit vs. Supply Voltage

09490-333

15

10

5

0

–5

OUTPUT VOLTAGE SWING (V)

–10

–15

100 1k 100k10k

LOAD RESIST ANCE ()

Figure 36. Output Voltage Swing vs. Load Resistance

–40°C +25°C +85°C +105°C +125°C

09490-130

+

S

–0.1

–0.2

–0.3

–0.4

–40°C +25°C +85°C +105°C +125°C

+0.4

+0.3

OUTPUT VOLTAGE SWING (V)

+0.2

REFERRED TO SUPPLY VOLTAGES

+0.1

–V

S

2 4 6 8 10 12 14 16 18

SUPPLY VOLTAGE (±V

)

S

Figure 34. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ

+

S

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–40°C +25°C +85°C +105°C +125°C

+

S

–0.2

–0.4

–0.6

–0.8

–40°C +25°C +85°C +105°C +125°C

+0.8

+0.6

OUTPUT VOLTAGE SWING (V)

+0.4

REFERRED TO S UPPLY VOLTAGES

+0.2

–V

S

0.01 0.1 101

09490-334

OUTPUT CURRENT (µA)

09490-131

Figure 37. Output Voltage Swing vs. Output Current, G = 1

+1.2

+1.0

+0.8

+0.6

OUTPUT VOLTAGE SWING (V)

REFERRED TO SUPPLY VOLTAGES

+0.4

LINEARITY ( 10ppm/DI V)

+0.2

–V

S

2 4 6 8 10 12 14 16 18

SUPPLY VOLTAGE (±V

)

S

Figure 35. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ

09490-335

Figure 38. Gain Nonlinearity, RL ≥ 10 kΩ, G = 1

OUTPUT VOLTAGE (V)

09490-338

Rev. 0 | Page 16 of 28

AD8426

1k

GAIN = 1

100

LINEARITY (10ppm/DIV)

OUTPUT VOLTAGE (V)

Figure 39. Gain Nonlinearity, RL ≥ 10 kΩ, G = 10

LINEARITY ( 10ppm/DI V)

OUTPUT VOLTAGE (V)

Figure 40. Gain Nonlinearity, RL ≥ 10 kΩ, G = 100

NOISE (n V/ Hz)

09490-339

10

1 100k1k 10k10010

FREQUENCY ( Hz)

GAIN = 100

GAIN = 1000

GAIN = 10

09490-342

Figure 42. Voltage Noise Spectral Density vs. Frequency

GAIN = 1000, 200nV/DIV

GAIN = 1, 1µV/DIV

1s/DIV

09490-340

09490-343

Figure 43. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1, G = 1000

LINEARITY ( 100ppm/DI V)

OUTPUT VOLTAGE (V)

Figure 41. Gain Nonlinearity, RL ≥ 10 kΩ, G = 1000

09490-341

Rev. 0 | Page 17 of 28

1k

100

NOISE (fA/ Hz)

10

1 10 100 1k 10k

FREQUENCY ( Hz)

Figure 44. Current Noise Spectral Density vs. Frequency

09490-344

AD8426

5V/DIV

17µs TO 0.01%

23µs TO 0.001%

0.002%/DIV

1.5pA/DIV 1s/DIV

Figure 45. 0.1 Hz to 10 Hz Current Noise

30

VS= ±15V

27

24

21

18

15

12

9

OUTPUT VOLTAGE (V p-p)

6

VS= +5V

3

0

100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 46. Large Signal Frequency Response

09490-345

50µs/DIV

09490-348

Figure 48. Large Signal Pulse Response and Settling Time,

10 V Step, Dual Supply, V

5V/DIV

42µs TO 0. 01%

60µs TO 0.001%

0.002%/DIV

09490-346

= ±15 V, G = 10

S

100µs/DIV

09490-349

Figure 49. Large Signal Pulse Response and Settling Time,

10 V Step, Dual Supply, V

= ±15 V, G = 100

S

5V/DIV

26µs TO 0. 01%

27µs TO 0.001%

0.002%/DIV

50µs/DIV

Figure 47. Large Signal Pulse Response and Settling Time,

10 V Step, Dual Supply, V

= ±15 V, G = 1

S

09490-347

Rev. 0 | Page 18 of 28

5V/DIV

580µs TO 0. 01%

780µs TO 0. 001%

0.002%/DIV

500µs/DIV

Figure 50. Large Signal Pulse Response and Settling Time,

10 V Step, Dual Supply, V

= ±15 V, G = 1000

S

09490-350

AD8426

20mV/DIV 4µs/DIV

09490-145

Figure 51. Small Signal Pulse Response, RL = 10 kΩ, CL = 100 pF, G = 1

20mV/DIV 4µs/DIV

09490-146

Figure 52. Small Signal Pulse Response, RL = 10 kΩ, CL = 100 pF, G = 10

20mV/DIV 100µs/DIV

09490-148

Figure 54. Small Signal Pulse Response, RL = 10 kΩ, CL = 100 pF, G = 1000

NO LOAD 47pF 100pF 147pF

20mV/DIV 4µs/DIV

09490-149

Figure 55. Small Signal Pulse Response with Various Capacitive Loads,

= Infinity

G = 1, R

L

60

50

20mV/DIV 20µs/DIV

09490-147

Figure 53. Small Signal Pulse Response, RL = 10 kΩ, CL = 100 pF, G = 100

Rev. 0 | Page 19 of 28

40

SETTL ED TO 0.001%

30

20

SETTLING TIME (µs)

10

0

2468101214161820

SETTLED TO 0.01%

STEP SIZ E (V)

Figure 56. Settling Time vs. Step Size, Dual Supply, VS = ±15 V

09490-356

AD8426

R A

760

740

720

700

680

660

SUPPLY CURRENT (µA)

640

620

06124110218

SUPPLY VOLTAGE (±VS)

Figure 57. Supply Current vs. Supply Voltage (Both Amplifiers)

1864

09490-151

70

GAIN = 1000

60

50

GAIN = 100

40

30

GAIN = 10

GAIN (dB)

20

10

GAIN = 1

0

–10

–20

100 1M10k 100k1k

FREQUENCY ( Hz)

Figure 59. Gain vs. Frequency, Differential Output Configuration

09490-359

200

180

160

140

TION (dB)

120

GAIN = 1

100

80

60

CHANNEL SEPA

40

20

0

100 1M10k 100k1k

GAIN = 1000

FREQUENCY ( Hz)

Figure 58. Channel Separation vs. Frequency, RL = 2 kΩ,

09490-358

100

90

80

70

LIMITED BY MEASUREMENT

60

SYSTEM

50

40

30

OUTPUT BALANCE (dB)

20

10

0

1 10 100 1 k 10k 100k 1M 10M

FREQUENCY ( Hz)

09490-360

Figure 60. Output Balance vs. Frequency, Differential Output Configuration

Source Channel at G = 1 and G = 1000

Rev. 0 | Page 20 of 28

AD8426

V

THEORY OF OPERATION

+V

S

–V

S

R1

24.7k

NODE 1

ESD AND

OVERVOLTAGE

+IN

PROTECTION

R

A1 A2

B

+

S

R

G

–V

V

BIAS

S

–V

NODE 4NODE 3

R2

24.7k

NODE 2

S

Q2Q1

R

B

Figure 61. Simplified Schematic

ESD AND

OVERVOLTAGE

PROTECTION

R4

50k

R5

50k

–IN

R3

50k

A3

+V

R6

50k

–V

DIFFERENCE

AMPLIFIER STAGEGAIN STAGE

+V

S

V

OUT

S

–V

S

REF

S

9490-003

ARCHITECTURE

The AD8426 is based on the classic 3-op-amp topology. This topology has two stages: a gain stage (preamplifier) to provide differential amplification, followed by a difference amplifier stage to remove the common-mode voltage. Figure 61 shows a simplified schematic of one of the instrumentation amplifiers in the AD8426.

The first stage works as follows. To maintain a constant voltage across the bias resistor, R diode drop above the positive input voltage. Similarly, A2 keeps Node 4 at a constant diode drop above the negative input voltage. Therefore, a replica of the differential input voltage is placed across the gain setting resistor, R this resistance must also flow through the R1 and R2 resistors, creating a gained differential signal between the A2 and A1 outputs. Note that, in addition to a gained differential signal, the original common-mode signal, shifted up by a diode drop, is also still present.

The second stage is a difference amplifier, composed of A3 and four 50 kΩ resistors. The purpose of this stage is to remove the common-mode signal from the amplified differential signal.

The transfer function of the AD8426 is

V

= G × (V

OUT

where:

G

1 +=

GR

, A1 must keep Node 3 at a constant

B

. The current that flows across

G

− V

) + V

IN+

IN−

REF

k49.4

GAIN SELECTION

Placing a resistor across the RG terminals sets the gain of the

AD8426. The gain can be calculated by referring to Tabl e 11

or by using the following gain equation:

k49.4

R

G

Table 11. Gains Achieved Using 1% Resistors

1% Standard Table Value of RG Calculated Gain

49.9 kΩ 1.990

12.4 kΩ 4.984

5.49 kΩ 9.998

2.61 kΩ 19.93

1.00 kΩ 50.40 499 Ω 100.0 249 Ω 199.4 100 Ω 495.0

49.9 Ω 991.0

The AD8426 defaults to G = 1 when no gain resistor is used. The tolerance and gain drift of the R to the AD8426 specifications to determine the total gain accuracy of the system. When the gain resistor is not used, gain error and gain drift are minimal.

1

−=G

resistor should be added

G

Rev. 0 | Page 21 of 28

AD8426

REFERENCE TERMINAL

The output voltage of the AD8426 is developed with respect to the potential on the reference terminal. This is useful when the output signal needs to be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin to levelshift the output so that the AD8426 can drive a single-supply ADC. The REF pin is protected with ESD diodes and should not exceed either +V

or −VS by more than 0.3 V.

S

For the best performance, source impedance to the REF terminal should be kept below 2 Ω. As shown in Figure 62, the reference terminal, REF, is at one end of a 50 k resistor. Additional impedance at the REF terminal adds to this 50 k resistor and results in amplification of the signal connected to the positive input. The amplification from the additional R can be computed by 2 × (50 k + R

)/100 k + R

REF

.

Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades the CMRR of the amplifier.

INCORRECT

AD8426

V

REF

CORRECT

AD8426

V

REF

Figure 62. Driving the Reference Pin

REF R EF

+

OP1177

–

CORRECT

AD8426

V

REF

+

AD8426

–

INPUT VOLTAGE RANGE

The 3-op-amp architecture of the AD8426 applies gain in the first stage before removing common-mode voltage in the difference amplifier stage. In addition, the input transistors in the first stage shift the common-mode voltage up one diode drop. Therefore, internal nodes between the first and second stages (Node 1 and Node 2 in Figure 61) experience a combination of gained signal, common-mode signal, and a diode drop. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not limited. Figure 9 to Figure 15 and Figure 18 show the allowable commonmode input voltage ranges for various output voltages and supply voltages.

09490-156

Equation 1 to Equation 3 can be used to understand the interaction of the gain (G), common-mode input voltage (V differential input voltage (V The values for the constants (V

), and reference voltage (V

DIFF

, V

+LIMIT

, and V

−LIMIT

CM

REF_LIMIT

),

REF

).

) at different temperatures are shown in Tab l e 1 2. These three equations, along with the input and output voltage range specifications in Tab l e 2 and Tab l e 5 , set the operating boundaries of the part.

GV

×

CM

DIFF

−

2

GV

×

DIFF

+

2

GV

×

2

CM

++

2

V

⎛ ⎜

⎜ ⎜ ⎜

⎝

VV

+−>

S

−+<

S

⎞

VV

⎟

REF

⎟ ⎟ ⎟

⎠

(1)

LIMIT

−

VV

(2)

LIMIT

+

S

VV

−+<

REF_LIMIT

(3)

Table 12. Input Voltage Range Constants for Various Temperatures

Temperature V

−LIMIT

(V) V

+LIMIT

(V) V

REF_LIMIT

(V)

−40°C −0.55 +0.8 +1.3 +25°C −0.35 +0.7 +1.15 +85°C −0.15 +0.65 +1.05 +125°C −0.05 +0.6 +0.9

The common-mode input voltage range shifts upward with temperature. At cold temperatures, the part requires extra headroom from the positive supply, whereas operation near the negative supply has more margin. Conversely, at hot temperatures, the part requires less headroom from the positive supply but is subject to the worst-case conditions for input voltages near the negative supply.

A typical part functions up to the boundaries described in this section. However, for best performance, designing with a few hundred millivolts of extra margin is recommended. As signals approach the boundary, internal transistors begin to saturate, which can affect frequency and linearity performance.

Rev. 0 | Page 22 of 28

AD8426

V

LAYOUT

To ensure optimum performance of the AD8426 at the PCB level, care must be taken in the design of the board layout. The AD8426 pins are arranged in a logical manner to aid in this task.

S

+VSOUT1

AD8426

1

–IN1

2

RG1

3

RG1

4

+IN1

5678

S

+V

Figure 63. Pinout Diagram

Package Considerations

The AD8426 is available in a 16-lead, 4 mm × 4 mm LFCSP with no exposed paddle. The footprint from another 4 mm × 4 mm LFCSP part should not be copied because it may not have the correct lead pitch and lead width dimensions. Refer to the Outline Dimensions section to verify that the corresponding dimensional symbol has the correct dimensions.

Hidden Paddle Package

The AD8426 is available in an LFCSP package with a hidden paddle. Unlike chip scale packages where the pad limits routing capability, this package allows routes and vias directly beneath the chip. In this way, the full space savings of the small LFCSP can be realized. Although the package has no metal in the center of the part, the manufacturing process leaves a very small section of exposed metal at each of the package corners, as shown in Figure 64 and in Figure 73 in the Outline Dimensions section. This metal is connected to −V possibility of a short, vias should not be placed beneath these exposed metal tabs.

BOTTOM VIEW

NOTES

1. EXPOSED METAL TABS AT THE FOUR CORNERS OF THE PACKAGE ARE INTERNALLY CONNECTED TO –V

Figure 64. Hidden Paddle Package, Bottom View

–V

OUT2

13141516

–IN2

12

RG2

11

RG2

10

+IN2

9

S

–V

REF1

REF2

through the part. Because of the

S

HIDDEN PADDLE

EXPOSED METAL TABS

.

S

09490-002

09490-158

Common-Mode Rejection Ratio over Frequency

Poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. Such conversions occur when one input path has a frequency response that is different from the other. To keep CMRR over frequency high, the input source impedance and capacitance of each path should be closely matched. Additional source resistance in the input paths (for example, for input protection) should be placed close to the in-amp inputs to minimize the interaction of the inputs with parasitic capacitance from the PCB traces.

Parasitic capacitance at the gain setting pins can also affect CMRR over frequency. If the board design has a component at the gain setting pins (for example, a switch or jumper), the component should be chosen so that the parasitic capacitance is as small as possible.

Power Supplies

A stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. See the PSRR performance curves in Figure 22 and Figure 25 for more information.

A 0.1 µF capacitor should be placed as close as possible to each supply pin. As shown in Figure 65, a 10 µF capacitor can be used farther away from the part. In most cases, it can be shared by other precision integrated circuits.

+

S

REF

10µF

LOAD

OUT

09490-006

0.1µF

+IN

R

G

AD8426

–IN

0.1µF 10µF

–V

S

Figure 65. Supply Decoupling, REF, and Output Referred to Local Ground

References

The output voltage of the AD8426 is developed with respect to the potential on the reference terminal. Care should be taken to tie the REFx pins to the appropriate local ground. This should also help minimize crosstalk between the two channels.

Rev. 0 | Page 23 of 28

AD8426

T

V

INPUT BIAS CURRENT RETURN PATH

The input bias current of the AD8426 must have a return path to ground. When the source, such as a thermocouple, cannot provide a current return path, one should be created, as shown in Figure 66.

INCORREC

+V

S

AD8426

REF

–V

S

TRANSFORME R

+V

S

AD8426

REF

–V

S

THERMOCOUP LE

+V

S

C

AD8426

C

CAPACITIVEL Y COUPLED

REF

–V

S

f

HIGH-PASS

1

=

2RC

CAPACITIVE LY COUPLED

Figure 66. Creating an Input Bias Current Return Path

10M

CORRECT

TRANSFORME R

THERMOCOUP LE

C

R

C

R

+V

S

AD8426

–V

S

+V

S

AD8426

–V

S

+V

S

AD8426

–V

S

REF

INPUT PROTECTION

The AD8426 has very robust inputs and typically does not need additional input protection. Input voltages can be up to 40 V from the opposite supply rail. For example, with a +5 V positive supply and a −8 V negative supply, the part can safely withstand voltages from −35 V to +32 V. Unlike some other instrumentation amplifiers, the part can handle large differential input voltages even when the part is in high gain. Figure 16, Figure 17, Figure 19, and Figure 20 show the behavior of the part under overvoltage conditions.

09490-007

The other AD8426 terminals should be kept within the supplies. All terminals of the AD8426 are protected against ESD.

For applications where the AD8426 encounters voltages beyond the allowed limits, external current limiting resistors and low leakage diode clamps such as the BAV199L, the FJH1100, or the SP720 should be used.

RADIO FREQUENCY INTERFERENCE (RFI)

RF interference is often a problem when amplifiers are used in applications where there are strong RF signals. The precision circuits in the AD8426 can rectify the RF signals so that they appear as a dc offset voltage error. To avoid this rectification, place a low-pass RC filter at the input of the instrumentation amplifier (see Figure 67). The filter limits both the differential and common-mode bandwidth, as shown in the following equations:

π2

0.1µF

R

G

0.1µF

1

RC

+IN

–IN

1

D

C

+

AD8426

–V

where C

≥ 10 CC.

D

R

4.02k

R

4.02k

DIFF

CM

C

1nF

C

D

10nF

C

1nF

=

uencyFilterFreq

Figure 67. RFI Suppression

CD affects the differential signal, and CC affects the commonmode signal. Values of R and C

should be chosen to minimize

C

RFI. Any mismatch between the R × C and the R × C

AD8426. By using a value of C

than C

C

at the negative input degrades the CMRR of the

C

one order of magnitude larger

D

, the effect of the mismatch is reduced, and performance

is improved.

)2(π2

CCR

+

C

S

10µF

OUT

REF

10µF

S

at the positive input

C

09490-008

Rev. 0 | Page 24 of 28

AD8426

V

APPLICATIONS INFORMATION

PRECISION STRAIN GAGE

The low offset and high CMRR over frequency of the AD8426 make it an excellent candidate for bridge measurements. The bridge can be connected directly to the inputs of the amplifier (see Figure 68).

5

10µF 0.1µF

350

350350

Figure 68. Precision Strain Gage

+IN

+

R

AD8426

G

–

–IN

2.5V

09490-010

DIFFERENTIAL DRIVE

The differential output configuration of the AD8426 has the same excellent dc precision specifications as the single-ended output configuration.

Differential Output Using Both AD8426 Amplifiers

The circuit configuration is shown in Figure 69. The differential output specifications in Tabl e 2, Tab l e 4, Ta b le 5 , and Tab le 7 refer to this configuration only. The circuit includes an RC filter that maintains the stability of the loop.

+IN1

+

10k

100pF

− V

+ V

IN−

REF2

V

+INx

V

)

)/2

OUT+

OUT–

09490-163

R

AD8426

G

–IN1

–

AD8426

+

REF2

Figure 69. Differential Circuit Schematic

The differential output voltage is set by the following equation:

V

DIFF_OUT

= V

OUT+

− V

OUT−

= G × (V

IN+

where:

G

R

G

Ω

k4.49

+=

1

The common-mode output voltage is set by the average of +IN2 and REF2. The transfer function is

V

CM_OUT

= (V

OUT+

+ V

OUT−

)/2 = (V

+IN2

A common application sets the common-mode output voltage to the midscale of a differential ADC. In this case, the ADC reference voltage is sent to the +IN2 terminal, and ground is connected to the REF2 terminal. This produces a commonmode output voltage of half the ADC reference voltage.

2-Channel Differential Output Using a Dual Op Amp

Another differential output topology is shown in Figure 70. Instead of a second in-amp, one-half of a dual op amp creates the inverted output. The recommended dual op amps (the

AD8642 and the AD822) are packaged in an MSOP. This

configuration allows the creation of a dual-channel, precision differential output in-amp with little board area.

Figure 70 shows how to configure the AD8426 for differential output.

+IN

V

BIAS

+

V

OUT+

OUT–

09490-009

AD8426

–IN

REF

RECOMMENDED O P AMPS: AD8642, AD822. RECOMMENDED R VALUES: 5k TO 20k.

Figure 70. Differential Output Using an Op Amp

R

–

R

OP AMP

The differential output voltage is set by the following equation:

V

DIFF_OUT

= V

OUT+

− V

OUT−

= G × (V

IN+

− V

IN−

)

where:

G

R

G

Ω

k4.49

+=

1

The common-mode output voltage is set by the following equation:

V

CM_OUT

= (V

OUT+

− V

OUT−

)/2 = V

BIAS

The advantage of this circuit is that the dc differential accuracy depends on the AD8426 and not on the op amp or the resistors. This circuit takes advantage of the precise control of the AD8426 over its output voltage relative to the reference voltage. Op amp dc performance and resistor matching do affect the dc commonmode output accuracy. However, because common-mode errors are likely to be rejected by the next device in the signal chain, these errors typically have little effect on overall system accuracy.

For best ac performance, an op amp with gain bandwidth of at least 2 MHz and a slew rate of at least 1 V/µs is recommended. Good choices for op amps are the AD8642 and the AD822.

Rev. 0 | Page 25 of 28

AD8426

Tips for Best Differential Output Performance

Keep trace lengths from resistors to the inverting terminal of the op amp as short as possible. Excessive capacitance at this node can cause the circuit to be unstable. If capacitance cannot be avoided, use lower value resistors.

For best linearity and ac performance, a minimum positive supply voltage (+V voltage required for optimum performance, where V

) is required. Table 1 3 shows the minimum supply

S

CM_MAX

indicates the maximum common-mode voltage expected at the input of the AD8426.

Table 13. Minimum Positive Supply Voltage

Temperature Equation

Less than −10°C +VS > (V

−10°C to +25°C +VS > (V More than +25°C +VS > (V

CM_MAX

+ V + V + V

)/2 + 1.4 V

BIAS

)/2 + 1.25 V

BIAS

)/2 + 1.1 V

BIAS

DRIVING A CABLE

All cables have a certain capacitance per unit length, which varies widely with cable type. The capacitive load from the cable may cause peaking in the output response of the AD8426. To reduce the peaking, use a resistor between the AD8426 outputs and the cable (see Figure 71). Because cable capacitance and desired output response vary widely, this resistor is best determined empirically. A good starting point is 50 .

AD8426

DIFFERENTIAL OUTPUT

AD8426

SINGLE OUTPUT

Figure 71. Driving a Cable

The AD8426 operates at such a relatively low frequency that transmission line effects are rarely an issue; therefore, the resistor need not match the characteristic impedance of the cable.

09490-165

Rev. 0 | Page 26 of 28

AD8426

DRIVING AN ADC

Figure 72 shows several different methods of driving an ADC. The ADC in the ADuC7026 microcontroller was chosen for this example because it has an unbuffered, charge sampling architecture that is typical of most modern ADCs. This type of architecture typically requires an RC buffer stage between the ADC and the amplifier to work correctly.

Option 1 shows the minimum configuration required to drive a charge sampling ADC. The capacitor provides charge to the ADC sampling capacitor, and the resistor shields the AD8426 from the capacitance. To keep the AD8426 stable, the RC time constant of the resistor and capacitor needs to stay above 5 µs. This circuit is mainly useful for lower frequency signals.

OPTION 1: DRIVING LOW FREQUENCY SIGNALS

3.3V

AD8426

REF

100

100nF

Option 2 shows a circuit for driving higher frequency signals. It uses a precision op amp (AD8616) with relatively high bandwidth and output drive. This amplifier can drive a resistor and capacitor with a much higher time constant and is, therefore, suited for higher frequency applications.

Option 3 is useful for applications where the AD8426 must operate from a large voltage supply but drives a single-supply ADC. In normal operation, the AD8426 output signal stays within the ADC range, and the AD8616 simply buffers the signal. However, in a fault condition, the output of the AD8426 may go outside the supply range of both the AD8616 and the ADC. This is not a problem in this circuit, because the 10 k resistor between the two amplifiers limits the current into the AD8616 to a safe level.

3.3V

AV

DD

ADC0

ADuC7026

OPTION 2: DRIVING HIGH FREQUENCY SIGNALS

3.3V

AD8426

REF

OPTION 3: PROTECTI NG ADC FROM LARGE VOLTAGES

+15V

REF

–15V

AD8616

3.3V

10k

AD8616

10

10nF

ADC1

ADC2

AGND

09490-065

Figure 72. Driving an ADC

Rev. 0 | Page 27 of 28

AD8426

A

X

OUTLINE DIMENSIONS

4.00

BSC SQ

0.60 MAX

0.60 M

PIN 1

INDICATOR

1.00

0.85

0.80

SEATING

PLANE

12° MAX

13

3.75

BCS SQ

TOP VIEW

0.80 MAX

0.65 TYP

0.35

0.30

0.25

COMPLIANTTOJEDEC STANDARDS MO-263-VBBC

0.05 MAX

0.02 NOM

0.20 REF

0.65

BSC

0.75

0.60

0.50

COPLANARITY

0.08

12

9

8

BOTTOM VIEW

16

1

1.95 REF SQ

4

5

062309-B

Figure 73. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad, with Hidden Paddle

(CP-16-19)

Dimensions shown in millimeters

ORDERING GUIDE

1

Model

AD8426ACPZ-R7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-19 AD8426ACPZ-WP −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-19 AD8426BCPZ-R7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-19 AD8426BCPZ-WP −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-19

1

Z = RoHS Compliant Part.

Temperature Range Package Description Package Option

Rev. 0 | Page 28 of 28

Datasheet AD8426 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

CONNECTION DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DUAL-SUPPLY OPERATION

Dynamic Performance Specifications

SINGLE-SUPPLY OPERATION

Dynamic Performance Specifications

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

ARCHITECTURE

GAIN SELECTION

REFERENCE TERMINAL

INPUT VOLTAGE RANGE

LAYOUT

Package Considerations

Hidden Paddle Package

Common-Mode Rejection Ratio over Frequency

Power Supplies

References

INPUT BIAS CURRENT RETURN PATH

INPUT PROTECTION

RADIO FREQUENCY INTERFERENCE (RFI)

APPLICATIONS INFORMATION

PRECISION STRAIN GAGE

DIFFERENTIAL DRIVE

Differential Output Using Both AD8426 Amplifiers

2-Channel Differential Output Using a Dual Op Amp

Tips for Best Differential Output Performance

DRIVING A CABLE

DRIVING AN ADC

OUTLINE DIMENSIONS

ORDERING GUIDE