R
1-/2-/4-Channel
FEATURES
256-position variable resistance device
Replaces 1, 2, or 4 potentiometers
1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Power shutdown—less than 5 µA
3-wire,SPI-compatible serial data input
10 MHz update data loading rate
2.7 V to 5.5 V single-supply operation
APPLICATIONS
Mechanical potentiometer replacement
Programmable filters, delays, time constants
Volume control, panning
Line impedance matching
Power supply adjustment
GENERAL DESCRIPTION
The AD8400/AD8402/AD8403 provide a single-, dual-, or
quad-channel, 256-position, digitally controlled variable resistor
(VR) device.
ment function as a mechanical potentiometer or variable
resistor. The AD8400 contains a single variable resistor in the
compact SOIC-8 package. The AD8402 contains two independent
variable resistors in space-saving SOIC-14 surface-mount
packages. The AD8403 contains four independent variable
resistors in 24-lead PDIP, SOIC, and TSSOP packages. Each
part contains a fixed resistor with a wiper contact that taps the
fixed resistor value at a point determined by the digital code
loaded into the controlling serial input register. The resistance
between the wiper and either endpoint of the fixed resistor
varies linearly with respect to the digital code transferred into
the VR latch. Each variable resistor offers a completely
programmable value of resistance between the A terminal and
the wiper or the B terminal and the wiper. The fixed A-to-B
terminal resistance of 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ has a ±1%
channel-to-channel matching tolerance with a nominal
temperature coefficient of 500 ppm/°C. A unique switching
circuit minimizes the high glitch inherent in traditional
switched resistor designs, avoiding any make-before-break
or break-before-make operation.
1
These devices perform the same electronic adjust-
(continued on Page 3)
Digital Potentiometers
AD8400/AD8402/AD8403
FUNCTIONAL BLOCK DIAGRAM
8-BIT
LATCH
CK RS
8-BIT
LATCH
CK RS
8-BIT
LATCH
CK RS
8-BIT
LATCH
CK RS
8
8
8
8
AD8403
V
DD
DGND
SDI
CLK
CS
DAC
SELECT
1
2
3
4
A1, A0
2
10-BIT
8
SERIAL
LATCH
D
CK RSQ
SDO SHDNRS
Figure 1.
100
R
)
AB
75
50
(D) (% of Nominal R
WB
25
(D),
WA
R
0
0 64 128 192 255
WA
CODE ( Decimal )
Figure 2. RWA and RWB vs. Code
RDAC1
SHDN
RDAC2
SHDN
RDAC3
SHDN
RDAC4
SHDN
R
WB
A1
W1
B1
AGND1
A2
W2
B2
AGND2
A3
W3
B3
AGND3
A4
W4
B4
AGND4
1092-001
01092-002
1
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
www.analog.com
AD8400/AD8402/AD8403
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution................................................................................ 11
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 4
Electrical Characteristics—10 kΩ Version................................ 4
Electrical Characteristics—50 kΩ and 100 kΩ Versions......... 6
Electrical Characteristics—1 kΩ Version.................................. 8
Electrical Characteristics—All Versions .................................10
Timing Diagrams........................................................................ 10
Absolute Maximum Ratings.......................................................... 11
Serial Data-Word Format.......................................................... 11
REVISION HISTORY
10/05—Rev. C to Rev. D
Updated Format..................................................................Universal
Changes to Features...........................................................................1
Changes to Table 1.............................................................................4
Changes to Table 2.............................................................................6
Changes to Table 3.............................................................................8
Changes to Table 5...........................................................................11
Added Figure 36...............................................................................18
Replaced Figure 37 ..........................................................................19
Changes to Theory of Operation Section.....................................20
Changes to Applications Section...................................................24
Updated Outline Dimensions........................................................26
Changes to Ordering Guide...........................................................28
Pin Configurations and Function Descriptions......................... 12
Typical Performanc e Character istics ........................................... 14
Test Circ uit s..................................................................................... 19
Theory of Operation ...................................................................... 20
Programming the Variable Resistor......................................... 20
Programming the Potentiometer Divider............................... 21
Digital Interfacing...................................................................... 21
Applications..................................................................................... 24
Active Filter .................................................................................24
Outline Dimensions .......................................................................26
Ordering Guide .......................................................................... 28
11/01—Rev. B to Rev. C
Addition of new Figure.....................................................................1
Edits to Specifications.......................................................................2
Edits to Absolute Maximum Ratings..............................................6
Edits to TPCs 1, 8, 12, 16, 20, 24, 35...............................................9
Edits to
the Programming the Variable Resistor Section..........................13
Rev. D | Page 2 of 32
AD8400/AD8402/AD8403
GENERAL DESCRIPTION
(continued from Page 1)
Each VR has its own VR latch that holds its programmed
resistance value. These VR latches are updated from an SPIcompatible, serial-to-parallel shift register that is loaded from
a standard 3-wire, serial-input digital interface. Ten data bits
make up the data-word clocked into the serial input register.
The data-word is decoded where the first two bits determine
the address of the VR latch to be loaded, and the last eight bits
are the data. A serial data output pin at the opposite end of the
serial register allows simple daisy chaining in multiple VR
applications without additional external decoding logic.
RS
The reset (
into the VR latch. The
to-end open-circuit condition on the A terminal and shorts the
wiper to the B terminal, achieving a microwatt power shutdown
state. When
settings put the wiper in the same resistance setting prior to
shutdown. The digital interface is still active in shutdown so
that code changes can be made that will produce new wiper
positions when the device is taken out of shutdown.
) pin forces the wiper to midscale by loading 80H
SHDN
pin forces the resistor to an end-
SHDN
is returned to logic high, the previous latch
The AD8400 is available in the SOIC-8 surface mount. The
AD8402 is available in both surface-mount (SOIC-14) and
14-lead PDIP packages, while the AD8403 is available in a
narrow-body, 24-lead PDIP and a 24-lead, surface-mount
package. The AD8402/AD8403 are also offered in the 1.1 mm
thin TSSOP-14/TSSOP-24 packages for PCMCIA applications.
All parts are guaranteed to operate over the extended industrial
temperature range of −40°C to +125°C.
Rev. D | Page 3 of 32
AD8400/AD8402/AD8403
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—10 KΩ VERSION
VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL
2
R-DNL RWB, VA = no connect −1 ±1/4 +1 LSB
Resistor Nonlinearity2 R-INL RWB, VA = no connect −2 ±1/2 +2 LSB
Nominal Resistance
3
R
AB
TA = 25°C, model: AD840XYY10 8 10 12 kΩ
Resistance Tempco ∆RAB/∆T VAB = VDD, wiper = no connect 500 ppm/°C
Wiper Resistance R
R
Nominal Resistance Match ∆R/R
W
W
AB
VDD = 5V, IW = VDD/RAB 50 100 Ω
VDD = 3V, IW = VDD/RAB 200 Ω
CH 1 to CH 2, CH 3, or CH 4, VAB = VDD, TA = 25°C 0.2 1 %
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)
Resolution N 8 Bits
Integral Nonlinearity
4
INL −2 ±1/2 +2 LSB
Differential Nonlinearity4 DNL VDD = 5 V −1 ±1/4 +1 LSB
DNL VDD = 3 V, TA = 25°C −1 ±1/4 +1 LSB
DNL VDD = 3 V, TA = −40°C to +85°C −1.5 ±1/2 +1.5 LSB
Voltage Divider Tempco ∆VW/∆T Code = 80
Full-Scale Error V
Zero-Scale Error V
WFSE
WZSE
Code = FF
Code = 00
H
H
H
15 ppm/°C
−4 −2.8 0 LSB
0 1.3 2 LSB
RESISTOR TERMINALS
Voltage Range
Capacitance6 Ax, Capacitance Bx C
Capacitance6 Wx C
Shutdown Current
Shutdown Wiper Resistance R
5
7
V
I
A_SD
A, B, W
A, B
W
W_SD
0 V
f = 1 MHz, measured to GND, code = 80
f = 1 MHz, measured to GND, code = 80
VA = VDD, VB = 0 V,
VA = VDD, VB = 0 V,
SHDN
SHDN
= 0
= 0, VDD = 5 V
H
H
75 pF
120 pF
0.01 5 µA
100 200 Ω
DIGITAL INPUTS AND OUTPUTS
Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
IH
IL
IH
IL
OH
OL
IL
VDD = 5 V 2.4 V
VDD = 5 V 0.8 V
VDD = 3 V 2.1 V
VDD = 3 V 0.6 V
RL = 2.2 kΩ to V
DD
V
− 0.1 V
DD
IOL = 1.6 mA, VDD = 5 V 0.4 V
VIN = 0 V or 5 V, VDD = 5 V ±1 µA
Input Capacitance6 CIL 5 pF
POWER SUPPLIES
Power Supply Range VDD range 2.7 5.5 V
Supply Current (CMOS) I
Supply Current (TTL)
Power Dissipation (CMOS)
8
9
DD
I
DD
P
DISS
VIH = VDD or VIL = 0 V 0.01 5 µA
VIH = 2.4 V or 0.8 V, VDD = 5.5 V 0.9 4 mA
VIH = VDD or VIL = 0 V, VDD = 5.5 V 27.5 µW
Power Supply Sensitivity PSS VDD = 5 V ± 10% 0.0002 0.001 %/%
PSS VDD = 3 V ± 10% 0.006 0.03 %/%
1
Max Unit
DD
V
Rev. D | Page 4 of 32
AD8400/AD8402/AD8403
Parameter Symbol Conditions Min Typ
DYNAMIC CHARACTERISTICS
6, 10
1
Max Unit
Bandwidth −3 dB BW_10 K R = 10 kΩ 600 kHz
Total Harmonic Distortion THD
VW Settling Time t
Resistor Noise Voltage e
Crosstalk
1
Typical represents average readings at 25°C and VDD = 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
11
W
S
NWB
C
T
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38.
= 50 µA for VDD = 3 V and IW = 400 µA for VDD = 5 V for the 10 kΩ versions.
I
W
3
VAB = VDD, wiper (VW) = no connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in .
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7
Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8
Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See for a plot of IFigure 28
9
P
is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
DISS
10
All dynamic characteristics use VDD = 5 V.
11
Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.003 %
VA = VDD, VB = 0 V, ±1% error band 2 µs
RWB = 5 kΩ, f = 1 kHz, RS = 0
9 nV/√Hz
VA = VDD, VB = 0 V −65 dB
Figure 37
vs. logic voltage.
DD
Rev. D | Page 5 of 32
AD8400/AD8402/AD8403
ELECTRICAL CHARACTERISTICS—50 KΩ AND 100 KΩ VERSIONS
VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL
2
R-DNL RWB, VA = No Connect −1 ±1/4 +1 LSB
Resistor Nonlinearity2 R-INL RWB, VA = No Connect −2 ±1/2 +2 LSB
Nominal Resistance
R
3
R
AB
AB
TA = 25°C, Model: AD840XYY50 35 50 65 kΩ
TA = 25°C, Model: AD840XYY100 70 100 130 kΩ
Resistance Tempco ∆RAB/∆T VAB = VDD, Wiper = No Connect 500 ppm/°C
Wiper Resistance R
R
Nominal Resistance Match ∆R/R
W
W
AB
VDD = 5V, IW = VDD/R
VDD = 3V, IW = VDD/R
AB
AB
50 100 Ω
200 Ω
CH 1 to CH 2, CH 3, or CH 4, VAB = VDD, TA = 25°C 0.2 1 %
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)
Resolution N 8 Bits
Integral Nonlinearity
4
INL −4 ±1 +4 LSB
Differential Nonlinearity4 DNL VDD = 5 V −1 ±1/4 +1 LSB
DNL VDD = 3 V, TA = 25°C −1 ±1/4 +1 LSB
DNL VDD = 3 V, TA = −40°C to +85°C −1.5 ±1/2 +1.5 LSB
Voltage Divider Tempco ∆VW/∆T Code = 80
Full-Scale Error V
Zero-Scale Error V
WFSE
WZSE
Code = FF
Code = 00
H
H
H
15 ppm/°C
−1 −0.25 0 LSB
0 +0.1 +1 LSB
RESISTOR TERMINALS
Voltage Range
Capacitance6 Ax, Bx CA, C
Capacitance6 Wx C
Shutdown Current
Shutdown Wiper Resistance R
5
7
VA, VB, V
B
W
I
A_SD
W_SD
0 V
W
f = 1 MHz, measured to GND, code = 80
f = 1 MHz, measured to GND, code = 80
VA = VDD, VB = 0 V,
VA = VDD, VB = 0 V,
SHDN
= 0
SHDN
= 0, VDD = 5 V
H
H
15 pF
80 pF
0.01 5 µA
100 200 Ω
DIGITAL INPUTS AND OUTPUTS
Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
IH
IL
IH
IL
OH
OL
IL
VDD = 5 V 2.4 V
VDD = 5 V 0.8 V
VDD = 3 V 2.1 V
VDD = 3 V 0.6 V
RL = 2.2 kΩ to V
DD
V
− 0.1 V
DD
IOL = 1.6 mA, VDD = 5 V 0.4 V
VIN = 0 V or 5 V, VDD = 5 V ±1 µA
Input Capacitance6 CIL 5 pF
POWER SUPPLIES
Power Supply Range VDD range 2.7 5.5 V
Supply Current (CMOS) I
Supply Current (TTL)
Power Dissipation (CMOS)
8
9
DD
I
DD
P
DISS
VIH = VDD or VIL = 0 V 0.01 5 µA
VIH = 2.4 V or 0.8 V, VDD = 5.5 V 0.9 4 mA
VIH = VDD or VIL = 0 V, VDD = 5.5 V 27.5 µW
Power Supply Sensitivity PSS VDD = 5 V ± 10% 0.0002 0.001 %/%
PSS VDD = 3 V ± 10% 0.006 0.03 %/%
1
Max Unit
DD
V
Rev. D | Page 6 of 32
AD8400/AD8402/AD8403
Parameter Symbol Conditions Min Typ
DYNAMIC CHARACTERISTICS
6, 10
1
Max Unit
Bandwidth −3 dB BW_50 K R = 50 kΩ 125 kHz
BW_100 K R = 100 kΩ 71 kHz
Total Harmonic Distortion THD
W
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.003 %
VW Settling Time tS_50 K VA = VDD, VB = 0 V, ±1% error band 9 µs
t
Resistor Noise Voltage e
e
Crosstalk
1
Typicals represent average readings at 25°C and VDD = 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38.
= VDD/R for VDD = 3 V or 5 V for the 50 kΩ and 100 kΩ versions.
I
W
3
VAB = VDD, wiper (VW) = no connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in .
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7
Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8
Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See for a plot of IFigure 28
9
P
DISS
10
All dynamic characteristics use VDD = 5 V.
11
Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
11
is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
_100 K VA = VDD, VB = 0 V, ±1% error band 18 µs
S
C
NWB
NWB
T
_50 K
_100 K
R
= 25 kΩ, f = 1 kHz, RS = 0
WB
R
= 50 kΩ, f = 1 kHz, RS = 0
WB
VA = VDD, VB = 0 V −65 dB
20 nV/√Hz
29 nV/√Hz
Figure 37
vs. logic voltage.
DD
Rev. D | Page 7 of 32
AD8400/AD8402/AD8403
ELECTRICAL CHARACTERISTICS—1 KΩ VERSION
VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL
2
R-DNL RWB, VA = no connect −5 −1 +3 LSB
Resistor Nonlinearity2 R-INL RWB, VA = no connect −4 ±1.5 +4 LSB
Nominal Resistance
3
R
AB
TA = 25°C, model: AD840XYY1 0.8 1.2 1.6 kΩ
Resistance Tempco ∆RAB/∆T VAB = VDD, wiper = no connect 700 ppm/°C
Wiper Resistance R
R
W
W
Nominal Resistance Match ∆R/R
VDD = 5V, IW = VDD/R
VDD = 3V, IW = VDD/R
CH 1 to CH 2, VAB = VDD, TA = 25°C 0.75 2 %
AB
AB
AB
53 100 Ω
200 Ω
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)
Resolution N 8 Bits
Integral Nonlinearity
4
INL −6 ±2 +6 LSB
Differential Nonlinearity4 DNL VDD = 5 V −4 −1.5 +2 LSB
DNL VDD = 3 V, TA = 25°C −5 −2 +5 LSB
Voltage Divider Temperature Coefficient ∆VW/∆T Code = 80H 25 ppm/°C
Full-Scale Error V
Zero-Scale Error V
WFSE
WZSE
Code = FF
Code = 00
H
H
−20 −12 0 LSB
0 6 10 LSB
RESISTOR TERMINALS
Voltage Range
Capacitance6 Ax, Bx CA, C
Capacitance6 Wx C
Shutdown Supply Current
Shutdown Wiper Resistance R
5
7
VA, VB, VW 0 V
f = 1 MHz, measured to GND, code = 80H 75 pF
B
f = 1 MHz, measured to GND, code = 80H 120 pF
VA = VDD, VB = 0 V,
VA = VDD, VB = 0 V,
SHDN
= 0
SHDN
= 0, VDD = 5 V
0.01 5 µA
50 100 Ω
I
W
A_SD
W_SD
DIGITAL INPUTS AND OUTPUTS
Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low V
Input Current I
Input Capacitance6 C
IH
IL
IH
IL
OH
OL
IL
IL
VDD = 5 V 2.4 V
VDD = 5 V 0.8 V
VDD = 3 V 2.1 V
VDD = 3 V 0.6 V
RL = 2.2 kΩ to V
DD
V
− 0.1 V
DD
IOL = 1.6 mA, VDD = 5 V 0.4 V
VIN = 0 V or 5 V, VDD = 5 V ±1 µA
5 pF
POWER SUPPLIES
Power Supply Range VDD range 2.7 5.5 V
Supply Current (CMOS) I
Supply Current (TTL)
Power Dissipation (CMOS)
8
9
DD
I
DD
P
DISS
VIH = VDD or VIL = 0 V 0.01 5 µA
VIH = 2.4 V or 0.8 V, VDD = 5.5 V 0.9 4 mA
VIH = VDD or VIL = 0 V, VDD = 5.5 V 27.5 µW
Power Supply Sensitivity PSS ∆VDD = 5 V ± 10% 0.0035 0.008 %/%
PSS ∆VDD = 3 V ± 10% 0.05 0.13 %/%
1
Max Unit
DD
V
Rev. D | Page 8 of 32
AD8400/AD8402/AD8403
Parameter Symbol Conditions Min Typ
DYNAMIC CHARACTERISTICS
6, 10
1
Max Unit
Bandwidth −3 dB BW_1 K R = 1 kΩ 5,000 kHz
Total Harmonic Distortion THD
VW Settling Time t
Resistor Noise Voltage e
Crosstalk
1
Typicals represent average readings at 25°C and VDD = 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
11
W
S
NWB
C
T
positions. R-DNL measures the relative step change from ideal between successive tap positions. See the test circuit in . I
I
= 2.5 mA for VDD = 5 V for 1 kΩ version.
W
3
VAB = VDD, wiper (VW) = no connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in .
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.
The remaining resistor terminals are left open circuit.
7
Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8
Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See for a plot of IFigure 28
9
P
is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
DISS
10
All dynamic characteristics use VDD = 5 V.
11
Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.015 %
VA = VDD, VB = 0 V, ±1% error band 0.5 µs
RWB = 500 Ω, f = 1 kHz, RS = 0
3 nV/√Hz
VA = VDD, VB = 0 V −65 dB
Figure 38
Figure 37
= 500 µA for VDD = 3 V and
W
vs. logic voltage.
DD
Rev. D | Page 9 of 32
AD8400/AD8402/AD8403
V
ELECTRICAL CHARACTERISTICS—ALL VERSIONS
VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 4.
Parameter Symbol Conditions Min Typ
SWITCHING CHARACTERISTICS
Input Clock Pulse Width tCH, t
Data Setup Time t
Data Hold Time t
CLK to SDO Propagation Delay
CS
Setup Time
CS
High Pulse Width
Reset Pulse Width t
CLK Fall to CS Rise Hold Time
CS
Rise to Clock Rise Setup
1
Typicals represent average readings at 25°C and VDD = 5 V.
2
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.
The remaining resistor terminals are left open circuit.
3
See the timing diagram in for location of measured values. All input control voltages are specified with tFigure 3
timed from a voltage level of 1.6 V. Switching characteristics are measured using V
of 1 V/µs should be maintained.
4
Propagation delay depends on the value of VDD, RL, and CL (see the section). Applications
TIMING DIAGRAMS
1
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
V
DD
0V
Figure 3. Timing Diagram
V
SDI
CLK
CS
OUT
2, 3
4
DAC REG ISTE R LOAD
CL
DS
DH
t
PD
t
CSS
t
CSW
RS
t
CSH
t
CS1
Clock level high or low 10 ns
5 ns
5 ns
RL = 1 kΩ to 5 V, CL ≤ 20 pF 1 25 ns
10 ns
10 ns
50 ns
0 ns
10 ns
= tF = 1 ns (10% to 90% of VDD) and
= 3 V or 5 V. To avoid false clocking, a minimum input logic slew rate
DD
R
t
1
RS
0
V
DD
OUT
01092-003
VDD/2
Figure 5. Reset Timing Diagram
RS
±1% ERROR BAND
1
SDI
(DATA IN)
SDO
(DATA OUT)
CLK
V
OUT
0
1
A'x OR D'x A'x OR D'x
0
t
PD_MIN
1
0
1
CS
0
V
DD
0V
t
CSS
Figure 4. Detailed Timing Diagram
Ax OR DxAx OR Dx
t
DS
t
DH
t
t
CH
t
CL
PD_MAX
t
CS1
t
CSH
±1% ERROR BAND
t
t
S
CSW
±1%
01092-004
1
Max Unit
t
S
±1%
01092-005
Rev. D | Page 10 of 32
AD8400/AD8402/AD8403
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter Rating
VDD to GND −0.3 V, +8 V
VA, VB, VW to GND 0 V, V
DD
Maximum Current
IWB, IWA Pulsed ±20 mA
IWB Continuous (RWB ≤ 1 kΩ, A Open)1±5 mA
IWA Continuous (RWA ≤ 1 kΩ, B Open)1±5 mA
IAB Continuous (RAB = 1 kΩ/10 kΩ/
50 kΩ/100 kΩ)
1
Digital Input and Output Voltage
±5 mA/±500 μA/
±100 μA/±50 μA
0 V, 7 V
to GND
Operating Temperature Range −40°C to +125°C
Maximum Junction Temperature
(T
Maximum)
J
150°C
Storage Temperature −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Package Power Dissipation (TJ max − TA)/θ
JA
Thermal Resistance (θJA)
SOIC (R-8) 158°C/W
PDIP (N-14) 83°C/W
PDIP (N-24) 63°C/W
SOIC (R-14) 120°C/W
SOIC (R-24) 70°C/W
TSSOP-14 (RU-14) 180°C/W
TSSOP-24 (RU-24) 143°C/W
1
Maximum terminal current is bounded by the maximum applied voltage
across any two of the A, B, and W terminals at a given resistance, the maximum
current handling of the switches, and the maximum power dissipation of the
package; VDD = 5 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
SERIAL DATA-WORD FORMAT
Table 6.
ADDR DATA
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB MSB LSB
9
8
2
2
7
2
2
0
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 11 of 32
AD8400/AD8402/AD8403
A
A
A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
B1
2
GND
CS
SDI
3
(Not to Scale)
4
AD8400
TOP VIEW
Figure 6. AD8400 Pin Configuration
Table 7. AD8400 Pin Function Descriptions
Pin No. Mnemonic Description
1 B1 Terminal B RDAC.
2 GND Ground.
3
CS
4 SDI Serial Data Input.
5 CLK Serial Clock Input, Positive Edge Triggered.
6 V
DD
7 W1 Wiper RDAC, Addr = 002.
8 A1 Terminal A RDAC.
Table 8. AD8402 Pin Function Descriptions
Pin No. Mnemonic Description
1 AGND Analog Ground.
2 B2 Terminal B RDAC 2.
3 A2 Terminal A RDAC 2.
4 W2 Wiper RDAC 2, Addr = 012.
5 DGND Digital Ground.
6
7
SHDN
CS
8 SDI Serial Data Input.
9 CLK Serial Clock Input, Positive Edge Triggered.
10
11 V
RS
DD
12 W1 Wiper RDAC 1, Addr = 002.
13 A1 Terminal A RDAC 1.
14 B1 Terminal B RDAC 1.
1
All AGND pins must be connected to DGND.
A1
8
7
W1
6
V
DD
5
CLK
01092-006
GND
W2
DGND
SHDN
CS
B2
A2
1
2
3
AD8402
TOP VIEW
4
(Not to Scale)
5
6
7
14
B1
13
A1
12
W1
11
V
DD
10
RS
9
CLK
8
SDI
01092-007
Figure 7. AD8402 Pin Configuration
GND2
W2
GND4
W4
DGND
SHDN
CS
SDI
B2
A2
B4
A4
1
2
3
4
5
6
(Not to Scale)
7
8
9
10
11
12
AD8403
TOP VIE W
Figure 8. AD8403 Pin Configuration
Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded,
based on the address bits, and loaded into the target DAC register.
Positive Power Supply. Specified for operation at both 3 V and 5 V.
1
1
Terminal A Open Circuit. Shutdown controls Variable Resistor 1 and Variable Resistor 2.
Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded,
based on the address bits, and loaded into the target DAC register.
Active Low Reset to Midscale. Sets RDAC registers to 80H.
Positive Power Supply. Specified for operation at both 3 V and 5 V
24
23
22
21
20
19
18
17
16
15
14
13
B1
A1
W1
AGND1
B3
A3
W3
AGND3
V
DD
RS
CLK
SDO
01092-008
Rev. D | Page 12 of 32
AD8400/AD8402/AD8403
Table 9. AD8403 Pin Function Descriptions
Pin No. Mnemonic Description
1 AGND2 Analog Ground 2.
2 B2 Terminal B RDAC 2.
3 A2 Terminal A RDAC 2.
4 W2 Wiper RDAC 2, Addr = 012.
5 AGND4 Analog Ground 4.
6 B4 Terminal B RDAC 4.
7 A4 Terminal A RDAC 4.
8 W4 Wiper RDAC 4, Addr = 112.
9 DGND Digital Ground.
10
11
SHDN
CS
Active Low Input. Terminal A open circuit. Shutdown controls Variable Resistor 1 through Variable Resistor 4.
Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded,
based on the address bits, and loaded into the target DAC register.
12 SDI Serial Data Input.
13 SDO Serial Data Output. Open drain transistor requires a pull-up resistor.
14 CLK Serial Clock Input, Positive Edge Triggered.
15
16 V
RS
DD
Active Low Reset to Midscale. Sets RDAC registers to 80H.
Positive Power Supply. Specified for operation at both 3 V and 5 V.
17 AGND3 Analog Ground 3.
18 W3 Wiper RDAC 3, Addr = 102.
19 A3 Terminal A RDAC 3.
20 B3 Terminal B RDAC 3.
21 AGND1 Analog Ground 1.
22 W1 Wiper RDAC 1, Addr = 002.
23 A1 Terminal A RDAC 1.
24 B1 Terminal B RDAC 1.
1
All AGND pins must be connected to DGND.
1
1
1
1
1
Rev. D | Page 13 of 32
AD8400/AD8402/AD8403
C
C
TYPICAL PERFORMANCE CHARACTERISTICS
10
8
VDD=3V OR5V
R
= 10kΩ
AB
60
SS = 1205 UNITS
V
DD
T
A
48
=4.5V
=25°C
6
4
RESISTANCE (kΩ)
2
0
0 32 256
R
WB
64 96 128 160 192 224
CODE (Decimal )
R
WA
Figure 9. Wiper to End Terminal Resistance vs. Code
5
4
3
VOLTAGE (V)
2
WB
V
1
0
80
H
FF
H
40
H
20
H
CODE = 10
05
H
012 34 567
IWBCURRENT (mA)
H
TA=25°C
V
Figure 10. Resistance Linearity vs. Conduction Current
1.0
0.5
0
TA=–40°C
R-INL ERROR (LSB)
–0.5
TA=+85°C
TA=+25°C
VDD=5V
Y
36
24
FREQUEN
12
0
40.0 42.5 65. 045.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5
01092-009
WIPER RESISTANCE (Ω)
01092-012
Figure 12. 10 kΩ Wiper-Contact-Resistance Histogram
1.0
0.5
TA=+25°C
0
–0.5
INL NONL INEARI TY ERRO R (LSB)
=5V
DD
01092-010
–1.0
0 32 25664 96 128 160 192 224
DIGITAL INPUT CODE (Decimal)
TA= –40°C
TA=+85°C
VDD=5V
01092-013
Figure 13. Potentiometer Divider Nonlinearity Error vs. Code
60
SS = 184 UNI TS
V
=4.5V
DD
T
=25°C
A
48
Y
36
24
FREQUEN
12
–1.0
0 32 256
64 96 128 160 192 224
DIGITAL INPUT CODE (Decimal)
Figure 11. Resistance Step Position Nonlinearity Error vs. Code
01092-011
0
35 37 5539 41 43 45 47 49 51 53
WIPER RESISTANCE (Ω)
Figure 14. 50 kΩ Wiper-Contact-Resistance Histogram
01092-014
Rev. D | Page 14 of 32
AD8400/AD8402/AD8403
A
60
SS = 184 UNITS
V
DD
T
A
48
=4.5V
=25°C
700
600
C)
°
500
VDD=5V
T
= –40°C/+85 °C
A
= NO CONNECT
V
A
MEASURED
R
WB
36
24
FREQUENCY
12
0
40.0 42.5 65.045.0 47.5 50.0 52.5 55.0 57. 5 60.0 62.5
WIPER RESISTANCE (Ω)
01092-015
Figure 15. 100 kΩ Wiper-Contact-Resistance Histogram
10
RAB(END-TO-END)
8
)
Ω
6
4
L RESISTANCE (k
NOMIN
2
RAB=10kΩ
0
–75 –50 125
–25 0 25 50 75 100
RWB(WIPER-TO-END)
CODE = 80
TEMPERATURE (°C)
H
1092-016
Figure 16. Nominal Resistance vs. Temperature
70
C)
°
60
50
40
30
20
10
0
POTENTIOMETER MODE TEMPCO (ppm/
–10
0 32 16064 96 128
Figure 17. ∆V
CODE (Decimal )
/∆T Potentiometer Mode Tempco
WB
VDD=5V
T
=–40°C/+ 85°C
A
V
=2V
A
=0V
V
B
192 224 256
01092-017
400
300
200
100
RHEOSTAT MO DE TEMPCO (ppm/
0
–100
0 32 16064 96 128
CODE (Decimal )
Figure 18. ∆R
/∆T Rheostat Mode Tempco
WB
20mV
R
W
(20mV/DIV)
CS
(5V/DIV)
TIME 500ns/DIV
Figure 19. One Position Step Change at Half-Scale (Code 7F
6
0
–6
–12
–18
–24
GAIN (dB)
–30
–36
–42
–48
TA=25°C
–54
10 1M100 1k 10k 100k
FREQUENCY (Hz)
CODE = F F
80
40
20
10
08
04
02
01
Figure 20. 10 kΩ Gain vs. Frequency vs. Code
(See Figure 43)
192 224 256
500ns5V
to 80H)
H
01092-018
01092-019
01092-020
Rev. D | Page 15 of 32
AD8400/AD8402/AD8403
∆
0.75
CODE = 80
VDD=5V
SS = 158 UNI TS
0.50
0.25
0
RESISTANCE (%)
WB
–0.25
R
–0.50
–0.75
0 600
H
AVERAGE + 2 SI GMA
AVERAGE – 2 SIGMA
100 300 400
200 500
HOURS OF OPERATION AT 150°C
Figure 21. Long-Term Drift Accelerated by Burn-In
2V
OUTPUT
AVERAGE
10
FILTER = 22kHz
V
=5V
DD
=25°C
T
A
1
0.1
THD + NOISE (%)
0.01
0.001
10 100k100 1k 10k
01092-021
FREQUENCY (Hz)
01092-024
Figure 24. Total Harmonic Distortion Plus Noise vs. Frequency
(See Figure 41 and Figure 42)
45.25µs
V
OUT
(50mV/DIV)
INPUT
5V
TIME 500µs/DIV
Figure 22. Large Signal Settling Time
5µs
01092-022
Figure 25. Digital Feedthrough vs. Time
6
0
–6
–12
–18
–24
GAIN (dB)
–30
–36
–42
–48
–54
1k 10k 1M
FREQUENCY (Hz)
100k
CODE = F F
80
H
40
H
20
H
10
08
04
02
01
H
H
H
H
H
H
01092-023
Figure 23. 50 kΩ Gain vs. Frequency vs. Code
6
0
80
–6
–12
–18
–24
GAIN (dB)
–30
–36
–42
–48
–54
H
40
H
20
H
10
H
08
H
04
H
02
H
01
H
1k 10k 1M
Figure 26. 100 kΩ Gain vs. Frequency vs. Code
50mV
TIME 200ns/DIV
100k
FREQUENCY (Hz)
200ns
CODE = FF
01092-025
H
01092-026
Rev. D | Page 16 of 32
AD8400/AD8402/AD8403
(
(
CODE = 80
VDD=5V
T
X
NORMALIZED GAIN FLATNESS (0.1dB/DIV)
10 10k 1M100k100 1k
=25°C
A
H
R=50kΩ
R = 100k Ω
FREQUENCY (Hz)
Figure 27. Normalized Gain Flatness vs. Frequency
(See Figure 43)
10
TA=25°C
1
VDD=5V
R=10kΩ
01092-027
12
6
0
–6
–12
–18
GAIN (dB)
–24
–30
VIN= 100mV rms
–36
V
DD
=1M
R
L
–42
1k 10k 1M
=5V
f
= 71kHz, R = 100k
–3dB
Ω
FREQUENCY (Hz)
f
= 125kHz, R = 50k
–3dB
f
= 700kHz, R = 10k
–3dB
Ω
100k
Figure 30. −3 dB Bandwidths
1200
A: VDD=5.5V
1000
A)
µ
800
600
CODE = 55
C: VDD=5.5V
CODE = FF
D: VDD=3.3V
CODE = FF
CODE = 55
B: VDD=3.3V
H
H
H
H
Ω
TA=25°C
Ω
01092-030
0.1
– SUPPLY CURRENT (mA)
DD
I
VDD=3V
0.01
01234
DIGITAL INPUT VOLTAGE (V)
Figure 28. Supply Current vs. Digital Input Voltage
80
VDD=+5VDC±1V p-p AC
=25°C
T
A
CODE = 80
CL= 10pF
V
60
40
PSRR (dB)
20
0
100 1M1k 10k 100k
=4V,VB=0V
A
H
FREQUENCY (Hz)
Figure 29. Power Supply Rejection Ratio vs. Frequency
(See Figure 40)
5
01092-028
01092-029
400
– SUPPLY CURRENT
DD
I
200
0
1k 1M 10M10k 100k
FREQUENCY (Hz)
A
Figure 31. Supply Current vs. Clock Frequency
160
140
120
100
Ω)
80
ON
R
60
40
20
0
0123456
VDD=2.7V
V
BIAS
VDD=5.5V
(V)
TA=25°C
Figure 32. AD8403 Incremental Wiper On Resistance vs. V
(See Figure 39)
B
C
D
01092-031
01092-032
DD
Rev. D | Page 17 of 32
AD8400/AD8402/AD8403
(
1
µA)
– SUPPLY CURRENT
DD
I
0.01
0.001
LOGIC INPUT
VOLTAGE = 0, V
0.1
–55 –35
DD
–15 5 25 45 65 85 105 125
TEMPERATURE (°C)
Figure 35. Supply Current vs. Temperature
6
5
RAB= 1kΩ
VDD=5.5V
VDD=3.3V
01092-035
0
–10
GAIN (dB)
–20
0
–45
–90
VDD=5V
PHASE (Degrees)
100k 2M200k 1M
T
=25°C
A
WIPER SET AT
HALF-SCALE 80
400k 4M 6M 10M
Figure 33. 1 kΩ Gain and Phase vs. Frequency
100
VDD=5V
H
FREQUENCY (Hz)
01092-033
SHUTDOWN CURRENT (nA)
A
I
10
1
–55 –35
–15 5 25 45 65 85 105 125
TEMPERATURE (°C)
Figure 34. Shutdown Current vs. Temperature
(mA)
4
WB_MAX
3
2
THEORETICAL I
1
0
0 32 64 96 128 160 192 224 256
01092-034
RAB= 10kΩ
RAB= 50kΩ
RAB= 100kΩ
CODE (Decimal)
Figure 36. I
WB_MAX
vs. Code
VA= VB= OPEN
T
=25°C
A
01092-057
Rev. D | Page 18 of 32
AD8400/AD8402/AD8403
V
V
A
V
O
V
TEST CIRCUITS
DUT
V
IN
2.5V DC
B
5V
W
OP279
V
OUT
01092-040
DUT
A
V+
W
B
V+ = V
DD
1LSB = V+/256
V
MS
01092-036
Figure 37. Potentiometer Divider Nonlinearity Error (INL, DNL)
~
OFFSET
GND
Figure 41. Inverting Programmable Gain
NO CONNECT
DUT
A
B
W
I
W
V
MS
Figure 38. Resistor Position Nonlinearity Error
(Rheostat Operations; R-INL, R-DNL)
MS2
DUT
A
B
W
IW=VDD/R
V
W
RW=[V
V
MS1
Figure 39. Wiper Resistance
A
A
V
DD
V+
~
W
B
V
MS
V+ = VDD± 10%
PSRR (dB) = 20LOG
PSS (%/%) =
Figure 40. Power Supply Sensitivity (PSS, PSRR)
01092-037
NOMI NAL
MS1–VMS2
()
%
∆V
MS
%
∆V
DD
IN
2.5V
5
V
OP279
W
~
A
B
DUT
OUT
01092-041
V
OFFSET
GND
Figure 42. Noninverting Programmable Gain
A
V
~
IN
DUT
FFSET
]/I
W
01092-038
GND
B
2.5V
+15V
W
OP42
–15V
V
OUT
01092-042
Figure 43. Gain vs. Frequency
DUT
W
∆V
MS
∆V
DD
01092-039
B
I
SW
RSW=
CODE =
V
BIAS
0.1
I
SW
H
+
0.1V
–
A=NC
01092-043
Figure 44. Incremental On Resistance
Rev. D | Page 19 of 32
AD8400/AD8402/AD8403
THEORY OF OPERATION
The AD8400/AD8402/AD8403 provide a single, dual, and quad
channel, 256-position, digitally controlled variable resistor (VR)
device. Changing the programmed VR setting is accomplished
by clocking in a 10-bit serial data-word into the SDI (Serial
Data Input) pin. The format of this data-word is two address
bits, MSB first, followed by eight data bits, also MSB first.
Table 6 provides the serial register data-word format. The
AD8400/AD8402/AD8403 have the following address assignments for the ADDR decoder, which determines the location
of the VR latch receiving the serial register data in Bit B7 to
Bit B0:
VR# = A1 × 2 + A0 + 1 (1)
The single-channel AD8400 requires A1 = A0 = 0. The dualchannel AD8402 requires A1 = 0. VR settings can be changed
one at a time in random sequence. A serial clock running at
10 MHz makes it possible to load all four VRs under 4 µs
(10 × 4 × 100 ns) for AD8403. The exact timing requirements
are shown in Figure 3, Figure 4, and Figure 5.
The AD8400/AD8402/AD8403 do not have power-on midscale
preset, so the wiper can be at any random position at power-up.
However, the AD8402/AD8403 can be reset to midscale by
RS
asserting the
Both parts have a power shutdown
pin, simplifying initial conditions at power-up.
SHDN
pin that places the
VR in a zero-power-consumption state where Terminal Ax is
open-circuited and the Wiper Wx is connected to Terminal Bx,
resulting in the consumption of only the leakage current in the
VR. In shutdown mode, the VR latch settings are maintained
so that upon returning to the operational mode, the VR settings
return to the previous resistance values. The digital interface is
still active in shutdown, except that SDO is deactivated. Code
changes in the registers can be made during shutdown that will
produce new wiper positions when the device is taken out of
shutdown.
Ax
Wx
SHDN
R
S
R
D7
D6
D5
D4
D3
D2
D1
D0
S
R
S
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the VR (RDAC) between Terminal A
and Terminal B is available with values of 1 kΩ, 10 kΩ, 50 kΩ,
and 100 kΩ. The final digits of the part number determine the
nominal resistance value; that is, 10 kΩ = 10; 100 kΩ = 100.
The nominal resistance (R
accessible by the wiper terminal, and the resulting resistance
can be measured either across the wiper and B terminals (R
or across the wiper and A terminals (R
loaded into the RDAC latch is decoded to select one of the
256 possible settings. The wiper’s first connection starts at the
B terminal for data 00
contact resistance of 50 Ω. The second connection (for the 10 kΩ
part) is the first tap point located at 89 Ω = [R
resistance) + R
= 39 Ω + 50 Ω] for data 01H. The third
W
connection is the next tap point representing 78 Ω + 50 Ω =
128 Ω for data 02
. Each LSB data value increase moves the
H
wiper up the resistor ladder until the last tap point is reached at
10,011 Ω. Note that the wiper does not directly connect to the
B terminal even for data 00
diagram of the equivalent RDAC circuit.
The AD8400 contains one RDAC, the AD8402 contains
two independent RDACs, and the AD8403 contains four
independent RDACs. The general transfer equation that
determines the digitally programmed output resistance
between Wx and Bx is
()
DR +×=
where D, in decimal, is the data loaded into the 8-bit RDAC#
latch, and R
is the nominal end-to-end resistance.
AB
For example, when the A terminal is either open-circuited or
tied to the Wiper W, the following RDAC latch codes result in
the following R
(for the 10 kΩ version):
WB
Table 10.
D (Dec)
R
(Ω)
WB
255 10,011 Full scale
128 5,050
1 89 1 LSB
0 50 Zero-scale (wiper contact resistance)
) of the VR has 256 contact points
AB
). The 8-bit data-word
WA
. This B terminal connection has a wiper
H
(nominal
AB
. See Figure 45 for a simplified
H
D
256
(2)
RR
WABWB
Output State
Midscale (
RS
= 0 condition)
WB
)
RDAC
LATCH
AND
DECODER
Figure 45. AD8402/AD8403 Equivalent VR (RDAC) Circuit
R
S
R
S=RNOMI NAL
/256
Bx
01092-044
Note that in the zero-scale condition, a finite wiper resistance of
50 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum value of 5 mA to
avoid degradation or possible destruction of the internal switch
contact.
Rev. D | Page 20 of 32
AD8400/AD8402/AD8403
S
Like a mechanical potentiometer, RDAC is symmetrical. The
resistance between the Wiper W and Terminal A also produces
a digitally controlled complementary resistance, R
. When
WA
these terminals are used, the B terminal can be tied to the wiper
or left floating. R
starts at the maximum and decreases as the
WA
data loaded into the RDAC latch increases. The general transfer
equation for this R
is
WA
−
256
()
DR +×
=
256
D
(3)
RR
WABWA
Here the output voltage is dependent on the ratio of the internal
resistors, not the absolute value; therefore, the temperature drift
improves to 15 ppm/°C.
At the lower wiper position settings, the potentiometer divider
temperature coefficient increases because the contribution of
the CMOS switch wiper resistance becomes an appreciable
portion of the total resistance from the B terminal to the
Wiper W. See Figure 17 for a plot of potentiometer tempco
performance vs. code setting.
where D is the data loaded into the 8-bit RDAC# latch, and R
AB
is the nominal end-to-end resistance.
For example, when the B terminal is either open-circuited or
tied to the Wiper W, the following RDAC latch codes result in
the following R
(for the 10 kΩ version):
WA
Table 11.
D (Dec)
R
(Ω)
WA
Output State
255 89 Full-Scale
128 5,050
Midscale (RS = 0 Condition)
1 10,011 1 LSB
0 10,050 Zero-Scale
The typical distribution of RAB from channel to channel
matches within ±1%. However, device-to-device matching
is process lot dependent and has a ±20% variation. The temperature coefficient, or the change in R
with temperature,
AB
is 500 ppm/°C.
The wiper-to-end-terminal resistance temperature coefficient
has the best performance over the 10% to 100% of adjustment
range where the internal wiper contact switches do not contribute any significant temperature related errors. The graph in
Figure 18 shows the performance of R
tempco vs. code. Using
WB
the potentiometer with codes below 32 results in the larger
temperature coefficients plotted.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper starting
at 0 V up to 1 LSB less than 5 V. Each LSB is equal to the voltage
applied across the A to B terminals divided by the 256-position
resolution of the potentiometer divider. The general equation
defining the output voltage with respect to ground for any given
input voltage applied to the A to B terminals is
DIGITAL INTERFACING
The AD8400/AD8402/AD8403 contain a standard SPIcompatible, 3-wire, serial input control interface. The three
inputs are clock (CLK), chip select (
CS
), and serial data input
(SDI). The positive-edge sensitive CLK input requires clean
transitions to avoid clocking incorrect data into the serial input
register. For the best result, use logic transitions faster than
1 V/µs. Standard logic families work well. If mechanical switches
are used for product evaluation, they should be debounced by
a flip-flop or other suitable means. The block diagrams in
Figure 46, Figure 47, and Figure 48 show the internal digital
CS
circuitry in more detail. When
is taken active low, the clock
loads data into the 10-bit serial register on each positive clock
edge (see Table 12).
CS
CLK
SDI
CS
CLK
SDI DI
D7
D0
RDAC
LATCH
NO. 1
AD8400
10-BIT
SER
REG
DI D0
EN
ADDR
A1
DEC
A0
D7
8
Figure 46. AD8400 Block Diagram
D7
D0
D7
D0
RDAC
LATCH
NO. 1
R
RDAC
LATCH
NO. 2
R
10-BIT
SER
REG
EN
ADDR
A1
DEC
A0
D7
D0
8
GND
AD8402
V
A1
W1
B1
V
A1
W1
B1
A4
W4
B4
DD
1092-045
DD
V +×=
D
256
(4)
VV
BABW
Operation of the digital potentiometer in the voltage divider
HDN
DGND
RS
Figure 47. AD8402 Block Diagram
AGND
01092-046
mode results in more accurate operation over temperature.
Rev. D | Page 21 of 32
AD8400/AD8402/AD8403
A
V
A1
W1
B1
A4
W4
B4
DD
01092-047
CLK
SDO
SDI
SHDN
CS
DO
SER
REG
DI
DGND
EN
ADDR
A1
DEC
A0
D7
D7
RDAC
LATCH
NO. 1
R
D0
AD8403
RS
D7
RDAC
LATCH
NO. 4
R
D0
AGND
D0
8
Figure 48. AD8403 Block Diagram
Table 12. Input Logic Control Truth Table
1
CLK CS RS SHDN Register Activity
L L H H No SR effect; enables SDO pin
P L H H
Shift one bit in from the SDI pin. The
10th previously entered bit is shifted
out of the SDO pin.
X P H H
Load SR data into RDAC latch based
on A1, A0 decode (Table 13).
X H H H No operation
X X L H
Sets all RDAC latches to midscale,
wiper centered, and SDO latch
cleared
X H P H Latches all RDAC latches to 80
X H H L
Open-circuits all Resistor A terminals,
H
connects W to B, turns off SDO
1
P = positive edge, X = don’t care, SR = shift register
output transistor.
The serial data output (SDO) pin, which exists only on the
AD8403 and not on the AD8400 or AD8402, contains an
open-drain, n-channel FET that requires a pull-up resistor to
transfer data to the SDI pin of the next package. The pull-up
resistor termination voltage may be larger than the V
(but less than the max V
of 8 V) of the AD8403 SDO output
DD
device. For example, the AD8403 could operate at V
supply
DD
= 3.3 V,
DD
and the pull-up for interface to the next device could be set at 5 V.
This allows for daisy-chaining several RDACs from a single processor serial data line. The clock period needs to be increased
when using a pull-up resistor to the SDI pin of the following
device in the series. Capacitive loading at the daisy-chain node
SDO to SDI between devices must be accounted for in order to
transfer data successfully. When daisy chain is used,
CS
should
be kept low until all the bits of every package are clocked into
their respective serial registers and the address and data bits are
in the proper decoding location.
If two AD8403 RDACs are daisy-chained, it requires 20 bits
of address and data in the format shown in Table 6. During
SHDN
shutdown (
= logic low), the SDO output pin is forced
to the off (logic high) state to disable power dissipation in the
pull-up resistor. See Figure 50 for equivalent SDO output circuit
schematic.
The data setup and hold times in the specification table determine the data valid time requirements. The last 10 bits of the
CS
data-word entered into the serial register are held when
CS
returns high. At the same time
goes high it gates the address
decoder, which enables one of the two (AD8402) or four (AD8403)
positive edge-triggered RDAC latches. See Figure 49 and Table 13.
Table 13. Address Decode Table
A1 A0 Latch Decoded
0 0 RDAC#1
0 1 RDAC#2
1 0 RDAC#3 AD8403 Only
1 1 RDAC#4 AD8403 Only
CS
CLK
SDI
ADDR
DECODE
SERIAL
REGISTER
Figure 49. Equivalent Input Control Logic
D8403
RDAC 1
RDAC 2
RDAC 4
1092-048
The target RDAC latch is loaded with the last eight bits of the
serial data-word completing one RDAC update. In the case of
AD8403, four separate 10-bit data-words must be clocked in to
change all four VR settings.
SHDN
SDI
CLK
CS
RS
SERIAL
REGISTER
D
CK RS
Q
SDO
1092-049
Figure 50. Detailed SDO Output Schematic of the AD8403
All digital pins are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 51. This structure
applies to digital pins
CS
, SDI, SDO, RS,
SHDN
, and CLK. The
digital input ESD protection allows for mixed power supply
applications where 5 V CMOS logic can be used to drive an
AD8400, AD8402, or AD8403 operating from a 3 V power
supply. Analog Pin A, Pin B, and Pin W are protected with a
20 Ω series resistor and parallel Zener diode (see Figure 52).
Rev. D | Page 22 of 32
AD8400/AD8402/AD8403
A
A
DIGITAL
PINS
1kΩ
LOGIC
01092-050
Figure 51. Equivalent ESD Protection Circuits
20
,B,W
Ω
01092-051
Figure 52. Equivalent ESD Protection Circuit (Analog Pins)
RD
C
A
C
CA= 90.4pF (DW/256) + 30pF CB= 90.4pF [1 – (DW/ 256)] + 30pF
10kΩ
A
C
W
120pF
W
B
C
B
01092-052
Figure 53. RDAC Circuit Simulation Model for RDAC = 10 kΩ
The AC characteristics of the RDAC are dominated by the
internal parasitic capacitances and the external capacitive loads.
The −3 dB bandwidth of the AD8403AN10 (10 kΩ resistor)
measures 600 kHz at half scale as a potentiometer divider.
Figure 30 provides the large signal Bode plot characteristics
of the three available resistor versions 10 kΩ, 50 kΩ, and 100 kΩ.
The gain flatness vs. frequency graph of the 1 kΩ version predicts
filter applications performance (see Figure 33). A parasitic
simulation model has been developed and is shown in Figure 53.
Listing I provides a macro model net list for the 10 kΩ RDAC.
Listing I. Macro Model Net List for RDAC
.PARAM DW=255, RDAC=10E3
*
.SUBCKT DPOT (A,W,)
*
CA A 0 {DW/256*90.4E-12+30E-12}
RAW A W {(1-DW/256)*RDAC+50}
CW W 0 120E-12
RBW W B {DW/256*RDAC+50}
CB B 0 {(1-DW/256)*90.4E-12+30E-12}
*
.ENDS DPOT
The total harmonic distortion plus noise (THD + N), shown in
Figure 41, is measured at 0.003% in an inverting op amp circuit
using an offset ground and a rail-to-rail OP279 amplifier.
Thermal noise is primarily Johnson noise, typically 9 nV/√Hz
for the 10 kΩ version at f = 1 kHz. For the 100 kΩ device,
thermal noise becomes 29 nV/√Hz. Channel-to-channel
crosstalk measures less than −65 dB at f = 100 kHz. To achieve
this isolation, the extra ground pins provided on the package to
segregate the individual RDACs must be connected to circuit
ground. AGND and DGND pins should be at the same voltage
potential. Any unused potentiometers in a package should be
connected to ground. Power supply rejection is typically −35 dB
at 10 kHz. Care is needed to minimize power supply ripple in
high accuracy applications.
Rev. D | Page 23 of 32
AD8400/AD8402/AD8403
APPLICATIONS
The digital potentiometer (RDAC) allows many of the applications of a mechanical potentiometer to be replaced by a solidstate solution offering compact size and freedom from vibration,
shock, and open contact problems encountered in hostile
environments. A major advantage of the digital potentiometer
is its programmability. Any settings can be saved for later recall
in system memory.
The two major configurations of the RDAC include the
potentiometer divider (basic 3-terminal application) and
the rheostat (2-terminal configuration) connections shown
in Figure 37 and Figure 38.
Certain boundary conditions must be satisfied for proper
AD8400/AD8402/AD8403 operation. First, all analog signals
must remain within the GND to V
range used to operate the
DD
single-supply AD8400/AD8402/AD8403. For standard
potentiometer divider applications, the wiper output can be
used directly. For low resistance loads, buffer the wiper with
a suitable rail-to-rail op amp such as the OP291 or the OP279.
Second, for ac signals and bipolar dc adjustment applications,
a virtual ground is generally needed. Whichever method is used
to create the virtual ground, the result must provide the necessary
sink and source current for all connected loads, including
adequate bypass capacitance. Figure 41 shows one channel of
the AD8402 connected in an inverting programmable gain
amplifier circuit. The virtual ground is set at 2.5 V, which allows
the circuit output to span a ±2.5 V range with respect to virtual
ground. The rail-to-rail amplifier capability is necessary for the
widest output swing. As the wiper is adjusted from its midscale
reset position (80
) toward the A terminal (code FFH), the
H
voltage gain of the circuit is increased in successively larger
increments. Alternatively, as the wiper is adjusted toward the B
terminal (code 00
), the signal becomes attenuated. The plot in
H
Figure 54 shows the wiper settings for a 100:1 range of voltage
gain (V/V). Note the ±10 dB of pseudologarithmic gain around
0 dB (1 V/V). This circuit is mainly useful for gain adjustments
in the range of 0.14 V/V to 4 V/V; beyond this range the step
sizes become very large, and the resistance of the driving circuit
can become a significant term in the gain equation.
256
224
192
160
128
96
DIGITAL CODE (Decimal)
64
32
0
0.1 1 10
Figure 54. Inverting Programmable Gain Plot
INVERTING GAIN (V/V)
01092-053
ACTIVE FILTER
The state variable active filter is one of the standard circuits
used to generate a low-pass, high-pass, or band-pass filter.
The digital potentiometer allows full programmability of the
frequency, gain, and Q of the filter outputs. Figure 55 shows
the filter circuit using a 2.5 V virtual ground, which allows a
input and output swing. RDAC2 and RDAC3 set the
±2.5 V
P
LP, HP, and BP cutoff and center frequencies, respectively.
These variable resistors should be programmed with the same
data (as with ganged potentiometers) to maintain the best
Circuit Q. Figure 56 shows the measured filter response at the
band-pass output as a function of the RDAC2 and RDAC3
settings that produce a range of center frequencies from 2 kHz
to 20 kHz. The filter gain response at the band-pass output is
shown in Figure 57. At a center frequency of 2 kHz, the gain is
adjusted over a −20 dB to +20 dB range determined by RDAC1.
Circuit Q is adjusted by RDAC4. For more detailed reading on
the state variable active filter, see Analog Devices’ application
note AN-318.
10kΩ
10kΩ
RDAC4
V
IN
B
RDAC1
B
A1
A2
OP279 × 2
RDAC2
0.01µF
B
A3
RDAC3
0.01µF
B
LOWPAS S
A4
BANDPAS S
HIGH-
1092-054
PAS S
Figure 55. Programmable State Variable Active Filter
Rev. D | Page 24 of 32
AD8400/AD8402/AD8403
40
20
–0.16
20.0000 k
40
20
–19.01
2.00000 k
0
–20
AMPLITUDE (dB)
–40
–60
–80
20 100k100 1k 10k
FREQUENCY (Hz)
Figure 56. Programmed Center Frequency Band-Pass Response
200k
0
–20
AMPLITUDE ( dB)
–40
–60
–80
01092-055
20 100k100 1k 10k
FREQUENCY (Hz)
200k
01092-056
Figure 57. Programmed Amplitude Band-Pass Response
Rev. D | Page 25 of 32
AD8400/AD8402/AD8403
OUTLINE DIMENSIONS
4.00 (0.1574)
3.80 (0.1497)
5.00 (0.1968)
4.80 (0.1890)
85
6.20 (0.2440)
5.80 (0.2284)
41
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
14
1
8
6.20 (0.2441)
7
5.80 (0.2283)
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
8°
1.27 (0.0500)
0°
0.40 (0.0157)
Figure 58. 8-Lead Standard Small outline package [SOIC]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
14
1
PIN 1
0.100 (2.54)
0.210
(5.33)
MAX
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
8
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
7
BSC
0.005 (0.13)
MIN
COMPLIANT TO JEDEC STANDARDS MS-001-AA
0.015
(0.38)
MIN
SEATING
PLANE
0.060 (1.52)
MAX
0.015 (0.38)
GAUGE
PLANE
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.430 (10.92)
MAX
Figure 59. 14-Lead Plastic Dual-In-Line Package [PDIP]
Narrow Body (N-14)
Dimensions shown in inches and (millimeters)
× 45°
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
1.27 (0.0500)
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
BSC
0.51 (0.0201)
0.31 (0.0122)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0197)
0.25 (0.0098)
8°
0°
1.27 (0.0500)
0.40 (0.0157)
× 45°
Figure 60. 14-Lead Standard Small Outline Package [SOIC]
Narrow Body (R-14)
Dimensions shown in millimeters and (inches)
5.10
5.00
4.90
14
4.50
4.40
4.30
PIN 1
1.05
1.00
0.80
0.65
BSC
0.15
0.05
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 61. 14-Lead Thin Shrink Small Outline Package [TSSOP]
8
6.40
BSC
71
0.20
1.20
0.09
MAX
0.30
SEATING
0.19
PLANE
COPLANARITY
0.10
(RU-14)
Dimensions shown in millimeters
8°
0°
0.75
0.60
0.45
Rev. D | Page 26 of 32
AD8400/AD8402/AD8403
Y
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)
24
1
PIN 1
0.100 (2.54)
0.210
(5.33)
MAX
BSC
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001-AF
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
13
12
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.015
(0.38)
MIN
SEATING
PLANE
0.005 (0.13)
MIN
0.060 (1.52)
0.015 (0.38)
GAUGE
PLANE
MAX
Figure 62. 24-Lead Plastic Dual-In-Line Package [PDIP]
Narrow Body (N-24-1)
Dimensions shown in inches and (millimeters)
15.60 (0.6142)
15.20 (0.5984)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.430 (10.92)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
7.90
7.80
7.70
24
PIN 1
0.65
0.15
BSC
0.05
0.30
0.19
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 64. 24-Lead Thin Shrink Small Outline Package [TSSOP]
Dimensions shown in millimeters
13
121
1.20
MAX
SEATING
PLANE
(RU-24)
4.50
4.40
4.30
6.40 BSC
0.20
0.09
8°
0°
0.75
0.60
0.45
24 13
1
0.30 (0.0118)
0.10 (0.0039)
COPLANARIT
1.27 (0.0500)
0.10
BSC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
0.51 (0.020)
0.31 (0.012)
COMPLIANT TO JEDEC STANDARDS MS-013-AD
7.60 (0.2992)
7.40 (0.2913)
12
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
10.65 (0.4193)
10.00 (0.3937)
0.33 (0.0130)
0.20 (0.0079)
Figure 63. 24-Lead Standard Small Outline Package [SOIC]
Wide Body (R-24)
Dimensions shown in millimeters and (inches)
0.75 (0.0295)
0.25 (0.0098)
8°
0°
× 45°
1.27 (0.0500)
0.40 (0.0157)
Rev. D | Page 27 of 32
AD8400/AD8402/AD8403
ORDERING GUIDE
Temperature
Range (°C)
Model
1
Number of
Channels
End-to-End
(kΩ)
R
AB
AD8400AR10 1 10 −40 to +125 8-Lead SOIC R-8 98 AD8400A10
AD8400AR10-REEL 1 10 −40 to +125 8-Lead SOIC R-8 2,500 AD8400A10
AD8400ARZ10
2
1 10 −40 to +125 8-Lead SOIC R-8 98 AD8400A10
AD8400ARZ10-REEL2 1 10 −40 to +125 8-Lead SOIC R-8 2,500 AD8400A10
AD8400AR50 1 50 −40 to +125 8-Lead SOIC R-8 98 AD8400A50
AD8400AR50-REEL 1 50 −40 to +125 8-Lead SOIC R-8 2,500 AD8400A50
AD8400ARZ502 1 50 −40 to +125 8-Lead SOIC R-8 98 AD8400A50
AD8400ARZ50-REEL2 1 50 −40 to +125 8-Lead SOIC R-8 2,500 AD8400A50
AD8400AR100 1 100 −40 to +125 8-Lead SOIC R-8 98 AD8400AC
AD8400AR100-REEL 1 100 −40 to +125 8-Lead SOIC R-8 2,500 AD8400AC
AD8400ARZ1002 1 100 −40 to +125 8-Lead SOIC R-8 98 AD8400AC
AD8400ARZ100-REEL2 1 100 −40 to +125 8-Lead SOIC R-8 2,500 AD8400AC
AD8400AR1 1 1 −40 to +125 8-Lead SOIC R-8 98 AD8400A1
AD8400AR1-REEL 1 1 −40 to +125 8-Lead SOIC R-8 2,500 AD8400A1
AD8400ARZ12 1 1 −40 to +125 8-Lead SOIC R-8 98 AD8400A1
AD8400ARZ1-REEL2 1 1 −40 to +125 8-Lead SOIC R-8 2,500 AD8400A1
AD8402AN10 2 10 −40 to +125 14-Lead PDIP N-14 25 AD8402A10
AD8402AR10 2 10 −40 to +125 14-Lead SOIC R-14 56 AD8402A10
AD8402AR10-REEL 2 10 −40 to +125 14-Lead SOIC R-14 2,500 AD8402A10
AD8402ARU10 2 10 −40 to +125 14-Lead TSSOP RU-14 96 8402A10
AD8402ARU10-REEL 2 10 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A10
AD8402ARUZ102 2 10 −40 to +125 14-Lead TSSOP RU-14 96 8402A10
AD8402ARUZ10-REEL2 2 10 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A10
AD8402ARZ102 2 10 −40 to +125 14-Lead SOIC R-14 96 AD8402A10
AD8402ARZ10-REEL2 2 10 −40 to +125 14-Lead SOIC R-14 2,500 AD8402A10
AD8402AR50 2 50 −40 to +125 14-Lead SOIC R-14 56 AD8402A50
AD8402AR50-REEL 2 50 −40 to +125 14-Lead SOIC R-14 2,500 AD8402A50
AD8402ARU50 2 50 −40 to +125 14-Lead TSSOP RU-14 96 8402A50
AD8402ARU50-REEL 2 50 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A50
AD8402ARUZ502 2 50 −40 to +125 14-Lead TSSOP RU-14 96 8402A50
AD8402ARUZ50-REEL2 2 50 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A50
AD8402ARZ502 2 50 −40 to +125 14-Lead SOIC R-14 96 AD8402A50
AD8402ARZ50-REEL2 2 50 −40 to +125 14-Lead SOIC R-14 2,500 AD8402A50
AD8402AR100 2 100 −40 to +125 14-Lead SOIC R-14 56 AD8402AC
AD8402AR100-REEL 2 100 −40 to +125 14-Lead SOIC R-14 2,500 AD8402AC
AD8402ARU100 2 100 −40 to +125 14-Lead TSSOP RU-14 96 8402A-C
AD8402ARU100-REEL 2 100 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A-C
AD8402ARUZ1002 2 100 −40 to +125 14-Lead TSSOP RU-14 96 8402A-C
AD8402ARUZ100-REEL2 2 100 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A-C
AD8402ARZ1002 2 100 −40 to +125 14-Lead SOIC R-14 96 AD8402AC
AD8402ARZ100-REEL2 2 100 −40 to +125 14-Lead SOIC R-14 2,500 AD8402AC
AD8402AR1 2 1 −40 to +125 14-Lead SOIC R-14 56 AD8402A1
AD8402AR1-REEL 2 1 −40 to +125 14-Lead SOIC R-14 2,500 AD8402A1
AD8402ARU1 2 1 −40 to +125 14-Lead TSSOP RU-14 96 8402A1
AD8402ARU1-REEL 2 1 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A1
AD8402ARUZ12 2 1 −40 to +125 14-Lead TSSOP RU-14 AD8402A1
AD8402ARUZ1-REEL2 2 1 −40 to +125 14-Lead TSSOP RU-14 2,500 AD8402A1
AD8402ARZ12 2 1 −40 to +125 14-Lead SOIC R14 AD8402A1
AD8402ARZ1-REEL2 2 1 −40 to +125 14-Lead SOIC R-14 2,500 AD8402A1
Package
Description
Package
Option
Ordering
Quantity
Branding Information
Rev. D | Page 28 of 32
AD8400/AD8402/AD8403
Temperature
Range (°C)
Model
1
Number of
Channels
End-to-End
(kΩ)
R
AB
AD8403AN10 4 10 −40 to +125 24-Lead PDIP N-24-1 15 AD8403A10
AD8403AR10 4 10 −40 to +125 24-Lead SOIC R-24 31 AD8403A10
AD8403AR10-REEL 4 10 −40 to +125 24-Lead SOIC R-24 1,000 AD8403A10
AD8403ARU10 4 10 −40 to +125 24-Lead TSSOP RU-24 63 8403A10
AD8403ARU10-REEL 4 10 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A10
AD8403ARUZ102 4 10 −40 to +125 24-Lead TSSOP RU-24 63 8403A10
AD8403ARUZ10-REEL2 4 10 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A10
AD8403ARZ102 4 10 −40 to +125 24-Lead SOIC R-24 63 AD8403A10
AD8403ARZ10-REEL2 4 10 −40 to +125 24-Lead SOIC R-24 2,500 AD8403A10
AD8403AN50 4 50 −40 to +125 24-Lead PDIP N-24-1 15 AD8403A50
AD8403AR50 4 50 −40 to +125 24-Lead SOIC R-24 31 AD8403A50
AD8403AR50-REEL 4 50 −40 to +125 24-Lead SOIC R-24 1,000 AD8403A50
AD8403ARU50 4 50 −40 to +125 24-Lead TSSOP RU-24 63 8403A50
AD8403ARUZ502 4 50 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A50
AD8403ARZ502 4 50 −40 to +125 24-Lead SOIC R-24 63 AD8403A50
AD8403ARZ50-REEL2 4 50 −40 to +125 24-Lead SOIC R-24 2,500 AD8403A50
AD8403AR100 4 100 −40 to +125 24-Lead SOIC R-24 31 AD8403A100
AD8403AR100-REEL 4 100 −40 to +125 24-Lead SOIC R-24 1,000 AD8403A100
AD8403ARU100 4 100 −40 to +125 24-Lead TSSOP RU-24 63 8403A100
AD8403ARU100-REEL 4 100 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A100
AD8403ARUZ1002 4 100 −40 to +125 24-Lead TSSOP RU-24 63 8403A100
AD8403ARUZ100-REEL2 4 100 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A100
AD8403ARZ1002 4 100 −40 to +125 24-Lead SOIC R-24 63 AD8403A100
AD8403ARZ100-REEL2 4 100 −40 to +125 24-Lead SOIC R-24 2,500 AD8403A100
AD8403AR1 4 1 −40 to +125 24-Lead SOIC R-24 31 AD8403A1
AD8403AR1-REEL 4 1 −40 to +125 24-Lead SOIC R-24 1,000 AD8403A1
AD8403ARU1 4 1 −40 to +125 24-Lead TSSOP RU-24 63 8403A1
AD8403ARU1-REEL 4 1 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A1
AD8403ARUZ12 4 1 −40 to +125 24-Lead TSSOP RU-24 63 8403A1
AD8403ARUZ1-REEL2 4 1 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A1
AD8403ARZ12 4 1 −40 to +125 24-Lead SOIC R-24 63 AD8403A1
AD8403ARZ1-REEL2 4 1 −40 to +125 24-Lead SOIC R-24 2,500 AD8403A1
AD8403EVAL Evaluation Board
1
Non-lead-free parts have date codes in the format of either YWW or YYWW, and lead-free parts have date codes in the format of #YWW, where Y/YY is the year of
production and WW is the work week. For example, a non-lead-free part manufactured in the 30
lead-free part has the date code of #530.
2
Z = Pb-free part.
Package
Description
th
work week of 2005 has the date code of either 530 or 0530, while a
Package
Option
Ordering
Quantity Branding Information
Rev. D | Page 29 of 32
AD8400/AD8402/AD8403
NOTES
Rev. D | Page 30 of 32
AD8400/AD8402/AD8403
NOTES
Rev. D | Page 31 of 32
AD8400/AD8402/AD8403
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01092-0-10/05(D)
Rev. D | Page 32 of 32
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