Analog Devices AD8392 Service Manual

Low Power, High Output Current, Quad Op Amp,

T

V

Dual-Channel ADSL/ADSL2+ Line Driver

FEATURES

Four current feedback, high current amplifiers Ideal for use as ADSL/ADSL2+ dual-channel Central Office

(CO) line drivers

Low power operation

Power supply operation from ±5 V (+10 V) up to ±12 V (+24 V) Less than 3 mA/Amp quiescent supply current for full

power ADSL/ADSL2+ CO applications (20.4 dBm line power, 5.5 CF)

Three active power modes plus shutdown

High output voltage and current drive

400 mA peak output drive current 44 V p-p differential output voltage

Low distortion

−72 dBc @1 MHz second harmonic

−82 dBc @ 1 MHz third harmonic High speed: 900 V/µs differential slew rate Additional functionality of AD8392ACP

On-chip common-mode voltage generation

APPLICATIONS

ADSL/ADSL2+ CO line drivers XDSL line drives High output current, low distortion amplifiers DAC output buffer

GENERAL DESCRIPTION

The AD8392 is comprised of four high output current, low power consumption, operational amplifiers. It is particularly well suited for the CO driver interface in digital subscriber line systems, such as ADSL and ADSL2+. The driver is capable of providing enough power to deliver 20.4 dBm to a line, while compensating for losses due to hybrid insertion and back termination resistors. In addition, the low distortion, fast slew rate, and high output current capability make the AD8392 ideal for many other applications, including medical instrumentation, DAC output drivers, and other high peak current circuits.

The AD8392 is available in two thermally enhanced packages, a 28-lead TSSOP/EP (AD8392ARE) and a 5 mm × 5 mm 32-lead LFCSP (AD8392ACP). Four bias modes are available via the use of two digital bits (PD1, PD0).

AD8392

PIN CONFIGURATIONS

V

1

EE

+V –V

V

–V +V

IN IN

OUT

V

CC

NC

OUT

IN IN

NC NC

GND

2 3

1

4

1

5

1

6 7 8

3

9

3

10

3

11 12 13 14

1

AD8392

3

NC = NO CONNECT

PD0 1, 2 PD1 1, 2

Figure 1. AD8392ARE, 28-Lead TSSOP/EP

1

IN

+V

32 31 30 29 28 27 2526

1

NC

2

–V

1

IN

3

1

OUT

4

V

CC

5

NC

6

3

OUT

7

3

–V

IN

8

NC

91011121314

3

IN

+V

NC = NO CONNEC

PD1 1, 2

1

3

NC

EE

V

PD0 1, 2

AD8392

3, 4

GND

COM

V

Figure 2. AD8392ACP, 32-Lead LFCSP 5 mm × 5 mm

Additionally, the AD8392ACP provides V common mode voltage generation.

The low power consumption, high output current, high output voltage swing, and robust thermal packaging enable the AD8392 to be used as the CO line drivers in ADSL and other xDSL systems, as well as other high current, single-ended or differential amplifier applications.

GND

EE

V

2

4

1, 2

COM

V

2

4

PD0 3, 4

28

GND

27

NC

26

NC

2

+V

25

IN

–V

2

24

IN

2

V

23

OUT

22

NC

21

V

CC

20

V

4

OUT

19

–VIN4

18

4

+V

IN

17

PD1 3, 4

16

PD0 3, 4

15

V

EE

2

IN

NC

+V

24

NC –V

23

V

22

OUT

21

NC V

20

CC

V

19

OUT

–VIN4

18 17

NC

1615

4

IN

+V

PD1 3, 4

pins for on-chip

COM

04802-0-001

2

IN

2

4

04802-0-002

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

AD8392

REVISION HISTORY

3/05—Rev. 0 to Rev. A

Changes to Figure 1 and Figure 2................................................... 1

Changes to Ordering Guide.......................................................... 16

7/04—Revision 0: Initial Version

Driving Capacitive Loads.......................................................... 12

Thermal Considerations............................................................ 13

Typical ADSL/ADSL2+ Application........................................ 13

Multitone Power Ratio............................................................... 14

Lightning and AC Power Fault................................................. 15

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 16

Rev. A | Page 2 of 16

AD8392

SPECIFICATIONS

VS = ±12 V or +24 V, RL = 100 Ω, G = +5, PD = (0, 0), T = 25°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

−3 dB Small Signal Bandwidth 30 40 MHz V

−3 dB Large Signal Bandwidth 20 25 MHz V Peaking 0.05 dB V Slew Rate 850 900 V/µs V

NOISE/DISTORTION PERFORMANCE

Second Harmonic Distortion −72 dBc fC = 1 MHz, V Third Harmonic Distortion −82 dBc fC = 1 MHz, V Multitone Input Power Ratio −70 dBc 26 kHz to 2.2 MHz, Z Voltage Noise (RTI) 4.3 nV/√Hz f = 10 kHz +Input Current Noise 10 pA/√Hz f = 10 kHz

−Input Current Noise 13 pA/√Hz f = 10 kHz

INPUT CHARACTERISTICS

RTI Offset Voltage −5.0 ±3.0 +5.0 mV V +Input Bias Current 5.0 10.0 µA

−Input Bias Current 10.0 15.0 µA Input Resistance 400 kΩ Input Capacitance 2.0 pF Common-Mode Rejection Ratio 64 68 dB (∆V

OUTPUT CHARACTERISTICS

Differential Output Voltage Swing 42.0 44.0 46.0 V ∆V Single-Ended Output Voltage Swing 21.0 22.0 23.0 V ∆V Linear Output Current 400 mA RL = 10 Ω, fC = 100 kHz

POWER SUPPLY

Operating Range (Dual Supply) ±5 ±12 V Operating Range (Single Supply) 10 24 V Total Quiescent Current

PD1, PD0 = (0, 0) 6.0 7.0 mA/Amp PD1, PD0 = (0, 1) 3.6 4.0 mA/Amp PD1, PD0 = (1, 0) 2.8 3.3 mA/Amp

PD1, PD0 = (1, 1) (Shutdown State) 0.4 1.2 mA/Amp PD = 0 Threshold 0.8 V PD = 1 Threshold 1.8 V +Power Supply Rejection Ratio 64 68 dB ∆V

−Power Supply Rejection Ratio 76 79 dB ∆V

= 0.1 V p-p, RF = 2 kΩ

OUT

= 4 V p-p, RF = 2 kΩ

OUT

= 0.1 V p-p, RF = 2 kΩ

OUT

= 20 V p-p, RF = 2 kΩ

OUT

= 2 V p-p

OUT

= 2 V p-p

OUT

− V

+IN

−IN

)/(∆V

OS, DM (RTI)

OUT

OS, DM (RTI)

IN, CM

/∆VCC, ∆VCC = ±1 V /∆VEE, ∆VEE = ±1 V

= 100 Ω Differential Load

LINE

)

Rev. A | Page 3 of 16

AD8392

VS = ±5 V or +10 V, RL = 100 Ω, G = +5, PD = (0, 0), T = 25°C, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

−3 dB Small Signal Bandwidth 30 40 MHz V

−3 dB Large signal Bandwidth 20 25 MHz V Peaking 0.05 dB V Slew Rate (Rise) 300 350 V/µs V Slew Rate (Fall) 400 450 V/µs V

NOISE/DISTORTION PERFORMANCE

Second Harmonic Distortion −72 dBc fC = 1 MHz, V Third Harmonic Distortion −82 dBc fC = 1 MHz, V Voltage Noise (RTI) 4.3 nV/√Hz f = 10 kHz +Input Current Noise 10 pA/√Hz f = 10 kHz

−Input Current Noise 13 pA/√Hz f = 10 kHz

INPUT CHARACTERISTICS

RTI Offset Voltage −5.0 ±3.0 +5.0 mV V +Input Bias Current 5.0 10.0 µA

−Input Bias Current 10.0 15.0 µA Input Resistance 400 kΩ Input Capacitance 2.0 pF Common-Mode Rejection Ratio 62 66 dB (∆V

OUTPUT CHARACTERISTICS

Differential Output Voltage Swing 14.0 16.0 18.0 V ∆V Single-Ended Output Voltage Swing 7.0 8.0 9.0 V ∆V Linear Output Current 400 mA RL = 10 Ω, fC = 100 kHz

POWER SUPPLY

Operating Range (Dual Supply) ±5 ±12 V Operating Range (Single Supply) +10 +24 V Total Quiescent Current

PD1, PD0 = (0, 0) 5.4 6.0 mA/Amp PD1, PD0 = (0, 1) 3.5 4.0 mA/Amp PD1, PD0 = (1, 0) 2.6 3.0 mA/Amp

PD1, PD0 = (1, 1) (Shutdown State) 0.4 1.0 mA/Amp PD = 0 Threshold 0.8 V PD = 1 Threshold 1.8 V +Power Supply Rejection Ratio 72 76 dB ∆V

−Power Supply Rejection Ratio 64 68 dB ∆V

= 0.1 V p-p, RF = 2 kΩ

OUT

= 4 V p-p, RF = 2 kΩ

OUT

= 0.1 V p-p, RF = 2 kΩ

OUT

= 7 V p-p, RF = 2 kΩ

OUT

= 7 V p-p, RF = 2 kΩ

OUT

= 2 V p-p

OUT

= 2 V p-p

OUT

− V

+IN

−IN

)/(∆V

OS, DM (RTI)

OUT

OS, DM (RTI)

IN, CM

/∆VCC, ∆VCC = ±1 V /∆VEE, ∆VEE = ±1 V

)

Rev. A | Page 4 of 16

AD8392

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

RMS output voltages should be considered. If R

as in single-supply operation, the total power is VS × I

to V

S−

Supply Voltage ±13 V (+26 V)

Power Dissipation See Figure 3

Storage Temperature −65°C to +150°C

Operating Temperature Range −40°C to +85°C

Lead Temperature Range (Soldering 10 sec) 300°C

Junction Temperature 150°C

In single supply with R

Airflow increases heat dissipation, effectively reducing θ more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces

.

the θ

JA

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

Figure 3 shows the maximum safe power dissipation in the package versus the ambient temperature for the LFCSP-32 and TSSOP-28/EP packages on a JEDEC standard 4-layer board. θ values are approximations.

7

device reliability.

THERMAL RESISTANCE

6

θJA is specified for the worst-case conditions, i.e., θJA is specified

for device soldered in circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θ

JA

Unit

LFCSP-32 (CP) 27.27 °C/W

TSSOP-28/EP (RE) 35.33 °C/W

Maximum Power Dissipation

The power dissipated in the package (PD) is the sum of the

quiescent power dissipation and the power dissipated in the

package due to the load drive for all outputs. The quiescent

power is the voltage between the supply pins (V

quiescent current (I

the total drive power is V

). Assuming that the load (RL) is midsupply,

S

/2 × I

S

, some of which is

OUT

dissipated in the package and some in the load (V

) times the

S

× I

OUT

).

5

4

3

2

1

MAXIMUM POWER DISSIPATION (W)

0

–40–30–20–100 102030405060708090

Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

See the Thermal Considerations section for additional thermal design guidance.

to VS−, worst case is V

L

LFCSP-32

TSSOP-28/EP

TEMPERATURE (°C)

is referenced

L

= VS/2.

OUT

TJ = 150°C

. Also,

JA

OUT

JA

04802-0-003

.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features proprie-

tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic

discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of

functionality.

Rev. A | Page 5 of 16

AD8392

TYPICAL PERFORMANCE CHARACTERISTICS

–45

–50

CREST FACTOR = 5.45

950

CREST FACTOR = 5.45

900

850

PD (0, 0)

–55

–60

–65

MULTITONE POWER RATIO (dBc)

–70

15

PD (1, 0) PD (0, 1)

PD (0, 0)

16 18 21

OUTPUT POWER (dBm)

Figure 4. MTPR vs. Output Power (1.75 MHz Empty Bin)

ADSL/ADSL2+ Circuit (Figure 32)

= ±12 V, R

V

S

–50

–60

–70

HD2 PD (0, 0)

–80

–90

HARMONIC DISTORTION (dBc)

–100

0.1 1 10

HD3 PD (1, 0)

= 100 Ω, CF = 5.45

LOAD

HD2 PD (1, 0)

HD2 PD (0, 1)

HD3 PD (0, 0)

HD3 PD (0, 1)

FREQUENCY (MHz)

Figure 5. Harmonic Distortion vs. Frequency

Dual Differential Driver Circuit (Figure 30)

–50

–60

= ±12 V, R

V

S

= 100 Ω, G = +5, V

LOAD

HD2 PD (1, 0) HD2 PD (0, 1)

= 2 V p-p

OUT

800

750

700

650

POWER CONSUMPTION (mW)

600

550

201917

04802-0-004

15 16 17 18 19 20 21

OUTPUT POWER (dBm)

PD (0, 1)

PD (1, 0)

04802-0-007

Figure 7. Power Consumption vs. Output Power (26 kHz to 2.2 MHz)

ADSL/ADSL2+ Circuit (Figure 32)

04802-0-005

= ±12 V, R

V

S

–50

–60

–70

–80

–90

HARMONIC DISTORTION (dBc)

–100

HD2 PD (0, 0)

HD3 PD (1, 0)

0.1 1 10

= 100 Ω, CF = 5.45

LOAD

HD2 PD (1, 0)

HD2 PD (0, 1)

HD3 PD (0, 0)

HD3 PD (0, 1)

FREQUENCY (MHz)

04802-0-008

Figure 8. Harmonic Distortion vs. Frequency

Dual Differential Driver Circuit (Figure 30)

–50

–60

= ±5 V, R

V

S

= 100 Ω, G = +5, V

LOAD

HD2 PD (1, 0) HD2 PD (0, 1)

= 2 V p-p

OUT

HARMONIC DISTORTION (dBc)

–100

–110

–120

–70

–80

HD2 PD (0, 0)

–90

HD3 PD (1, 0)

0.1

11

FREQUENCY (MHz)

Figure 6. Harmonic Distortion vs. Frequency

Quad Op Amp Circuit (Figure 29)

= ±12 V, R

V

S

= 100 Ω, G = +5, V

LOAD

HD3 PD (0, 0) HD3 PD (0, 1)

= 2 V p-p

OUT

HARMONIC DISTORTION (dBc)

0

04802-0-006

Rev. A | Page 6 of 16

–70

–80

–90

–100

–110

–120

0.1

HD2 PD (0, 0)

HD3 PD (1, 0)

FREQUENCY (MHz)

HD3 PD (0, 0) HD3 PD (0, 1)

11

Figure 9. Harmonic Distortion vs. Frequency

Quad Op Amp Circuit (Figure 29)

= ±5 V, R

V

S

= 100 Ω, G = +5, V

LOAD

OUT

= 2 V p-p

0

04802-0-009

AD8392

15

10

5

0

–5

GAIN (dB)

–10

–15

–20

0.1 1 10 100 1000 FREQUENCY (MHz)

PD (0, 1)

PD (0, 0)

PD (1, 0)

Figure 10. Small Signal Frequency Response

Quad Op Amp Circuit (Figure 29)

= ±12 V, R

V

S

15

10

5

0

–5

GAIN (dB)

–10

–15

–20

0.1 1 10 100 1000

= 100 Ω, G = +5, V

LOAD

FREQUENCY (MHz)

= 100 mV p-p

OUT

1Ω

4.7Ω

75Ω

10Ω

Figure 11. Small Signal Frequency Response vs. Load

Quad Op Amp Circuit (Figure 29)

= ±12 V, G = +5, V

V

S

15

= 100 mV p-p

OUT

100Ω

25Ω

50Ω

04802-0-010

04802-0-011

10

5

0

–5

GAIN (dB)

–10

–15

–20

0.1 1 10 100 1000 FREQUENCY (MHz)

PD (0, 1)

PD (0, 0)

PD (1, 0)

Figure 13. Small Signal Frequency Response

Quad Op Amp Circuit (Figure 29)

= ±5 V, R

V

S

0

–10

–20

–30 –40

–50

–60

–70

–80

SIGNAL FEEDTHROUGH (dB)

–90

–100

0.1 1 1000

= 100 Ω, G = +5, V

LOAD

FREQUENCY (MHz)

= 100 mV p-p

OUT

10 100

Figure 14. Signal Feedthrough vs. Frequency

Quad Op Amp Circuit (Figure 29)

= ±12 V, G = +5, VIN = 800 mV p-p, PD (1, 1)

V

S

15

04802-0-013

04802-0-014

10

5

0

–5

GAIN (dB)

–10

–15

–20

0.1 1 10 100 1000 FREQUENCY (MHz)

PD (0, 1)

PD (1, 0)

PD (0, 0)

Figure 12. Large Signal Frequency Response

Quad Op Amp Circuit (Figure 29)

= ±12 V, R

V

S

= 100 Ω, G = +5, V

LOAD

= 4 V p-p

OUT

04802-0-012

Rev. A | Page 7 of 16

10

5

0

–5

GAIN (dB)

–10

–15

–20

0.1 1 10 100 1000 FREQUENCY (MHz)

PD (0, 1)

PD (0, 0)

PD (1, 0)

Figure 15. Large Signal Frequency Response

Quad Op Amp Circuit (Figure 29)

= ±5 V, R

V

S

= 100 Ω, G = +5, V

LOAD

= 4 V p-p

OUT

04802-0-015

AD8392

0.06

0.04

0.02

0

–0.02

OUTPUT VOLTAGE (V)

–0.04

–0.06

–10–8–6–4–20246810

1

TIME (µs)

Figure 16. Small Signal Pulse Response

Quad Op Amp Circuit (Figure 29)

= ±12 V, R

V

S

= 100 Ω, G = +5, 100 mV Step

LOAD

OUTPUT

04802-0-016

2.5

2.0

1.5

1.0

0.5

0

–0.5

–1.0

OUTPUT VOLTAGE (V)

–1.5

–2.0

–2.5

–10–8–6–4–20246810

TIME (µs)

Figure 19. Large Signal Pulse Response

Quad Op Amp Circuit (Figure 29)

V

= ±12 V, R

S

1

= 100 Ω, G = +5, 4 V Step

LOAD

PD PINS

04802-0-019

2

PD PINS

CH1 200mVΩ CH2 1.00mVΩ M 50.0ns A CH2 2.38V

B

W

B

W

Figure 17. Power-Up Time: PD (1, 1) to PD (0, 0)

Quad Op Amp Circuit (Figure 29)

= ±12 V, R

V

S

1 2

CH1 5.00VΩ CH2 5.00VΩ M1.00µs CH1 700mV

= 100 Ω, G = +5, V

LOAD

INPUT

= 1 V p-p

OUT

OUTPUT

∆: 460ns @: –1.32µs

C1 p-p

27.0V C2 p-p

21.4V

Figure 18. Input Overdrive Recovery

Quad Op Amp Circuit (Figure 29)

= ±12 V, R

V

S

= 100 Ω, G = +1, VIN = 27 V p-p

LOAD

004802-0-017

004802-0-018

OUTPUT

2

CH1 200mVΩ

B

CH2 1.00VΩ

W

B

M 400ns CH2 2.38V

W

Figure 20. Power-Down Time: PD (0, 0) to PD (1, 1)

Quad Op Amp Circuit (Figure 29)

= ±12 V, R

V

S

1 2

CH1 1.00VΩ CH2 5.00VΩ M1.00µs CH1 800mV

= 100 Ω, G = +5, V

LOAD

INPUT

= 1 V p-p

OUT

OUTPUT

∆: 420ns @: 2.84µs

C1 p-p

6.00V C2 p-p

21.8V

Figure 21. Output Overdrive Recovery

Quad Op Amp Circuit (Figure 29)

= ±12 V, R

V

S

= 100 Ω, G = +5, VIN = 6 V p-p

LOAD

004802-0-020

004802-0-021

Rev. A | Page 8 of 16

AD8392

0

–10

–20

–30

–40

–50

–60

CROSSTALK (dB)

–70

–80

–90

0.1

0

–10

–20

–30

–40

–50

–60

CROSSTALK (dB)

–70

–80

–90

0.1

100

ADSL CHANNEL 3, 4

FREQUENCY (MHz)

Figure 22. Cross talk vs. Frequency

ADSL/ADSL2+ Circuit (Figure 32)

V

= ±12 V, G = +11, R

S

LOAD

FREQUENCY (MHz)

Figure 23. Cross talk vs. Frequency

Quad Op Amp Circuit (Figure 29)

V

= ±12 V, G = +5, R

S

LOAD

ADSL CHANNEL 1, 2

10 1001

= 100 Ω, VIN = 200 mV p-p

CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4

10 1001

= 100 Ω, VIN = 200 mV p-p

04802-0-022

04802-0-023

0

–10

–20

–30

–40

–50

–60

CROSSTALK (dB)

–70

–80

–90

0.1

45

40

35

30

25

20

15

DIFFERENTIAL OUTPUT SWING (V)

10

1000

DIFF CHANNEL 3, 4

DIFF CHANNEL 1, 2

FREQUENCY (MHz)

10 1001

Figure 25. Cross talk vs. Frequency

Dual Differential Driver Circuit (Figure 30)

V

= ±12 V, G = +5, R

S

= 100 Ω, VIN = 200 mV p-p

LOAD

RESISTIVE LOAD (Ω)

Figure 26. Differential Output Swing vs. R

ADSL/ADSL2+ Circuit (Figure 32)

G = +11

VS = ±12V

VS = ±5V

LOAD

9010 20 30 40 50 60 70 80 100

04802-0-025

04802-0-026

10

VOLTAGE NOISE (nV/ Hz)

1

0.01 0.1 1 10 100 1000 FREQUENCY (kHz)

Figure 24. Voltage Noise vs. Frequency

04802-0-024

Rev. A | Page 9 of 16

100

–I

NOISE

+I

10

CURRENT NOISE (pA/ Hz)

1

0.01 0.1 1 10 100 1000

NOISE

FREQUENCY (kHz)

Figure 27. Current Noise vs. Frequency

04802-0-027

AD8392

1G

100M

10M

1M

TRANSIMPEDANCE

100k

10k

1k

100

10

1

TRANSIMPEDANCE (Ω)

0.1

0.01

0.001

0.0001 100 1G100M10M1M100k10k1k

PHASE

FREQUENCY (Hz)

Figure 28. Open-Loop Transimpedance and Phase

100nF

49.9Ω

499Ω

2kΩ

100Ω

Figure 29. Quad Op Amp Circuit

100nF

49.9Ω

180 160 140 120 100 80 60 40 20 0 –20 –40 –60 –80

04802-0-033

PHASE (Degrees)

04802-0-028

100

10

1

0.1

OUTPUT IMPEDANCE (Ω)

0.01

0.01 1000100100.1

100nF

V

100nF

PD (1, 0)

1

FREQUENCY (MHz)

Figure 31. Output Impedance vs. Frequency

Quad Op Amp Circuit (Figure 29)

= ±12 V, G = +5, PD (0, 0)

V

S

280kΩ

866Ω

6.19Ω

162Ω

CM

162Ω

866Ω

226Ω

100nF

2kΩ

6.19Ω

280kΩ

Figure 32. ADSL/ADSL2+ Circuit

PD (0, 0)

PD (0, 1)

100Ω

04802-0-032

04802-0-031

2kΩ

1kΩ

100nF

2kΩ

49.9Ω

100Ω

04802-0-030

Figure 30. Dual Differential Driver Circuit

Rev. A | Page 10 of 16

AD8392

THEORY OF OPERATION

The AD8392 is a current feedback amplifier with high (400 mA) output current capability. With a current feedback amplifier, the current into the inverting input is the feedback signal, and the open-loop behavior is that of a transimpedance,

/dIIN or TZ.

dV

O

The open-loop transimpedance is analogous to the open-loop voltage gain of a voltage feedback amplifier. Figure 33 shows a simplified model of a current feedback amplifier. Since R proportional to 1/g where g

is the transconductance of the input stage. Basic

m

, the equivalent voltage gain is just TZ × gm,

m

is

IN

analysis of the follower with gain circuit yields

()

Z

ST

+×+

RRGST

FIN

V

O

G

V

×=

IN

Z

where:

R

G += 1

F

R

G

Of course, for a real amplifier there are additional poles that contribute excess phase, and there is a value for R

below which

F

the amplifier is unstable. Tolerance for peaking and desired flatness determines the optimum R

R

G

R

N

V

IN

Figure 33. Simplified Block Diagram

in each application.

F

R

F

R

IN

T

Z

I

IN

V

OUT

04802-0-034

The AD8392 is capable of delivering 400 mA of output current while swinging to within 2 V of either power supply rail. The AD8392 also has a power management system included on-chip. It features four user-programmable power levels (three active power modes as well as the provision for complete shutdown).

R

IN

Since G × R

g

Ω501≈=

m

<< RF for low gains, a current feedback amplifier

IN

has relatively constant bandwidth versus gain, the 3 dB point being set when |T

| = RF.

Z

Rev. A | Page 11 of 16

AD8392

APPLICATIONS

SUPPLIES, GROUNDING, AND LAYOUT

The AD8392 can be powered from either single or dual supplies, with the total supply voltage ranging from 10 V to 24 V. For optimum performance, a well regulated low ripple supply should be used.

As with all high speed amplifiers, close attention should be paid to supply decoupling, grounding, and overall board layout. Low frequency supply decoupling should be provided with 10 µF tantalum capacitors from each supply to ground. In addition, all supply pins should be decoupled with 0.1 µF quality ceramic chip capacitors placed as close as possible to the driver. An internal low impedance ground plane should be used to provide a common ground point for all driver and decoupling capacitor ground requirements. Whenever possible, separate ground planes should be used for analog and digital circuitry.

High speed layout techniques should be followed to minimize parasitic capacitance around the inverting inputs. Some practical examples of these techniques are keeping feedback traces as short as possible and clearing away ground plane in the area of the inverting inputs. Input and output traces should be kept short and as far apart from each other as practical to avoid crosstalk. When used as a differential driver, all differential signal traces should be kept as symmetrical as possible.

RESISTOR SELECTION

In current feedback amplifiers, selection of feedback and gain resistors can impact harmonic distortion performance, bandwidth, and gain flatness. Care should be exercised in the selection of these resistors so that optimum performance is achieved. Table 5 shows some suggested resistor values for use in a variety of gain settings. These values are suggested as a good starting point when designing for any application.

Table 5. Resistor Selection Guide

Gain R

F

1 2.0k Open 2 1.5k 1.5k 5 1.0k 249 10 750 82.5

POWER MANAGEMENT

The AD8392 can be configured in any of three active bias states as well as a shutdown state via the use of two sets of digitally programmable logic pins. Pins PD(0, 1) 1, 2 control Amplifiers 1 and 2, while PD(0, 1) 3, 4 control Amplifiers 3 and 4. These pins can be controlled directly with either 3.3 V or 5 V CMOS logic by using the GND pins as a reference. If left unconnected, the PD pins float low, placing the amplifier in the full bias mode. Refer to the Specifications for the per amplifier quiescent current for each of the available bias states.

R

G

The AD8392 exhibits low output impedance for the three active states. However, the output impedance in the shutdown state (PD1, 0 = 1, 1) is undefined.

DRIVING CAPACITIVE LOADS

When driving a capacitive load, most op amps exhibit peaking in their frequency response. In general, to minimize peaking or to ensure device stability for larger values of capacitive loads, a small series resistor can be added between the op amp output and the load capacitor. Figure 34 shows the frequency response of the AD8392 for various capacitive loads without any series resistance. In this condition, the maximum recommended capacitive load is around 20 pF. As shown in Figure 35, the addition of a 5.1 Ω series resistor limits peaking to approximately 3 dB when driving capacitive loads up to 100 pF.

20

15

10

5

0

GAIN (dB)

–5

–10

–15

20

15

10

GAIN (dB)

–5

–10

–15

499Ω

V

IN

0.1 1 10 100 1000

Figure 34. AD8392 Capacitive Load Frequency Response

5

0

499Ω

V

IN

0.1 1 10 100 1000

Figure 35. AD8392 Capacitive Load Frequency Response

2kΩ

C

50Ω

L

FREQUENCY (MHz)

without Series Resistance

2kΩ

FREQUENCY (MHz)

with Series Resistance

5.1Ω

1kΩ

C

L

1kΩ

100pF

47pF

20pF

15pF

22pF

10pF

04802-0-034

04802-0-035

Rev. A | Page 12 of 16

AD8392

THERMAL CONSIDERATIONS

When using a quad, high output current amplifier, such as the AD8392, special consideration should be given to system level thermal design. In applications such as ADSL/ADSL2+, the AD8392 could be required to dissipate as much as 1.4 W or more on chip. Under these conditions, particular attention should be paid to the thermal design in order to maintain safe operating temperatures on the die. To aid in the thermal design, the thermal information in the Thermal Resistance section can be combined with what follows here.

The information in Table 4 and Figure 3 is based on a standard JEDEC 4-layer board and a maximum die temperature of 150°C. To provide additional guidance and design suggestions, a thermal study was performed under a set of conditions more closely aligned with an actual ADSL/ADSL2+ application.

In a typical ADSL/ADSL2+ line card, component density usually dictates that most of the copper plane used for thermal dissipation be internal. Additionally, each ADSL/ADSL2+ port may be allotted only 1 square inch, or even less, of board space. For these reasons, a special thermal test board was constructed for this study. The 4-layer board measured approximately 4 inches × 4 inches and contained two internal 1 oz copper ground planes, each measuring 2 inches × 3 inches. The top layer contained signal traces and an exposed copper strip ¼ inch × 3 inches to accommodate heat sinking, with no other copper on the top or bottom of the board.

Three 28-lead TSSOPs were placed on the board representing six ADSL channels, or one channel per square inch of copper, with each channel dissipating 700 mW on-chip (1.4 W per package). The die temperature is then measured in still air and in a wind tunnel with calibrated airflow of 100 LFM, 200 LFM, and 400 LFM. Figure 36 shows the power dissipation versus the ambient temperature for each airflow condition. The figure assumes a maximum die temperature of 135°C. No heat sink was used.

4.5

4.0

3.5

3.0

2.5

STILL AIR

2.0

POWER DISSIPATION (W)

1.5

1.0 5 1525354555657585

400LFM

200LFM

100LFM

AMBIENT TEMPERATURE (°C)

Figure 36. Power Dissipation vs. Ambient

Temperature and Air Flow 28-Lead TSSOP/EP

TJ = 135°C

04802-0-036

This data is only provided as guidance to assist in the thermal design process. Due diligence should be performed with regards to power dissipation because there are many factors that can affect thermal performance.

TYPICAL ADSL/ADSL2+ APPLICATION

In a typical ADSL/ADSL2+ application, a differential line driver is used to take the signal from the analog front end (AFE) and drive it onto the twisted pair telephone line. Referring to the typical circuit representation in Figure 37, the differential input appears at V

IN+

and V output is transformer coupled to the telephone line at tip and ring. The common-mode operating point, generally midway between the supplies, is set through V

V

IN+

R

IN

V

IN–

R4

R

BIAS

COM

R

BIAS

R4

Figure 37. Typical ADSL/ADSL2+ Application Circuit

In ADSL/ADSL2+ applications, it is common practice to conserve power by using positive feedback to synthesize the output resistance, thereby lowering the required ohmic value of the line matching resistors, R somewhat unique in that the positive feedback introduced via R3 has the effect of synthesizing the input resistance as well. The following definitions and equations can be used to calculate the resistor values necessary to obtain the desired gain, input resistance, and output resistance for a given application. For simplicity the following calculations assume a lossless transformer.

The following values are used in the design equations and are assumed already known or chosen by the designer.

V

Differential input voltage

IN

R

Desired differential input resistance

IN

N

Transformer turns ratio

V

Differential output voltage at tip and ring

LINE

R

Each is typically 5% to 15% of the transformer reflected

m

line impedance

R2

Recommended in the amplifier data sheet

V

Voltage at the + inputs to the amplifier, approximately ½

P

R

L

(must be less than VIN for positive input resistance)

V

IN

Transformer reflected line impedance

from the AFE, while the differential

IN−

.

COM

R3

V

P

R1

V

P

OA

R

m

R2

R

m

V

OA

R3

. The circuit in Figure 37 is

m

TIP

1:N

RING

R

OUT

04802-0-037

Rev. A | Page 13 of 16

AD8392

N

(

−

(

)

N

Additional definitions for calculating resistor values include:

V

OA

k A

V

β α Note: R1 must be calculated before β and α.

With the above known quantities and definitions, the remaining resistors can readily be calculated.

After building the circuit with the closest 1% resistor values, the actual gain, input resistance, and output resistance can be verified with the following equations.

Voltage at the amplifier outputs Matching resistance reduction factor Gain from VIN to transformer primary Negative feedback factor Positive feedback factor

2

()

kV

+=1

V

β

R1−=

R4−=

R3

R

GAIN

R

LINE

OA

R1

=

+

OA

R2R1

2

RV

P

VV

()

V2

V

=

BIAS

()

LINEtoV

IN

=

IN

1

−

R4

=

OUT

⎛ ⎜

1

− ⎜

⎝

22

P

VVR

PININ

IN

m

()

L

R4R3

α

()

R4R3R4

+−=α

()

k

2

+

⎛

m

⎜

A

β

V

⎜

RR4

⎝

2

RR4

BIAS

RR4R1

()

+

BIAS

R

m

=

k

R

L

R2R1R

2α

+

R4

⎛ ⎜

⎝

RR

L

+++=11β

R3

⎞ ⎟

⎟ ⎠

2

NR

m

⎛ ⎜

⎞

⎜

⎟ ⎟

⎜

⎠

R3

+

⎜ ⎝

R

−−+

R4

BIAS

+

2αα2

R2R1

2

RR4

+

V

A =

V

= 1βα

RR2RR1RR1RR1R4A

LLL

R4

⎞

−

⎟

R3

⎠

⎞ ⎟

⎟ ⎟

BIAS

⎟

BIAS

⎠

LINE

VN

IN

k

MULTITONE POWER RATIO

The DMT signal used in ADSL/ADSL2+ systems carries data in discrete tones or bins, which appear in the frequency domain in evenly spaced 4.3125 kHz intervals. In applications using this type of waveform, multitone power ratio (MTPR) is a commonly used measure of linearity. Generally, there are two types of MTPR that designers are typically concerned with: in-band and out-of-band MTPR. In-band MTPR is defined as the

)

measured difference from the peak of one tone that is loaded with data to the peak of an adjacent tone that is intentionally left empty. Out-of-band MTPR is more loosely defined as the spurious emissions that occur in the receive band located between 25.875 kHz and the first downstream tone at 138 kHz. Figure 38 and Figure 39 show the AD8392 in-band MTPR for a

5.5 crest factor waveform for empty bins in the ADSL and extended ADSL2+ bandwidths. Figure 40 shows the AD8392 out-of-band MTPR for the same waveform.

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

CENTER 647kHz

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

CENTER 1.75MHz

Figure 38. In-Band MTPR at 647 kHz

Figure 39. In-Band MTPR at 1.751 MHz

72.2dB

64.4dB

SPAN 10kHz1kHz/

04802-0-038

04802-0-039

Rev. A | Page 14 of 16

AD8392

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

START 3kHz

Figure 40. Out-of-Band MTPR

STOP 145kHz14.2kHz/

04802-0-040

LIGHTNING AND AC POWER FAULT

The AD8392 can be used is as an ADSL/ADSL2+ line driver. In this application, the line driver is transformer-coupled to the twisted pair telephone line and could be subjected to large line transients resulting from events such as lightning strikes or downed power lines. In this type of environment, additional circuitry may be required to protect the AD8392 from damage that may occur as a result of these events. Using a minimal amount of external protection, the AD8392 has successfully passed overvoltage and overcurrent compliance testing per the ITU K-20 specification. For details on the external protection circuitry, contact the high current driver product line at high_current_drivers.com@analog.com.

Rev. A | Page 15 of 16

AD8392

OUTLINE DIMENSIONS

9.80

9.70

9.60

BOTTOM VIEW

1.20

MAX

PIN 1

0.15

0.00

28

1

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153AET

15

14

SEATING

PLANE

1.05

1.00

0.80

4.50

4.40

4.30

6.40

BSC

0.20

0.09

EXPOSED

PAD

(Pins Down)

3.50

BSC

8° 0°

0.75

0.60

0.45

3.00 BSC

Figure 41. 28-Lead Thin Shrink Small Outline with Exposed Pad [TSSOP/EP], (RE-28-1), Dimensions shown in millimeters

0.60 MAX

25

24

EXPOSED

PAD

(BOTTOM VIEW)

17

16

32

1

8

9

3.50 REF

PIN 1 INDICATOR

3.45

3.30 SQ

3.15

0.25 MIN

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING PLANE

5.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

4.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARITY

0.08

Figure 42. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 5 mm × 5 mm Body, Very Thin Quad (CP-32-3)—Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Outline

AD8392ARE −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP/EP) RE-28-1 AD8392ARE-REEL −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP/EP) RE-28-1 AD8392ARE-REEL7 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP/EP) RE-28-1 AD8392AREZ AD8392AREZ-REEL1 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP/EP) RE-28-1 AD8392AREZ-REEL71 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP/EP) RE-28-1 AD8392ACP-R2 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-3 AD8392ACP-REEL −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-3 AD8392ACP-REEL7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-3

1

Z = Pb-free part.

D04802–0–3/05(A)

1

−40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP/EP) RE-28-1

Rev. A | Page 16 of 16

Analog Devices AD8392 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

PIN CONFIGURATIONS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Maximum Power Dissipation

ESD CAUTION

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

APPLICATIONS

SUPPLIES, GROUNDING, AND LAYOUT

RESISTOR SELECTION

POWER MANAGEMENT

DRIVING CAPACITIVE LOADS

THERMAL CONSIDERATIONS

TYPICAL ADSL/ADSL2+ APPLICATION

MULTITONE POWER RATIO

LIGHTNING AND AC POWER FAULT

OUTLINE DIMENSIONS

ORDERING GUIDE