Analog Devices AD8390 Service Manual

Low Power, High Output Current

FEATURES

Voltage feedback amplifier

Ideal for ADSL and ADSL2+ central office (CO) and

customer premises equipment (CPE) applications

Enables high current differential applications

Low power operation

Single- or dual-power supply operation from 10 V (±5 V)

up to 24 V (±12 V)

4 mA total quiescent supply current for full power ADSL

and ADSL2+ CO applications

Adjustable supply current to minimize power

consumption
High output voltage and current drive
400 mA peak output drive current

44.2 V p-p differential output voltage
Low distortion
–82 dBc @ 1 MHz second harmonic
–91 dBc @ 1 MHz third harmonic
High speed: 300 V/µs differential slew rate

APPLICATIONS

ADSL/ADSL2+ CO and CPE line drivers
xDSL line driver
High current differential amplifiers

GENERAL DESCRIPTION

The AD8390 is a high output current, low power consumption
differential amplifier. It is particularly well suited for the central
office (CO) driver interface in digital subscriber line systems
such as ADSL and ADSL2+. While in full bias operation, the
driver is capable of providing 24.4 dBm output power into low
resistance loads. This is enough to power a 20.4 dBm line while
compensating for losses due to hybrid insertion, transformer
insertion, and back termination resistors.

The AD8390 fully differential amplifier is available in a ther­mally enhanced lead frame chip scale package (LFCSP-16) and
a 16-lead QSOP/EP. Significant control and flexibility in bias
current have been designed into the AD8390. The four power
modes are controlled by two digital bits,
provide three levels of driver bias and one powered-down state.
In addition, the I

pin can be used for fine quiescent current

ADJ

trimming to tailor the performance of
the AD8390.

PWDN (1,0) which

Differential Amplifier

AD8390

PIN CONFIGURATIONS

V

NC NCNC

OCM

1

+IN

PWDN1

PWDN0

4

–IN

DGND

NC NC

NC = NO CONNECT

Figure 1. 4 mm × 4 mm 16-Lead LFCSP

V

OCM

NC

+IN

PWDN1

PWDN0

–IN

NC

DGND

NC = NO CONNECT

Figure 2. 16-Lead QSOP/EP

The low power consumption, high output current, high output
voltage swing, and robust thermal packaging enable the AD8390
to be used as the central office line driver in ADSL, ADSL2+,
and proprietary xDSL systems, as well as in other high current
applications requiring a differential amplifier.

I

ADJ

1316

12

–OUT

V

EE

V

CC

+OUT

9

85

03600-0-001

161

NC

–OUT

NC

V

EE

V

CC

NC

+OUT

98

I

ADJ

03600-0-002

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD8390

TABLE OF CONTENTS

Specifications..................................................................................... 3

Setting the Output Common-Mode Voltage .......................... 10

Absolute Maximum Ratings............................................................ 5

Typical Thermal Properties............................................................. 5

ESD Caution.................................................................................. 5

Typical Performance Characteristics............................................. 6

Theory of Operation ........................................................................ 9

Applications....................................................................................... 9

Circuit Definitions ....................................................................... 9

Analyzing a Basic Application Circuit....................................... 9

Setting the Closed-Loop Gain .................................................... 9

Calculating Input Impedance ..................................................... 9

REVISION HISTORY

9/04–Data Sheet Changed from Rev. B to Rev. C

Change to Ordering Guide............................................................ 16

2/04–Data Sheet Changed from Rev. A to Rev. B.

Power-Down Features and the I

PWDN Pins............................................................................. 10

ADSL and ADSL2+ Applications......................................... 10

ADSL and ADSL2+ Applications Circuit............................ 10

Multitone Power Ratio (MTPR) ............................................... 11

Layout, Grounding, and Bypassing .......................................... 12

Power Dissipation and Thermal Management....................... 12

Outline Dimensions....................................................................... 13

Ordering Guide .......................................................................... 13

Pin ................................... 10

ADJ

Changed pub code.......................................................................... 16

1/04–Data sheet changed from Rev. Sp0f to Rev. A.

Added detailed description of product............................ Universal

Updated Outline Dimensions....................................................... 13

Rev. C | Page 2 of 16

AD8390

SPECIFICATIONS

VS = ±12 V or +24 V, RL = 100 Ω, G = 10, PWDN = (1,1), I

= NC, V

ADJ

= float, TA = 25°C, unless otherwise noted.

OCM

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth V
Large Signal Bandwidth V
Peaking V
Slew Rate V

= 0.2 V p-p, RF = 10 kΩ 40 60 MHz

OUT

= 4 V p-p 25 40 MHz

OUT

= 0.2 V p-p 0.1 dB

OUT

= 4 V p-p 300 V/µs

OUT

NOISE/DISTORTION PERFORMANCE

Second Harmonic Distortion
Third Harmonic Distortion
Multitone Power Ratio (26 kHz to 1.1 MHz) Z = 100 Ω, P = 19.8 dBm,

= 1 MHz, V

f

C

= 1 MHz, V

f

C

LINE LINE

= 2 V p-p

OUT

= 2 V p-p

OUT

–82 dBc
–91 dBc
–70 dBc

crest factor (CF) = 5.4

Multitone Power Ratio (26 kHz to 2.2 MHz) Z = 100 Ω, P = 19.8 dBm,

LINE LINE

–65 dBc

crest factor (CF) = 5.4
Voltage Noise (RTI) f = 10 kHz 8 nV/√Hz
Input Current Noise f = 10 kHz 1 pA/√Hz

INPUT CHARACTERISTICS

RTI Offset Voltage (V
RTI Offset Voltage (V

) V

OS,DM(RTI)

) V

OS,DM(RTI)

– V

, V

+IN

– V

+IN

= midsupply –3.0 ±1.0 +3.0 mV

–IN

OCM

, V

= float –3.0 ±1.0 +3.0 mV

–IN

OCM

±Input Bias Current –4.0 –7.0 µA
Input Offset Current –0.35 ±0.05 +0.35 µA
Input Resistance 400 kΩ
Input Capacitance 2 pF
Common-Mode Rejection Ratio (∆V

OS,DM(RTI)

)/(∆V

) 58 64 dB

IN,CM

OUTPUT CHARACTERISTICS

Differential Output Voltage Swing ∆V
Output Balance Error (∆V

OUT

OS,CM

)/∆V

OUT

43.8 44.2 44.6 V

60 dB
Linear Output Current RL = 10 Ω, fC = 100 kHz 400 mA
Worst harmonic = –60 dBc
Output Common-Mode Offset (V
Output Common-Mode Offset (V

+OUT

+OUT

+ V
+ V

–OUT

–OUT

)/2, V

= midsupply –75 ±35 +75 mV

OCM

)/2, V

= float –75 ±35 +75 mV

OCM

POWER SUPPLY

Operating Range (Dual Supply) ±5 ±12 V
Operating Range (Single Supply) +10 +24 V
Total Quiescent Current PWDN1, PWDN0 = (1,1); I
(1,0); I
(0,1); I
(0,0); I
Total Quiescent Current PWDN1, PWDN0 = (1,1); I
(1,0); I
(0,1); I
(0,0); I
Power Supply Rejection Ratio (PSRR) ∆V

/∆VS, ∆VS = ±1 V, V

OS,DM

= V

ADJ

EE

= V

ADJ

EE

= V

ADJ

EE

= V

ADJ

EE

= NC 10.0 11.0 mA

ADJ

= NC 6.7 8.0 mA

ADJ

= NC 3.8 5.0 mA

ADJ

= NC 0.67 1.0 mA

ADJ

= midsupply 70 76 dB

OCM

5.2 6.5 mA

3.8 5.0 mA

2.5 3.5 mA

0.57 1.0 mA

PWDN = 0 (Low Logic State) 1.0 V
PWDN = 1 (High Logic State) 1.6 V

V

OCM

TO ±V

SPECIFICATIONS

OUT

Input Voltage Range –11.0 to +10.0 V
Input Resistance 28 kΩ
V

Accuracy ∆V

OCM

1

V

bypassed with 0.1 µF capacitor.

OCM

2

See . Figure 3

OUT,CM

/∆V

OCM

0.996 1.0 1.004 V/V

1, 2

Rev. C | Page 3 of 16

AD8390

VS = ±5 V or +10 V, RL = 100 Ω, G = 10, PWDN = (1,1), I

= NC, V

ADJ

= float, TA = 25°C, unless otherwise noted.

OCM

1, 2

Table 2.
Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth V
Large Signal Bandwidth V
Peaking V
Slew Rate V

= 0.2 V p-p, RF = 10 kΩ, G = 10 40 60 MHz

OUT

= 4 V p-p 25 40 MHz

OUT

= 0.2 V p-p 0.1 dB

OUT

= 4 V p-p 300 V/µs

OUT

NOISE/DISTORTION PERFORMANCE

Second Harmonic Distortion fC = 1 MHz, V
Third Harmonic Distortion fC = 1 MHz, V

= 2 V p-p –82 dBc

OUT

= 2 V p-p –91 dBc

OUT

Voltage Noise (RTI) f = 10 kHz 8 nV/√Hz
Input Current Noise f = 10 kHz 1 pA/√Hz

INPUT CHARACTERISTICS

RTI Offset Voltage (V
RTI Offset Voltage (V

OS,DM(RTI)

OS,DM(RTI)

) V
) V

+IN

+IN

– V
– V

, V

= midsupply –3.0 ±1.0 +3.0 mV

–IN

OCM

, V

= float –3.0 ±1.0 +3.0 mV

–IN

OCM

±Input Bias Current –4.0 –7.0 µA
Input Offset Current –0.35 ±0.05 +0.35 µA
Input Resistance 400 kΩ
Input Capacitance 2 pF
Common-Mode Rejection Ratio (∆V

OS,DM(RTI)

)/(∆V

) 58 64 dB

IN,CM

OUTPUT CHARACTERISTICS

Differential Output Voltage Swing ∆V
Output Balance Error (∆V

OUT

OS,CM

)/∆V

OUT

16.0 16.4 16.8 V

60 dB
Linear Output Current RL = 10 Ω, fC = 100 kHz 400 mA
Worst harmonic = –60 dBc
Output Common-Mode Offset (V
Output Common-Mode Offset (V

+OUT

+OUT

+ V
+ V

–OUT

–OUT

)/2, V
)/2, V

= midsupply

OCM

= float

OCM

–75

–75

±35 +75 mV
±35 +75 mV

POWER SUPPLY

Operating Range (Dual Supply) ±5 ±12 V
Operating Range (Single Supply) +10 +24 V
Total Quiescent Current PWDN1, PWDN0 = (1,1); I
(1,0); I
(0,1); I
(0,0); I
Total Quiescent Current PWDN1, PWDN0 = (1,1); I
(1,0); I
(0,1); I
(0,0); I
Power Supply Rejection Ratio ∆V

/∆VS, ∆VS = ±1 V, V

OS,DM

= V

ADJ

EE

= V

ADJ

EE

= V

ADJ

EE

= V

ADJ

EE

= NC 8.7 10.0 mA

ADJ

= NC 5.8 7.0 mA

ADJ

= NC 3.3 4.0 mA

ADJ

= NC 0.55 1.0 mA

ADJ

= midsupply 70 76 dB

OCM

4.5 5.5 mA

3.3 4.0 mA

2.1 3.0 mA

0.43 1.0 mA

PWDN = 0 (Low Logic State) 1.0 V
PWDN = 1 (High Logic State) 1.6 V

V

OCM

TO ±V

SPECIFICATIONS

OUT

Input Voltage Range –4.0 to +3.0 V
Input Resistance 28 kΩ
V

Accuracy ∆V

OCM

1

V

bypassed with 0.1 µF capacitor.

OCM

2

See . Figure 3

OUT,CM

/∆V

OCM

0.996 1.0 1.004 V/V

Rev. C | Page 4 of 16

AD8390

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage ±13.2 V (26.4 V)
V

OCM

Package Power Dissipation (TJ
Maximum Junction Temperature (TJ

MAX

Operating Temperature Range (TA) –40°C to +85°C
Storage Temperature Range –65°C to +150°C
Lead Temperature (Soldering 10 s) 300°C

Stresses above those listed under Absolute Maximum Ratings

VEE < V

MAX

< V

OCM

– TA)/θ

) 150°C

CC

JA

TYPICAL THERMAL PROPERTIES

Table 4.

Package Typical Thermal Resistance (θJA)
16-lead LFCSP (CP-16)

JEDEC 2S2P – 0 airflow
Paddle soldered to board
Nine thermal vias in pad

16-lead QSOP/EP (RC-16)
JEDEC 1S2P – 0 airflow
Paddle soldered to board
Nine thermal vias in pad

may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

= 1kΩ

= 1kΩ

RF = 10kΩ

AD8390

RF = 10kΩ

Figure 3. Basic Test Circuit

R

L,DM

= 100Ω

V

49.9Ω
R

G

V

IN

R

G

49.9Ω

OUT,DM

03600-0-003

30.4°C/W

44.3°C/W

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. C | Page 5 of 16

AD8390

TYPICAL PERFORMANCE CHARACTERISTICS

Default Conditions: VS = ±12 V or +24 V, RL = 100 Ω, G = 10, PWDN = (1,1), I

= 25°C, unless otherwise noted. See Figure 3.

T

A

25

20

15

10

5

GAIN (dB)

0

–5

PWDN(0,1); I

PWDN(0,1); I

PWDN(1,0); I

= V

ADJ

ADJ

PWDN(1,1); I

ADJ

EE

= NC

= NC

ADJ

= NC

PWDN(1,0); I

PWDN(1,1); I

ADJ

ADJ

= V

= V

EE

EE

GAIN (dB)

= NC, V

ADJ

30

25

PWDN(0,1); I

20

15

10

5

0

–5

OCM

ADJ

PWDN(0,1); I

= float (bypassed with 0.1 μF capacitor),

= V

ADJ

EE

= NC

PWDN(1,0); I
PWDN(1,1); I

PWDN(1,0); I

PWDN(1,1); I

ADJ
ADJ
ADJ

ADJ

= V
= V
= NC

= NC

EE
EE

–10

1 10 100 1000

FREQUENCY (MHz)

Figure 4. Small Signal Frequency Response;

V

= ±12 V, Gain = 10, V

S

25

20

15

PWDN(0,1); I

10

PWDN(0,1); I

5

GAIN (dB)

0

–5

–10

1 10 100 1000

= V

ADJ

ADJ

PWDN(1,0); I

PWDN(1,1); I

EE

= NC

= NC

ADJ

= NC

ADJ

FREQUENCY (MHz)

OUT

= 200 mV p-p

PWDN(1,0); I

PWDN(1,1); I

ADJ

ADJ

Figure 5. Large Signal Frequency Response;

V

= ±12 V, Gain = 10, V

S

–10
–15
–20
–25
–30
–35
–40
–45
–50
–55

FEEDTHROUGH (dB)

–60
–65
–70
–75

1 10 100

FREQUENCY (MHz)

= 4 V p-p

OUT

Figure 6. Signal Feedthrough; PWDN = (0,0)

= V

= V

–10

03600-0-004

1 10 100 1000

FREQUENCY (MHz)

03600-0-026

Figure 7. Small Signal Frequency Response;

V

= ±5 V, Gain = 5, V

S

25

PWDN(0,1); I

20

EE

EE

03600-0-006

15

10

5

GAIN (dB)

0

–5

–10

1 10 100 1000

ADJ

PWDN(0,1); I

PWDN(1,0); I

= V

EE

= NC

ADJ

FREQUENCY (MHz)

= 200 mV p-p

OUT

ADJ

= V

EE

PWDN(1,1); I

PWDN(1,0); I
PWDN(1,1); I

ADJ

ADJ

ADJ

= V

= NC
= NC

EE

03600-0-027

Figure 8. Large Signal Frequency Response;

03600-0-008

= ±5 V, Gain = 5, V

V

S

100

10

1

0.1

OUTPUT IMPEDANCE (Ω)

0.01

0.001

0.01 0.1 1 10 100
FREQUENCY (MHz)

Figure 9. Output Impedance vs. Frequency; PWDN = (1,1)

= 2 V p-p

OUT

03600-0-020

Rev. C | Page 6 of 16

AD8390

–50

–55

PWDN(0,1); I

ADJ

= V

EE

CREST FACTOR = 5.4

–45

–50

PWDN(0,1); I

CREST FACTOR = 5.4

= V

ADJ

EE

–60

PWDN(0,1); I

ADJ

= NC

PWDN(1,0); I

–65

PWDN(1,1); I

–70

MULTITONE POWER RATIO (dBc)

–75

12 14 201816 22

PWDN(1,0); I

OUTPUT POWER (dBm)

= NC

ADJ

PWDN(1,1); I

ADJ

ADJ

= NC

Figure 10. MTPR vs. Output Power;

970 kHz Empty Bin (26 kHz to 1.1 MHz)

900

CREST FACTOR = 5.4

800

700

600

PWDN(1,0); I

PWDN(1,1); I

PWDN(1,1); I

= V

ADJ

ADJ

EE

ADJ

= NC

= NC

PWDN(0,1); I

500

POWER CONSUMPTION (mW)

400

300

12 1614 18 20 22

OUTPUT POWER (dBm)

PWDN(1,0); I

PWDN(0,1); I

ADJ

ADJ

= V

= V

EE

Figure 11. Power Consumption vs. Output Power

(Includes Output Power Delivered to Load)

ADJ

= V

ADJ

EE

= V

EE

EE

= NC

03600-0-010

03600-0-028

–55

–60

–65

MULTITONE POWER RATIO (dBc)

–70

12 2220181614

PWDN(1,0); I

PWDN(0,1); I

ADJ

= V

ADJ

EE

PWDN(1,1); I

PWDN(1,1); I

PWDN(1,0); I

ADJ

OUTPUT POWER (dBm)

= NC

= NC

Figure 13. MTPR vs. Output Power;

1.75 MHz Empty Bin (26 kHz to 2.2 MHz)

50

45

40

VS = ±12V

35

30

25

20

15

10

DIFFERENTIAL OUTPUT SWING (V)

V

= ±5V

S

5

0

10 20 30 40 50 60 70 80 90 100

Figure 14. Differential Output Swing vs. R

R

LOAD

(Ω)

LOAD

ADJ

ADJ

= V

= NC

EE

03600-0-030

03600-0-031

–50

–55

PWDN(0,1); I

ADJ

= V

EE

–60

PWDN(0,1); I

–65

–70

–75

–80

TOTAL HARMONIC DISTORTION (dBc)

–85

–90

0.1 1 10

= NC

ADJ

FREQUENCY (MHz)

PWDN(1,1); I

PWDN(1,0); I

PWDN(1,1); I

PWDN(1,0); I

ADJ

ADJ

= V

ADJ

= V

Figure 12. Total Harmonic Distortion vs. Frequency;

= ±12 V, V

V

S

= 2 V p-p

OUT

ADJ

EE

= NC

= NC

EE

03600-0-029

Rev. C | Page 7 of 16

–50

ADJ

ADJ

= NC

= V

EE

–55

PWDN(0,1); I

–60

PWDN(0,1); I

–65

–70

–75

–80

TOTAL HARMONIC DISTORTION (dBc)

–85

–90

0.1 1 10
FREQUENCY (MHz)

PWDN(1,1); I

PWDN(1,0); I

PWDN(1,1); I

PWDN(1,0); I

ADJ

ADJ

= V

ADJ

= V

Figure 15. Total Harmonic Distortion vs. Frequency;

V

= ±5 V, V

S

= 2 V p-p

OUT

ADJ

EE

= NC

= NC

EE

03600-0-032

AD8390

11

10

9

8

7

6

5

SUPPLY CURRENT (mA)

4

3

2

1 10 100 1k 10k 100k 1M

Figure 16. Quiescent Current vs. I

PWDN(1,1)

PWDN(1,0)

PWDN(0,1)

I

SERIES RESISTOR (Ω)

ADJ

Resistor; VS = ±12 V

ADJ

03600-0-016

9

8

7

6

5

4

SUPPLY CURRENT (mA)

3

2

1

1 10 100 1k 10k 100k 1M

I

ADJ

Figure 19. Quiescent Current vs. I

PWDN(1,1)

SERIES RESISTOR (Ω)

Resistor; VS = ±5 V

ADJ

PWDN(1,0)

PWDN(0,1)

03600-0-017

3

2

1

0

–1

DIFFERENTIAL OUTPUT (V)

–2

–3

–0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

PWDN PINS

OUTPUT

TIME (µs)

Figure 17. Power-Up Time;

PWDN = (0,0) to PWDN = (1,1)

100

Hz)

10

5.5

4.5

3.5

2.5

1.5

0.5

–0.5

PWDN PIN VALUES (V)

03600-0-018

3

2

1

0

–1

DIFFERENTIAL OUTPUT (V)

–2

–3

–20246810

TIME (µs)

OUTPUT

PWDN PINS

Figure 20. Power-Down Time;

PWDN = (1,1) to PWDN = (0,0)

100

10

5.5

4.5

3.5

2.5

1.5

0.5

–0.5

PWDN PIN VALUES (V)

03600-0-019

VOLTAGE NOISE (nV/

1

10 100 100k 1M10k1k 10M

FREQUENCY (Hz)

Figure 18. Voltage Noise (RTI)

03600-0-014

Rev. C | Page 8 of 16

1.0

CURRENT NOISE (pA/ Hz)

0.1
10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 21. Current Noise (RTI)

03600-0-015

AD8390

(

−

=

(

)

×

=

THEORY OF OPERATION

R

F

V

R

G

+IN

I

ADJ

R

ADJ

PWDN0

PWDN1

V

EE

DGND

–IN

R

G

A

50kΩ

C

B

50kΩ

AD8390

R

Figure 22. Functional Block Diagram

The AD8390 is a true differential operational amplifier with
common-mode feedback. The AD8390 is functionally equivalent
to three op amps, as shown in Figure 22. Amplifiers A and B act
like a standard dual op amp in an inverting configuration that
requires four resistors to set the desired gain.

The third amplifier (C) maintains the common-mode voltage

) at the output of the AD8390. V

(V

OCM

generated, as shown in Figure 22. The common-mode feedback
amplifier (C) drives the noninverting terminals of A and B such
that the difference between the output common-mode voltage
and V

is always zero. This functionality forces the outputs to

OCM

sit at midsupply, which results in differential outputs of identical
amplitude and 180 degrees out of phase. The user also has the
option to externally drive the V
output common-mode voltage. For details, see the Setting the
Output Common-Mode Voltage section.

CC

–OUT

56kΩ

V

OCM

56kΩ

V

EE

F

OCM

pin as an input to set the dc

OCM

BYP

+OUT

is internally

03600-0-035

APPLICATIONS

CIRCUIT DEFINITIONS

Differential voltage refers to the difference between two node
voltages. For example, the output differential voltage (or output
differential-mode voltage) is defined as

)

VVV

(1)

OUTOUTDMOUT

+IN

–IN

−+

VV

+

OUTOUT

−+

2

(2)

R

F

–OUT

R

+OUT

–

L,DMVOUT,DM

+

can also

OCM

,

V

+OUT

and V

refer to the voltages at the +OUT and –OUT

–OUT

terminals with respect to a common reference.

Common-mode voltage refers to the average of the two node
voltages. The output common-mode voltage is defined as

V

=

,

CMOUT

ANALYZING A BASIC APPLICATION CIRCUIT

The AD8390 uses high open-loop gain and negative feedback to
force its differential and common-mode output voltages in such
a way as to minimize the differential and common-mode error
voltages. The differential error voltage is defined as the voltage
between the differential inputs +IN and –IN, as shown in
Figure 23. For most purposes, this voltage can be assumed to be
zero. Similarly, the difference between the actual output
common-mode voltage and the voltage applied to V
be assumed to be zero. Starting from these two assumptions, any
application circuit can be analyzed.

R

G

+

V

IN,DM

V

OCM

R

G

–

SETTING THE CLOSED-LOOP GAIN

The differential-mode gain of the circuit in Figure 23 can be
described by

CALCULATING INPUT IMPEDANCE

The input impedance of the circuit in Figure 23 between the
inputs (V

Rev. C | Page 9 of 16

R

F

(I

ADJ

V

V

,

+IN

,

Figure 23. Basic Applications Circuit

Pin Not Connected, and PWDN0 and PWDN1 Held High)

R

DMOUT

,

DMIN

=

and V

2

F

(3)

R

G

) is simply

−IN

RR

(4)

GDMIN

03600-0-022

AD8390

SETTING THE OUTPUT COMMON-MODE VOLTAGE

By design, the AD8390’s V
voltage equal to the midsupply point (average value of the
voltages on V

and VEE), eliminating the need for external

CC

resistors. The high impedance nature of the V
allows the designer to force it to a desired level with an external
low impedance source. It should be noted that the V
not intended for use as an ac signal input.

The three configurations for the V
single supply, floating with dual supplies, and forcing the pin
with an external source. If not externally forcing the V
the designer must decouple it to ground with a 0.1 µF capacitor
in close proximity to the AD8390.

With dual equal supplies (for example, ±12 V) such that the
midpoint of the supplies is nominally 0 V, the user may opt to
connect the V

pin directly to ground, thus eliminating the

OCM

need for an external decoupling capacitor.

POWER-DOWN FEATURES AND THE I

The AD8390 offers significant versatility in setting quiescent
bias levels for a particular application from full ON to full OFF.
This versatility gives the circuit designer the flexibility to maxi­mize efficiency while maintaining optimal levels of performance.

pin is internally biased at a

OCM

OCM

pin are floating with a

OCM

ADJ

pin, however,

pin is

OCM

pin,

OCM

PIN

When I

is not connected, the bias current in the various

ADJ

power modes is set to approximately 10 mA, 6.7 mA, and

3.8 mA for power modes PWDN1,0 = (1,1), (1,0), and (0,1),
respectively, as seen in Table 5. Setting I
operation (or grounding the I

pin for single-supply opera-

ADJ

= VEE for dual-supply

ADJ

tion) cuts the bias setting approximately in half for each mode.

A resistor (R
operation, or I

) between I

ADJ

and VEE for dual-supply operation, allows fine

ADJ

and ground for single-supply

ADJ

bias adjustment between the bias levels preset by the PWDN
pins. Figure 16 and Figure 19 depict the effect of different R

ADJ

values on setting the bias levels.

Table 5. PWDN Code Selection Guide

PWDN1 PWDN0 R

1 1
1 0
0 1
0 0

(Ω) I

ADJ

∞
∞
∞

∞

(mA)

Q

10.0

6.7

3.8

0.67
1 1 0 5.2
1 0 0 3.8
0 1 0 2.5
0 0 0 0.57

ADSL and ADSL2+ Applications

Optimizing driver efficiency while delivering the required signal
level is accomplished with the AD8390 through the use of two
on-chip power management features: two PWDN pins used to
select one of four bias modes, and an I

pin used for additional

ADJ

power management including fine bias adjustments.

PWDN Pins

Two digitally programmable logic pins, PWDN1 and PWDN0,
may be used to select four different bias levels (see Table 5).
These levels start with full power if the I
The top bias level can also start at approximately half of full bias,
if the I
configuration, R

pin is connected to VEE or to ground in a single-supply

ADJ

= 0. The bias level can be controlled with

ADJ

CMOS logic levels (high = 1) applied to the PWDN1 and PWDN0
pins alone or in combination with the I
digital ground pin (DGND) is the logic ground reference for the
PWDN1 and PWDN0 pins. PWDN = (0,0) is the power-down
mode of the amplifier.

The AD8390 exhibits a low output impedance for PWDN1,0 =
(1,1), (1,0), and (0,1). At PWDN1,0 = (0,0), however, the output
impedance is undefined. The lowest power mode (0,0) of the
AD8390 alone may not be suitable for systems that rely on a
high impedance OFF state, such as multiplexing.

I

Pin

ADJ

The I

feature offers users significant flexibility in setting the

ADJ

bias level of the AD8390 by allowing for fine tuning of the bias
setting. Use of the I

feature is not required for operation of

ADJ

the AD8390.

pin is not connected.

ADJ

control pin. The

ADJ

The AD8390 line driver amplifier is an efficient class AB amplifier
that is ideal for driving xDSL signals. The AD8390 may be used
for driving ADSL or ADSL2+ modulated signals in either direc­tion: upstream from CPE to the CO or downstream from the
CO to CPE.

ADSL and ADSL2+ Applications Circuit

Increased CO port density has made driver power efficiency an
important requirement in ADSL and ADSL2+ systems. The lar­gest impact on efficiency is due to the need for back termina­tion of the driver. In the simplest case, this is accomplished with
a pair of resistors, each equal to half the reflected line impedance,
in series with the outputs of the differential driver. In this scen­ario, half the transmitted power is consumed by the back term­ination resistors. This results in the need for higher turns ratio
transformers, which attenuate the receive signal and tend to be
more lossy. They also increase current requirements of the dri­ver, effectively reducing headroom because the output devices
can no longer swing as close to the rail.

To solve this problem, it is common practice to use a combination
of negative and positive feedback to synthesize the output impe­dance, thus decreasing the required ohmic value of the back
termination. Overall efficiency is improved because less power
is wasted in the back termination and a lower turns ratio trans­former can be used without the need for increased supply rails.
The application circuit in Figure 24 depicts such an approach,
where the positive feedback, negative feedback, and back termi­nation are provided by R2, R3, and R

, respe ctively.

M

Rev. C | Page 10 of 16

AD8390

V

N

V

+IN

OCM

–IN

V

CC

EE

0.1µF

10µF0.1µF

0.1µF

R1

0.1µF

R1

R

ADJ

10µF

Figure 24. ADSL/ADSL2+ Application Circuit

PWDN1

I

PWDN0

ADJ

R2

R3

–OUT

+OUT

R3

R2

R

M

1:N

R

M

RLV

+

OUT,DM

–

Referring to Figure 24, the following describes how to calculate
the resistor values necessary to obtain the desired input imped­ance, gain, and output impedance.

The differential input impedance to the circuit is simply 2R1.
As such, R1 is chosen by the designer to yield the desired input
impedance.

When synthesizing the output impedance, a factor k is
introduced, which is used to express the ratio of the negative
feedback resistor to the positive feedback resistor by

R3

=−1 (5)

k

R2

Along with the turns ratio N, k is also used to define the value of
the back termination resistors R

. Commonly used values for k

M

are 0.1 to 0.25. A k value of 0.1 would result in back termination
resistors that are only 1/10 as large as those in the simplest case
described above. Lower values of k result in greater amounts of
positive feedback. Therefore, values much lower than 0.1 can
lead to instability and are generally not recommended.

R

L

×=

kR

M

This factor (k), along with R1, R

(6)

2

2

×

, and the desired gain (AV), is

M

then used to calculate the necessary values for R3 and R2.

()

2

RkRkR1AR1AkR1AR3 ×−+××××+××=

MMVVV

(7)

Table 6 shows a comparison of the results using the exact values,
the simplified approximation, and the closest 1% resistor values.

R1, A

In this example,

, and k were chosen to be 1.0 kΩ, 10 kΩ,

V

and 0.1 kΩ, respectively.

It should be noted that decreasing the value of the back termi­nation resistors attenuates the receive signal by approximately
1/k. However, advances in low noise receive amplifiers permit
k values as small as 0.1 to be commonly used.

The line impedance, turns ratio, and k factor specify the output
voltage and current requirements from the AD8390. To accom-

03600-0-036

modate higher crest factors or lower supply rails, the turns ratio,
N, may have to be increased. Since higher turns ratios and smaller
k factors both attenuate the receive signal, a large increase in N
may require an increase in k to maintain the desired noise
performance. Any particular design process requires that these
trade-offs be visited.

Table 6. Resistor Selection

Standard 1%

Component

Exact
Values

Approximate
Calculation

Resistor
Values

R1 (Ω) 1000 1000 1000
R2 (Ω) 2246.95 2222.22 2210
R3 (Ω) 2022.25 2000 2000
RM (Ω) 5 5 4.99
Actual A

V

10.000 9.889 10.138

Actual k (Eq. 5) 0.1 0.1 0.095

MULTITONE POWER RATIO (MTPR)

Multitone power ratio is a commonly used figure of merit that
xDSL designers use to help describe system performance.
MTPR is the measured delta between the peak of a filled
frequency bin and the harmonic products that appear in an
intentionally empty frequency bin. Figure 25 illustrates this
principle. The plots in Figure 10 and Figure 13 show MTPR
performance in various power modes. All data were taken with
a circuit with a k factor of 0.1, a 1:1 turns ratio transformer, and
a waveform with a 5.4 peak-to-average ratio, also known as the
crest factor (CF).

10dB/DIV

The usually small value for R

allows a simplified approximation

M

for R3.

–70dBc

R2−=

Once R

AkR1R3 ×××≅ 2 (8)

V

R3

(9)

k

1

, R3, and R2 are computed, the closest 1% resistors can

M

be chosen and the gain rechecked with the following equation:

R3R2

A

=

V

()

M

×

(10)

R1R3R2R2kR

×−+×+

Rev. C | Page 11 of 16

CENTER 431.25kHz SPAN 10kHz1kHz/DIV

Figure 25. MTPR Measurement

03600-0-033

AD8390

LAYOUT, GROUNDING, AND BYPASSING

The first layout requirement is for a good solid ground plane
that covers as much of the board area around the AD8390 as
possible. The only exception to this is that the two input pins
should be kept a few millimeters from the ground plane, and
ground should be removed from inner layers and the opposite
side of the board under the input traces. This minimizes the
stray capacitance on these nodes and helps preserve the gain
flatness versus frequency.

The power supply pins should be bypassed as close as possible
to the device on a ground plane common with signal ground.
Good high frequency, ceramic chip capacitors should be used.
This bypassing should be done with a capacitance value of

0.01 μF to 0.1 μF for each supply. Low frequency bypassing
should be provided with 10 μF tantalum capacitors from each
supply to signal ground. The signal routing should be short and
direct to avoid parasitic effects, particularly on traces connected
to the amplifier inputs. Wherever there are complementary
signals, a symmetrical layout should be provided to the extent
possible to maximize the balance performance. When running
differential signals over a long distance, the traces on the PCB
should be close together.

POWER DISSIPATION AND THERMAL MANAGEMENT

The AD8390 was designed to be the most efficient class AB
ADSL/ADSL2+ line driver available. Figure 11 shows the total
power consumption (delivered line power and power consumed)
of the AD8390 driving ADSL signals at varying output powers
and power modes. To accurately determine the amount of
power dissipated by the AD8390, it is necessary to subtract the
power delivered to the load, matching losses, and transformer
losses as follows:

PPPP

AD8390

where:

P

is the total supply power in mW drawn by the AD8390.

supply,mW

P

is the power delivered into a 100 Ω twisted-pair line in mW.

load,mW

P

is the power dissipated by the matching resistors and

losses,mW

the transformer in mW.

While this discussion focuses mainly on ADSL applications, the
same premise can be applied to determining the power dissipa­tion of the AD8390 in any application.

−−= (11)

mWlossesmWloadsupply,mW

,,

To obtain optimum thermal performance from the AD8390 in
either package, it is essential that the thermal pad be soldered to
a ground plane with minimal thermal resistance. This is par­ticularly true for dense circuit designs with multiple integrated
circuits. Furthermore, the PCB should be designed in such a
manner as to draw the heat away from the ICs. Figure 26
illustrates the relationship between thermal resistance (°C/W)
and the copper area (mm

2

) for the AD8390ACP soldered down

to a 4-layer board with a given copper area.

Figure 26 can be used to help determine the copper board area
required for proper thermal management of the AD8390. The
power dissipation of the AD8390 can be computed using
Equation 11. This number can then be inserted into the
following equation to yield the required θ

θ

where T

T

RISE

JA

P

AD8390

is the delta from the maximum expected ambient

RISE

°

C

==

(12)

W

:

JA

temperature to the highest allowable die temperature. It is
generally recommended that the maximum die temperature be
limited to 125°C, and in no case should it be allowed to exceed
150°C.

Using the θ

computed in Equation 12, Figure 26 can be used to

JA

determine the minimum copper area required for proper thermal
dissipation of the AD8390.

90

80

70

60

50

(°C/W)

40

JA

θ

30

20

10

0

1 100 100010 10000

Figure 26. Thermal Resistance vs. Copper Area

Cu AREA (mm

2)

03600-0-034

Rev. C | Page 12 of 16

AD8390

OUTLINE DIMENSIONS

PIN 1

INDICATOR

1.00

0.85

0.80

4.0

12° MAX

SEATING
PLANE

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

COMPLIANT TO JEDEC STANDARDS MO-220-VGGC

0.35

0.28

0.25

3.75

BSC SQ

0.20 REF

0.60 MAX

0.65 BSC

0.05 MAX

0.02 NOM

COPLANARITY

0.75

0.60

0.50

0.08

Figure 27. 4 × 4 mm 16-Lead Lead Frame Chip Scale Package [LFCSP]

(CP-16)

Dimensions shown in millimeters

0.197

0.189

13

12

9

8

0.60 MAX

BOTTOM

VIEW

16

1

4

5

1.95 BSC

0.096

PIN 1
INDICATOR

2.25

2.10 SQ

1.95

0.25MIN

0.012

0.008

9

8

0.236
BSC

0.069

0.053

SEATING
PLANE

0.077

0.010

0.006

BOTTOM VIEW

8°
0°

0.090

0.050

0.016

0.154
BSC

0.065

0.049

0.010

0.004

COPLANARITY

0.004

16

TOP VIEW

1

PIN 1

0.025
BSC

COMPLIANT TO JEDEC STANDARDS MO-137

Figure 28. 16-Lead Shrink Small Outline Package, Exposed Pad [QSOP/EP]

(RC-16)

Dimensions shown in inches

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8390ACP-R2 –40°C to +85°C 16-Lead LFCSP CP-16, 250 Piece Reel
AD8390ACP-REEL –40°C to +85°C 16-Lead LFCSP CP-16, 13” Tape and Reel
AD8390ACP-REEL7 –40°C to +85°C 16-Lead LFCSP CP-16, 7” Tape and Reel
AD8390ACP-EVAL Evaluation Board LFCSP
AD8390ARC –40°C to +85°C 16-Lead QSOP/EP RC-16
AD8390ARC-REEL –40°C to +85°C 16-Lead QSOP/EP RC-16, 13” Tape and Reel
AD8390ARC-REEL7 –40°C to +85°C 16-Lead QSOP/EP RC-16, 7” Tape and Reel
AD8390ARC-EVAL Evaluation Board QSOP/EP

Rev. C | Page 13 of 16

AD8390

NOTES

Rev. C | Page 14 of 16

AD8390

NOTES

Rev. C | Page 15 of 16

AD8390

NOTES

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C02694–0–9/04(C)

Rev. C | Page 16 of 16