Analog Devices AD8385 Datasheet

10-Bit, 12-Channel Decimating

FEATURES

High voltage drive to within 1.3 V of supply rails
Output short-circuit protection
High update rates

Fast, 100 Ms/s 10-bit input data update rate

Static power dissipation: 1.84 W

Voltage controlled video reference (brightness), offset,
and full-scale (contrast) output levels

INV bit reverses polarity of video signal

3.3 V logic, 9 V to 18 V analog supplies
Level shifters for panel timing signals

High accuracy voltage outputs

Laser trimming eliminates the need for adjustments or

calibration

Flexible logic

STSQ/XFR allow parallel AD8385 operation

Fast settling into capacitive loads

30 ns settling time to 0.25% into 150 pF load
Slew rate 460 V/µs

Available in 100-lead 14 mm × 14 mm TQFP E-pad

GENERAL DESCRIPTION

The AD8385 provides a fast, 10-bit, latched decimating digital
input that drives 12 high voltage outputs. 10-bit input words are
loaded into 12 separate high speed, bipolar DACs sequentially.
Flexible digital input format allows several AD8385s to be used
in parallel in high resolution displays. The output signal can be
adjusted for dc reference, signal inversion, and contrast for
maximum flexibility. Integrated level shifters convert timing
signals from a 3 V timing controller to high voltage for LCD
panel timing inputs. Two, serial, 8-bit DACs are integrated to
provide dc reference signals. A 3-wire serial interface controls
overload protection, output mode, and the serial DACs.

LCD DECDRIVER

FUNCTIONAL BLOCK DIAGRAM

BYP
VRH

VRH
VRL

DB(0:9)

R/L

CLK

STSQ

XFR

INV

TSTM

SDI
SCL
SEN

SVRH
SVRL
SVRL

DYIN

DXIN
DIRYIN
DIRXIN

NRGIN
ENBX1I
ENBX2I
ENBX3I
ENBX4I

CLXIN
CLYIN

MONITI

3

10

4

V1
V2

BIAS

/

SCALING

CONTROL

/

SEQUENCE

/

3

/

3

/

9

/

2

/

CONTROL

®

with Level Shifters

AD8385

VID0
VID1
VID2

9

/

2

/

2

/

AD8385

12

/

VID3
VID4
VID5
VID6
VID7
VID8
VID9
VID10
VID11

VAO1
VAO2

DY
DX
DIRY
DIRX
NRG
ENBX1
ENBX2
ENBX3
ENBX4

CLX
CLY

CLXN
CLYN

MONITO

2-STAGE

LATCH

CONTROL

12-BIT
SHIFT

REGISTER

INV

R

S

Figure 1.

DACs

DUAL

DAC

04514-0-001

The AD8385 is fabricated on ADI’s fast bipolar, 26 V XFHV
process, which provides fast input logic, bipolar DACs with
trimmed accuracy and fast settling, high voltage, precision drive
amplifiers on the same chip.

The AD8385 dissipates 1.84 W nominal static power.

The AD8385 is offered in a 100-lead, 14 mm × 14 mm TQFP
E-pad package and operates over the commercial temperature
range of 0°C to 85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

www.analog.com

AD8385

TABLE OF CONTENTS

Specifications..................................................................................... 3

DECDRIVER Section .................................................................. 3

Level Shifters ................................................................................. 4

Level Shifting Edge Detector ...................................................... 5

Serial Interface.............................................................................. 5

Power Supplies .............................................................................. 6

Operating Temperature ............................................................... 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Overload Protection ..................................................................... 8

Exposed Paddle............................................................................. 8

Maximum Power Dissipation ..................................................... 8

Operating Temperature Range ................................................... 8

Pin Configuration and Function Descriptions............................. 9

Block Diagrams and Timing Diagrams .......................................11

Reference and Control Input.................................................... 16

Output Operating Mode............................................................ 17

Overload Protection................................................................... 17

Serial DACs ................................................................................. 17

Theory of Operation...................................................................... 18

Transfer Function and Analog Output Voltage ...................... 18

Accuracy ...................................................................................... 18

Applications..................................................................................... 19

Optimized Reliability with the Thermal Switch..................... 19

Operation in High Ambient Temperature .............................. 20

Power Supply Sequencing ......................................................... 20

VBIAS Generation—V1, V2 Input Pin Functionality ........... 20

Applications Circuit................................................................... 21

PCB Design for Optimized Thermal Performance ............... 21

Thermal Pad Design .................................................................. 21

DECDRIVER Section ................................................................ 11

Level Shifters ............................................................................... 13

Level Shifting Edge Detector .................................................... 14

Serial Interface............................................................................ 15

Functional Description ..................................................................16

REVISION HISTORY

1/05—Revision 0: Initial Version

Thermal Via Structure Design.................................................. 21

AD8385 PCB Design Recommendations ............................... 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 23

Rev. 0 | Page 2 of 24

AD8385

SPECIFICATIONS

DECDRIVER SECTION

@ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, T

Table 1.

Parameter Conditions Min Typ Max Unit

VIDEO DC PERFORMANCE

1

VDE DAC Code 450 to 800 –7.5 +7.5 mV
VCME DAC Code 450 to 800 –3.5 +3.5 mV

VIDEO OUTPUT DYNAMIC PERFORMANCE T

Data Switching Slew Rate 20% to 80% 460 V/µs
Invert Switching Slew Rate 20% to 80% 560 V/µs
Data Switching Settling Time to 1% 19 24 ns
Data Switching Settling Time to 0.25% 30 50 ns
Invert Switching Settling Time to 1% 75 120 ns
Invert Switching Settling Time to 0.25% 250 500 ns
Invert Switching Overshoot 100 200 mV
CLK and Data Feedthrough
All-Hostile Crosstalk

2

3

Amplitude 10 mV p-p
Glitch Duration 30 ns

DAC Transition Glitch Energy DAC Code 511 to 512 0.3 nV-s

VIDEO OUTPUT CHARACTERISTICS

Output Voltage Swing AVCC – VOH, VOL – AGND 1.1 1.3 V
Output Voltage—Grounded Mode 0.25 V
Data Switching Delay: t
INV Switching Delay: t
INV to CLK Setup Time: t

4

9

5

10

27

Output Current 100 mA
Output Resistance 22 Ω

REFERENCE INPUTS

V1 Range
V2 Range
V1 Input Current –5 µA

V2 Input Current –27 µA
VRL Range VRH ≥ VRL V1 – 0.5 AVCC – 1.3 V
VRH Range VRH ≥ VRL VRL AVCC V
VRH to VRL Range VFS =2 × (VRH – VRL) 0 2.75 V
VRH Input Resistance To VRL 20 kΩ
VRL Bias Current –0.2 µA
VRH Input Current 125 µA

RESOLUTION

Coding Binary 10 Bits

A MIN

= 0°C, T

T

to T

MIN

to T

MIN

= 85°C, VRH = 9.5 V, VRL = V1 = V2 = 7 V, unless otherwise noted.

A MAX

MAX

, VO = 5 V step, CL = 150 pF

MAX

10 mV p-p

50 % of VIDx 10 12 14 ns
50 % of VIDx 13 15 17 ns

0.5 f

V2 ≥ (V1 – 0.25 V)
V2 ≥ (V1 – 0.25 V)

5 AVCC – 4 V
5 AVCC – 4 V

CLK

5.5 f

CLK

ns

Rev. 0 | Page 3 of 24

AD8385

Parameter Conditions Min Typ Max Unit

DIGITAL INPUT CHARACTERISTICS Input tr, tf = 2 ns

Max. Input Data Update Rate 100 Ms/s
Data Setup Time: t
STSQ Setup Time: t
XFR Setup Time: t
Data Hold Time: t
STSQ Hold Time: t
XFR Hold Time: t
CLK High Time: t
CLK Low Time: t
C

IN

I

IH

I

IL

V

IH

V

IL

V

TH

1

3

5

2

4

6

7

8

1

VDE = differential error voltage; VCME = common-mode error voltage; VFS = full-scale output voltage = 2 × (VRH – VRL). See the section. Accuracy

2

Measured on two outputs differentially as CLK and DB(0:9) are driven and XFR is held low.

3

Measured on two outputs differentially as the other four are transitioning by 5 V. Measured for both states of INV.

4

Measured from 50% of rising CLK edge to 50% of output change. Measurement is made for both states of INV.

5

Measured from 50% of rising CLK edge that follows a valid XFR to 50% of output change. Refer to for the definition. Figure 6

LEVEL SHIFTERS

@ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, T

Table 2.

Parameter Conditions Min Typ Max Unit

LEVEL SHIFTER LOGIC INPUTS

C

IN

I

IH

I

IL

V

TH

V

IH

V

IL

LEVEL SHIFTER OUTPUTS RL > 10 kΩ

V

OH

V

OL

LEVEL SHIFTER DYNAMIC PERFORMANCE T

Output Rise, Fall Times—tr, t

DX, CLX, CLXN, ENBX[1–4] CL = 40 pF 18.5 30 ns
DY, CLY, CLYN CL = 40 pF 40 70 ns
DIRX, DIRY CL = 40 pF 102 200 ns
NRG CL = 200 pF 43 50 ns
NRG CL = 300 pF 61 100 ns

Propagation Delay Times—t11, t12, t13, t

DX, CLX, CLXN, ENBX[1–4] CL = 40 pF 20 50 ns
DY, CLY, CLYN CL = 40 pF 29 50 ns
DIRX, DIRY CL = 40 pF 70 100 ns
NRG CL = 200 pF 30 100 ns
NRG CL = 300 pF 37 ns

Output Skew

ENBX[1-4]—t15, t

16

DX to ENBX[1–4]—t
DX to CLX—t15, t16, t17, t
DY, CLY, CLYN—t15, t16, t17, t

f

14

16

18

18

0 ns
0 ns
0 ns
3 ns

3 ns
3 ns
3 ns

2.5 ns
3 pF

0.05 µA
–0.6 µA
2 V

0.8 V

1.65 V

A MIN

= 0°C, T

= 85°C, VRH = 9.5 V, VRL = V1 = V2 = 7 V, unless otherwise noted.

A MAX

3 pF

0.05 2 µA
–2 –0.6 µA

1.65 V

2.0 DVCC V
DGND 0.8 V

AVCC – 0.25 V

0.25 V

A MIN

to T

A MAX

CL = 40 pF 2 ns
CL = 40 pF 2 ns
CL = 40 pF 10 ns
CL = 40 pF 20 ns

Rev. 0 | Page 4 of 24

AD8385

LEVEL SHIFTING EDGE DETECTOR

@ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, T

Table 3.

Parameter Conditions Min Typ Max Unit

V
V
V
V
V

V
I
I
t
∆t
t
∆t
t
t

IL

IH

TH LH

TH HL

OH

OL

IH

IL

19

19

20

20

r

f

Input Low Voltage AGND AGND + 0.75 V
Input High Voltage AVCC – 0.7 AVCC V
Input Rising Edge Threshold Voltage AGND + 1 V
Input Falling Edge Threshold Voltage AVCC – 1 V
Output High Voltage

Output Low Voltage 0.25 V
Input Current High State 1.2 2.5 µA
Input Current Low State –2.5 –1.2 µA
Input Rising Edge Propagation Delay Time CL = 10 pF 16 ns
t19 Variation with Temperature 2 ns
Input Falling Edge Propagation Delay Time CL = 10 pF 12 ns
t20 Variation with Temperature 2 ns
Output Rise Time 10% to 90% 5 ns
Output Fall Time 10% to 90% 6 ns

SERIAL INTERFACE

@ 25 C, AVCC = 15.5 V, DVCC = 3.3 V, T

Table 4.

Parameter Conditions Min Typ Max Unit

SERIAL DAC REFERENCE INPUTS SVFS = (SVRH – SVRL)

SVRH Range SVRL ≤ SVRH SVRL + 1 AVCC – 3.5 V
SVRL Range SVRL ≤ SVRH AGND + 1.5 SVRH – 1 V
SVFS Range 1 8 V
SVRH Input Current SVFS = 5 V 125 150 µA
SVRL Input Current SVFS = 5 V –2.8 –2.5 mA
SVRH Input Resistance 40 kΩ

SERIAL DAC ACCURACY

DNL SVFS = 5 V, RL = ∞ –1.0 +1.0 LSB
INL SVFS = 5 V, RL = ∞ –1.5 +1.5 LSB
Output Offset Error –2.0 +2.0 LSB
Scale Factor Error –3 +3 LSB

SERIAL DAC LOGIC INPUTS Input tr, tf = 10 ns

C

IN

I

Low Level Input Current –0.6 µA

IN LOW

I

High Level Input Current 0.05 µA

IN HIGH

VTH Input Threshold Voltage 1.65 V
VIH Input High Voltage 2.0 DVCC V
VIL Input Low Voltage DGND 0.8 V

SERIAL DAC OUTPUTS

Maximum Output Voltage SVRH – 1 LSB V
Minimum Output Voltage SVRL V
VAO1—Grounded Mode 0.1 V
I

OUT

C

Low Range

LOAD

C

High Range1 0.047 µF

LOAD

1

A MIN

A MIN

= 0°C, T

= 0°C, T

= 85°C, VRH = 9.5 V, VRL = V1 = V2 = 7 V, unless otherwise noted.

A MAX

DVCC − 0.25

= 85°C, SVFS = 5 V, SVRL = 4 V, SVRH = 9 V, unless otherwise noted.

A MAX

V

3 pF

±30 mA

0.002 µF

Rev. 0 | Page 5 of 24

AD8385

Parameter Conditions Min Typ Max Unit

SERIAL INTERFACE DYNAMIC PERFORMANCE

SEN to SCL Setup Time, t
SCL, High Level Pulse Width, t
SCL, Low Level Pulse Width, t
SDI Setup Time, t
SDI Hold Time, t

25

SCL to SEN Hold Time, t
VAO1, VAO2 Settling Time, t
VAO1, VAO2 Settling Time, t

20

21

22

24

23

26

26

1

Outputs VAO1 and VAO2 are designed to drive very high capacitive loads. For proper operation of these outputs, load capacitance must be ≤0.002 µF or ≥0.047 µF.

Load capacitance in the range of 0.002 µF to 0.047 µF causes the output overshoot to exceed 100 mV.

POWER SUPPLIES

@ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, T

Table 5.

AD8385 Power Supplies Min Typ Max Unit

DVCC, Operating Range 3 3.3 3.6 V
DVCC, Quiescent Current 56 mA
AVCC Operating Range 9 18 V
Total AVCC Quiescent Current 111 mA

10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
SVFS = 5 V, to 0.5%, CL = 100 pF 1 2 ms
SVFS = 5 V, to 0.5%, CL = 33 µF 15 ms

A MIN

= 0°C, T

= 85°C, SVFS = 5 V, SVRL = 4 V, SVRH = 9 V, unless otherwise noted.

A MAX

OPERATING TEMPERATURE

@ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, T

Table 6.

Parameter Min Typ Max Unit

Ambient Temperature Range, T
Ambient Temperature Range, T

1

A

2

A

1

Operation at high ambient temperature requires a thermally-optimized PCB layout (see the section), input data update rate not exceeding 85 MHz, black-

to-white transition ≤ 4 V and C
protection enabled. For operation above 75°C, see Endnote 2.

2

In addition to the requirements stated in Endnote 1, operation at 85°C ambient temperature requires 200 lfm airflow or the overload protection disabled.

≤ 150 pF. In systems with limited or no airflow, the maximum ambient operating temperature is limited to 75°C with the overload

L

A MIN

= 0°C, T

= 85°C, SVFS = 5 V, SVRL = 4 V, SVRH = 9 V, unless otherwise noted.

A MAX

0 75 °C
0 85 °C

Applications

Rev. 0 | Page 6 of 24

AD8385

ABSOLUTE MAXIMUM RATINGS

Table 7.

Parameter Rating

Supply Voltage

AVCCx – AGNDx 18 V
DVCC – DGND 4.5 V

Input Voltage

Maximum Digital Input Voltage DVCC + 0.5 V
Minimum Digital Input Voltage DGND – 0.5 V
Maximum Analog Input Voltage AVCC + 0.5 V
Minimum Analog Input Voltage AGND – 0.5 V

Internal Power Dissipation

TQFP E-Pad Package @ TA = 25°C 5.00 W
Operating Temperature Range 0°C to 85°C
Storage Temperature Range –65°C to 125°C
Lead Temperature Range (Soldering, 10 sec) 300°C

1

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the
absolute maximum ratings for extended periods may reduce
device reliability.

1

100-lead TQFP E-pad package: θJA = 20°C/W (still air),

JEDEC STD, 4-layer PCB in still air.

Rev. 0 | Page 7 of 24

AD8385

(

)

−

OVERLOAD PROTECTION

The AD8385 employs a 2-stage overload protection circuit with
an enable/disable function that is programmable through the
3-wire serial interface. It consists of an output current limiter
and a thermal shut down.

OPERATING TEMPERATURE RANGE

The maximum operating junction temperature is 150°C. The
junction temperature trip point of the overload protection is
165°C. Production test guarantees a minimum junction
temperature trip point of 125°C.

When enabled, the maximum current at any one output of the
AD8385 is, on average, internally limited to 100 mA. In the
event of a momentary short circuit between a video output and
a power supply rail (VCC or AGND), the output current limit is
sufficiently low to provide temporary protection.

The thermal shutdown debiases the output amplifier when the
junction temperature reaches the internally set trip point. In the
event of an extended short circuit between a video output and a
power supply rail, the output amplifier current continues to
switch between 0 mA and 100 mA typ, with a period deter­mined by the thermal time constant and the hysteresis of the
thermal trip point. Thermal shutdown provides long-term
protection by limiting the average junction temperature to a
safe level. When disabled, no overload protection is present.

EXPOSED PADDLE

To ensure optimal thermal performance, the exposed paddle
must be electrically connected to an external plane such as
AVCC or GND, as described in the Applications Circuit section.

MAXIMUM POWER DISSIPATION

The junction temperature limits the maximum power that can
be safely dissipated by the AD8385. The maximum safe junction
temperature for plastic encapsulated devices, determined by the
glass transition temperature of the plastic, is approximately
150°C. Exceeding this limit can cause a temporary shift in the
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
175°C for an extended period can result in device failure.

Consequently, the maximum guaranteed operating junction
temperature is 125°C with the overload protection enabled, and
150°C with the overload protection disabled.

To ensure operation within the specified operating temperature
range, the maximum power dissipation must be limited:

TT

≈

P

DMAX

3.0

STILL AIR

100MHz

2.5

60Hz XGA

2.0
QUIESCENT

MAXIMUM POWER DISSIPATION (W)

AD8385 on a 4-layer JEDEC PCB with a thermally optimized landing pattern,
as described in the Applications Circuit section.

*OVERLOAD PROTECTION ENABLED

**OVERLOAD PROTECTION DISABLED

1.5

Figure 2. Maximum Power Dissipation vs. Temperature

×−

JA

AMBIENT TEMPERATURE (°C)

AJMAX

3

200 lfm

858070 75*65 90 95 100 105

11010595 100**90 115 120 125 130

)9.0(

lfminAirflowθ

500 lfm

04514-0-002

Note that the quiescent power dissipation of the AD8385 is

1.84 W when operating under the conditions specified in this
data sheet. When driving a 12-channel XGA panel with an input
capacitance of 150 pF, the AD8385 dissipates a total of 2.3 W
when displaying 1 pixel wide alternating white and black
vertical lines generated by a standard 60 Hz XGA input video.
When the frequency of the pixel clock is raised to 100 MHz, the
total power dissipation increases to 2.54 W. These specific
power dissipations are shown in Figure 2 for reference.

Rev. 0 | Page 8 of 24