Analog Devices AD8384 Service Manual

10-Bit, 6-Channel Decimating

PRODUCT FEATURES

High accuracy, high resolution voltage outputs 10-bit input resolution Laser trimmed outputs Fast settling, high voltage drive 30 ns settling time to 0.25% into a 150 pF load Slew rate 460 V/µs Outputs to within 1.3 V of supply rails High update rates Fast, 100 Ms/s 10-bit input data update rate Voltage controlled video reference (brightness), offset, and

full-scale (contrast) output levels Flexible logic STSQ/XFR allow parallel AD8384 operation INV bit reverses polarity of video signal Output short-circuit protection

3.3 V logic, 9 V to 18 V analog supplies 18 V level shifters for panel timing signals Available in 80-lead 12 mm × 12 mm TQFP E-pad

APPLICATIONS

LCD analog column drivers

LCD DecDriver

FUNCTIONAL BLOCK DIAGRAM

BYP

VRH VRL

DB(0:9)

R/L

CLK

STSQ

XFR

INV

TSTM

SDI SCL SEN

SVRH SVRL

DYIN

DXIN DIRYIN DIRXIN

NRGIN ENBX1IN ENBX2IN ENBX3IN ENBX4IN

CLXIN CLYIN

10

V1 V2

BIAS

2

/

4

SEQUENCE

/

3

2

9

2

CONTROL

/ /

/

®

with Level Shifters

AD8384

SCALING

CONTROL

2-STAGE

LATCH

CONTROL

12-BIT SHIFT

REGISTER

INV

DACs

DUAL

DAC

6

/

9

/

2

/

2

/

VID0 VID1 VID2 VID3 VID4 VID5

VAO1 VAO2

DY DX DIRY DIRX NRG ENBX1 ENBX2 ENBX3 ENBX4

CLX CLY

CLXN CLYN

PRODUCT DESCRIPTION

The AD8384 DecDriver provides a fast, 10-bit, latched, decimating digital input that drives six high voltage outputs. 10-bit input words are loaded sequentially into six separate high speed, bipolar DACs. Flexible digital input format allows several AD8384s to be used in parallel in high resolution displays. The output signal can be adjusted for dc reference, signal inversion, and contrast for maximum flexibility. Integrated level shifters convert timing signals from a 3 V timing controller to high voltage for LCD panel timing inputs. Two serial input, 8-bit DACs are integrated to provide dc reference signals. DAC addresses and 8-bit data are loaded in one 12-bit serial word.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

MONITI

R

S

AD8384

Figure 1.

The AD8384 is fabricated on the 26 V, fast, bipolar XFHV process developed by Analog Devices, Inc. This process provides fast input logic, bipolar DACs with trimmed accuracy and fast settling, high voltage, precision drive amplifiers on the same chip.

The AD8384 dissipates 1.1 W nominal static power.

The AD8384 is offered in an 80-lead 12 mm × 12 mm TQFP E-pad package and operates over the 0°C to 85°C commercial temperature range.

www.analog.com

MONITO

04512-0-001

AD8384

TABLE OF CONTENTS

Specifications..................................................................................... 3

DecDriver...................................................................................... 3

Level Shifters ................................................................................. 5

Level Shifting Edge Detector ...................................................... 5

Serial Interface .............................................................................. 6

Power Supplies .............................................................................. 7

Operating Temperature ............................................................... 7

Absolute Maximum Ratings............................................................ 8

Maximum Power Dissipation ..................................................... 8

Operating Temperature Range ................................................... 8

Overload Protection ..................................................................... 8

Exposed Paddle............................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Timing Characteristics................................................................... 11

DecDriver Section...................................................................... 11

Functional Description .................................................................. 15

Accuracy ...................................................................................... 16

TSTM Control—Test Mode ...................................................... 16

Grounded Output Mode ........................................................... 16

Overload Protection................................................................... 16

3-Wire Serial Interface............................................................... 16

Serial DACs................................................................................. 16

Level Shifters ............................................................................... 16

Applications..................................................................................... 17

Power Supply Sequencing ......................................................... 17

VBIAS Generation—V1, V2 Input Pin Functionality ........... 18

Applications Circuit ................................................................... 18

PCB Design for Optimized Thermal Performance ............... 19

Thermal Pad Design .................................................................. 19

Thermal Via Structure Design.................................................. 19

Level Shifter Section................................................................... 12

Level Shifting Edge Detector ....................................................13

Serial Interface ............................................................................ 14

REVISION HISTORY

Revision 0: Initial Version

AD8384 PCB Design Recommendations ............................... 20

Outline Dimensions....................................................................... 21

Ordering Guide .......................................................................... 21

Rev. 0 | Page 2 of 24

AD8384

SPECIFICATIONS

DecDriver

Table 1. @ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, T unless otherwise noted

Parameter Conditions Min Typ Max Unit

VIDEO DC PERFORMANCE

1

T VDE DAC Code 450 to 800 –7.5 +7.5 mV VCME DAC Code 450 to 800 –3.5 +3.5 mV

VIDEO OUTPUT DYNAMIC PERFORMANCE T

Data Switching Slew Rate 20% to 80% 460 V/µs Invert Switching Slew Rate 20% to 80% 560 V/µs Data Switching Settling Time to 1% 19 24 ns Data Switching Settling Time to 0.25% 30 50 ns Invert Switching Settling Time to 1% VO = 10 V Step 75 120 ns Invert Switching Settling Time to 0.25% VO = 10 V Step 250 500 ns Invert Switching Overshoot VO = 10 V Step 100 200 mV CLK and Data Feedthrough All-Hostile Crosstalk

2

3

10 mV p-p

Amplitude 10 mV p-p Glitch Duration 30 ns

DAC Transition Glitch Energy DAC Code 511 to 512 0.3 nV-s

VIDEO OUTPUT CHARACTERISTICS

Output Voltage Swing AVCC – VOH, VOL – AGND 1.1 1.3 V Output Voltage—Grounded Mode 0.25 V Data Switching Delay: t INV Switching Delay: t

4

9

5

10

50 % of VIDx 10 12 14 ns

50 % of VIDx 13 15 17 ns Output Current 100 mA Output Resistance 22 Ω

REFERENCE INPUTS

V1 Range V2 ≥ (V1-0.25V) 5.25 AVCC – 4 V V2 Range V2 ≥ (V1-0.25V) 5.25 AVCC – 4 V V1 Input Current –3 µA V2 Input Current –14 µA VRL Range VRH ≥ VRL V1 – 0.5 AVCC – 1.3 V VRH Range VRH ≥ VRL VRL AVCC V (VRH–VRL) Range VFS = 2(VRH – VRL) 0 2.75 V VRH Input Resistance To VRL 20 kΩ VRL Bias Current –0.2 µA VRH Input Current 125 µA

RESOLUTION

Coding Binary 10 Bits

1

VDE = differential error voltage; VCME = common-mode error voltage; VFS = full-scale output voltage = 2 × (VRH – VRL). See the section. Accuracy

2

Measured differentially on two outputs as CLK and DB(0:9) are driven and STSQ and XFR are held LOW.

3

Measured differentially on two outputs as the other four are transitioning by 5 V. Measured for both states of INV.

4

Measured from 50% of rising CLK edge to 50% of output change. Measurement is made for both states of INV.

5

Measured from 50% of rising CLK edge to 50% of output change. Refer to Figure 7 for the definition.

A MIN

to T

= 0°C, T

A MAX

, VO = 5 V Step, CL = 150 pF

A MAX

= 85°C, VRH = 9.5 V, VRL = V1 = V2 = 7 V,

A MAX

Rev. 0 | Page 3 of 24

AD8384

DecDriver (continued)

Parameter Conditions Min Typ Max Unit

DIGITAL INPUT CHARACTERISTICS

Max. Input Data Update Rate 100 Ms/s CLK to Data Setup Time: t CLK to STSQ Setup Time: t CLK to XFR Setup Time: t CLK to Data Hold Time: t CLK to STSQ Hold Time: t CLK to XFR Hold Time: t CLK High Time: t CLK Low Time: t

7

8

1

3

5

2

4

6

CIN 3 pF I

IH

I

IL

V

IH

V

IL

V

TH

0 ns 0 ns 0 ns 3 ns 3 ns 3 ns 3 ns

2.5 ns

0.05 µA –0.6 µA 2 V

0.8 V

1.65 V

Rev. 0 | Page 4 of 24

AD8384

LEVEL SHIFTERS

Table 2. @ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, T unless otherwise noted

Parameter Conditions Min Typ Max Unit

LEVEL SHIFTER LOGIC INPUTS

CIN 3 pF IIH 0.05 µA IIL –0.6 µA VTH 1.65 V VIH 2.0 DVCC V VIL DGND 0.8 V

LEVEL SHIFTER OUTPUTS RL ≥ 10 kΩ

VOH AVCC – 0.45 AVCC – 0.25 V VOL 0.25 0.45 V

LEVEL SHIFTER DYNAMIC PERFORMANCE T

Output Rise, Fall Times—tr, tf

DX, CLX, CLXN, ENBX(1–4) CL = 40 pF 18.5 30 ns DY, CLY, CLYN CL = 40 pF 40 70 ns DIRX, DIRY CL = 40 pF 100 150 ns NRG CL = 200 pF 35 50 ns C Propagation Delay Times—t11, t12, t13, t14 DX, CLX, CLXN, ENBX(1–4) CL = 40 pF 20 50 ns DY, CLY, CLYN CL = 40 pF 29 50 ns DIRX, DIRY CL = 40 pF 60 100 ns NRG CL = 200 pF 25 55 ns C

Output Skew

ENBX(1–4)—t15, t16 C DX to ENBX(1–4)—t16 C DX to CLX—t15, t16, t17, t18 C DY to CLY, CLYN—t15, t16, t17, t18 C

A MIN

= 0°C, T

A MIN

L

= 85°C, VRH = 9.5 V, VRL = V1 = V2 = 7 V,

A MAX

to T

A MAX

= 300 pF 55 100 ns

= 300 pF 32 ns

= 40 pF 2 ns = 40 pF 2 ns = 40 pF 10 ns = 40 pF 20 ns

LEVEL SHIFTING EDGE DETECTOR

Table 3. CL = 10 pF, T

Parameter Min Typ Max Unit

VIL Input Low Voltage AGND AGND + 2.75 V VIH Input High Voltage AVCC – 2.7 AVCC V VTH LH Input Rising Edge Threshold Voltage AGND + 3 V VTH HL Input Falling Edge Threshold Voltage AVCC – 3 V VOH Output High Voltage DVCC – 0.45 DVCC – 0.25 V VOL Output Low Voltage 0.25 0.45 V IIH Input Current High State 1.2 2.5 µA IIL Input Current Low State –2.5 –1.2 µA t19 Input Rising Edge Propagation Delay Time 16 ns ∆t19 t

19

t20 Input Falling Edge Propagation Delay Time 12 ns ∆t20 t

20

tr Output Rise Time 5 ns tf Output Fall Time 6 ns

A MIN

to T

, unless otherwise noted

A MAX

Variation with Temperature 2 ns

Rev. 0 | Page 5 of 24

AD8384

SERIAL INTERFACE

Table 4. @ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, T

Parameter Conditions Min Typ Max Unit

SERIAL DAC REFERENCE INPUTS SVFS = (SVRH – SVRL)

SVRH Range SVRL < SVRH SVRL + 1 AVCC – 3.5 V SVRL Range SVRL < SVRH AGND + 1.5 SVRH – 1 V SVFS Range 1 8 V SVRH Input Current SVFS = 5 V –70 nA SVRL Input Current SVFS = 5 V –2.8 –2.5 mA SVRH Input Resistance 40 kΩ

SERIAL DAC ACCURACY

DNL SVFS = 5 V, RL = ∞ –1.0 +1.0 LSB INL SVFS=5 V, RL = ∞ –1.5 +1.5 LSB Output Offset Error –2.0 +2.0 LSB Scale Factor Error –4.0 +4.0 LSB

SERIAL DAC LOGIC INPUTS

C

IN

3 pF IIL –0.6 µA I

IH

0.05 µA VTH 1.65 V VIH 2.0 DVCC V VIL DGND 0.8 V

SERIAL DAC OUTPUTS

Maximum Output Voltage SVRH – 1 LSB V Minimum Output Voltage SVRL V VAO1—Grounded Mode 0.1 V I

OUT

C

Low Range

LOAD

C

High Range1 0.047 µF

LOAD

6

±30 mA

0.002 µF

SERIAL DAC DYNAMIC PERFORMANCE

SEN to SCL Setup Time, t

20

SCL, High Level Pulse Width, t SCL, Low Level Pulse Width, t SDI Setup Time, t SDI Hold Time, t SCL to SEN Hold Time, t

24

25

23

VAO1, VAO2 Settling Time, t VAO1, VAO2 Settling Time, t

21

22

26

10 ns 15 ns 10 ns 10 ns 10 ns 15 ns SVFS = 5 V, to 0.5%, CL = 100 pF 1 2 µs SVFS = 5 V, to 0.5%, CL = 33 µF 10 15 ms

6

Outputs VAO1 and VAO2 are designed to drive very high capacitive loads. The load capacitance must be ≤ 0.002 µF or ≥0.047 µF.

Load capacitance in the range 0.002 µF to 0.047 µF causes the output overshoot to exceed 100 mV.

A MIN

= 0°C, T

= 85°C, SVRL = 4 V, SVRH = 9 V, unless otherwise noted

A MAX

Rev. 0 | Page 6 of 24

AD8384

POWER SUPPLIES

Table 5. @ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, T

Parameter Min Typ Max Unit

DVCC, Operating Range 3 3.3 3.6 V DVCC, Quiescent Current 40 50 mA AVCC Operating Range 9 18 V Total AVCC Quiescent Current 70 85 mA

OPERATING TEMPERATURE

Parameter Conditions Min Typ Max Unit

Ambient Temperature Range, T Ambient Temperature Range, T Junction Temperature Range, TJ 100% Tested 25 125 °C

7

Operation at high ambient temperature requires a thermally optimized PCB layout (see the Applications section), input data update rate not exceeding 85 MHz, black-

to-white transition ≤ 4V and C 75°C, see Note 8 below.

8

In addition to the requirements stated in Note 7 above, operation at 85°C ambient temperature requires 200 lfm airflow.

7

Still Air 0 75 °C

A

8

200 lfm 0 85 °C

A

≤ 150 pF. In systems with limited or no airflow, the maximum ambient operating temperature is limited to 75°C. For operation above

L

A MIN

= 0°C, T

= 85°C, SVRL = 4 V, SVRH = 9 V, unless otherwise noted

A MAX

Rev. 0 | Page 7 of 24

AD8384

ABSOLUTE MAXIMUM RATINGS

Table 6. AD8384 Stress Ratings

Parameter Rating

Supply Voltages

AVCCx – AGNDx 18 V DVCC – DGND 4.5 V

Input Voltages

Maximum Digital Input Voltage DVCC + 0.5 V Minimum Digital Input Voltage DGND – 0.5 V Maximum Analog Input Voltage AVCC + 0.5 V Minimum Analog Input Voltages AGND – 0.5 V

Internal Power Dissipation

TQFP E-Pad Package @ TA = 25°C 4.16 W

Operating Temperature Range 0°C to 85°C Storage Temperature Range –65°C to +125°C Lead Temperature Range (Soldering 10 sec) 300°C

9

Stresses above those listed under the Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum ratings for extended periods may reduce device reliability.

10

80-lead TQFP E-pad package:

= 24°C/W (JEDEC STD, 4-layer PCB in still air)

θ

JA

θJC = 16°C/W

OVERLOAD PROTECTION

The AD8384 employs a 2-stage overload protection circuit that consists of an output current limiter and a thermal shutdown. The maximum current at any one output of the AD8384 is, on average, internally limited to 100 mA. In the event of a momentary short circuit between a video output and a power supply rail (VCC or AGND), the output current limit is sufficiently low to provide temporary protection.

The thermal shutdown debiases the output amplifier when the junction temperature reaches the internally set trip point. In the event of an extended short-circuit between a video output and a power supply rail, the output amplifier current continues to switch between 0 mA and 100 mA typical with a period determined by the thermal time constant and the hysteresis of the thermal trip point. Thermal shutdown provides long term protection by limiting average junction temperature to a safe level.

EXPOSED PADDLE

To ensure optimized thermal performance, the exposed paddle must be thermally connected to an external plane, such as AVCC or GND, as described in the Application Notes.

9

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the AD8384 is limited by its junction temperature. The maximum safe junction temperature for plastic encapsulated devices, as determined by the glass transition temperature of the plastic, is approximately 150°C. Exceeding this limit temporarily may cause a shift in the parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can

10

result in device failure.

OPERATING TEMPERATURE RANGE

Although the maximum safe operating junction temperature is higher, the AD8384 is 100% tested at a junction temperature of 125°C. Consequently, the maximum guaranteed operating junction temperature is 125°C.

To ensure operation within the specified temperature range, it is necessary to limit the maximum power dissipation as follows:

2.5

100MHz

2.0

60Hz XGA

1.5

MAXIMUM POWER DISSIPATION (W)

QUIESCENT

1.0

Figure 2. Maximum Power Dissipation vs. Temperature*

*AD8384 on a 4-layer JEDEC PCB with thermally optimized landing pattern, as

described in the Application Notes.

Note: When operating under the conditions specified in this

data sheet, the AD8384’s quiescent power dissipation is 1.1 W. When driving a 6-channel XGA panel with a 150 pF input capacitance, the AD8384 dissipates a total of 1.58 W when displaying 1-pixel-wide alternating white and black vertical lines generated by a standard 60 Hz XGA input video. When the pixel clock frequency is raised to 100 MHz (the AD8384’s maximum specified operating frequency), total power dissipation increases to 1.83 W. Figure 2 shows these specific power dissipations.

DMAX

P

≈

JA

×θ

200lfm

500lfm

STILL AIR

858070 7565 90 95 100 105

AMBIENT TEMPERATURE (°C)

AJMAX

)–(

TT

)(5.0–

lfmAirflow

04512-0-002

Rev. 0 | Page 8 of 24