Analog Devices AD8383 Service Manual

Low Cost 10-Bit, 6-Channel Output

FEATURES

High voltage drive to within 1.3 V of supply rails Output short-circuit protection High update rates Fast, 100 Ms/s, 10-bit input data update rate Low static power dissipation: 0.7 W

Includes STBY function

Voltage-controlled video reference (brightness) and

full-scale (contrast) output levels

INV bit reverses polarity of video signal

3.3 V logic, 9 V to 18 V analog supplies High accuracy voltage outputs Laser trimming eliminates the need for adjustments Flexible logic STSQ/XFR allow parallel AD8383 operation at various

resolutions

Fast settling into capacitive loads

30 ns settling time to 0.25% into 150 pF load Slew rate 460 V/µs

Available in 48-lead 7 mm × 7 mm LFCSP package

APPLICATIONS

LCD analog column driver

PRODUCT DESCRIPTION

The AD8383 provides a fast, 10-bit latched decimating digital input that drives six high voltage outputs. 10-bit input words are sequentially loaded into six separate, high speed, bipolar DACs. Flexible digital input format allows several AD8383s to be used in parallel for higher resolution displays. STSQ synchronizes sequential input loading, XFR controls synchronous output updating, and R/L controls the direction of loading as either left-to-right or right-to-left. Six channels of high voltage output drivers drive to within 1.3 V of the rail. For maximum flexibility, the output signal can be adjusted for dc reference, signal inversion.

Decimating LCD DecDriver

AD8383

FUNCTIONAL BLOCK DIAGRAM

1010

10 10

DB(0:9)

STBY

BYP

R/L E/O

CLK

STSQ

XFR

AD8383

SEQUENCE

CONTROL

VREFHI

BIAS

VREFLO

2-STAGE

LATCH

10 10

2-STAGE

LATCH

10 10

2-STAGE

LATCH

10 10

2-STAGE

LATCH

10 10

2-STAGE

LATCH

10 10

2-STAGE

LATCH

SCALING

CONTROL

Figure 1

The AD8383 is fabricated on the 26 V, fast bipolar XFHV process developed by Analog Devices, Inc. This process provides fast input logic, bipolar DACs with trimmed accuracy and fast settling, high voltage, precision drive amplifiers on the same chip.

The AD8383 dissipates 0.7 W nominal static power. The STBY pin reduces power to a minimum with fast recovery.

The AD8383 is offered in a 48-lead, 7 mm × 7 mm × 0.85 mm LFCSP package and operates over the commercial temperature range of 0°C to 85°C.

DAC

INV V1 V2

VID0

VID1

VID2

VID3

VID4

VID5

04513-0-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

AD8383

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Maximum Power Dissipation ..................................................... 5

Pin Configuration and Function Descriptions............................. 6

Timing Diagrams.............................................................................. 7

Theory of Operation ........................................................................ 8

Transfer Function and Analog Output Voltage ........................ 8

Applications....................................................................................... 9

External VBIAS Generation........................................................ 9

REVISION HISTORY

Revision 0: Initial Version

PCB Design for Good Thermal Performance........................ 10

Thermal Pad Design .................................................................. 10

Thermal Via Structure Design.................................................. 11

Solder Masking........................................................................... 11

Reference PCB Design............................................................... 11

Estimated Junction Temperature ............................................. 12

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. 0 | Page 2 of 16

AD8383

SPECIFICATIONS

Table 1. @25°C, AVCC = 15.5 V, DVCC = 3.3 V, T unless otherwise noted

Parameter Conditions Min Typ Max Unit

VIDEO DC PERFORMANCE

VDE –7.5 +7.5 mV VCME –3.5 +3.5 mV

REFERENCE INPUTS

V1, V2 Range 5 AVCC – 4 V V2 to V1 Range –0.25 V V1 Input Current +0.2 µA V2 Input Current –7.5 µA VREFHI Range VREFHI ≥ VREFLO VREFLO AVCC V VREFLO Range VREFHI ≥ VREFLO V1 – 0.5 AVCC – 1.3 V VREFHI Input Resistance To VREFLO 20 kΩ VREFLO Bias Current –0.2 µA VREFHI Input Current 125 µA VFS Range

RESOLUTION

Coding Binary 10 Bits

DIGITAL INPUT CHARACTERISTICS

Maximum Input Data Update Rate

CLK to Data Setup Time 0 ns CLK to STSQ Setup Time 1 ns CLK to XFR Setup Time 1 ns CLK to Data Hold Time 3 ns CLK to STSQ Hold Time 3 ns CLK to XFR Hold Time 3 ns CLK High Time 3 ns CLK Low Time 2.5 ns C

IIL, CLK 1.2 µA V

VIDEO OUTPUT CHARACTERISTICS

Output Voltage Swing AVCC – VOH, VOL – AGND 1.1 1.3 V CLK to VID Delay

INV to VID Delay 50% of VIDx 10.4 12.4 14.4 ns Output Current 100 mA Output Resistance 22 Ω

VDE = Differential Error Voltage = Common-Mode Error Voltage. See section. Theory of Operation

VFS = 2 × (VREFHI – VREFLO).

Maximum input transition time (10% to 90%) = 0.8/(2f) where f is the operating CLK rate.

Measured from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV.

MIN

= 0°C, T

MIN

to T

, DAC Code 450 to 800

MAX

= 75°C, VFS = 5 V, VREFLO = V1 = V2 = 7 V,

MAX

0 5.5 V

100 Ms/s

3 pF

0.05 µA

0.6 µA

2 V

0.8 V

1.5 V

50% of VIDx 10.0 12.0 14.0 ns

Rev. 0 | Page 3 of 16

AD8383

SPECIFICATIONS (continued)

Parameter Conditions Min Typ Max Unit

VIDEO OUTPUT DYNAMIC PERFORMANCE T

Data Switching Slew Rate 20% to 80% 460 V/µs Invert Switching Slew Rate 20% to 80% 560 V/µs Data Switching Settling Time to 1% 19 24 ns Data Switching Settling Time to 0.25% 30 50 ns Invert Switching Settling Time to 1% VO = 10 V Step 75 120 ns Invert Switching Settling Time to 0.25% VO = 10 V Step 250 500 ns Invert Switching Overshoot VO = 10 V Step 100 200 mV CLK and Data Feedthrough All-Hostile Crosstalk

Amplitude 40 mV p-p Duration 20 ns

DAC Transition Glitch Energy Code 511 to Code 512 0.3 nV-s

POWER SUPPLY

DVCC, Operating Range 3 3.3 3.6 V DVCC, Quiescent Current 20 28 mA AVCC, Operating Range 9 18 V Total AVCC Quiescent Current 40 48 mA STBY AVCC Current STBY = H 0.15 0.45 mA

STBY DVCC Current STBY = H 3.5 5 mA OPERATING TEMPERATURE RANGE, T AMBIENT TEMPERATURE RANGE OPERATING TEMPERATURE RANGE, T

Measured on two outputs differentially as CLK and DB(0:9) are driven and STSQ and XFR are held low.

Measured on two outputs differentially as the other four outputs make a full-scale transition for both states of INV.

Operation at 85°C ambient temperature requires a thermally optimized PCB layout (see Application Notes), minimum airflow of 200 lfm, input clock rate not

exceeding 100 MHz, black-to-white transition ≤4 V, C

C, MIN

to T

, VO = 5 V Step, CL = 150 pF

C, MAX

10 mV p-p

Ambient Temperature 0 75 °C 0 85 °C 100% tested 25 125 °C

≤150 pF.

Rev. 0 | Page 4 of 16

AD8383

ABSOLUTE MAXIMUM RATINGS

Table 2. AD8383 Stress Ratings

Parameter Rating

Supply Voltages

AVCCx – AGNDx 18 V DVCC – DGND 4.5 V

Input Voltages

Maximum Digital Input Voltages DVCC + 0.5 V Minimum Digital Input Voltages DGND – 0.5 V Maximum Analog Input Voltages AVCC + 0.5 V Minimum Analog Input Voltages AGND – 0.5 V

Internal Power Dissipation

LFCSP Package @ 25°C Ambient 3.8 W Operating Temperature Range 0°C to 85°C Storage Temperature Range –65°C to +125°C Lead Temperature Range (Soldering 10 sec) 300°C

Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum ratings for extended periods may reduce device reliability.

48-Lead LFCSP Package:

= 26°C/W (Still Air): JEDEC STD, 4-layer board with 0 CFM airflow

= 20°C/W

= 11.0°C/W in Still Air

MAXIMUM POWER DISSIPATION

Junction Temperature

The maximum power that can be safely dissipated by the AD8383 is limited by its junction temperature. The maximum safe junction temperature for plastic encapsulated devices as determined by the glass transition temperature of the plastic is approximately 150°C. Exceeding this limit temporarily may cause a shift in the parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure.

Overload Protection

The AD8383 employs a 2-stage overload protection circuit that consists of an output current limiter and a thermal shutdown. The maximum current at any one output of the AD8383 is internally limited to 100 mA, average. In the event of a momentary short-circuit between a video output and a power supply rail (AVCC or AGND), the output current limit is sufficiently low to provide temporary protection.

The thermal shutdown debiases the output amplifier when the junction temperature reaches the internally set trip point. In the event of an extended short-circuit between a video output and a power supply rail, the output amplifier current continues to switch between 0 mA and 100 mA typical with a period determined by the thermal time constant and the hysteresis of the thermal trip point. The thermal shutdown provides longterm protection by limiting the average junction temperature to a safe level.

Operating Temperature Range

Production testing guarantees a minimum thermal shutdown junction temperature (T

) of at least 125°C.

To ensure operation at T maximum power dissipation as described in the Applications section.

Exposed Paddle

The die paddle must be soldered to AVCC for reliable electrical operation.

See the Applications section for details regarding use of the exposed paddles to dissipate excess heat.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 5 of 16

< 125°C, it is necessary to limit the

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