Analog Devices AD8382 Service Manual

High Performance 12-Bit, 6-Channel Output,

V

PRODUCT FEATURES

High accuracy, high resolution voltage outputs 12-bit input resolution

Laser trimmed outputs Fast settling, high voltage drive 33 ns settling time to 0.25% into 200 pF load

Slew rate 390 V/µs Outputs to within 1.3 V of supply High update rates Fast, 120 Ms/s data update rate Voltage controlled video reference (brightness) and full-scale (contrast) output levels Flexible logic STSQ/XFR allow parallel AD8382 operation

INV bit reverses polarity of video signal Output overload protection Low static power dissipation: 743 mW Includes STBY function

3.3 V logic, 9 V to 18 V analog supplies Available in 48-lead 7 mm × 7 mm LFCSP

APPLICATIONS

LCD analog column driver

Decimating LCD DecDriver

AD8382

FUNCTIONAL BLOCK DIAGRAM

12 12

1212

DB(0:11)

STBY

BYP

R/L E/O

CLK

STSQ

XFR

2-STAGE

LATCH

12 12

AD8382

SEQUENCE

CONTROL

VREFHI

BIAS

VREFLO

2-STAGE

LATCH

12 12

2-STAGE

LATCH

12 12

2-STAGE

LATCH

12 12

2-STAGE

LATCH

12 12

2-STAGE

LATCH

SCALING

CONTROL

Figure 1. Functional Block Diagram

DAC

INV V1 V2

®

ID0

ID1

ID2

ID3

ID4

ID5

PRODUCT DESCRIPTION

The AD8382 DecDriver provides a fast, 12-bit latched decimating digital input that drives six high voltage outputs.12-bit input words are sequentially loaded into six separate, high speed, bipolar DACs. A flexible digital input format allows several AD8382s to be used in parallel for higher resolution displays.

STSQ synchronizes sequential input loading, XFR controls synchronous output updating, and R/L controls the direction of loading as either left-to-right or right-to-left. Six channels of high voltage output drivers drive to within 1.3 V of the rail. The output signal can be adjusted for dc reference, signal inversion, and contrast for maximum flexibility.

The AD8382 is fabricated on Analog Devices’ XFHV, fast bipolar 26 V process, providing fast input logic bipolar DACs with trimmed accuracy and fast settling, high voltage, precision drive amplifiers on the same chip. The AD8382 dissipates 743 mW nominal static power. The STBY pin reduces power to a minimum, with fast recovery.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

www.analog.com

AD8382

TABLE OF CONTENTS

Specifications..................................................................................... 3

Applications..................................................................................... 15

Absolute Maximum Ratings............................................................ 5

Timing Characteristics..................................................................... 6

Pin Configuration and Functional Descriptions.......................... 7

Typical Performance Characteristics ............................................. 8

Functional Description.................................................................. 13

Transfer Function ....................................................................... 13

Accuracy ...................................................................................... 14

REVISION HISTORY

Revision 0: Initial Version

VBIAS Generation—V1, V2 Input Pin Functionality ........... 17

Power Supply Sequencing ......................................................... 18

PCB Design for Optimized Thermal Performance ............... 18

Layout Considerations............................................................... 20

Outline Dimensions....................................................................... 21

Ordering Guide .......................................................................... 21

Rev. 0 | Page 2 of 24

AD8382

SPECIFICATIONS

Table 1. @ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, T otherwise noted.

Parameter Conditions Min Typ Max Unit

VIDEO DC PERFORMANCE1 T VDE DAC Code 1500 to 3200 –5 +5 mV VCME DAC Code 1500 to 3200 –3.5 +0.5 +3.5 mV

∆V ∆V VIDEO OUTPUT DYNAMIC PERFORMANCE T

Data Switching Slew Rate 20% to 80% 390 Invert Switching Slew Rate 20% to 80% 530 Data Switching Settling Time to 1% 22 27 ns Data Switching Settling Time to 0.25% 33 50 ns Invert Switching Settling Time to 1% 34 100 ns Invert Switching Settling Time to 0.25% 130 300 ns Invert Switch Overshoot 100 200 mV CLK and Data Feedthrough2 10 mV p-p All-Hostile Crosstalk3 Amplitude 40 mV p-p Duration 30 ns DAC Transition Glitch Energy Code 2047 to Code 2048 0.3 nV-s

VIDEO OUTPUT CHARACTERISTICS Output Voltage Swing AVCC – VOH, VOL– AGND 1.1 1.3 V CLK to VID Delay: t INV to VID Delay: t10 50% of VIDx 10.4 12.4 14.4 ns Output Current 100 mA Output Resistance 22

RESOLUTION Coding Binary 12 Bits

DIGITAL INPUT CHARACTERISTICS Input tr, tf = 2 ns (10% to 90%) Max. Input Data Update Rate 120 Ms/s Data Setup Time: t1 0 ns STSQ Setup Time: t3 1 ns XFR Setup Time: t5 1 ns Data Hold Time: t2 3 ns STSQ Hold Time: t4 3 ns XFR Hold Time: t6 3 ns CLK High Time: t7 3 ns CLK Low Time: t8 2.5 ns CIN 3 pF IIH 0.05 IIL—All Inputs except CLK 0.6 IIL—CLK 1.2 VIH 2 V VIL 0.8 V VTH 1.6 V

4

50% of VIDx 10 12 14 ns

9

MIN

= 0°C, T

MIN

to T

MAX

= 85°C, VREFHI = 9.5 V, VREFLO = V1 = V2 = 7 V, unless

MAX

DAC Code 2048 2.5 7.5 mV DAC Code 0 to 4095 4 15 mV

to T

C, MIN

V

= 5 V Step, CL = 200 pF

O

C, MAX

,

V/µs V/µs

Ω

µA µA µA

Rev. 0 | Page 3 of 24

AD8382

Parameter Conditions Min Typ Max Unit

REFERENCE INPUTS1 V1 Range V2 Range

V2 ≥ (V1 – 0.25 V) V2 ≥ (V1 – 0.25 V)

V1 Input Current 0.2 V2 Input Current –7.5 VREFLO Range VREFHI Range

VREFHI ≤ (VREFLO + 2.75 V) VREFHI ≤ (VREFLO + 2.75 V)

(VREFHI – VREFLO) Range 0 2.75 V VREFHI Input Resistance 20 VREFLO Bias Current –0.2 VREFHI Input Current 125 VFS Range

VFS = 2 × (VREFHI – VREFLO)

POWER SUPPLY DVCC, Operating Range 3 3.3 3.6 V DVCC, Quiescent Current 23 31 mA AVCC, Operating Range 9 18 V Total AVCC Quiescent Current 43 52 mA STBY AVCC Current STBY = HIGH 0.15 0.45 mA STBY DVCC Current STBY = HIGH 3.5 5 mA

OPERATING TEMPERATURE RANGE Ambient Temperature Range, TA Still Air 0 75 °C Ambient Temperature Range, T

5

0 85 °C

A

Junction Temperature Range, TJ 100% Tested 25 125 °C

5 AVCC – 4 V 5 AVCC – 4 V

µA µA

V1 – 0.5 AVCC – 1.3 V VREFLO AVCC V

kΩ

µA µA

5.5 V

1

VDE = differential error voltage. VCME = common-mode error voltage. ∆V = maximum deviation between outputs.

Full-scale output voltage = VFS = 2 × (VREFHI – VREFLO). See the Accu section on page 14. racy

2

Measured on two outputs differentially as CLK and DB(0:11) are driven and STSQ and XFR are held LOW.

3

Measured on two outputs differentially as the other four are transitioning by 5 V. Measured for both states of INV.

4

Measured from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV.

5

Operation at 85°C ambient temperature requires a thermally optimized PCB layout (see section), minimum airflow of 200 lfm, input clock rate not

exceeding 120 MHz, black-to-white transition ≤ 4 V, and CL ≤ 200 pF.

Applications

Rev. 0 | Page 4 of 24

AD8382

ABSOLUTE MAXIMUM RATINGS

Table 2. Absolute Maximum Ratings1

Parameter Rating

Supply Voltages AVCCx to AGNDx 18 V DVCC to DGND 4.5 V Input Voltages Maximum Digital Input Voltage DVCC + 0.5 V Minimum Digital Input Voltage DGND – 0.5 V Maximum Analog Input Voltage AVCC + 0.5 V Minimum Analog Input Voltage AGND – 0.5 V Internal Power Dissipation2 LFCSP Package @ 25°C Ambient 3.84 W Operating Temperature Range 0°C to 85°C Storage Temperature Range –65°C to +125°C Lead Temperature Range (Soldering 10 sec) 300°C

1

Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum ratings for extended periods may reduce device reliability.

2

48-lead LFCSP Package:

θ

= 26°C/W (JEDEC STD, 4-layer PCB in still air)

JA

θ

= 20°C/W.

JC

ΨJB = 11°C/W in Still Air

OVERLOAD PROTECTION

The AD8382 employs a two-stage overload protection circuit that consists of an output current limiter and a thermal shutdown. The maximum current at any output of the AD8382 is internally limited to 100 mA average. In the event of a momentary short circuit between a video output and a power supply rail (VCC or AGND), the output current limit is sufficiently low to provide temporary protection.

The thermal shutdown “debiases” the output amplifier when the junction temperature reaches the internally set trip point. In the event of an extended short circuit between a video output and power supply rail, the output amplifier current continues to switch between 0 mA and 100 mA typ. with a period set by the thermal time constant and hysteresis of the thermal trip point. The thermal shutdown provides long-term protection by limiting average junction temperature to a safe level.

MAXIMUM POWER DISSIPATION

The maximum power that the AD8382 can safely dissipate is limited by its junction temperature. The maximum safe junction temperature for plastic encapsulated devices, as determined by the plastic’s glass transition temperature, is approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for extended periods can result in device failure.

OPERATING TEMPERATURE RANGE

Although the maximum safe operating junction temperature is higher, the AD8382 is 100% tested at a junction temperature of 125°C. Consequently, the maximum guaranteed operating junction temperature is 125°C. To ensure operation within the specified operating temperature range, it is necessary to limit the maximum power dissipation to:

)–(

TT

JMAX

P

≈

DMAX

where T

= 125°C

JMAX

AD8382 ON A 4–LAYER JEDEC PCB WITH THERMALLY OPTIMIZED

LANDING PATTERN AS DESCRIBED IN THE APPLICATION NOTES

2.00

1.75 120MHz

1.50

STILL AIR

1.25 60Hz XGA

1.00

POWER DISSIPATION (W)

Quiescent

0.75

0.50

65 90 95 100 105 11085807570 115

MAXIMUM AMBIENT TEMPERATURE (°C)

Figure 2. Maximum Power Dissipation vs. Temperature.

JA

200 lfm

9.0–(θ

×

A

3

500 lfm

Note: Quiescent power dissipation is 0.74 W when operating

under the conditions specified in this data sheet.

)

lfminAirflow

EXPOSED PADDLE

To ensure a high degree of reliability, the exposed paddle must be electrically connected to AVCC.

To ensure optimized thermal performance, the exposed paddle must be thermally connected to the AVCC plane as described in the Applications section.

Rev. 0 | Page 5 of 24

When driving a 6-channel XGA panel with an input capacitance of 200 pF, the AD8382 dissipates a total of 1.14 W when displaying 1 pixel wide alternating white and black vertical lines generated by a standard 60 Hz XGA input video.

The total power dissipation of the AD8382 is 1.67 W when operating at the maximum specified frequency of 120 MHz, under the conditions specified in this data sheet (Figure 2).

AD8382

V

TIMING CHARACTERISTICS

Table 3. Timing Parameters and Conditions

Parameter Conditions Min Typ Max Unit

t1, Data Setup Time 0 ns

t2, Data Hold Time 3 ns

t3, STSQ Setup Time 1 ns

t4, STSQ Hold Time 3 ns

t5, XFR Setup Time 1 ns

t6, XFR Hold Time 3 ns

t7, CLK High Time 3 ns

t8, CLK Low Time

t9, CLK to VIDx Delay To 50% of VIDx 10 12 14 ns

t

INV to VIDx Delay To 50% of VIDx 10.4 12.4 14.4 ns

10,

CLK

DB(0:11)

STSQ

XFR

t

f

Figure 3. Timing Requirement E/O = HIGH

t

r

t

7

t

1

t

3

t

5

t

4

t

6

t

8

tr, tf = 2 ns (10% to 90%)

t

8

2

V

TH

V

TH

t

7

2.5 ns

CLK

V

TH

XFR

V

TH

INV

ID(0:5)

V

TH

50%

t

10

Figure 5. Output Timing

V

TH

V

TH

t

9

CLK

DB(0:11)

STSQ

XFR

t

1

t

3

t

5

t

6

t

4

V

TH

Figure 4. Timing Requirement E/O = LOW

t

2

V

TH

V

TH

V

TH

Rev. 0 | Page 6 of 24

AD8382

A

4

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

CLK

XFR

STSQNCNC

4847464544

V1

AVCCDAC

AGNDDACVREFHI

4342414039

VREFLO

V2

38

AGND0

37

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

DB10

DB11

1

PIN 1 INDICATOR

2

3

4

5

6

7

8

9

10

11

12

13

E/O

14

R/L

(Not to Scale)

15

16

INV

DGND

AD8382

TOP VIEW

17

18NC19

DVCC

AVCCBIAS

20

STBY

21

22

BYP

AGNDBIAS

Figure 6. 48-Lead LFCSP, 7 mm × 7 mm Package

36

VID0

35

AVCC0,1

34

VID1

33

GND1,2

32

VID2

31

AVCC2,3

30

VID3

29

GND3,

28

VID4

27

AVCC4,5

VID5

26

25

AGND5

23

24

NC

NC = NO CONNECT

Table 4. Pin Function Descriptions

Mnemonic Function Description

DB(0:11) Data Input 12-Bit Data Input. MSB = DB(11). CLK Clock Clock Input. STSQ Start Sequence

R/L Right/Left Select

E/O Even/Odd Select

XFR Data Transfer

VID0–VID5 Analog Outputs These pins are directly connected to the analog inputs of the LCD panel. V1,V2 Reference Voltages

VREFHI,

Full-Scale References The voltage applied between these pins sets the full-scale output voltage.

VREFLO INV Invert

DVCC Digital Power Supply Digital Power Supply. DGND Digital Supply Return This pin is normally connected to the analog ground plane. AVCCx Analog Power Supplies Analog Power Supplies. AGNDx Analog Supply Returns Analog Supply Returns. BYP Bypass A 0.1 µF capacitor connected between this pin and AGND ensures optimum settling time. STBY Standby When HIGH, the internal circuits are debiased and the power dissipation drops to a minimum.

A new data loading sequence begins on the rising edge of CLK when this input was HIGH on the preceding rising edge of CLK and the E/O input is held HIGH. A new data loading sequence begins on the falling edge of CLK when this input was HIGH on the preceding falling edge of CLK and the E/O input is held LOW.

A new data loading sequence begins on the left, with Channel 0, when this input is LOW, and on the right, with Channel 5, when this input is HIGH.

The active CLK edge is the rising edge when this input is held HIGH and the falling edge when this input is held LOW. Data is loaded sequentially on the rising edges of CLK when this input is HIGH and on the falling edges when this input is LOW.

Data is transferred to the outputs on the immediately following falling edge of CLK when this input is HIGH on the rising edge of CLK.

The voltages applied between these pins and AGND set the reference levels of the analog outputs.

When this pin is HIGH, the analog output voltages are at or above V2. When this pin is LOW, the analog output voltages are at or below V1.

Rev. 0 | Page 7 of 24

AD8382

TYPICAL PERFORMANCE CHARACTERISTICS

1.00

0.75

0.50

0.25

0.00

7V

–0.25

–0.50

OUTPUT (%)

–0.75

–1.00

–1.25

–1.50

–20 0 20 40 60 80 100 120 140 160 180

TIME (ns)

Figure 7. Output Settling Time (Rising Edge),

C

= 200 pF, 5 V Step, INV = LOW

L

1.50

1.25

1.00

0.75

0.50

0.25

0.00

OUTPUT (%)

–0.25

–0.50

–0.75

–1.00

2V

–20 0 20 40 60 80 100 120 140 160 180

TIME (ns)

Figure 10. Output Settling Time (Falling Edge),

C

= 200 pF, 5 V Step, INV = LOW

L

1.00

0.75

0.50

0.25

0.00

12V

–0.25

–0.50

OUTPUT (%)

–0.75

–1.00

–1.25

–1.50

–20 0 20 40 60 80 100 120 140 160 180

TIME (ns)

Figure 8. Output Settling Time (Rising Edge),

C

= 200 pF, 5 V Step, INV = HIGH

L

0pF, 12V

47pF, 12V

100pF, 12V

150pF, 12V

200pF, 12V

0.25%/DIV

OUTPUT (%)

250pF, 12V

300pF, 12V

1.50

1.25

1.00

0.75

0.50

0.25

0.00

OUTPUT (%)

–0.25

–0.50

–0.75

–1.00

OUTPUT (%)

7V

–20 0 20 40 60 80 100 120 140 160 180

TIME (ns)

Figure 11. Output Settling Time (Falling Edge),

C

= 200 pF, 5 V Step, INV = HIGH

L

0pF, 7V

47pF, 7V

100pF, 7V

0.25%/DIV

150pF, 7V

200pF, 7V

250pF, 7V

300pF, 7V

–15 0 15 30 45 60 75 90 105 120 135

TIME (ns)

Figure 9. Output Settling Time (Rising Edge) vs. CL,

5 V Step, INV = HIGH

Rev. 0 | Page 8 of 24

–15 0 15 30 45 60 75 90 105 120 135

TIME (ns)

Figure 12. Output Settling Time (Falling Edge) vs. CL,

5 V Step, INV = HIGH