Analog Devices AD8380 b Datasheet

Fast, High-Voltage Drive, 6-Channel Output

DecDriver™ Decimating LCD Panel Driver

FEATURES High-Voltage Drive to Within 1.3 V of Supply Rails 24 V Supply for Fast Output Voltage Drivers High Update Rates: Fast 75 Ms/s 10-Bit Input Word Rate Low Power Dissipation, 550 mW with Power-Down Voltage Controlled Video Reference and Full-Scale

(Contrast) Output Levels INV Bit Reverses Polarity of Video Signal Nominal 3.3 V Logic and 15 V Analog Supplies Flexible Logic

Addressable or Sequential Channel Loading

STSQ/CS Allow Parallel AD8380 Operation for XGA

and Greater Resolution Drives Capacitive Loads 26 ns Settling Time to 1% Up to 150 pF Load Slew Rate 270 V/␮s Available in 44-Lead MQFP

APPLICATIONS Poly Si LCD Panel Analog Column Driver

DB [0:9]

CLK

STSQ/CS

XFR

E/O

R/L

A[0:2]

STBY

BYP

VREFHI

VREFLO

AD8380

FUNCTIONAL BLOCK DIAGRAM

CHANNEL

SELECTOR

BIAS

SCALING

CONTROL

AD8380

1010

2-STAGE

LATCH

2-STAGE

LATCH

2-STAGE

LATCH

2-STAGE

LATCH

2-STAGE

LATCH

2-STAGE

LATCH

INV VMID

DAC

VID0

VID1

VID2

VID3

VID4

VID5

PRODUCT DESCRIPTION

The AD8380 provides a fast, 10-bit latched decimating digital input that drives 6-channel high voltage drive outputs. The 10bit input word is sequentially muxed into six separate high speed, bipolar DACs. Flexible digital input formats allow several AD8380s to be used in parallel for higher resolution displays. STSQ/CS, in conjunction with 3-bit addressable channel-loading pins, allows loading of the digital words either sequentially or randomly, and R/L control sets loading as either left to right, or vice versa. 6-channel high voltage output drivers drive to within

1.3 V of the rails to rated settling time. The output signal can be adjusted for dc signal reference, signal inversion or contrast for maximum flexibility.

The AD8380 is fabricated on ADI’s XFCB26 fast bipolar 26 V process, providing fast input logic, trimmed accuracy bipolar DACs and fast settling, high voltage precision drive amplifiers on the same chip.

The AD8380 dissipates nominally 0.55 W of static power. STBY pin reduces power to a minimum, with fast recovery.

The AD8380 is offered in a 44-lead 10 × 10 × 2.0 mm MQFP package and operates over the commercial temperature range of 0°C to 85°C.

DecDriver is a trademark of Analog Devices, Inc.

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001

AD8380–SPECIFICATIONS

(@ 25ⴗC, AVCC = 15 V, DVCC = 3.3 V, T otherwise noted)

= 0ⴗC, T

MIN

= 85ⴗC, unless

MAX

Model Conditions Min Typ Max Unit

VIDEO DC PERFORMANCE

to T

MIN

MAX

VDE DAC Code = 450 to 800 –7.5 +1 +7.5 mV VCME DAC Code = 450 to 800 –3.5 +0.5 +3.5 mV Scale Factor Error DAC Code = 0 to 1023 –0.25 +0.25 % Offset Error DAC Code = 0 to 1023 –7 +1 +7 mV

REFERENCE INPUTS

VMID Range

6 7 7.5 V VMID Bias Current 3 µA VFS Range VFS = 2 × (VREFHI–VREFLO) 1 5 6 V VREFHI VREFLO +0.5 AVCC – 2.5 AVCC V VREFLO VMID – 0.5 VREFHI – 2.5 VREFHI – 0.5 V VREFHI Input Resistance to VREFLO 3.3 kΩ VREFLO Bias Current 0.2 µA VREFHI Input Current

VFS = 5 V 750 µA

RESOLUTION

Coding Binary 10 Bits

DIGITAL INPUT CHARACTERISTICS

Input Data Update Rate 75 Ms/s

Clock to Data Setup Times: t Clock to STSQ Setup Times: t Clock to XFR Setup Times: t

Maximum CLK Rise and Fall Time, t Clock to A[0:2] Hold Times: t Clock to Data Hold Times: t Clock to STSQ Hold Times: t Clock to XFR Hold Times: t Clock to A[0:2] Setup Times: t

Threshold Voltage 1.4 V

1ns

4ns

1ns

3pF

0.6 µA

2.0 V

0.8 V

VIDEO OUTPUT CHARACTERISTICS

Output Voltage Swing AVCC – VOH, VOL – AVEE 1.1 1.3 V CLK to VID Delay

50% of VIDx 13.5 15.5 17.5 ns

Output Current 30 mA

VIDEO OUTPUT DYNAMIC PERFORMANCE T

MIN

to T

MAX

, VO = 5 V Step,

CL = 150 pF, RS = 25 Ω Data Switching Slew Rate 270 V/µs Invert Switching Slew Rate 625 V/µs Data Switching Settling Time to 1% Data Switching Settling Time to 0.25% 35 65 ns Invert Switching Settling Time to 1% Invert Switching Settling Time to 0.25% 85 100 ns CLK Feedthrough All-Hostile Crosstalk

26 32 ns

30 40 ns

2 5 mV p-p

Amplitude 95 mV p-p Glitch Duration 40 ns

POWER SUPPLY

Supply Rejection (VDE) +VS = 15 V ± 1 V 1 mV/V DVCC, Operating Range 3 5.5 V DVCC, Quiescent Current 22 35 mA AVCC, Operating Range 9 24 V Total AVCC Quiescent Current 33 44 mA STBY AVCC Current STBY = H 0.5 5 mA STBY DVCC Current STBY = H 0.1 5 mA

OPERATING TEMPERATURE RANGE 0 85 °C

NOTES

For definitions of VDE and VCME, see the Transfer Function section. Scale factor error is expressed as percentage of VFS.

See Figure 1 for valid ranges of VMID.

VREFHI Input Current = (VREFHI – VREFLO)/(VREFHI Input Resistance) = 2.5 V/3.3 kΩ.

Delay time from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV.

For best settling time results, use minimum series output resistance, RS of 25 Ω.

An output channel is selected, and glitch is monitored as CLK is driven. STSQ and XFR are set to logic low.

Input data is loaded such that any five output channels change by VFS (i.e., 5 V), and the sixth unselected channel is monitored. Measurement is made for both states of INV.

Specifications subject to change without notice.

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REV. B

AD8380

VFS – Volts

6 7.5

VMID – Volts

4.5

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 NC No Connect. 2–11 DB[0:9] Video Data Inputs. DB9 is the MSB. 12 E/O Even/Odd data select, input latches are loaded at the falling edge of CLK if E/O is low or

rising edge if E/O is high.

13 R/L Determines starting point of internally generated channel-loading sequence.

R/L Low (when address = 111) loads from Channel 0 up to Channel 5.

14 INV When high, analog video outputs are above the VMID setpoint. See Figure 3. 15, 16 DVEE, DVCC Digital Supplies. Nominally 3.3 V and 0 V, respectively. 17, 20, 22, 24,

26, 28, 30, 32, 34, 37, 38 AVCCxxx, AVEExxx Analog Supplies. Nominally 15 V and 0 V, respectively.

18 STBY Stand By. When high, all digital and analog circuits are “debiased” and the power dissipation

drops to a minimum. 19 BYP An external capacitor connected from here to V 21 VMID Externally supplied voltage applied here sets the midpoint reference for the video output. 23, 25, 27, 29,

31, 33 VID5–VID0 Analog Video Outputs. 36, 35 VREFHI, VREFLO Voltage between these pins sets DAC full-scale range. An external reference must be applied

and should be common to all devices to ensure best tracking. 39–41 A[0:2] 3-bit channel address for addressable loading of the digital input latches. 42 STSQ/CS STSQ to start internal sequencing or Chip Select to enable addressable channel addressing.

See functional description. Used in conjunction with A[0:2]. 43 XFR If XFR = HIGH at the rising edge of CLK, data is transferred to the DACs on the next falling

edge of CLK. See Figures 4, 6, 7, and 8. 44 CLK Master Clock Input.

will help to ensure rapid DAC settling time.

CHANNEL SELECTION FUNCTIONALITY

There are two channel selection modes, addressed channel loading, (in which the user directly controls which DAC is loaded), and internally sequenced loading (in which the user controls the direction and clock phase in which the loading proceeds).

ADDRESSED CHANNEL LOADING:

When channel address (A0, A1, A2) = 000 through 101, the video data is loaded into Channels 0 through 5. (STSQ/CS functions as “Chip Selection” this case.)

INTERNALLY SEQUENCED LOADING:

When channel address = 111 the video data is loaded in a sequence determined internally. The sequencing is initiated by a pulse applied to STSQ/CS input. The count proceeds from 0 to 5 if R/L is LOW or from 5 to 0 if R/L is HIGH.

DAC TRANSFER FUNCTION

= VMID + VFS × (1 – N/1023); if INV is HIGH,

OUT

= VMID – VFS × (1 – N/1023); if INV is LOW

OUT

where VFS = 2 × (VREFHI – VREFLO)

MAXIMUM OUTPUT VOLTAGE

The maximum output signal swing is constrained by the output voltage compliance of the DACs and the output dynamic range of the output amplifiers. The minimum voltage allowed at the outputs of the DACs is about 6 V. This constrains the minimum value of VMID to be 6 V. The output amplifiers will swing and settle cleanly, as described on the specification page, for output voltages within 1.5 V from each supply voltage rail.

For a given value of V

, the voltage required to saturate the

MID

video output voltages defines the maximum usable full-scale voltage. For example, if VMID is less than AVCC/2, the maximum value of VFS is (VMID – 1.5 V). If VMID is greater than AVCC/2, the maximum useful VFS is (AVCC – 1.5 – VMID). Figure 1 graphically describes these limiting factors.

Figure 1. Valid Range for VMID with Respect to VFS (AVCC = 15 V)

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AD8380

ABSOLUTE MAXIMUM RATINGS

Supply Voltage AVCC–AVEE . . . . . . . . . . . . . . . . . . . . . 26 V

Internal Power Dissipation

Quad Flat Package (S) . . . . . . . . . . . . . . . . . . . . . . . 1.7 W

Output Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Associated Text

Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C

Operating Temperature Range . . . . . . . . . . . . . . 0°C to 85°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Specification is for device in free air:

44-Lead MQFP Package: θJA = 73°C/W (Still Air), where PD = (TJ – TA)/θJA.

θJC = 22°C/W.

PIN CONFIGURATION

CLK

XFR

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

(MSB) DB9

NC = NO CONNECT

STSQ/CSA0A1A2AVCCDAC

44 43 42 41 40 39 38 37 36 35 34

PIN 1 IDENTIFIER

AD8380

TOP VIEW

(Not to Scale)

12 13 14 15 16 17 18 19 20 21 22

INV

R/L

E/O

DVEE

DVCC

AVCC BIAS

AVEEDAC

BYP

STBY

VREFHI

VREFLO

AVEE0

VMID

AVEE5

AVEE BIAS

VID0

AVCC0,1

VID1

AVEE1,2

VID2

AVCC2,3

VID3

AVEE3,4

VID4

AVCC4,5

VID5

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the AD8380 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure.

Output Short Circuit Limit

The AD8380’s internal short circuit limitation is not sufficient to protect the device in the event of a direct short circuit between a video output and a power supply voltage rail (V

or VEE). Tem-

porary short circuits can reduce an output’s ability to source or sink current and, therefore, impact the device’s ability to drive a load. Short circuits of extended duration can cause metal lines to fuse open, rendering the device nonfunctional.

To prevent these problems, it is recommended that a series resistor of 25 Ω or greater be placed as close as possible to the AD8380’s video outputs. This will serve to substantially reduce the magnitude of the fault currents and protect the outputs from damage caused by intermittent short circuits. This may not be enough to guarantee that the maximum junction temperature (150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curve in Figure 2 below.

3.0

TJ, MAX = 150ⴗC

2.5

2.0

1.5

1.0

MAXIMUM POWER DISSIPATION – Watts

0.5 10 20 30 40 50 60 70

AMBIENT TEMPERATURE – ⴗC

800

Figure 2. Maximum Power Dissipation vs. Temperature

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD8380JS 0°C to 85°C 44-Lead MQFP S-44A

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8380 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4–

WARNING!

ESD SENSITIVE DEVICE

REV. B

Typical Performance Characteristics–AD8380

20ns/DIV

VMID = 7V VFS = 5V

VMID

1V/DIV

25⍀

150pF

VIDX

VMID – VFS

20ns/DIV

VMID = 7V VFS = 5V

VMID

1V/DIV

25⍀

150pF

VIDX

VMID + VFS

20ns/DIV

VMID = 7V VFS = 5V

VMID

1V/DIV

25⍀

150pF

VIDX

VMID + VFS

1.25V/DIV

VMID – VFS

CODE = 0 VMID = 7V VFS = 5V

25⍀

VIDX

INV = L

150pF

20ns/DIV

INV = H

TPC 1. Invert Switching 10 V Step Response (Rise) at C

VMID + VFS

1.25V/DIV

INV = H

CODE = 0 VMID = 7V VFS = 5V

25⍀

VIDX

150pF

TPC 4. Data Switching Full-Scale Step Response (Fall) at

CL, INV = L

VMID – VFS

20ns/DIV

INV = L

TPC 2. Invert Switching 10 V Step Response (Fall) at C

VMID = 7V VFS = 5V

VMID

1V/DIV

VMID – VFS

20ns/DIV

VIDX

25⍀

150pF

TPC 3. Data Switching Full-Scale Step Response (Rise) at CL, INV = L

TPC 5. Data Switching Full-Scale Step Response (Rise) at

, INV = H

TPC 6. Data Switching Full-Scale Step Response (Fall) at CL, INV = H

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