ANALOG DEVICES AD8376 Service Manual

A0A1A2A3A

VCCA

–

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Ultralow Distortion IF Dual VGA

FEATURES

Dual independent digitally controlled VGAs Bandwidth of 700 MHz (−3 dB) Gain range: −4 dB to +20 dB Step size: 1 dB ± 0.2 dB Differential input and output Noise figure: 8.7 dB @ maximum gain Output IP3 of ~50 dBm at 200 MHz Output P1dB of 20 dBm at 200 MHz Dual parallel 5-bit control interface Provides constant SFDR vs. gain Power-down control Single 5 V supply operation 32-lead, 5 mm x 5 mm LFCSP

APPLICATIONS

Differential ADC drivers Main and diversity IF sampling receivers Wideband multichannel receivers Instrumentation

GENERAL DESCRIPTION

The AD8376 is a dual channel, digitally controlled, variable gain wide bandwidth amplifier that provides precise gain control, high IP3, and low noise figure. The excellent distortion performance and high signal bandwidth make the AD8376 an excellent gain control device for a variety of receiver applications.

Using an advanced high speed SiGe process and incorporating

roprietary distortion cancellation techniques, the AD8376

p achieves 50 dBm output IP3 at 200 MHz.

The AD8376 provides a broad 24 dB gain range with 1 dB

solution. The gain of each channel is adjusted through

re dedicated 5-pin control interfaces and can be driven using standard TTL levels. The open-collector outputs provide a flexible interface, allowing the overall signal gain to be set by the loading impedance. Thus, the signal voltage gain is directly proportional to the load.

Each channel of the AD8376 can be individually powered on by

pplying the appropriate logic level to the ENBA and ENBB

a power enable pins. The quiescent current of the AD8376 is typically 130 mA per channel. When powered down, the

AD8376

FUNCTIONAL BLOCK DIAGRAM

4

CHANNEL A

GAIN

DECODER

IPA+

α

IPA–

VCMA

VCMB

IPB+

α

IPB–

CHANNEL B

GAIN

DECODER

B0B1B2B3B4

Figure 1.

AD8376 consumes less than 5 mA and offers excellent input-tooutput isolation, lower than −50 dB at 200 MHz.

Fabricated on an Analog Devices, Inc., high speed SiGe process, th

e AD8376 is supplied in a compact, thermally enhanced, 5 mm × 5mm 32-lead LFCSP package and operates over the temperature range of −40°C to +85°C.

40

–50

–60

–70

–80

–90

–100

HARMONIC DISTO RTION (dBc), OUTPUT @ 2V p-p

–110

40 60 80 100 120 140 160 180 200

Figure 2. Harmonic Distortion and Output IP3 vs. Frequency

FREQUENCY (MHz )

OIP3

HD2

HD3

AD8376

POST-AMP

GNDA

GNDBVCCB

OPA+

OPA–

ENBA

ENBB

OPB+

OPB–

06725-001

65

60

55

50

45

40

OIP3 (dBm), OUTPUT @ 3dBm/TONE

35

30

06725-052

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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REVISION HISTORY

8/07—Revision 0: Initial Version

Basic Structure............................................................................ 12

Applications..................................................................................... 13

Basic Connections...................................................................... 13

Single-Ended-to-Differential Conversion............................... 13

Broadband Operation................................................................ 15

ADC Interfacing......................................................................... 15

Layout Considerations............................................................... 18

Characterization Test Circuits.................................................. 18

Evaluation Board ........................................................................ 19

Outline Dimensions .......................................................................23

Ordering Guide .......................................................................... 23

Rev. 0 | Page 2 of 24

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SPECIFICATIONS

VS = 5 V, T = 25°C, RS = RL = 150 Ω at 140 MHz, 2 V p-p differential output, both channels enabled, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth V Slew Rate 5 V/ns

INPUT STAGE Pin IPA+ and Pin IPA−, Pin IPB+ and Pin IPB−

Maximum Input Swing For linear operation (AV = −4 dB) 8.5 V p-p Differential Input Resistance Differential 120 150 165 Ω Common-Mode Input Voltage 1.85 V CMRR Gain code = 00000 45.5 dB

GAIN

Amplifier Transconductance Gain code = 00000 0.060 0.067 0.074 S Maximum Voltage Gain Gain code = 00000 20 dB Minimum Voltage Gain Gain code ≥ 11000 −4 dB Gain Step Size From gain code = 00000 to 11000 0.93 0.98 1.02 dB Gain Flatness All gain codes, 20% fractional bandwidth for fC < 200 MHz 0.18 dB Gain Temperature Sensitivity Gain code = 00000 8 mdB/°C Gain Step Response For VIN = 100 mV p-p, gain code = 10100 to 00000 5 ns

OUTPUT STAGE Pin OPA+ and Pin OPA−, Pin OPB+ and Pin OPB−

Output Voltage Swing At P1dB, gain code = 00000 13.1 V p-p Output Impedance Differential 16||0.8 kΩ||pF Channel Isolation

NOISE/HARMONIC PERFORMANCE

46 MHz Gain code = 00000

Noise Figure 8.7 dB Second Harmonic V Third Harmonic V Output IP3 2 MHz spacing, 3 dBm per tone 50 dBm Output 1 dB Compression Point 21.3 dBm

70 MHz Gain code = 00000

Noise Figure 8.7 dB Second Harmonic V Third Harmonic V Output IP3 2 MHz spacing, 3 dBm per tone 50 dBm Output 1 dB Compression Point 21.4 dBm

140 MHz Gain code = 00000

Noise Figure 8.7 dB Second Harmonic V Third Harmonic V Output IP3 2 MHz spacing, 3 dBm per tone 51 dBm Output 1 dB Compression Point

200 MHz Gain code = 00000

Noise Figure 8.7 dB Second Harmonic V Third Harmonic V Output IP3 2 MHz spacing, 3 dBm per tone 50 dBm Output 1 dB Compression Point 20.9 dBm

< 2 V p-p (5.2 dBm) 700 MHz

OUT

Measured at differential output f applied to alternate channel (referred to output)

= 2 V p-p −92 dBc

OUT

= 2 V p-p −94 dBc

OUT

= 2 V p-p −89 dBc

OUT

= 2 V p-p −95 dBc

OUT

= 2 V p-p −87 dBc

OUT

= 2 V p-p −97 dBc

OUT

= 2 V p-p −82 dBc

OUT

= 2 V p-p −91 dBc

OUT

or differential input

73 dB

21.6

dBm

Rev. 0 | Page 3 of 24

AD8376

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Parameter Conditions Min Typ Max Unit

POWER INTERFACE

Supply Voltage

VCC and Output Quiescent Current

with Both Channels Enabled vs. Temperature −40°C ≤ TA ≤ +85°C

Power-Down Current, Both Channels ENBA and ENBB Low

vs. Temperature −40°C ≤ TA ≤ +85°C

POWER-UP/GAIN CONTROL Pin A0 to Pin A4, Pin B0 to Pin B4, Pin ENBA, and Pin ENBB

V

IH

V

IL

Logic Input Bias Current 900 nA

Table 2. Gain Code vs. Voltage Gain Look-Up Table

5-Bit Binary Gain Code Voltage Gain (dB)

00000 +20 00001 +19 00010 +18 00011 +17 00100 +16 00101 +15 00110 +14 00111 +13 01000 +12 01001 +11 01010 +10 01011 +9 01100 +8

Thermal connection made to exposed paddle under device 245 250 255 mA

Minimum voltage for a logic high 1.6 Maximum voltage for a logic low

5-Bit Binary Gain Code Voltage Gain (dB)

01101 +7 01110 +6 01111 +5 10000 +4 10001 +3 10010 +2 10011 +1 10100 0 10101 −1 10110 −2 10111 −3 11000 −4 >11000 −4

4.5 5.0 5.5 V

5.4

285 mA

7 mA

0.8 V

mA

V

Rev. 0 | Page 4 of 24

AD8376

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ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage, V ENBA, ENBB, A0 to A4, B0 to B4 −0.6 V to (V Input Voltage, V DC Common Mode VCMA, VCMB ± 0.25 V VCMA, VCMB ± 6 mA Internal Power Dissipation 1.6 W θJA (Exposed Paddle Soldered Down) 34.6°C/W θJC (At Exposed Paddle) 3.6°C/W Maximum Junction Temperature 140°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C

IN+

POS

, V

IN−

5.5 V + −0.6 V)

POS

−0.15 V to +4.15 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 24

AD8376

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

A

GNDA

IPA+

IPA–

A0

29

31

30

PIN 1 INDICATOR

AD8376

TOP VIEW

11

10

12

B0

IPB–

IPB+

VCC

OPA+

OPA–

28

27

26

25

24 OPA+ 23 OPA– 22 ENBA 21 GNDA 20 GNDB 19 ENBB 18 OPB– 17 OPB+

13

14

15

16

OPB–

OPB+

VCCB

GNDB

A1

32

1A2 2A3 3A4 4VCMA 5

CMB

6B4

(Not to Scal e) 7B3 8B2

9

B1

Figure 3. 32-Lead LFCSP

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 A2 MSB − 2 for the Gain Control Interface for Channel A. 2 A3 MSB − 1 for the Gain Control Interface for Channel A. 3 A4 4 VCMA 5 VCMB 6 B4 7 B3 8 B2 9 B1 10 B0 11 IPB+ 12 IPB− 13, 20 GNDB 14 VCCB 15, 17 OPB+ 16, 18 OPB− 19 ENBB 21, 28 GNDA 22 ENBA 23, 25 OPA− 24, 26 OPA+ 27 VCCA 29 IPA− 30 IPA+ 31 A0

MSB for the 5-Bit Gain Control Interface for Channel A. Channel A Input Common-Mode Voltage. Typically bypassed to ground through capacitor. Channel B Input Common-Mode Voltage. Typically bypassed to ground through capacitor. MSB for the 5-Bit Gain Control Interface for Channel B. MSB − 1 for the Gain Control Interface for Channel B. MSB − 2 for the Gain Control Interface for Channel B. LSB + 1 for the Gain Control Interface for Channel B. LSB for the Gain Control Interface for Channel B. Channel B Positive Input. Channel B Negative Input. Device Common (DC Ground) for Channel B. Positive Supply Pin for Channel B. Should be bypassed to ground using suitable bypass capacitor. Positive Output Pins (Open Collector) for Channel B. Require dc bias of +5 V nominal. Negative Output Pins (Open Collector) for Channel B. Require dc bias of +5 V nominal. Power Enable Pin for Channel B. Channel B is enabled with a logic high and disabled with a logic low. Device Common (DC Ground) for Channel A. Power Enable Pin for Channel A. Channel A is enabled with a logic high and disabled with a logic low. Negative Output Pins (Open Collector) for Channel A. Require dc bias of +5 V nominal. Positive Output Pins (Open Collector) for Channel A. Require dc bias of +5 V nominal. Positive Supply Pins for Channel A. Should be bypassed to ground using suitable bypass capacitor. Channel A Negative Input. Channel A Positive Input. LSB for the Gain Control Interface for Channel A.

32 A1 LSB + 1 for the Gain Control Interface for Channel A.

6725-002

Rev. 0 | Page 6 of 24

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TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V, TA = 25°C, RS = RL = 150 Ω, 2 V p-p output, maximum gain unless otherwise noted.

25

46MHz, +5V 70MHz, +5V

20

140MHz, +5V

15

10

5

GAIN (dB)

0

–5

–10

–4

11000010100

5

01111

GAIN CODE

10

01010

15

00101

Figure 4. Gain vs. Gain Code at 46 MHz, 70 MHz, and 140 MHz

20

00000

06725-003

1.0

0.8

0.6

0.4

0.2

0

–0.2

GAIN ERROR (dB)

–0.4

–0.6

–0.8

–1.0

–4

11000010100

5

01111

GAIN CODE

10

01010

15

00101

Figure 7. Gain Step Error, Frequency 140 MHz

20

00000

06725-006

25

20

15

10

5

GAIN (dB)

0

–5

–10

10 100 1000

10

9

25°C

8

85°C

7

–40°C

6 5 4 3 2 1

0 –1 –2 –3

GAIN ERROR (dB)

–4 –5 –6 –7

–8 –9

–10

–4

11000010100

FREQUENCY (MHz)

Figure 5. Gain vs. Frequency Respo

5

01111

GAIN CODE

10

01010

nse

15

00101

Figure 6. Gain Error over Temperature at 140 MHz

20

00000

20dB 19dB 18dB 17dB 16dB 15dB 14dB 13dB 12dB 11dB 10dB 9dB 8dB 7dB 6dB 5dB 4dB 3dB 2dB 1dB 0dB –1dB –2dB –3dB –4dB

25

INPUT MAX RATING

20

BOUNDARY

15

10

OP1dB (dBm)

5

0

06725-004

–4 1 6 11 16 21

GAIN (dB)

200MHz 140MHz 70MHz 46MHz

06725-007

Figure 8. P1dB vs. Gain at 46 MHz, 70 MHz, 140 MHz, and 200 MHz

25

20

15

10

OP1dB (dBm)

5

0

46 100 150 200 250 3 00 350 400 450 500

06725-005

FREQUENCY (MHz)

+25°C +85°C –40°C

06725-008

Figure 9. P1dB vs. Frequency at Maximum Gain, Three Temperatures

Rev. 0 | Page 7 of 24

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52

51

50

49

48

47

46

45

OIP3 (dBm)

44

43

42

41

40

30 50 70 90 110 130 150 170 190 21 0

AV = +20dB

AV = +10dB

AV = 0dB

AV = –4dB

FREQUENCY (MHz)

Figure 10. Output Third-Order Intercept at Four Gains,

Output Level

52

51

50

49

48

47

46

45

OIP3 (dBm)

44

43

42

41

40

–4 –3 –2 –1 0 1 2 3 4 5 6

AV = +10dB

at 3 dBm/Tone

AV = +20dB

AV = –4dB

(dBm)

P

OUT

AV = 0dB

Figure 11. Output Third-Order Intercept vs. Power

at Fou

r Gains, Frequency 140 MHz

55

+25°C 20d B –40°C 20d B +85°C 20d B

50

+25°C 0dB –40°C 0d B +85°C 0dB

45

40

OIP3 (dBm)

35

30

25

–3 –2 –1 0 1 2 3 4 5

06725-009

AV = 20dB

AV = 0dB

P

PER TONE (dBm)

OUT

Figure 13. Output Third-Order Intercept vs. Power,

Freque

ncy 140 MHz, Three Temperatures

70

–75

–80

–85

–90

IMD3 (dBc)

–95

–100

–105

–110

–4 1 6 11 16

06725-010

at 4

6 MHz, 70 MHz, 140 MHz, and 200 MHz, Output Level at 3 dBm/Tone

Figure 14. Two-Tone Output IMD vs. Gain

GAIN (dB)

46MHz 70MHz 140MHz 200MHz

65

60

55

50

OIP3 (dBm)

45

40

35

06725-012

06725-013

70

65

60

55

50

OIP3 (dBm)

45

40

35

30

40 60 80 100 120 140 160 180 200

FREQUENCY (MHz)

+25°C

+85°C

Figure 12. Output Third-Order Intercept vs. Frequency,

e Temperatures, Output Level at 3 dBm/Tone

Thre

–40°C

06725-011

Rev. 0 | Page 8 of 24

70

–75

–80

–85

–90

IMD3 (dBc)

–95

–100

–105

–110

40 60 80 100 120 140 160 180 200

FREQUENCY (MHz)

+85°C

–40°C

+25°C

Figure 15. Two-Tone Output IMD vs. Frequency,

Thre

e Temperatures, Output Level at 3 dBm/Tone

06725-014

ANALOG DEVICES AD8376 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS