Bandwidth of 630 MHz (−3 dB)
Gain range: −4 dB to +20 dB
Step size: 1 dB ± 0.2 dB
Differential input and output
Noise figure: 8 dB @ maximum gain
Output IP3 of ~50 dBm at 200 MHz
Output P1dB of 19 dBm at 200 MHz
Provides constant SFDR vs. gain
Parallel 5-bit control interface
Power-down feature
Single 5 V supply operation
24-lead, 4 mm × 4 mm LFCSP
APPLICATIONS
Differential ADC drivers
High IF sampling receivers
Wideband multichannel receivers
Instrumentation
GENERAL DESCRIPTION
The AD8375 is a digitally controlled, variable gain, wide
bandwidth amplifier that provides precise gain control, high
IP3, and low noise figure. The excellent distortion performance
and high signal bandwidth make the AD8375 an excellent gain
control device for a variety of receiver applications.
Using an advanced high speed SiGe process and incorporating
proprietary distortion cancellation techniques, the AD8375
achieves 50 dBm output IP3 at 200 MHz.
The AD8375 provides a broad 24 dB gain range with 1 dB
resolution. The gain is adjusted through a 5-pin control interface
and can be driven using standard TTL levels. The open-collector
outputs provide a flexible interface, allowing the overall signal
gain to be set by the loading impedance. Thus, the signal
voltage gain is directly proportional to the load.
The AD8375 is powered on by applying the appropriate logic
level to the PWUP pin. The quiescent current of the AD8375 is
typically 130 mA. When powered down, the AD8375 consumes
less than 5 mA and offers excellent input-to-output isolation.
AD8375
FUNCTIONAL BLOCK DIAGRAM
POSCOMM
COM
VIN+
α
VIN–
REGIS TERS
GAIN DECODER
AD8375
POST-AMP
AND
A2A3A4A1 A0
Figure 1.
Fabricated on an Analog Devices, Inc., high speed SiGe process,
the AD8375 is supplied in a compact, thermally enhanced,
4 mm × 4 mm, 24-lead LFCSP package and operates over the
temperature range of −40°C to +85°C.
40
–50
–60
–70
–80
–90
–100
HARMONIC DIST ORTIO N (dBc), O UTPUT @ 2V p-p
–110
406080100120140160180200
Figure 2. Harmonic Distortion and Output IP3 vs. Frequency
FREQUENCY (MHz )
OIP3
HD2
HD3
PWUP
OUT+
OUT+
OUT–
OUT–
65
60
55
50
45
40
35
30
06724-001
OIP3 (dBm), OUTPUT @ 3dBm/TONE
06724-052
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
VS = 5 V, T = 25°C, RS = RL = 150 Ω at 140 MHz, 2 V p-p differential output, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth V
Slew Rate 5 V/ns
INPUT STAGE Pin VIN+ and Pin VIN−
Maximum Input Swing For linear operation (AV = −4 dB) 8.5 V p-p
Differential Input Resistance Differential 125 150 165 Ω
Common-Mode Input Voltage 1.9 V
CMRR Gain code = 00000 55 dB
GAIN
Amplifier Transconductance Gain code = 00000 0.060 0.067 0.074 S
Maximum Voltage Gain Gain code = 00000 20 dB
Minimum Voltage Gain Gain code ≥ 11000 −4 dB
Gain Step Size From gain code = 00000 to 11000 0.89 0.98 1.01 dB
Gain Flatness All gain codes, 20% fractional bandwidth for fC < 200 MHz 0.12 dB
Gain Temperature Sensitivity Gain code = 00000 8 mdB/°C
Gain Step Response For VIN = 100 mV p-p, gain code = 10100 to 00000 5 ns
OUTPUT STAGE Pin VOUT+ and Pin VOUT−
Output Voltage Swing At P1dB, gain code = 00000 12.6 V p-p
Output Impedance Differential 16||0.8 kΩ||pF
NOISE/HARMONIC PERFORMANCE
46 MHz Gain code = 00000
Noise Figure 8.3 dB
Second Harmonic V
Third Harmonic V
Output IP3 2 MHz spacing, +3 dBm per tone 50 dBm
Output 1 dB Compression Point 22 dBm
70 MHz Gain code = 00000
Noise Figure 8.3 dB
Second Harmonic V
Third Harmonic V
Output IP3 2 MHz spacing, 3 dBm per tone 51 dBm
Output 1 dB Compression Point 22 dBm
140 MHz Gain code = 00000
Noise Figure 8.3 dB
Second Harmonic V
Third Harmonic V
Output IP3 2 MHz spacing, 3 dBm per tone 51 dBm
Output 1 dB Compression Point 20 dBm
200 MHz Gain code = 00000
Noise Figure 8.3 dB
Second Harmonic V
Third Harmonic V
Output IP3 2 MHz spacing, 3 dBm per tone 50 dBm
Output 1 dB Compression Point 19 dBm
< 2 V p-p (5.2 dBm) 630 MHz
OUT
= 2 V p-p −92 dBc
OUT
= 2 V p-p −94 dBc
OUT
= 2 V p-p −98 dBc
OUT
= 2 V p-p −95 dBc
OUT
= 2 V p-p −90 dBc
OUT
= 2 V p-p −100 dBc
OUT
= 2 V p-p −85 dBc
OUT
= 2 V p-p −92 dBc
OUT
Rev. 0 | Page 3 of 24
AD8375
Parameter Conditions Min Typ Max Unit
POWER INTERFACE
Supply Voltage 4.5 5.0 5.5 V
VPOS and Output Quiescent Current Thermal connection made to exposed paddle under device 120 125 130 mA
Supply Voltage, V
PWUP, A0 to A4 −0.6 V to (V
Input Voltage, V
DC Common Mode VCOM ± 0.25 V
VCOM ±6 mA
Internal Power Dissipation 825 mW
θJA (Exposed Paddle Soldered Down) 63.6°C/W
θJC (At Exposed Paddle) 14.6°C/W
Maximum Junction Temperature 130°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
IN+
POS
, V
IN−
5.5 V
+ 0.6 V)
POS
−0.15 V to +4.15 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 24
AD8375
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
UP
PW
COMM
COMM
VPOS
COMM
COMM
19
20
21
22
23
24
PIN 1
INDICATOR
1VCOM
2VIN+
3VIN–
AD8375
4A4
TOP VIEW
5A3
(Not to Scale)
6A2
9
7
8
A0
A1
VPOS
Figure 3. 24-Lead LFCSP
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VCOM Common-Mode Pin. Typically bypassed to ground using external capacitor.
2 VIN+ Voltage Input Positive.
3 VIN− Voltage Input Negative.
4 A4 MSB for the 5-Bit Gain Control Interface.
5 A3 MSB − 1 for the Gain Control Interface.
6 A2 MSB − 2 for the Gain Control Interface.
7 A1 LSB + 1 for the Gain Control Interface.
8 A0 LSB for the 5-Bit Gain Control Interface.
9, 10, 12, 13, 23 VPOS Positive Supply Pins. Should be bypassed to ground using suitable bypass capacitor.
11, 14, 20, 21, 22, 24 COMM Device Common (DC Ground).
15, 17 VOUT+ Positive Output Pins (Open Collector). Require dc bias of +5 V nominal.
16, 18 VOUT− Negative Output Pins (Open Collector). Require dc bias of +5 V nominal.
19 PWUP Chip Enable Pin. Enabled with a logic high and disabled with a logic low.