Analog Devices AD8372 Service Manual
41 dB Range, 1 dB Step Size,
FEATURES
Dual independent digitally controlled VGA
Differential input and output
150 Ω differential input
Open-collector differential output
7.8 dB noise figure to 100 MHz @ maximum gain
HD2/HD3 better than 77 dBc for 1 V p-p differential output
−3 dB bandwidth of 150 MHz
41 dB gain range
1 dB step size ± 0.2 dB
Serial 8-bit bidirectional SPI control interface
Wide input dynamic range
Pin-programmable output stage
Power-down feature
Single 5 V supply: 106 mA per channel
32-lead LFCSP, 5 mm × 5 mm package
APPLICATIONS
Differential ADC drivers
CMTS upstream direct sampling receivers
CATV modem signal scaling
Generic RF/IF gain stages
Single-ended-to-differential conversion
Programmable Dual VGA
AD8372
FUNCTIONAL BLOCK DIAGRAM
ENB1
IPC1
INC1
RXT2
CLK1
SDO1
SDI1
LCH1
IPC2
INC2
REF1
AD8372
CHANNEL 2
CHANNEL 1
REGISTERS
AND
GAIN DECODER
Figure 1.
POSTAMP
POSTAMP
REF2
OPC1
ONC1
RXT2
CLK2
SDO2
SDI2
LCH2
OPC2
ONC2
ENB2
07051-001
GENERAL DESCRIPTION
The AD8372 is a dual, digitally controlled, variable gain
amplifier that provides precise gain control, high IP3, and
low noise figure. The excellent distortion performance and
moderate signal bandwidth make the AD8372 a suitable
gain control device for a variety of multichannel receiver
applications.
For wide input dynamic range applications, the AD8372
provides a broad 41 dB gain range. The gain is programmed
through a bidirectional 4-pin serial interface. The serial interface consists of a clock, latch, data input, and data output lines
for each channel.
The AD8372 provides the ability to set the transconductance of
the output stage using a single external resistor. The RXT1 and
RXT2 pins provide a band gap derived stable reference voltage
of 1.56 V. Typically 2.0 k shunt resistors to ground are used to
set the maximum gain to a nominal value of 31 dB. The current
setting resistors can be adjusted to manipulate the gain and
distortion performance of each channel. This is a flexible
feature in applications where it is desirable to trade off distortion
performance for lower power consumption.
The AD8372 is powered on by applying the appropriate logic
level to the ENB1, ENB2 pins. When powered down, the AD8372
consumes less than 2.6 mA and offers excellent input-to-output
isolation. The gain setting is preserved when powered down.
Fabricated on an Analog Devices high frequency BiCMOS
process, the AD8372 provides precise gain adjustment capabilities
with good distortion performance. The quiescent current of the
AD8372 is typically 106 mA per channel. The AD8372 amplifier
comes in a compact, thermally enhanced 5 mm × 5 mm 32-lead
LFCSP package and operates over the temperature range of
−40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
AD8372
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Serial Control Interface Timing ................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
REVISION HISTORY
11/07—Revision 0: Initial Version
Typical Perf or m an c e Charac t e r istics ..............................................8
Theory of Operation ...................................................................... 10
Single-Ended and Differential Signals..................................... 10
Passive Filter Techniques........................................................... 10
Digital Gain Control .................................................................. 10
Driving Analog-to-Digital Converters.................................... 10
Evaluation Board Schematic......................................................... 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 13
Rev. 0 | Page 2 of 16
AD8372
SPECIFICATIONS
VS = 5 V, T = 25°C, ZS = 150 Ω, ZL = 250 Ω at 35 MHz, 1 V p-p differential output, RXT1 = RXT2 = 2.0 k, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth V
INPUT STAGE Pin IPCI, Pin INC1, Pin IPC2, and Pin INC2
Maximum Input Swing at Each Input Pin 5 V p-p
Input Resistance Differential 150 Ω
Common-Mode Input Voltage 2.4 V
CMRR Gain code = 1x101010 (max gain) 55 dB
GAIN
Maximum Voltage Gain Gain code = 1x101010 32 dB
Minimum Voltage Gain Gain code = 1x000001 −9 dB
Gain Step Size From gain code 1x000001 to 1x101010 1.0 dB
Gain Step Accuracy From gain code 1x000001 to 1x101010 ±0.3 dB
Gain Flatness Gain code = 1x101010, from 5 MHz to 65MHz 0.7 dB
Gain Temperature Sensitivity Gain code = 1x101010 7.5 mdB/°C
Step Response For 6 dB gain step, 10% settling 20 ns
OUTPUT STAGE Pin OPCI, Pin ONC1, Pin OPC2, and Pin ONC2
Output Voltage Swing At P1dB, gain code = 1x101010 9 V p-p
Output Resistance Differential 3.5 kΩ
Channel Isolation
NOISE/HARMONIC PERFORMANCE
5 MHz Gain code = 1x101010 (max gain)
Noise Figure 7.8 dB
Second Harmonic 79 dBc
Third Harmonic 91 dBc
Output IP3 32 dBm
Output 1 dB Compression Point 18.2 dBm
35 MHz Gain code = 1x101010 (max gain)
Noise Figure 7.8 dB
Second Harmonic 79 dBc
Third Harmonic 87 dBc
Output IP3 35 dBm
Output 1 dB Compression Point 18.1 dBm
65 MHz Gain code = 1x101010 (max gain)
Noise Figure 7.9 dB
Second Harmonic 78 dBc
Third Harmonic 85 dBc
Output IP3 35 dBm
Output 1 dB Compression Point 17.9 dBm
85 MHz Gain code = 1x101010
Noise Figure 8.1 dB
Second Harmonic 77 dBc
Third Harmonic 85 dBc
Output IP3 35 dBm
Output 1 dB Compression Point 17.7 dBm
< 1 V p-p, C
OUT
Measured at differential output for differential input
applied to alternate channel
< 3pF 130 MHz
LOAD
55 dB
Rev. 0 | Page 3 of 16
AD8372
Parameter Conditions Min Typ Max Unit
POWER INTERFACE
Supply Voltage 4.5 5.5 V
Quiescent Current per Channel
Thermal connection made to exposed paddle under
device
vs. Temperature −40°C ≤ TA ≤ +85°C 135 mA
Power-Down Current, Both Channels ENB1 and ENB2 low 1.2 mA
vs. Temperature −40°C ≤ TA ≤ +85°C 1.3 mA
ENABLE INTERFACE Pin ENB1 and Pin ENB2
Enable Threshold Minimum voltage to enable the device 0.8 V
ENB1, ENB2 Input Bias Current ENB1, ENB2 = 0 V 400 nA
GAIN CONTROL INTERFACE
Pin CLK1, Pin CLK2, Pin SDI1, Pin SDI2, Pin SDO1, Pin
SDO2, Pin LCH1, and Pin LCH2
V
IH
Minimum voltage for a logic high 2.4 V
Input Bias Current 400 nA
Serial Port Output Feedthrough
Worse-case feedthrough from CLK1, CLK2, SDI1,
SDI2, SDO1, SDO2, LCH1, LCH2 to OPC1 and ONC2,
or OPC2 and ONC2
106 mA
−60 dB
Table 2. Gain Code vs. Voltage Gain Look-Up Table
8-Bit Binary Gain Code
1
Voltage Gain (dB)
RW DC 000000 < −60
RW DC 000001 −9
RW DC 000010 −8
RW DC 000011 −7
RW DC 000100 −6
RW DC 000101 −5
RW DC 000110 −4
RW DC 000111 −3
RW DC 001000 −2
RW DC 001001 −1
RW DC 001010 0
RW DC 001011 +1
RW DC 001100 +2
RW DC 001101 +3
RW DC 001110 +4
RW DC 001111 +5
RW DC 010000 +6
RW DC 010001 +7
RW DC 010010 +8
RW DC 010011 +9
RW DC 010100 +10
RW DC 010101 +11
1
RW is the Read/Write bit, RW = 0 for read mode, RW = 1 for write mode. DC is
the Don’t Care bit.
8-Bit Binary Gain Code
1
Voltage Gain (dB)
RW DC 010110 +12
RW DC 010111 +13
RW DC 011000 +14
RW DC 011001 +15
RW DC 011010 +16
RW DC 011011 +17
RW DC 011100 +18
RW DC 011101 +19
RW DC 011110 +20
RW DC 011111 +21
RW DC 100000 +22
RW DC 100001 +23
RW DC 100010 +24
RW DC 100011 +25
RW DC 100100 +26
RW DC 100101 +27
RW DC 100110 +28
RW DC 100111 +29
RW DC 101000 +30
RW DC 101001 +31
RW DC 101010 +32
RW DC 101011 < −60
Rev. 0 | Page 4 of 16
AD8372
SERIAL CONTROL INTERFACE TIMING
t
CLK
CLK1 OR CLK2
LCH1 OR LCH2
SDI1 OR SDI2
NOTES
1. THE FI RST SDI BIT DETERMINES WHETHER THE PART IS WRITING T O OR READING FROM THE INTERNAL GAIN WORD REGI STER. F OR A
WRITE O PERATION, THE FI RST BIT S HOULD BE A HIG H LOGIC LEVEL, FOR A READ OPERATION THE FIRST BI T SHOULD BE A LOGIC 1.
THE GAIN W ORD BIT IS THEN REGISTERED INTO THE SDI PI N ON THE NEXT RISING CL OCK.
t
LS
t
t
DH
DS
DON'T CAREWRITE BIT LSB LSB + 1 LSB + 2 MSB – 2 MSB – 1 MSB
Figure 2. Write Mode Timing Diagram
t
CLK
DCDCREAD BIT DC DC DC DC DC
CLK1 OR CLK2
LCH1 OR LCH2
SDI1 OR SDI2
t
D
t
LS
t
t
DH
DS
t
PW
t
LH
07051-003
t
t
PW
LH
SDO1 OR SDO2
NOTES
1. THE GAI N WORD BIT IS UPDATED AT THE SDO PIN ON THE FAL LING CL OCK EDGE.
LSB LSB + 1 LSB + 2 MSB – 2 MSB – 1 MSB
07051-004
Figure 3. Read Mode Timing Diagram
Table 3. Serial Programming Timing Parameters
Parameter Min Unit
Clock Pulse Width (tPW) 10 ns
Clock Period (tCK) 20 ns
Write Mode
Setup Time Data vs. Clock (tDS) 0.0 ns
Hold Time Data vs. Clock (tDH) 1.6 ns
Setup Time Latch vs. Clock (tLS) −1.8 ns
Hold Time Latch vs. Clock (tLH) 2.0 ns
Read Mode
Clock to Data Out (tD) 4.5 ns
Rev. 0 | Page 5 of 16
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