Analog Devices AD8370 Service Manual

LF to 750 MHz,

FEATURES

Programmable low and high gain (<2 dB resolution)

Low range: −11 dB to +17 dB
High range: 6 dB to 34 dB

Differential input and output

200 Ω differential input

100 Ω differential output
7 dB noise figure @ maximum gain
Two-tone IP3 of 35 dBm @ 70 MHz

−3 dB bandwidth of 750 MHz
40 dB precision gain range
Serial 8-bit digital interface
Wide input dynamic range
Power-down feature
Single 3 V to 5 V supply

APPLICATIONS

Differential ADC drivers
IF sampling receivers
RF/IF gain stages
Cable and video applications
SAW filter interfacing
Single-ended-to-differential conversion

GENERAL DESCRIPTION

The AD8370 is a low cost, digitally controlled, variable gain
amplifier (VGA) that provides precision gain control, high IP3,
and low noise figure. The excellent distortion performance and
wide bandwidth make the AD8370 a suitable gain control
device for modern receiver designs.

Digitally Controlled VGA

FUNCTIONAL BLOCK DIAGRAM

VCCI

3

ICOM

INHI

INLO

ICOM

4

2

1

PRE
AMP

16

15

BIAS CELL

TRANSCONDUCTANCE

SHIFT REGISTER

AND LATCHES

14

13

DATA CLCK LTCH

Figure 1.

70

CODE = LAST 7 BITS OF GAIN CODE
(NO MSB)

60

HIGH GAIN MODE

50

40

30

VOLTAGE GAIN (V/V)

20

10

0

LOW GAIN MODE

HIGH GAIN MODE

LOW GAIN MODE

0 10203040 60 10050 70 80 90 110 120 130

GAIN CODE

Figure 2. Gain vs. Gain Code at 70 MHz

VCCO

12

Δ GAIN

Δ CODE

Δ GAIN

Δ CODE

AD8370

VCCO

11 6

OUTPUT
AMP

AD8370

≅ 0.409

≅ 0.059

5

VOCMPWUP

OCOM

7

8

OPHI

9

OPLO

OCOM

10

03692-001

40

30

20

10

0

VOLTAGE GAIN (dB)

–10

–20

03692-002

–30

For wide input, dynamic range applications, the AD8370
provides two input ranges: high gain mode and low gain mode.
A vernier, 7-bit, transconductance (g

) stage provides 28 dB of

m

gain range at better than 2 dB resolution and 22 dB of gain
range at better than 1 dB resolution. A second gain range, 17 dB
higher than the first, can be selected to provide improved noise
performance.

The AD8370 is powered on by applying the appropriate logic
level to the PWUP pin. When powered down, the AD8370
consumes less than 4 mA and offers excellent input to output
isolation. The gain setting is preserved when operating in a
power-down mode.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

Gain control of the AD8370 is through a serial 8-bit gain control
word. The MSB selects between the two gain ranges, and the
remaining 7 bits adjust the overall gain in precise linear gain steps.

Fabricated on the ADI high speed XFCB process, the high
bandwidth of the AD8370 provides high frequency and low
distortion. The quiescent current of the AD8370 is 78 mA
typically. The AD8370 amplifier comes in a compact, thermally
enhanced 16-lead TSSOP package and operates over the
temperature range of −40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD8370

TABLE OF CONTENTS

Features .............................................................................................. 1

Basic Connections...................................................................... 15

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 13

Block Architecture...................................................................... 13

Preamplifier ................................................................................. 13

Transconductance Stage ............................................................ 13

Output Amplifier........................................................................ 14

Digital Interface and Timing .................................................... 14

Gain Codes.................................................................................. 15

Power-Up Feature ....................................................................... 15

Choosing Between Gain Ranges .............................................. 16

Layout and Operating Considerations .................................... 16

Package Considerations............................................................. 17

Single-Ended-to-Differential Conversion............................... 17

DC-Coupled Operation............................................................. 18

ADC Interfacing......................................................................... 19

3 V Operation ............................................................................. 20

Evaluation Board and Software .................................................... 22

Appendix ......................................................................................... 25

Characterization Equipment..................................................... 25

Composite Waveform Assumption.......................................... 25

Definitions of Selected Parameters.......................................... 25

Outline Dimensions ....................................................................... 28

Applications..................................................................................... 15

REVISION HISTORY

7/05—Rev. 0 to Rev. A

Changes to Features.......................................................................... 1

Changes to Table 1............................................................................ 3

Changes to Figure 11 and Figure 15............................................... 8

Added Figure 12; Renumbered Sequentially ................................ 8

Added Figure 16; Renumbered Sequentially ................................ 9

Changes to Evaluation Board and Software Section.................. 22

Changes to Figure 60...................................................................... 23

Updated Outline Dimensions....................................................... 28

Changes to Ordering Guide.......................................................... 28

1/04—Revision 0: Initial Version

Ordering Guide .......................................................................... 28

Rev. A | Page 2 of 28

AD8370

SPECIFICATIONS

VS = 5 V, T = 25°C, ZS = 200 Ω, ZL = 100 Ω at gain code HG127, 70 MHz, 1 V p-p differential output, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth V
Slew Rate Gain Code HG127, RL = 1 kΩ, AD8370 in compression 5750 V/ns
Gain Code LG127, RL = 1 kΩ, V

INPUT STAGE Pins INHI and IHLO

Maximum Input Gain Code LG2, 1 dB compression 3.2 V p-p
Input Resistance Differential 200 Ω
Common-Mode Input Range 3.2 V p-p
CMRR Differential, f = 10 MHz, Gain Code LG127 77 dB
Input Noise Spectral Density 1.9 nV/√Hz

GAIN

Maximum Voltage Gain
High Gain Mode Gain Code = HG127 34 dB
52 V/V
Low Gain Mode Gain Code = LG127 17 dB

7.4 V/V
Minimum Voltage Gain
High Gain Mode Gain Code = HG1 −8 dB

0.4 V/V
Low Gain Mode Gain Code = LG1 −25 dB

0.06 V/V
Gain Step Size High Gain Mode 0.408 (V/V)/Code
Low Gain Mode 0.056 (V/V)/Code
Gain Temperature Sensitivity Gain Code = HG127 –2 mdB/°C
Step Response For 6 dB gain step, settled to 10% of final value 20 ns

OUTPUT INTERFACE Pins OPHI and OPLO

Output Voltage Swing RL ≥ 1 kΩ (1 dB compression) 8.4 V p-p
Output Resistance Differential 95 Ω
Output Differential Offset V

NOISE/HARMONIC PERFORMANCE

10 MHz

Gain Flatness Within ±10 MHz of 10 MHz ±0.01 dB
Noise Figure 7.2 dB
Second Harmonic
Third Harmonic

1

1

Output IP3 35 dBm
Output 1 dB Compression Point 17 dBm

70 MHz

Gain Flatness Within ±10 MHz of 70 MHz ±0.02 dB
Noise Figure 7.2 dB
Second Harmonic
Third Harmonic

1

1

Output IP3 35 dBm
Output 1 dB Compression Point 17 dBm

< 1 V p-p 750 MHz

OUT

= 2 V p-p 3500 V/ns

OUT

= V

INHI

V

OUT

V

OUT

V

OUT

V

OUT

, over all gain codes ±60 mV

INLO

= 2 V p-p −77 dBc
= 2 V p-p −77 dBc

= 2 V p-p −65 dBc
= 2 V p-p −62 dBc

Rev. A | Page 3 of 28

AD8370

Parameter Conditions Min Typ Max Unit

140 MHz

Gain Flatness Within ±10 MHz of 140 MHz ±0.03 dB
Noise Figure 7.2 dB
Second Harmonic
Third Harmonic
Output IP3 33 dBm
Output 1 dB Compression Point 17 dBm

190 MHz

Gain Flatness Within ±10 MHz of 240 MHz ±0.03 dB
Noise Figure 7.2 dB
Second Harmonic
Third Harmonic
Output IP3 33 dBm
Output 1 dB Compression Point 17 dBm

240 MHz

Gain Flatness Within ±10 MHz of 240 MHz ±0.04 dB
Noise Figure 7.4 dB
Second Harmonic
Third Harmonic
Output IP3 32 dBm
Output 1 dB Compression Point 17 dBm

380 MHz

Gain Flatness Within ±10 MHz of 240 MHz ±0.04 dB
Noise Figure 8.1 dB
Output IP3 27 dBm
Output 1 dB Compression Point 14 dBm

POWER-INTERFACE

Supply Voltage 3.02 5.5 V
Quiescent Current

vs. Temperature
Total Supply Current

Power-Down Current PWUP low 3.7 mA
vs. Temperature

POWER-UP INTERFACE Pin PWUP

Power-Up Threshold
Power-Down Threshold
PWUP Input Bias Current PWUP = 0 V 400 nA

GAIN CONTROL INTERFACE Pins CLCK, DATA, and LTCH

4

V

IH

4

V

IL

Input Bias Current 900 nA

1

Refer to Figure 22 for performance into a lighter load.

2

See the 3 V Operation section for more information.

3

Minimum and maximum specified limits for this parameter are guaranteed by production test.

4

Minimum or maximum specified limit for this parameter is a 6-sigma value and not guaranteed by production test.

1

1

1

1

1

1

3

V

= 2 V p-p −54 dBc

OUT

V

= 2 V p-p −50 dBc

OUT

V

= 2 V p-p −43 dBc

OUT

V

= 2 V p-p −43 dBc

OUT

V

= 2 V p-p –28 dBc

OUT

V

= 2 V p-p –33 dBc

OUT

PWUP High, GC = LG127, RL = ∞, 4 seconds after

72.5 79 85.5 mA
power-on, thermal connection made to exposed
paddle under device

4

−40°C ≤ TA ≤ +85°C 105 mA
PWUP High, V

= 1 V p-p, ZL = 100 Ω reactive,

OUT

82 mA

GC = LG127 (includes load current)

4

4

4

−40°C ≤TA ≤ +85°C 5 mA

Voltage to enable the device 1.8 V
Voltage to disable the device 0.8 V

Voltage for a logic high 1.8 V
Voltage for a logic low 0.8 V

Rev. A | Page 4 of 28

AD8370

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage, VS 5.5 V
PWUP, DATA, CLCK, LTCH VS + 500 mV
Differential Input Voltage,

V

– V

INHI

INLO

Common-Mode Input Voltage,

or V

V

INHI

with Respect to

INLO,

ICOM or OCOM

2 V

V

+ 500 mV (max),

S

– 500 mV,

V

ICOM

V

– 500 mV (min)

OCOM

Internal Power Dissipation 575 mW
θJA (Exposed Paddle Soldered Down) 30°C/W
θJA (Exposed Paddle Not Soldered Down) 95°C/W
θJC (At Exposed Paddle) 9°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range

235°C

(Soldering 60 sec)

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 5 of 28

AD8370

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

116

INHI

2

ICOM

3

VCCI
PWUP
VOCM
VCCO

OCOM

OPHI OPLO

AD8370

4

TOP VIEW

(Not to Scale)

5
6
7
8

Figure 3.16-Lead TSSOP

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 INHI Balanced Differential Input. Internally biased.
2, 15, PADDLE ICOM

Input Common. Connect to a low impedance ground. This node is also connected to the exposed pad

on the bottom of the device.
3 VCCI Input Positive Supply. 3.0 V to 5.5 V. Should be properly bypassed.
4 PWUP Power Enable Pin. Device is operational when PWUP is pulled high.
5 VOCM

Common-Mode Output Voltage Pin. The midsupply ((V

to this pin for external bypassing for additional common-mode supply decoupling. This can be achieved

with a bypass capacitor to ground. This pin is an output only and is not to be driven externally.
6, 11 VCCO Output Positive Supply. 3.0 V to 5.5 V. Should be properly bypassed.
7, 10 OCOM Output Common. Connect to a low impedance ground.
8 OPHI Balanced Differential Output. Biased to midsupply.
9 OPLO Balanced Differential Output. Biased to midsupply.
12 LTCH

Serial Data Latch Pin. Serial data is clocked into the shift register via the DATA pin when LTCH is low. Data

in shift register is latched on the next high-going edge.
13 CLCK Serial Clock Input Pin.
14 DATA Serial Data Input Pin.
16 INLO Balanced Differential Input. Internally biased.

15
14
13
12
11
10

9

INLO
ICOM
DATA
CLCK
LTCH
VCCO
OCOM

03692-003

VCCO

− V

)/2) common-mode voltage is delivered

OCOM

Rev. A | Page 6 of 28

AD8370

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V, ZS = 200 Ω, ZL = 100 Ω, T = 25°C, unless otherwise noted.

70

CODE = LAST 7 BITS OF GAIN CODE
(NO MSB)

60

HIGH GAIN MODE

50

40

30

VOLTAGE GAIN (V/V)

20

10

0

LOW GAIN MODE

Δ GAIN

HIGH GAIN MODE

LOW GAIN MODE

0 10203040 60 10050 70 80 90 110 120 130

GAIN CODE

Δ CODE

Δ GAIN

Δ CODE

≅ 0.409

≅ 0.059

40

30

20

10

0

VOLTAGE GAIN (dB)

–10

–20

03692-004

–30

40

HIGH GAIN CODES SHOWN WITH DASHED LINES

35

30

25

20

15

10

VOLTAGE GAIN (dB)

5

0

–5

LOW GAIN CODES SHOWN WITH SOLID LINES

–10

10 100 1000

FREQUENCY (MHz)

HG127
HG77

HG51

HG25

LG90
HG9

LG36
HG3

LG9

HG102

LG127

HG18

LG18

03692-007

Figure 4. Gain vs. Gain Code at 70 MHz

40

HIGH GAIN MODE

35

30

LOW GAIN MODE

25

20

OUTPUT IP3 (dBm)

15

10

5

0 20 40 60 80 100 120 140

SHADING INDICATES ±3σ FROM THE
MEAN. DATA BASED ON 30 PARTS
FROM TWO BATCH LOTS.

GAIN CODE

Figure 5. Output Third-Order Intercept vs. Gain Code at 70 MHz

45

40

35

30

380MHz

25

20

NOISE FIGURE (dB)

15

10

5

0 20 40 60 80 100 120 140

70MHz

380MHz

70MHz

LOW GAIN MODE

HIGH GAIN MODE

GAIN CODE

Figure 6. Noise Figure vs. Gain Code at 70 MHz

30

25

20

15

10

5

0

–5

03692-006

OUTPUT IP3 (dBV rms)

03692-068

Figure 7. Frequency Response vs. Gain Code

40

35

30

25

20

OUTPUT IP3 (dBm) +25°C

15

SHADING INDICATES ±3σ FROM THE
MEAN. DATA BASED ON 30 PARTS
FROM TWO BATCH LOTS.

10

–40°C

+25°C

UNIT CONVERSION NOTE FOR

100Ω LOAD: dBVrms = dBm–10dB

+85°C

20015050 1000 250 300 350 400

FREQUENCY (MHz)

50

45

40

35

30

25

20

Figure 8. Output Third-Order Intercept vs. Frequency at Maximum Gain

25

20

LG127

15

10

NOISE FIGURE (dB)

5

0

HG18

HG127

03692-009

200 3000 100 400 500 600

FREQUENCY (MHz)

Figure 9. Noise Figure vs. Frequency at Various Gains

OUTPUT IP3 (dBm) –40°C, +85°C

03692-069

Rev. A | Page 7 of 28

AD8370

20

16

12

8

4

OUTPUT P1dB (dB)

0

–4

–8

0 20 40 60 80 100 120 140

LOW GAIN MODE

HIGH GAIN MODE
LOW GAIN MODE

HIGH GAIN MODE

UNIT CONVERSION NOTE:
FOR 100Ω LOAD: dBV rms = dBm–10dB
FOR 1kΩ LOAD: dBV rms = dBm

SHADING INDICATES ±3σ FROM THE
MEAN. DATA BASED ON 30 PARTS
FROM TWO BATCH LOTS.

GAIN CODE

100Ω LOAD

1kΩ LOAD

Figure 10. Output P1dB vs. Gain Code at 70 MHz

0

–10

LOW GAIN MODE OUTPUT IMD (dBc)

–20

–30

–40

–50

–60

–70

–80

–90

0 14012010080604020

HIGH GAIN MODE

LOW GAIN MODE

GAIN CODE

Figure 11. Two-Tone Output IMD3 vs. Gain Code at 70 MHz,

= 2 V p-p Composite Differential

OUT

HIGH GAIN

MODE

MODE

GAIN CODE

35

30

25

20

15

10

OUTPUT IP3 (dBm)

–5

RL = 1 kΩ, V

LOW GAIN

5

0

0 14012010080604020

–50

–60

–70

–80

–90

–100

–110

–120

–130

–140

25

20

15

10

5

0

–5

–10

–15

03692-010

HIGH GAIN MODE OUTPUT IMD (dBc)

03692-011

OUTPUT IP3 (dBV rms)

03692-005

2.0

1.5

1.0

0.5

0

–0.5

GAIN ERROR (dB)

–1.0

ERROR AT –40°C AND +85°C WITH RESPECT TO +25°C.

–1.5

SHADING INDICATES ±3σ FROM THE MEAN. DATA
BASED ON 30 PARTS FROM ONE BATCH LOT.

–2.0

10 100 1000

FREQUENCY (MHz)

–40°C

+85°C

Figure 13. Gain Error over Temperature vs. Frequency, R

20

18

16

14

12

10

OUTPUT P1dB (dBm) –40°C, +85°C

8

SHADING INDICATES ±3σ FROM
THE MEAN. DATA BASED ON 30
PARTS FROM TWO BATCH LOTS.

6

+85°C, 100Ω LOAD

UNIT CONVERSION NOTE:
RE 100Ω LOAD: dBV rms = dBm – 10dB
RE 1kΩ LOAD: dBV rms = dBm

+25°C, 1kΩ LOAD

+85°C, 1kΩ LOAD

FREQUENCY (MHz)

+25°C, 100Ω LOAD

–40°C, 100Ω LOAD

–40°C, 1kΩ LOAD

20015050 1000 250 300 350 400

Figure 14. Output P1dB vs. Frequency

–50
–52
–54
–56
–58
–60
–62
–64
–66

OUTPUT IMD (dBc)

–68
–70
–72
–74
–76
–78
–80
–82
–84

0 40035030025020015010050

–40°C

+25°C

+85°C

FREQUENCY (MHz)

= 100 Ω

L

03692-012

18

16

14

12

10

8

6

4

03692-014

OUTPUT P1dB (dBm) +25°C

03692-013

Figure 12. Output Third-Order Intercept vs. Gain Code at 70 MHz,

= 1 kΩ, V

R

L

= 2 V p-p Composite Differential

OUT

Rev. A | Page 8 of 28

Figure 15. Two-Tone Output IMD3 vs. Frequency at Maximum Gain,

R

= 1 kΩ, V

L

= 2 V p-p Composite Differential

OUT

AD8370

90

5MHz

S

11

270

= 100 Ω Differential

Z

O

60

30

0

330

300

16 DIFFERENT GAIN
CODES REPRESENTED
R+jX FORMAT

03692-017

100

50

OUTPUT IP3 (dBm)

34

32

30

28

26

24

22

20

18

16

14

0 40035030025020015010050

+85°C

–40°C

+25°C

FREQUENCY (MHz)

24

22

20

18

16

14

12

10

8

6

4

Figure 16. Output Third-Order Intercept vs. Frequency at Maximum Gain,

2.0

1.5

1.0

= 1 kΩ, V

R

L

= 2 V p-p Composite Differential

OUT

OUTPUT IP3 (dBV rms)

03692-008

120

1GHz

150

S

180

210

22

240

Figure 19. Input and Output Reflection Coefficients, S11 and S22,

250

200

0.5

0

–0.5

GAIN ERROR (dB)

–1.0

ERROR AT –40°C AND +85°C WITH RESPECT TO +25°C.

–1.5

SHADING INDICATES ±3σ FROM THE MEAN. DATA
BASED ON 30 PARTS FROM ONE BATCH LOT.

–2.0

10 100 1000

FREQUENCY (MHz)

–40°C

+85°C

03692-015

Figure 17. Gain Error over Temperature vs. Frequency, RL = 1 kΩ

0

–10

–20

–30

LOW GAIN, RL = 1k

–40

–50

–60

–70

HARMONIC DISTORTION (dBc)

–80

–90

LOW GAIN, RL = 100

HIGH GAIN, RL = 1k

0 20 40 60 80 100 120 140

Ω

Ω

GAIN CODE

Ω

HIGH GAIN, RL = 100

Ω

03692-016

Figure 18. Second-Order Harmonic Distortion vs. Gain Code at 70 MHz,

V

= 2 V p-p Differential

OUT

150

100

RESISTANCE (Ω)

50

0

0 100 200 300 400 500 600 700

FREQUENCY (MHz)

0

–50

–100

–150

REACTANCE (j Ω)

03692-018

Figure 20. Input Resistance and Reactance vs. Frequency

0

LOW GAIN RL = 1k

–10

–20

–30

–40

–50

–60

–70

HARMONIC DISTORTION (dBc)

–80

–90

0 20 40 60 80 100 120 140

Ω

HIGH GAIN RL = 1k

HIGH GAIN RL = 100

GAIN CODE

Ω

Ω

LOW GAIN RL = 100

Ω

03692-019

Figure 21. Third-Order Harmonic Distortion vs. Gain Code at 70 MHz,

= 2 V p-p Differential

V

OUT

Rev. A | Page 9 of 28

AD8370

0

–10

–20

–30

–40

–50

–60

–70

HARMONIC DISTORTION (dBc)

–80

–90

HD2 RL = 100

HD2 RL = 1k

20015050 1000 250 300 350 400

FREQUENCY (MHz)

Ω

Ω

HD3 RL = 100

HD3 RL = 1k

Ω

Figure 22. Harmonic Distortion vs. Frequency at Maximum Gain,

= 2 V p-p Composite Differential

V

OUT

120

100

80

Ω

03692-020

80

60

40

120

110

100

90

80

70

PSRR (dB)

60

50

40

30

20

1 10010 1000

FREQUENCY (MHz)

03692-023

Figure 25. Power Supply Rejection Ratio vs. Frequency at Maximum Gain

0

–20

–40

FORWARD TRANSMISSION, HG0

FORWARD TRANSMISSION, LG0

60

RESISTANCE (Ω)

40

16 DIFFERENT GAIN

20

CODES REPRESENTED
R+jX FORMAT

0

0 100 200 300 400 500 600 700

FREQUENCY (MHz)

Figure 23. Output Resistance and Reactance vs. Frequency

860

840

HIGH GAIN MODE

820

800

780

760

GROUP DELAY (ps)

LOW GAIN MODE

740

720

700

0 10203040 60 10050 70 80 90 110 120 130

GAIN CODE

Figure 24. Group Delay vs. Gain Code at 70 MHz

20

0

–20

–40

03692-022

REACTANCE (j Ω)

03692-021

–60

ISOLATION (dB)

–80

–100

FORWARD TRANSMISSION, PWUP LOW

REVERSE TRANSMISSION, HG127

–120

10 100 1000

FREQUENCY (MHz)

Figure 26. Various Forms of Isolation vs. Frequency

1400

1300

1200

1100

1000

900

GROUP DELAY (ps)

800

700

600

0 100 200 300 400 500 600 700 800 900

FREQUENCY (MHz)

RL = 100

RL = 1k

Ω

Figure 27. Group Delay vs. Frequency at Maximum Gain

03692-024

Ω

03692-025

Rev. A | Page 10 of 28

AD8370

80

70

60

50

LG32, LG127

HG32, HG127

DIFFERENTIAL OUTPUT (50mV/DIV)

ZERO

40

CMRR (dB)

30

20

10

0

10 100 1000

FREQUENCY (MHz)

Figure 28. Common-Mode Rejection Ratio vs. Frequency

12

10

8

6

4

2

NOISE SPECTRAL DENSITY (nV/ Hz)

0

LG127

HG18

HG127

210 31010 110 410 510 610

FREQUENCY (MHz)

Figure 29. Input Referred Noise Spectral Density vs.

Frequency at Various Gains

03692-026

03692-027

PWUP (2V/DIV)

GAIN CODE HG127

GND

INPUT = –30dBm, 70MHz 100 AVERAGES

TIME (40ns/DIV)

03692-029

Figure 31. PWUP Time Domain Response

DIFFERENTIAL OUTPUT (10mV/DIV)

ZERO

6dB GAIN STEP (HG36 TO LG127)

LTCH (2V/DIV)

GND

TIME (20ns/DIV)

INPUT = –30dBm, 70MHz
NO AVERAGING

03692-030

Figure 32. Gain Step Time Domain Response

VOLTAGE (600mV/DIV)

V

OPHI

V

OPLO

DIFFERENTIAL V

DIFFERENTIAL V

GND

TIME (2ns/DIV)

OUT

IN

Figure 30. DC-Coupled Large Signal Pulse Response

03692-028

Rev. A | Page 11 of 28

VOLTAGE (1V/DIV)

GND

V

DIFFERENTIAL

OUT

TIME (2ns/DIV)

Figure 33. Overdrive Recovery

03692-031

AD8370

85

2.75

80

75

70

65

60

SUPPLY CURRENT (mA)

55

50

35

30

25

20

COUNT

15

10

LOW GAIN

GAIN CODE

HIGH GAIN

644816 320 80 96 112 128

03692-032

2.70

2.65

2.60

(V)

CM

V

2.55

2.50

2.45

2.40

+85°C

+25°C

–40°C

LOW GAIN MODE HIGH GAIN MODE

09632 6403264

GAIN CODE

96128

Figure 34. Supply Current vs. Gain Code Figure 36. Common-Mode Output Voltage vs. Gain Code at

Various Temperatures

MEAN: 51.9

σ

: 0.518

DATA FROM 136 PARTS
FROM ONE BATCH LOT

03692-034

5

0

50 51 52 53 54 55

GAIN (V/V)

Figure 35. Distribution of Voltage Gain, HG127, 70 MHz, R

= 100 Ω

L

03692-033

Rev. A | Page 12 of 28

AD8370

THEORY OF OPERATION

The AD8370 is a low cost, digitally controlled, fine adjustment
variable gain amplifier (VGA) that provides both high IP3 and
low noise figure. The AD8370 is fabricated on an ADI
proprietary high performance 25 GHz silicon bipolar process.
The –3 dB bandwidth is approximately 750 MHz throughout
the variable gain range. The typical quiescent current of the
AD8370 is 78 mA. A power-down feature reduces the current to
less than 4 mA. The input impedance is approximately 200 Ω
differential, and the output impedance is approximately 100 Ω
differential to be compatible with saw filters and matching
networks used in intermediate frequency (IF) radio
applications. Because there is no feedback between the input
and output and stages within the amplifier, the input amplifier
is isolated from variations in output loading and from
subsequent impedance changes, and excellent input to output
isolation is realized. Excellent distortion performance and wide
bandwidth make the AD8370 a suitable gain control device for
modern differential receiver designs. The AD8370 differential
input and output configuration is ideally suited to fully
differential signal chain circuit designs, although it can be
adapted to single-ended system applications, if required.

BLOCK ARCHITECTURE

The three basic building blocks of the AD8370 are a high/low
gain selectable input preamplifier, a digitally controlled
transconductance (g

VCCI

3

4

2

ICOM

1

INHI

INLO

ICOM

PRE
AMP

16

15

) block, and a fixed gain output stage.

m

VCCO

11 6

BIAS CELL

TRANSCONDUCTANCE

SHIFT REGISTER

AND LATCHES

OUTPUT
AMP

AD8370

14

DATA CLCK LTCH

12

13

Figure 37. Functional Block Diagram

VCCO

10

5

7

8

9

VOCMPWUP

OCOM

OPHI

OPLO

OCOM

PREAMPLIFIER

There are two selectable input preamplifiers. Selection is made
by the most significant bit (MSB) of the serial gain control data­word. In the high gain mode, the overall device gain is 7.1 V/V
(17 dB) above the low gain setting. The two preamplifiers give
the AD8370 the ability to accommodate a wide range of input
amplitudes. The overlap between the two gain ranges allows the
user some flexibility based on noise and distortion demands.
See the

Choosing Between Gain Ranges section for more

information.

03692-035

The input impedance is approximately 200 Ω differential,
regardless of which preamplifier is selected. Note that the input
impedance is formed by using active circuit elements and is not
set by passive components. See

Figure 38 for a simplified

schematic of the input interface.

1mA

INHI/INLO

1mA

2kΩ

VCC/2

03692-036

Figure 38. INHI/INLO Simplified Schematic

TRANSCONDUCTANCE STAGE

The digitally controlled gm section has 42 dB of controllable
gain and makes gain adjustments within each gain range. The
step size resolution ranges from a fine ~ 0.07 dB up to a coarse
6 dB per bit, depending on the gain code. As shown in
the 42 dB total range, 28 dB has resolution of better than 2 dB,
and 22 dB has resolution of better than 1 dB.

Figure 39 shows typical input levels that can be applied to this
amplifier at different gain settings. The maximum input was
determined by finding the 1 dB compression or expansion point
of the V

OUT/VSOURCE

gain. Note that this is not V
way, the change in the input impedance of the device is also
taken into account.

3.2

<0.5dB

[V peak] (V)

V

OUT

2.8

2.4

2.0

1.6

1.2

0.8

0.4

RES

<1dB

17dB
GAIN

12dB
GAIN

RES

6dB
GAIN

34dB
GAIN

0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

<2dB

RES

–8dB GAIN

V

SOURCE

HIGH GAIN

0.1dB GAIN

[V peak] (V)

LOW GAIN

RESOLUTION

–5dB GAIN

–11dB GAIN

–25dB GAIN

Figure 39. Gain Resolution and Nominal Input and

Output Range over the Gain Range

OUT/VIN

<0.5dB

<1dB

RES

<2dB

RES

Figure 39, of

. In this

03692-037

Rev. A | Page 13 of 28

AD8370

O

V

OUTPUT AMPLIFIER

The output impedance is approximately 100 Ω differential and,
like the input preamplifier, this impedance is formed using
active circuit elements. See
of the output interface.

Figure 40 for a simplified schematic

Table 4. Serial Programming Timing Parameters

Parameter Min Unit

Clock Pulse Width (TPW) 25 ns
Clock Period (TCK) 50 ns
Setup Time Data vs. Clock (TDS) 10 ns
Setup Time Latch vs. Clock (TES) 20 ns
Hold Time Latch vs. Clock (TEH) 10 ns

OPHI/OPL

03692-038

VCC/2

740Ω

Figure 40. OPHI/OPLO Simplified Circuit

The gain of the output amplifier, and thus the AD8370 as a
whole, is load dependent. The following equation can be used to
predict the gain deviation of the AD8370 from that at 100 Ω as
the load is varied.

981

ionGainDeviat

For example, if R

LOAD

above that at 100 Ω, all other things being equal. If R

.

=

1

+

R

98

LOAD

is 1 kΩ, the gain is a factor of 1.80 (5.12 dB)

is 50

LOAD

Ω, the gain is a factor of 0.669 (3.49 dB) below that at 100 Ω.

DIGITAL INTERFACE AND TIMING

The digital control port uses a standard TTL interface. The 8-bit
control word is read in a serial fashion when the LTCH pin is
held low. The levels presented to the DATA pin are read on each
rising edge of the CLCK signal.
diagram for the control interface. Minimum values for timing
parameters are presented in
schematic of the digital input pins.

T

DS

DATA

(PIN 14)

CLCK

(PIN 13)

LTCH

(PIN 12)

MSB MSB-1 MSB-2 MSB-3 LSBLSB+1LSB+2LSB+3

T

ES

Figure 41. Digital Timing Diagram

Figure 41 illustrates the timing

Tabl e 4 . Figure 42 is a simplified

T

CK

T

PW

T

EH

03692-039

10μA

CLCK/DATA/LTCH/PWUP

03692-040

Figure 42. Simplified Circuit for Digital Inputs

VOCM

03692-041

CC/2

75Ω

Figure 43. Simplified Circuit for VOCM Output

Rev. A | Page 14 of 28

AD8370

APPLICATIONS

BASIC CONNECTIONS

Figure 44 shows the minimum connections required for basic
operation of the AD8370. Supply voltages between 3.0 V and

5.5 V are allowed. The supply to the VCCO and VCCI pins
should be decoupled with at least one low inductance, surface­mount ceramic capacitor of 0.1 μF placed as close as possible to
the device.

SERIAL CONTROL
INTERFACE

BALANCED
SOURCE

1nF

R

S

2

INLO

ICOM

DATA

AD8370

INHI

ICOM

R

S

2

1nF

VCCI

4

1nF

CLCK

PWUP

11 10 915 1416 13 12

LTCH

VOCM

67823 51

VCCO

VCCO

OCOM

OCOM

OPLO

OPHI

1nF

1nF

R

L

BALANCED
LOAD

GAIN CODES

The AD8370’s two gain ranges are referred to as high gain (HG)
and low gain (LG). Within each range, there are 128 possible
gain codes. Therefore, the minimum gain in the low gain range
is given by the nomenclature LG0 whereas the maximum gain
in that range is given by LG127. The same is true for the high
gain range. Both LG0 and HG0 essentially turn off the variable
transconductance stage, and thus no output is available with
these codes (see

The theoretical linear voltage gain can be expressed with respect
to the gain code as

= GainCode Vernier (1 + (PreGain − 1) MSB)

A

V

where:

is the linear voltage gain.

A

V

GainCode is the digital gain control word minus the MSB

(the final 7 bits).

Figure 26).

0.1μF100pF 0.1μF

FERRITE

Figure 44. Basic Connections

BEAD

FERRITE

BEAD

100pF

+V

(3.0V TO 5.0V)

S

03692-042

The AD8370 is designed to be used in differential signal chains.
Differential signaling allows improved even-order harmonic
cancellation and better common-mode immunity than can be
achieved using a single-ended design. To fully exploit these
benefits, it is necessary to drive and load the device in a
balanced manner. This requires some care to ensure that the
common-mode impedance values presented to each set of
inputs and outputs are balanced. Driving the device with an
unbalanced source can degrade the common-mode rejection
ratio. Loading the device with an unbalanced load can cause
degradation to even-order harmonic distortion and premature
output compression. In general, optimum designs are fully
balanced, although the AD8370 still provides impressive
performance when used in an unbalanced environment.

The AD8370 is a fine adjustment, VGA. The gain control
transfer function is linear in voltage gain. On a decibel scale,
this results in the logarithmic transfer functions shown in
Figure 4. At the low end of the gain transfer function, the slope
is steep, providing a rather coarse control function. At the high
end of the gain control range, the decibel step size decreases,
allowing precise gain adjustment.

Ve rn i er = 0.055744 V/V

PreGain = 7.079458 V/V

MSB is the most significant bit of the 8-bit gain control word.

The MSB sets the device in either high gain mode (MSB = 1)
or low gain mode (MSB = 0).

For example, a gain control word of HG45 (or 10101101 binary)
results in a theoretical linear voltage gain of 17.76 V/V,
calculated as

45 × 0.055744 × (1 + (7.079458 − 1) × 1)

Increments or decrements in gain within either gain range are
simply a matter of operating on the GainCode. Six –dB gain
steps, which are equivalent to doubling or halving the linear
voltage gain, are accomplished by doubling or halving the
GainCode.

When power is first applied to the AD8370, the device is
programmed to code LG0 to avoid overdriving the circuitry
following it.

POWER-UP FEATURE

The power-up feature does not affect the GainCode, and the
gain setting is preserved when in power-down mode. Powering
down the AD8370 (bringing PWUP low while power is still
applied to the device) does not erase or change the GainCode
from the AD8370, and the same gain code is in place when the
device is powered up, that is, when PWUP is brought high
again. Removing power from the device all together and
reapplying, however, reprograms to LG0.

Rev. A | Page 15 of 28

AD8370

CHOOSING BETWEEN GAIN RANGES

There is some overlap between the two gain ranges; users can
choose which one is most appropriate for their needs. When
deciding which preamp to use, consider resolution, noise,
linearity, and spurious-free dynamic range (SFDR). The most
important points to keep in mind are

• The low gain range has better gain resolution.

• The high gain range has a better noise figure.

• The high gain range has better linearity and SFDR at

higher gains.

• Conversely, the low gain range has higher SFDR at lower

gains.

Figure 45 provides a summary of noise, OIP3, IIP3, and SFDR
as a function of device power gain. SFDR is defined as

2

()

3

where:

IIP3 is the input third-order intercept point, the output
intercept point in dBm minus the gain in dB.

NF is the noise figure in dB.

N

is source resistor noise, –174 dBm for a 1 Hz bandwidth at

S

300°K (27°C).

In general, N

= 10 log10(kTB), where k = 1.374 ×10

S

temperature in degrees Kelvin, and B is the noise bandwidth in
Hertz.

50

40

30

20

10

0

–10

–20

NOISE FIGURE (dB); OIP3 AND IIP3 (dBm)

–30

–30 –20 –10 0 10 20 30 40

NF LOW GAIN

IIP3 LOW GAIN

SFDR LOW GAIN

Figure 45. OIP3, IIP3, NF, and SFDR Variation with Gain

As the gain increases, the input amplitude required to deliver
the same output amplitude is reduced. This results in less
distortion at the input stage, and therefore the OIP3 increases.
At some point, the distortion of the input stage becomes small
enough such that the nonlinearity of the output stage becomes
dominant. The OIP3 does not improve significantly because the

NNFIIP3SFDR −−=

S

OIP3 LOW GAIN

NF HIGH GAIN

POWER GAIN (dB)

−23

OIP3 HIGH GAIN

IIP3 HIGH GAIN

SFDR HIGH GAIN

, T is the

180

170

160

150

140

130

120

110

100

SFDR (dB)

03692-043

gain is increased beyond this point, which explains the knee in
the OIP3 curve. The IIP3 curve has a knee for the same reason;
however, as the gain is increased beyond the knee, the IIP3
starts to decrease rather than increase. This is because in this
region OIP3 is constant, therefore the higher the gain, the lower
the IIP3. The two gain ranges have equal SFDR at
approximately 13 dB power gain.

LAYOUT AND OPERATING CONSIDERATIONS

Each input and output pin of the AD8370 presents either a
100 Ω or 50 Ω impedance relative to their respective ac grounds.
To ensure that signal integrity is not seriously impaired by the
printed circuit board, the relevant connection traces should
provide an appropriate characteristic impedance to the ground
plane. This can be achieved through proper layout.

When laying out an RF trace with a controlled impedance,
consider the following:

• Space the ground plane to either side of the signal trace at

least three line-widths away to ensure that a microstrip
(vertical dielectric) line is formed, rather than a coplanar
(lateral dielectric) waveguide.

• Ensure that the width of the microstrip line is constant and

that there are as few discontinuities as possible, such as
component pads, along the length of the line. Width
variations cause impedance discontinuities in the line and
may result in unwanted reflections.

• Do not use silkscreen over the signal line because it alters

the line impedance.

Keep the length of the input and output connection lines as
short as possible.

Figure 46 shows the cross section of a PC board, and Tab l e 5
show the dimensions that provide a 100 Ω line impedance for
FR-4 board material with εr = 4.6.

Table 5.

100 Ω 50 Ω

W 22 mils 13 mils

H 53 mils 8 mils

T 2 mils 2 mils

W3W

H

E

R

Figure 46. Cross-Sectional View of a PC Board

It possible to approximate a 100 Ω trace on a board designed
with the 50 Ω dimensions above by removing the ground plane
within 3 line-widths of the area directly below the trace.

3W

T

3692-044

Rev. A | Page 16 of 28

AD8370

The AD8370 contains both digital and analog sections. Care
should be taken to ensure that the digital and analog sections
are adequately isolated on the PC board. The use of separate
ground planes for each section connected at only one point via
a ferrite bead inductor ensures that the digital pulses do not
adversely affect the analog section of the AD8370.

−j1.6 Ω on each input node at 100 MHz. This attenuates the
applied input voltage by 0.003 dB. If 10 pF capacitors had been
selected, the voltage delivered to the input would be reduced by

2.1 dB when operating with a 200 Ω source impedance.

0.5

Due to the nature of the AD8370’s circuit design, care must be
taken to minimize parasitic capacitance on the input and output.
The AD8370 could become unstable with more than a few pF of
shunt capacitance on each input. Using resistors in series with
input pins is recommended under conditions of high source
capacitance.

High transient and noise levels on the power supply, ground,
and digital inputs can, under some circumstances, reprogram the
AD8370 to an unintended gain code. This further reinforces the
need for proper supply bypassing and decoupling. The user
should also be aware that probing the AD8370 and associated
circuitry during circuit debug may also induce the same effect.

PACKAGE CONSIDERATIONS

The package of the AD8370 is a compact, thermally enhanced
TSSOP 16-lead design. A large exposed paddle on the bottom of
the device provides both a thermal benefit and a low inductance
path to ground for the circuit. To make proper use of this pack­aging feature, the PCB needs to make contact directly under the
device, connected to an ac/dc common ground reference with
as many vias as possible to lower the inductance and thermal
impedance.

SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION

SERIAL CONTROL
INTERFACE

C

AC

C

AC

HIGH GAIN MODE

0

–0.5

DIFFERENTIAL BALANCE (dB)

–1.0

0 100 200 300 400 500

(GAIN CODE HG255)

LOW GAIN MODE
(GAIN CODE LG127)

FREQUENCY (MHz)

03692-046

Figure 48. Differential Output Balance for a Single-Ended Input Drive at

Maximum Gain (R

= 1 kΩ, CAC = 10 nF)

L

Figure 48 illustrates the differential balance at the output for a
single-ended input drive for multiple gain codes. The differential
balance is better than 0.5 dB for signal frequencies less than
250 MHz.

Figure 49 depicts the differential balance over the
entire gain range at 10 MHz. The balance is degraded for lower
gain settings because the finite common gain allows some of the
input signal applied to INHI to pass directly through to the
OPLO pin. At higher gain settings, the differential gain dominates
and balance is restored.

0.6
LOW GAIN MODE

0.5

HIGH GAIN MODE

R

SINGLE­ENDED
SOURCE

S

INLO

ICOM

DATA

AD8370

INHI

ICOM

VCCI

C

AC

0.1μF

4

1nF

CLCK

PWUP

11 10 915 1416 13 12

LTCH

VOCM

VCCO

VCCO

67823 51

OCOM

OCOM

0.1μF

OPLO

OPHI

+V

R

L

C

AC

S

Figure 47. Single-Ended-to-Differential Conversion

The AD8370 is primarily designed for differential signal inter­facing. The device can be used for single-ended-to-differential
conversion simply by terminating the unused input to ground
using a capacitor as depicted in

Figure 47. The ac coupling
capacitors should be selected such that their reactance is
negligible at the frequency of operation. For example, using
1 nF capacitors for C

presents a capacitive reactance of

AC

Rev. A | Page 17 of 28

03692-045

0.4

0.3

0.2

DIFFERENTIAL BALANCE (dB)

0.1

0

09632 640 326496128

GAIN CODE

03692-047

Figure 49. Differential Output Balance at 10 MHz for a Single-Ended Drive vs.

Gain Code (R

= 1 kΩ, CAC = 10 nF)

L

Even though the amplifier is no longer being driven in a balanced
manner, the distortion performance remains adequate for most
applications.
performance of the circuit in

Figure 50 illustrates the harmonic distortion

Figure 47 over the entire gain range.

AD8370

If the amplifier is driven in single-ended mode, the input
impedance varies depending on the value of the resistor used to
terminate the other input as

Rin

where R

= Rin

SE

TERM

+ R

DIFF

TERM

is the termination resistor connected to the other

input.

–40

–50

–60

–70

–80

HARMONIC DISTORTION (dBc)

–90

–100

HD2

HD3

LOW GAIN MODE

09632 640 326496128

GAIN CODE

Figure 50. Harmonic Distortion of the Circuit in

HD2

HD3

HIGH GAIN MODE

03692-048

Figure 47

DC-COUPLED OPERATION

DATA

VCCI

0.1μF

CLCK

PWUP

4

–2.5V

11 10 915 1416 13 12

LTCH

VOCM

67823 51

VCCO

VCCO

OCOM

OCOM

1nF

1nF

OPLO

OPHI

+2.5V

0V

R

L

0V

SERIAL CONTROL
INTERFACE

R

T

R

S

SINGLE-

ENDED

GROUND

REFERENCED

SOURCE

–2.5V

INLO

AD8370

INHI

0.1μF

ICOM

ICOM

Figure 51. DC Coupling the AD8370. Dual supplies are used to set the input

and output common-mode levels to 0 V.

03692-049

R

S

SINGLE-ENDED GROUND
REFERENCED SOURCE

Figure 52. DC Coupling the AD8370. The AD8138 is used as a unity-gain level

shifting amplifier to lift the common-mode level of the source to midsupply.

The AD8370 is also a dc accurate VGA. The common-mode dc
voltage present at the output pins is internally set to midsupply
using what is essentially a buffered resistive divider network
connected between the positive supply rail and the common
(ground) pins. The input pins are at a slightly higher dc
potential, typically 250 mV to 550 mV above the output pins,
depending on gain setting. In a typical single-supply
application, it is necessary to raise the common-mode reference
level of the source and load to roughly midsupply to maintain
symmetric swing and to avoid sinking or sourcing strong bias
currents from the input and output pins. It is possible to use
balanced dual supplies to allow ground referenced source and
load, as shown in
unused input to ground, the input and output common-mode
potentials are forced to virtual ground. This allows direct
coupling of ground referenced source and loads. The initial
differential input offset is typically only a few 100 μV. Over
temperature, the input offset could be as high as a few tens of
mVs. If precise dc accuracy is needed over temperature and time,
it may be necessary to periodically measure the input offset and
to apply the necessary opposing offset to the unused differential
input, canceling the resulting output offset.

To address situations where dual supplies are not convenient, a
second option is presented in
amplifier is used to translate the common-mode level of the
driving source to midsupply, which allows dc accurate
performance with a ground-referenced source without the need
for dual supplies. The bandwidth of the solution in
limited by the gain-bandwidth product of the AD8138. The
normalized frequency response of both implementations is shown
in

Figure 53.

SERIAL CONTROL
INTERFACE

499Ω

R

T

499Ω

R

T

2

499Ω

+5V

100Ω

INLO

ICOM

DATA

CLCK

11 10 915 1416 13 12

LTCH

VCCO

OCOM

OPLO

AD8370AD8138

INHI

ICOM

VCCI

PWUP

VOCM

VCCO

OCOM

OPHI

67823 51

1nF1nF

+5V

499Ω

OCM

V

100Ω

4

0.1μF

Figure 51. By connecting the VOCM pin and

Figure 52. The AD8138 differential

Figure 52 is

V

OCM

R

L

V

OCM

03692-050

Rev. A | Page 18 of 28

AD8370

10

8

6

4

2

0

–2

–4

NORMALIZED RESPONSE (dB)

–6

–8

–10

1 10 100 1k 10k 100k 1M 10M 100M 1G

Figure 53. Normalized Frequency Response of the Two Solutions in

Figure 51 and Figure 52

AD8370 WITH
AD8138 SINGLE
+5V SUPPLY

FREQUENCY (Hz)

AD8370
USING DUAL
±2.5V SUPPLY

03692-051

ADC INTERFACING

Although the AD8370 is designed to provide a 100 Ω output
source impedance, the device is capable of driving a variety of
loads while maintaining reasonable gain and distortion
performance. A common application for the AD8370 is ADC
driving in IF sampling receivers and broadband wide dynamic
range digitizers. The wide gain adjustment range allows the use
of lower resolution ADCs.
interface network.

R

OPCACZS

AD8370

V

OCM

R

OP

Figure 54. Generic ADC Interface

Many factors need to be considered before defining component
values used in the interface network, such as the desired
frequency range of operation, the input swing, and input
impedance of the ADC. AC coupling capacitors, C
used to block any potential dc offsets present at the AD8370
outputs, which would otherwise consume the available low-end
range of the ADC. The C
so that they present negligible reactance over the intended
frequency range of operation. The VOCM pin may serve as an
external reference for ADCs that do not include an on-board
reference. In either case, it is suggested that the VOCM pin be
decoupled to ground through a moderately large bypassing
capacitor (1 nF to 10 nF) to help minimize wideband noise
pick-up.

Figure 54 illustrates a typical ADC

R

IP

V

V

R

IP

IN

Z

IN

, should be

AC

R

100Ω

C

Z

ACZS

capacitors should be large enough

AC

T

P

ADC

IN

03692-052

Often it is wise to include input and output parasitic suppression
resistors, R

and ROP. Parasitic suppressing resistors help to

IP

prevent resonant effects that occur as a result of internal bond­wire inductance, pad to substrate capacitance, and stray
capacitance of the printed circuit board trace artwork. If
omitted, undesirable settling characteristics may be observed.
Typically, only 10 Ω to 25 Ω of series resistance is all that is
needed to help dampen resonant effects. Considering that most
ADCs present a relatively high input impedance, very little
signal is lost across the R

and ROP series resistors.

IP

Depending on the input impedance presented by the input
system of the ADC, it may be desirable to terminate the ADC
input down to a lower impedance by using a terminating
resistor, R

. The high frequency response of the AD8370

T

exhibits greater peaking when driving very light loads. In
addition, the terminating resistor helps to better define the
input impedance at the ADC input. Any part-to-part variability
of ADC input impedance is reduced when shunting down the
ADC inputs by using a moderate tolerance terminating resistor
(typically a 1% value is acceptable).

After defining reasonable values for coupling capacitors,
suppressing resistors, and the terminating resistor, it is time to
design the intermediate filter network. The example in
Figure 54 suggests a second-order, low-pass filter network
comprised of series inductors and a shunt capacitor. The order
and type of filter network used depends on the desired high
frequency rejection required for the ADC interface, as well as
on pass-band ripple and group delay. In some situations, the
signal spectra may already be sufficiently band-limited such
that no additional filter network is necessary, in which case Z
would simply be a short and Z

would be an open. In other

P

S

situations, it may be necessary to have a rather high-order
antialiasing filter to help minimize unwanted high frequency
spectra from being aliased down into the first Nyquist zone of
the ADC.

To properly design the filter network, it is necessary to consider
the overall source and load impedance presented by the AD8370
and ADC input, including the additional resistive contribution
of suppression and terminating resistors. The filter design can
then be handled by using a single-ended equivalent circuit, as
shown in

Figure 55. A variety of references that address filter
synthesis are available. Most provide tables for various filter
types and orders, indicating the normalized inductor and
capacitor values for a 1 Hz cutoff frequency and 1 Ω load. After
scaling the normalized prototype element values by the actual
desired cut-off frequency and load impedance, it is simply a
matter of splitting series element reactances in half to realize the
final balanced filter network component values.

Rev. A | Page 19 of 28

AD8370

V

V

V

SOURCE LOAD

R

S

V

S

R

S

2

V

S

R

S

2

Z

S

SINGLE-ENDED

EQUIVALENT

Z

S

2

BALANCED

CONFIGURATION

Z

S

2

Z

P

Z

P

R

L

R

L

2

R

L

2

03692-053

Figure 55. Single-Ended-to-Differential Network Conversion

As an example, a second-order, Butterworth, low-pass filter
design is presented where the differential load impedance is
1200 Ω, and the padded source impedance of the AD8370 is
assumed to be 120 Ω. The normalized series inductor value for
the 10-to-1, load-to-source impedance ratio is 0.074 H, and the
normalized shunt capacitor is 14.814 F. For a 70 MHz cutoff
frequency, the single-ended equivalent circuit consists of a
200 nH series inductor followed by a 27 pF capacitor. To realize
the balanced equivalent, simply split the 200 nH inductor in
half to realize the network shown in

R

S

RS = = 0.1

R

L

S

RS = 120Ω

S

R

S

= 60Ω

2

S

R

S

= 60Ω

2

Figure 56. Second-Order, Butterworth, Low-Pass Filter Design Example

= 0.074H

L

N

NORMALIZED

SINGLE-ENDED

EQUIVALENT

200nH

DE-NORMALIZED

SINGLE-ENDED

EQUIVALENT

100nH

BALANCED

CONFIGURATION

100nH

Figure 56.

C

14.814F

N

27pF

27pF

R

= 1Ω

L

f

= 1Hz

C

R

= 1200Ω

L

f

= 70MHz

C

R

L

2

R

L

2

= 600Ω

= 600Ω

03692-054

A complete design example is shown in Figure 58. The AD8370
is configured for single-ended-to-differential conversion with
the input terminated down to present a single-ended 75 Ω input.
A sixth-order Chebyshev differential filter is used to interface
the output of the AD8370 to the input of the AD9430
170 MSPS, 12-bit ADC. The filter minimizes aliasing effects
and improves harmonic distortion performance.

The input of the AD9430 is terminated with a 1.5 kΩ resistor so
that the overall load presented to the filter network is ~1 kΩ.
The variable gain of the AD8370 extends the useable dynamic
range of the ADC. The measured intermodulation distortion of
the combination is presented in

0
–10
–20
–30
–40
–50
–60
–70

dBFS

–80
–90

–100
–110
–120
–130

0 10203040506070

FREQUENCY (MHz)

Figure 57. FFT Plot of Two-Tone Intermodulation Distortion at

42 MHz for the Circuit in

Figure 57 at 42 MHz.

03692-055

Figure 58

In Figure 57, the intermodulation products are comparable to
the noise floor of the ADC. The spurious-free dynamic range of
the combination is better than 66 dB for a 70 MHz measurement
bandwidth.

3 V OPERATION

It is possible to operate the AD8370 at voltages as low as 3 V
with only minor performance degradation.
specifications for operation at 3 V.

Table 6.

Parameter Typical (70 MHz, RL = 100 Ω)

Output IP3 +23.5 dBm
P1dB +12.7 dBm

−3 dB Bandwidth 650 MHz (HG 127)
IMD3 −82 dBc (RL = 1 kΩ)

Tabl e 6 gives typical

Rev. A | Page 20 of 28

AD8370

FROM 75Ω
Tx-LINE

R

120Ω

S

SERIAL CONTROL INTERFACE

C

AC

100nF

INLO

ICOM

DATA

AD8370

INHI

ICOM

VCCI

C

AC

100nF

0.1μF

+V

S

4

1nF

C

CLCK

PWUP

LTCH

VOCM

0.1μF

11 10 915 1416 13 12

67823 51

VCCO

VCCO

OCOM

OCOM

100nF

OPLO

OPHI

C

100nF

Figure 58. ADC Interface Example

AC

68nH 180nH 220nH

27pF

AC

68nH 180nH 220nH

39pF 27pF 1.5kΩ

25Ω

25Ω

VINA

AD9430

VINB

03692-056

Rev. A | Page 21 of 28

AD8370

–

EVALUATION BOARD AND SOFTWARE

The evaluation board allows quick testing of the AD8370 by
using standard 50 Ω test equipment. The schematic is shown in
Figure 59. Transformers T1 and T2 are used to transform 50 Ω
source and load impedances to the desired input and output
reference levels. The top and bottom layers are shown in
Figure 63 and Figure 64. The ground plane was removed under
the traces between T1 and Pins INHI and INLO to approximate
a 100 Ω characteristic impedance.

31012498761152 131

15 22 2416 21201918 231714 25

R7

1kΩ

INLO

ICOM

AD8370

INHI

ICOM

C5

1kΩR51kΩ

IN+

IN–

50Ω Tx LINE

50Ω Tx LINE

TC4-1W

C1

1nF

T1

R2
0Ω

1:4

R1
0Ω

C2

1nF

0.1μF

R6

DATA

VCCI

4

The evaluation board comes with the AD8370 control software
that allows serial gain control from most computers. The
evaluation board is connected via a cable to the parallel port of
the computer. Adjusting the appropriate slider bar in the control
software automatically updates the gain code of the AD8370 in
either a linear or linear-in-dB fashion.

D-SUB 25 PIN MALE

C3

1nF

R4
0Ω

C4

1nF

L2*

T2

2:1

JTX-2-10T

R3
0Ω

50Ω Tx LINE

50Ω Tx LINE

OUT+

OUT

CLCK

PWUP

C9 OPEN

11 10 915 1416 13 12

LTCH

VCCO

VOCM

VCCO

67823 51

OCOM

OCOM

C8

0.1μF

OPLO

OPHI

PWUP

VOCM

R8 49.9Ω

C10 OPEN

SW1

R9
OPEN

P2

23 514

C7

0.1μF

V

S

C6
1μF

GND

Figure 59. AD8370 Evaluation Board Schematic

L1*

+V

S

GND

*EMI SUPPRESSION FERRITE
HZ1206E601R-00

03692-057

Rev. A | Page 22 of 28

AD8370

3692-058

Figure 60. Evaluation Software

Table 7. AD8370 Evaluation Board Configuration Options

Component Function Default Condition

VS, GND, VOCM

SW1, R8,
C10, PWUP

P1, R5, R6,
R7, C9

J1, J2, J6, J7

C1, C2, C3, C4 AC Coupling Capacitors. Provide ac coupling of the input and output signals. C1, C2, C3, C4 = 1 nF (Size 0603)
T1, T2

R1, R2, R3, R4

C5, C6, C7,
C8 L1, L2

Power Interface Vector Pins. Apply supply voltage between VS and GND. The VOCM
pin allows external monitoring of the common-mode input and output bias levels.

Device Enable. Set to Position B to power up the device. When in Position A, the PWUP
pin is connected to the PWUP vector pin. The PWUP pin allows external power cycling
of the device. R8 and C10 are provided to allow for proper cable termination.

Serial Control Interfaces. The evaluation board can be controlled using most PCs.
Windows®-based control software is shipped with the evaluation kit. A 25-pin, D-sub
connector cable is required to connect the PC to the evaluation board. It may be
necessary to use a capacitor on the clock line, depending on the quality of the PC port
signals. A 1 nF capacitor for C9 is usually sufficient for reducing clock overshoot.

Input and Output Signal Connectors. These SMA connectors provide a convenient way
to interface the evaluation board with 50 Ω test equipment. Typically, the device is
evaluated using a single-ended source and load. The source should connect to
J1 (IN+), and the load should connect to J6 (OUT+).

Impedance Transformers. T1 provides a 50 Ω to 200 Ω impedance transformation.
T2 provides a 100 Ω to 50 Ω impedance transformation.

Single-Ended or Differential. R2 and R4 are used to ground the center tap of the
secondary windings on transformers T1 and T2. R1 and R3 should be used to ground
J2 and J7 when used in single-ended applications.

Power Supply Decoupling. Nominal supply decoupling consists of a ferrite bead
series inductor followed by a 1 μF capacitor to ground followed by a 0.1 μF capacitor
to ground positioned as close to the device as possible. C7 provides additional
decoupling of the input common-mode voltage. L1 provides high frequency
isolation between the input and output power supply. L2 provides high
frequency isolation between the analog and digital ground.

Not applicable

SW1 = installed
R8 = 49.9 Ω (Size 0805)
C10 = open (Size 0805)

P1 = installed
R5, R6, R7 = 1 kΩ (Size 0603)
C9 = open (Size 0603)

Not applicable

T1 = TC4 −1W (Mini-Circuits)
T2 = JTX−2−10T (Mini-Circuits)

R1, R2, R3, R4 = 0 Ω (Size 0603)

C6 = 1 μF (Size 0805)
C5, C7, C8 = 0.1 μF (Size 0603)
L1, L2 = HZ1206E601R-00
(Steward, Size 1206)

Rev. A | Page 23 of 28

AD8370

03692-059

Figure 61. Evaluation Board Top Silkscreen

Figure 63. Evaluation Board Top

03692-061

03692-060

Figure 62. Evaluation Board Bottom Silkscreen

Figure 64. Evaluation Board Bottom

03692-062

Rev. A | Page 24 of 28

AD8370

C

APPENDIX

CHARACTERIZATION EQUIPMENT

An Agilent N4441A Balanced-Measurement System was used to
obtain the gain, phase, group delay, reverse isolation, CMRR,
and s-parameter information contained in this data sheet. With
the exception of the s-parameter information, T-attenuator pads
were used to match the 50 Ω impedance of this instrument’s ports
to the AD8370. An Agilent 4795A Spectrum Analyzer was used
to obtain nonlinear measurements IMD, IP3, and P1dB through
matching baluns and/or attenuator networks. Various other
measurements were taken with setups shown in this section.

COMPOSITE WAVEFORM ASSUMPTION

The nonlinear two-tone measurements made for this data sheet,
that is, IMD and IP3, are based on the assumption of a fixed
value composite waveform at the output, generally 1 V p-p. The
frequencies of interest dictate the use of RF test equipment, and
because this equipment is generally not designed to work in
units of volts, but rather watts and dBm, an assumption was
made to facilitate equipment setup and operation. Two sinusoidal
tones can be represented as

DEFINITIONS OF SELECTED PARAMETERS

Common-mode rejection ratio (Figure 28) has been defined for
this characterization effort as

GainModealDifferenti

GainModeCommon

where the numerator is the gain into a differential load at the
output due to a differential source at the input, and the
denominator is the gain into a differential-mode load at the
output due to a common-mode source at the input. In terms of
mixed-mode s-parameters, this equates to

21

SDD

21

SD

More information on mixed-mode s-parameters can be
obtained in a reference by Bockelman, D.E. and Eisenstadt,
W. R . , Combined Differential and Common-Mode Scattering
Parameters: Theory and Simulation. IEEE Transactions on
Microwave Theory and Techniques, v 43, n 7, 1530 (July 1995).

= V sin (2∏f1t)

V

1

= V sin (2∏f2t)

V

2

The RMS average voltage of one tone is

2

T

T

0

()

1

11

=∫dtV

2

where T is the period of the waveform. The RMS average
voltage of the two-tone composite signal is

T

1

()

T

0

2

1

=+∫dtVV

1

2

It can be shown that the average power of this composite
waveform is twice (3 dB) that of the single tone. This also
means that the composite peak-to-peak voltage is twice (6 dB)
that of a single tone. This principle can be used to set correct
input amplitudes from generators scaled in dBm and is correct
if the two tones are of equal amplitude and are reasonably close
in frequency.

Reverse isolation (

Figure 26) is defined as SDD12.

Power supply rejection ratio (PSRR) is defined as

A

dm

A

s

where A
A

is the gain from the power supply pins (VCCI and VCCO,

s

is the differential mode forward gain (SDD21), and

dm

taken together) to the output (OPLO and OPHI, taken
differentially), corrected for impedance mismatch. The
following reference provides more information: Gray, P.R.,
Hurst, P.J., Lewis, S.H. and Meyer, R.G., Analysis and Design of

Analog Integrated Circuits, 4

th

Edition, John Wiley & Sons, Inc.,

page 422.

Rev. A | Page 25 of 28

AD8370

MINI-

CIRCUITS

TC4-1W

–22.5dB

SERIAL DATA

SOURCE

V

5.0V

S

1nF

T1 T2

0Ω

INLO

ICOM

DATA

CLCK

11 10 915 1416 13 12

LTCH

VCCO

OCOM

1nF

OPLO

AD8370

INHI

ICOM

VCCI

PWUP

VOCM

VCCO

OCOM

OPHI

67823 51

4

1nF

1nF

Figure 65. PSRR A

HP8133A

3GHz PULSE

GENERATOR

TRIG

1nF1nF

Test Setup

dm

1nF

V

1μF1μF

INPUTAUX IN

5.0VVS 5.0V

S

50Ω

MINI­CIRCUITS
TC2-1T

50Ω

INPUT

3dB

ATTEN

PORT 1

PORT 2

AGILENT 8753D

NETWORK ANALYZER

3692-063

1nF

200Ω

1nF

TEKTRONIX TDS5104
DPO OSCILLOSCOPE

SERIAL DATA

INLO

ICOM

AD8370

INHI

ICOM

SOURCE

11 10 915 1416 13 12

LTCH

CLCK

DATA

VCCI

4

1nF

PWUP

VOCM

VCCO

VCCO

67823 51

Figure 66. PSRR A

OCOM

OCOM

50Ω

INPUT

1nF

OPLO

OPHI

1nF

Test Setup

s

50Ω

INPUT

MINI­CIRCUITS
TC2-1T

PORT 1
BIAS TEE

CONNECTION
TO PORT 1

PORT 2

AGILENT 8753D

NETWORK ANALYZER

03692-064

OUT

OUT

6dB

SPLITTER

3dB

ATTEN

3dB

ATTEN

6dB

SPLITTER

3dB

ATTEN

200Ω

5.0V

V

S

AD8370

1μF

SERIAL DATA

INLO

ICOM

INHI

ICOM

1nF

SOURCE

CLCK

DATA

VCCI

PWUP

4

V

5.0V

S

11 10 915 1416 13 12

LTCH

VOCM

67823 51

VCCO

VCCO

1nF1nF

OCOM

OCOM

OPLO

OPHI

1μF

475Ω

52.3Ω

475Ω

52.3Ω

2dB

ATTEN

2dB

ATTEN

5.0V

V

S

03692-065

Figure 67. DC Pulse Response and Overdrive Recovery Test Setup

Rev. A | Page 26 of 28

AD8370

MINI-

CIRCUITS

TC4-1W

AGILENT 8648D

SIGNAL

GENERATOR

RF OUT

1nF

T1 T2

0Ω

1nF

1μF

SERIAL DATA

INLO

ICOM

AD8370

INHI

ICOM

1nF

SOURCE

CLCK

DATA

VCCI

PWUP

4

V

S

11 10 915 1416 13 12

LTCH

VOCM

5.0V

VCCO

VCCO

67823 51

1nF1nF

OCOM

OCOM

1nF

OPLO

OPHI

1nF

1μF

475Ω

475Ω

V

105Ω

5.0VVS 5.0V

S

TEKTRONIX

P6205 ACTIVE

FET PROBE

MINI­CIRCUITS
JTX-2-10T

TEKTRONIX

TDS5104 DPO

OSCILLOSCOPE

50Ω INPUT

50Ω INPUT

03692-066

Figure 68. Gain Step Time Domain Response Test Setup

AGILENT 8648D

SIGNAL

GENERATOR

10MHz REF OUT

RF OUT

MINI-

CIRCUITS

TC4-1W

SERIAL DATA

SOURCE

V

5.0V

S

1nF

T1 T2

0Ω

INLO

ICOM

DATA

CLCK

11 10 915 1416 13 12

LTCH

VCCO

OCOM

AD8370

1nF

OPLO

475Ω

105Ω

MINI­CIRCUITS
JTX-2-10T

TEKTRONIX

TDS5104 DPO

OSCILLOSCOPE

50Ω INPUT

INHI

ICOM

VCCI

PWUP

VOCM

VCCO

OCOM

OPHI

67823 51

4

1μF

1nF

475Ω

V

S

5.0VVS 5.0V

TEKTRONIX

P6205 ACTIVE

FET PROBE

50Ω INPUT

03692-067

AGILENT 33250A

FUNCTION/ARBITRARY

OUTPUT10MHz IN

WAVEFORM

GENERATOR

1nF

1μF

1nF

52.3Ω

1nF

1nF

Figure 69. PWUP Response Time Domain Test Setup

Rev. A | Page 27 of 28

AD8370

OUTLINE DIMENSIONS

5.10

5.00

4.90

BOTTOM

VIEW

0.15

0.00

16

TOP

VIEW

1.20 MAX

SEATING
PLANE

0.65

BSC

COMPLIANT TO JEDEC STANDARDS MO-153-ABT

9

81

0.30

0.19

4.50

4.40

4.30

1.05

1.00

0.80

6.40

BSC

0.20

0.09

8°
0°

EXPOSED

PAD

(Pins Up)

0.75

0.60

0.45

3.00
SQ

Figure 70. 16-Lead Thin Shrink Small Outline Package with Exposed Pad [TSSOP_EP]

(RE-16-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8370ARE
AD8370ARE-REEL7
AD8370AREZ

1

AD8370AREZ-RL7

1

–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C

AD8370-EVAL Evaluation Board

1

Z = Pb-free part.

16-lead TSSOP, Tube RE-16-2
16-lead TSSOP, 7” Reel RE-16-2
16-lead TSSOP, Tube RE-16-2
16-lead TSSOP, 7” Reel RE-16-2

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03692–0–7/05(A)

T

Rev. A | Page 28 of 28

TTT