ANALOG DEVICES AD8366 Service Manual

DC to 600 MHz,

K

FEATURES

Matched pair of differential, digitally controlled VGAs Gain range: 4.5 dB to 20.25 dB

0.25 dB gain step size Operating frequency

DC to 150 MHz (2 V p-p) 3 dB bandwidth: 600 MHz

Noise figure (NF)

11.4 dB at 10 MHz at maximum gain

18 dB at 10 MHz at minimum gain OIP3: 45 dBm at 10 MHz HD2/HD3

Better than −90 dBc for 2 V p-p output at 10 MHz at

maximum gain Differential input and output Adjustable output common-mode Optional dc output offset correction Serial/parallel mode gain control Power-down feature Single 5 V supply operation

Dual-Digital Variable Gain Amplifiers

AD8366

FUNCTIONAL BLOCK DIAGRAM

VCMA

VPSOA

OPPA

OPMA

OPPB

SENB

BIT0/CS

BIT1/SDAT

BIT2/SCL

BIT3

OCOM

BIT4

BIT 5

DENA

DENB

OPMB

07584-001

DECA

OFSA

CCMA

VPSIA

IPPA

IPMA

ENBL

ICOM

IPMB

IPPB

VPSIB

DECB

DIGITAL GAIN

CONTROL L OGIC

OFSB

CCMB

VCMB

VPSOB

Figure 1.

APPLICATIONS

Baseband I/Q receivers Diversity receivers Wideband ADC drivers

GENERAL DESCRIPTION

The AD8366 is a matched pair of fully differential, low noise and low distortion, digitally programmable variable gain amplifiers (VGAs). The gain of each amplifier can be programmed separately or simultaneously over a range of 4.5 dB to 20.25 dB in steps of

0.25 dB. The amplifier offers flat frequency performance from dc to 70 MHz, independent of gain code.

The AD8366 offers excellent spurious-free dynamic range, suitable for driving high resolution analog-to-digital converters (ADCs). The NF at maximum gain is 11.4 dB at 10 MHz and increases ~2 dB for every 4 dB decrease in gain. Over the entire gain range, the HD3/HD2 are better than −90 dBc for 2 V p-p at the output at 10 MHz into 200 Ω. The two-tone intermodulation distortion of

−90 dBc into 200 Ω translates to an OIP3 of 45 dBm (38 dBVrms). The differential input impedance of 200  provides a well-defined termination. The differential output has a low impedance of ~25 .

The output common-mode voltage defaults to V

/2 but can

POS

be programmed via the VCMA and VCMB pins over a range of voltages. The input common-mode voltage also defaults to V

/2 but can be driven down to 1.5 V. A built-in, dc offset

POS

compensation loop can be used to eliminate dc offsets from prior stages in the signal chain. This loop can also be disabled if dccoupled operation is desired.

The digital interface allows for parallel or serial mode gain programming. The AD8366 operates from a 4.75 V to 5.25 V supply and consumes typically 180 mA. When disabled, the part consumes roughly 3 mA. The AD8366 is fabricated using Analog Devices, Inc., advanced silicon-germanium bipolar process, and it is available in a 32-lead exposed paddle LFCSP package. Performance is specified over the −40°C to +85°C temperature range.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD8366

REVISION HISTORY

3/11—Rev. 0 to Rev. A

Changes to Table 2, Internal Power Dissipation Value................ 6

10/10—Revision 0: Initial Version

Rev. A | Page 2 of 28

AD8366

SPECIFICATIONS

VS = 5 V, TA = 25°C, ZS = 200 Ω, ZL = 200 Ω, f = 10 MHz, unless otherwise noted.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE

Bandwidth 3 dB; all gain codes 600 MHz 1 dB; all gain codes 200 MHz

Slew Rate Maximum gain 1100 V/μs Minimum gain 1500 V/μs INPUT STAGE IPPA, IPMA, IPPB, IPMB

Linear Input Swing At minimum gain AV = 4.5 dB, 1 dB gain compression 3.6 V p-p

Differential Input Impedance 217 Ω

Minimum Input Common-Mode Voltage 1.5 V

Maximum Input Common-Mode Voltage V Input pins left floating V GAIN

Minimum Voltage Gain 4.5 dB

Maximum Voltage Gain 20.25 dB

Gain Step Size All gain codes 0.25 dB

Gain Step Accuracy All gain codes ±0.25 dB

Gain Flatness Maximum gain, DC to 70 MHz 0.1 dB

Gain Mismatch Channel A/Channel B at minimum/maximum gain code 0.1 dB

Group Delay Flatness All gain codes, 20% fractional bandwidth, fC < 100 MHz <0.5 ns

Mismatch Channel A and Channel B at same gain code 2 ps Gain Step Response Maximum gain to minimum gain 30 ns Minimum gain to maximum gain 60 ns Common-Mode Rejection Ratio −66.2 dB

OUTPUT STAGE OPPA, OPMA, OPPB, OPMB, VCMA, VCMB

Linear Output Swing 1 dB gain compression 6 V p-p Differential Output Impedance 28 Ω Output DC Offset Inputs shorted, offset loop disabled at

minimum/maximum gain Inputs shorted, offset loop enabled (across all gain codes) 10 mV Minimum Output Common-Mode Voltage HD3, HD2 > −90 dBc, 2 V p-p output 1.6 V Maximum Output Common-Mode Voltage HD3, HD2 > −90 dBc, 2 V p-p output 3 V VCMA and VCMB left floating V Common-Mode Setpoint Input Impedance 4 kΩ

NOISE/DISTORTION

3 MHz

Noise Figure Maximum gain 11.3 dB Minimum gain 18.2 dB Second Harmonic 2 V p-p output, maximum gain −82 dBc 2 V p-p output, minimum gain −82 dBc Third Harmonic 2 V p-p output, maximum gain −87 dBc 2 V p-p output, minimum gain −90 dBc OIP31 2 V p-p composite, maximum gain 34 dBVrms 2 V p-p composite, minimum gain 35 dBVrms OIP21 2 V p-p composite, maximum gain 76 dBVrms 2 V p-p composite, minimum gain 76 dBVrms Output 1 dB Compression Point1 Maximum gain 6.7 dBVrms

Minimum gain 6.9 dBVrms

−10/−30 mV

/2 + 0.075 V

POS

/2 V

POS

/2 V

POS

Rev. A | Page 3 of 28

AD8366

Parameter Test Conditions/Comments Min Typ Max Unit

10 MHz

Noise Figure Maximum gain 11.4 dB Minimum gain 18 dB Second Harmonic 2 V p-p output, maximum gain −97 dBc 2 V p-p output, minimum gain −96 dBc Third Harmonic 2 V p-p output, maximum gain −97 dBc 2 V p-p output, minimum gain −90 dBc OIP31 2 V p-p composite, maximum gain 38 dBVrms 2 V p-p composite, minimum gain 36 dBVrms OIP21 2 V p-p composite, maximum gain 72 dBVrms 2 V p-p composite, minimum gain 76 dBVrms

Output 1 dB Compression Point1 Maximum gain 7 dBVrms Minimum gain 6.7 dBVrms 50 MHz

Noise Figure Maximum gain 11.8 dB

Minimum gain 18.2 dB

Second Harmonic 2 V p-p output, maximum gain −82 dBc

2 V p-p output, minimum gain −84 dBc

Third Harmonic 2 V p-p output, maximum gain −80 dBc

2 V p-p output, minimum gain −71 dBc

OIP31 2 V p-p composite, maximum gain 32 dBVrms

2 V p-p composite, minimum gain 26 dBVrms

OIP21 2 V p-p composite, maximum gain 71 dBVrms

2 V p-p composite, minimum gain 78 dBVrms

Output 1 dB Compression Point1 Maximum gain 6.7 dBVrms

Minimum gain 6.7 dBVrms DIGITAL LOGIC SENB, DENA, DENB, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5

Input High Voltage, V Input Low Voltage, V Input Capacitance, CIN 1 pF Input Resistance, RIN 50 kΩ

SPI INTERFACE TIMING SENB = high

f

Serial clock frequency (maximum) 44.4 MHz

SCLK

t1 CS rising edge to first SCLK rising edge (minimum) 7.5 ns t2 SCLK high pulse width (minimum) 7.5 ns t3 SCLK low pulse width (minimum) 15 ns t4 SCLK falling edge to CS low (minimum) 7.5 ns t5 SDAT setup time (minimum) 7.5 ns t6 SDAT hold time (minimum) 15 ns

PARALLEL PORT TIMING SENB = low

t7 DENA/DENB high pulse width (minimum) 7.5 ns t8 DENA/DENB low pulse width (minimum) 15 ns t9 BITx setup time (minimum) 7.5 ns t10 BITx hold time (minimum) 7.5 ns

POWER AND ENABLE VPSIA, VPSIB, VPSOA, VPSOB, ICOM, OCOM, ENBL

Supply Voltage Range 4.75 5.25 V Total Supply Current ENBL = 5 V 180 mA Disable Current ENBL = 0 V 3.2 mA Disable Threshold 1.65 V Enable Response Time Delay following high-to-low transition until device

Disable Response Time Delay following low-to-high transition until device

1

To convert to dBm for a 200 Ω load impedance, add 7 dB to the dBVrms value.

2.2 V

INH

1.2 V

INL

150 ns

meets full specifications

3 μs

produces full attenuation

Rev. A | Page 4 of 28

AD8366

PARALLEL AND SERIAL INTERFACE TIMING

CS

SCLK

SDAT

SENB

t

2

t

1

t

5

6

B-LSB B-MSB A-LSBX

t

3

ALWAYS HIG H

A-MSB

t

4

X

07584-003

Figure 2. SPI Port Timing Diagram

BIT[5:0]

DENA

DENB

SENB

GAIN A GAIN B

t

10

9

t

7

t

8

ALWAYS LOW

Figure 3. Parallel Port Timing Diagram

GAIN A, GAIN B

07584-004

Rev. A | Page 5 of 28

AD8366

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltages, VPSIx and VPSOx 5.5 V ENBL, SENB, DENA, DENB, BIT0, BIT1, BIT2,

BIT3, BIT4, BIT5

IPPA, IPMA, IPPB, IPMB 5.5 V OPPA, OPMA, OPPB, OPMB 5.5 V OFSA, OFSB 5.5 V DECA, DECB, VCMA, VCMB, CCMA, CCMB 5.5 V Internal Power Dissipation 1.4 W θJA (With Pad Soldered to Board) 45.4°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C

5.5 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 6 of 28

AD8366

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DECA

OFSA

CCMA

VCMA

VPSOAOPPA

OPMA

SENB

29

28

27

26

31

30

32

1

VPSIA

IPPA

IPMA ENBL ICOM

IPMB

IPPB

VPSIB

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.

2 3 4 5 6 7 8

PIN 1 INDICATOR

AD8366

TOP VIEW

(Not to Scale)

9

11

10

OFSB

DECB

CCMB

Figure 4. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1, 8, 13, 28

VPSIA, VPSIB, VPSOB,

Input and Output Stage Positive Supply Voltage (4.75 V to 5.25 V).

VPSOA

2, 3, 6, 7

IPPA, IPMA, IPMB,

Differential Inputs.

IPPB 4 ENBL Chip Enable. Pull this pin high to enable. 5, 20 ICOM, OCOM

Input and Output Ground Pins. Connect these pins via the lowest possible impedance to ground.

9, 32 DECB, DECA

/2 Reference Decoupling Node. Connect a decoupling capacitor from these nodes to

V

POS

ground.

10, 31 OFSB, OFSA

Output Offset Correction Loop Compensation. Connect a capacitor from these nodes to

ground to enable the correction loop. Tie this pin to ground to disable. 11, 30 CCMB, CCMA Connect These Nodes to Ground. 12, 29 VCMB, VCMA

Output Common-Mode Setpoint. These pins default to V

from a low impedance source to change the output common-mode voltage. 14, 15, 26, 27

OPPB, OPMB, OPMA,

Differential Outputs.

OPPA

16, 17 DENB, DENA

Data Enable. Pull these pins high to address each or both channels for parallel gain

programming. These pins are not used in serial mode. 18, 19, 21, 22, 23, 24

25 SENB

BIT5, BIT4, BIT3, BIT2/SCLK, BIT1/SDAT, BIT0/CS

Parallel Data Path (When SENB Is Low). When SENB is high, BIT0 becomes a chip select (CS),

BIT1 becomes a serial data input (SDAT ), and BIT2 becomes a serial clock (SCLK). BIT3 to BIT5

are not used in serial mode.

Serial Interface Enable. Pull this pin high for serial gain programming mode and pull this pin low

for parallel gain programming mode. EPAD The exposed pad must be connected to ground.

25

BIT0/CS

24

BIT1/SDAT

23

BIT2/SCLK

22

BIT3

21

OCOM

20

BIT4

19

BIT5

18

DENA

17

12

13

14

15

16

OPPB

DENB

VCMB

OPMB

VPSOB

07584-028

/2 if left open. Drive these pins

POS

Rev. A | Page 7 of 28

AD8366

A

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V, TA = 25°C, ZS = 200 Ω, ZL = 200 Ω, f = 10 MHz, unless otherwise noted.

22

20

18

16

14

12

GAIN (dB)

10

8

6

4

0 5 10 15 20 25 30 35 40 45 50 55 60

TA = +85°C

= +25°C

T

A

= –40°C

T

A

GAIN CODE

Figure 5. Gain vs. Gain Code at 500 kHz, 3 MHz, 10 MHz, and 50 MHz

25

20

15

10

5

0

5

GAIN CHANNEL A, GAIN CHANNEL B (dB)

–10

100k 1M 10M 100M 1G

GAIN CODE 63

GAIN CODE 48

GAIN CODE 32

GAIN CODE 16

GAIN CODE 00

FREQUENCY ( Hz)

Figure 6. Frequency Response vs. Gain Code

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

TCH (dB)

0.2

0.1 0

–0.1 –0.2 –0.3 –0.4 –0.5

AMPLITUDE MISM

–0.6 –0.7 –0.8 –0.9 –1.0

0 102030405060

GAIN CODE

Figure 7. Channel A-to-Channel B Amplitude Mismatch vs. Gain Code,

2 V p-p Output

07584-005

07584-007

07584-008

0.5

TA = +85°C

= +25°C

T

A

0.4

0.3

0.2

0.1

–0.1

GAIN ERROR (dB)

–0.2

–0.3

–0.4

–0.5

= –40°C

T

A

0

0 5 10 15 20 25 30 35 40 45 50 55 60

FREQUENCY = 3MHz FREQUENCY = 50MHz

GAIN CODE

Figure 8. Gain Error vs. Gain Code, Error Normalized to 10 MHz

21.0

20.8

20.6

20.4

20.2

20.0

GAIN (dB)

19.8

19.6

19.4

19.2

19.0

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80

TEMPERATURE (°C)

Figure 9. Gain vs. Temperature at Maximum Gain at 10 MHz

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

TCH (Degrees)

0 –0.1 –0.2 –0.3 –0.4 –0.5

PHASE MISM

–0.6 –0.7 –0.8 –0.9 –1.0

0 102030405060

GAIN CODE

Figure 10. Channel A-to-Channel B Phase Mismatch vs. Gain Code,

2 V p-p Output

07584-006

07584-017

07584-009

Rev. A | Page 8 of 28

AD8366

20

TA = +85°C T

= +25°C

A

18

T

= –40°C

A

16

14

12

10

8

OP1dB (dBm)

6

4

2

0

0 5 10 15 20 25 30 35 40 45 50 55 60

GAIN CODE

20

18

16

14

12

10

8

6

4

2

0

Figure 11. OP1dB vs. Gain Code at 500 kHz, 3 MHz, 10 MHz, and 50 MHz

50

45

40

35

30

25

OIP3 (dBm)

20

15

10

TA = +85°C

5

T

= +25°C

A

T

= –40°C

A

0

0 5 10 15 20 25 30 35 40 45 50 55 60

FREQUENCY = 10MHz FREQUENCY = 50MHz

GAIN CODE

60

55

50

45

40

35

30

25

20

15

10

Figure 12. OIP3 vs. Gain Code at 10 MHz and 50 MHz Frequency, 2 V p-p

Composite Output

0

TA = +85°C

= +25°C

T

–10

A

= –40°C

T

A

–20

–30

–40

–50

–60

IMD3 (dBc)

–70

–80

–90

–100

–110

0 5 10 15 20 25 30 35 40 45 50 55 60

GAIN CODE

FREQUENCY = 10MHz FREQUENCY = 50MHz

Figure 13. Two-Tone Output IMD3 vs. Gain Code at 10 MHz and 50 MHz

Frequency, 2 V p-p Composite Output

20

TA = +85°C T

= +25°C

A

18

T

= –40°C

A

16

14

12

10

8

OP1dB ( dBVrms)

07584-030

OP1dB (dBm)

6

4

2

0

0 102030405060708090100110120130140150

FREQUENCY ( MHz)

GAIN CODE 0 GAIN CODE 63

Figure 14. OP1dB vs. Frequency at Gain Code 0 and Gain Code 63

50

45

40

35

30

25

OIP3 (dBm)

OIP3 (dBVrms)

07584-039

20

15

10

TA = +85°C

5

T

= +25°C

A

T

= –40°C

A

0

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

FREQUENCY (M Hz)

GAIN CODE 63

GAIN CO DE 0

GAIN CO DE 32

CHANNEL A CHANNEL B

Figure 15. OIP3 vs. Frequency, Gain Code 0, Gain Code 32, and Gain Code 63,

2 V p-p Composite Output

TA = +85°C T

= +25°C

A

–10

T

= –40°C

A

–30

–50

IMD3 (dBc)

–70

–90

–110

10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

07584-042

Figure 16. Two-Tone Output IMD3 vs. Frequency at Gain Code 0,

GAIN CODE 0

GAIN CODE 63

FREQUENC Y (MHz)

CHANNEL A CHANNEL B

GAIN CODE 32

Gain Code 32, and Gain Code 63, 2 V p-p Composite Output

20

18

16

14

12

10

8

OP1dB (d BVrms)

6

4

2

0

07584-041

07584-040

07584-029

Rev. A | Page 9 of 28

ANALOG DEVICES AD8366 Service Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

PARALLEL AND SERIAL INTERFACE TIMING

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS