Analog Devices AD8362 b Datasheet

50 Hz to 2.7 GHz

V

VTGT

FEATURES

Complete fully calibrated measurement/control system
Accurate rms-to-dc conversion from 50 Hz to 2.7 GHz
Input dynamic range of >60 dB: −52 dBm to +8 dBm in 50 Ω
Waveform and modulation independent:

(Such as GSM/CDMA/TDMA)
Linear-in-decibels output, scaled 50 mV/dB
Law conformance error of 0.5 dB
All functions temperature and supply stable
Operates from 4.5 V to 5.5 V at 24 mA from −40°C to +85°C
Power-down capability to 1.3 mW

APPLICATIONS

Power amplifier linearization/control loops
Transmitter power control
Transmitter signal strength indication (TSSI)
RF instrumentation

GENERAL DESCRIPTION

The AD8362 is a true rms-responding power detector that has a
60 dB measurement range. It is intended for use in a variety of
high frequency communication systems and in instrumentation
requiring an accurate response to signal power. It is easy to use,
requiring only a single supply of 5 V and a few capacitors. It can
operate from arbitrarily low frequencies to over 2.7 GHz and
can accept inputs that have rms values from 1 mV to at least
1 V rms, with peak crest factors of up to 6, exceeding the
requirements for accurate measurement of CDMA signals.

The input signal is applied to a resistive ladder attenuator
that comprises the input stage of a variable gain amplifier.
The 12 tap points are smoothly interpolated using a proprietary
technique to provide a continuously variable attenuator, which
is controlled by a voltage applied to the VSET pin. The resulting
signal is applied to a high performance broadband amplifier. Its
output is measured by an accurate square-law detector cell. The
fluctuating output is then filtered and compared with the output
of an identical squarer, whose input is a fixed dc voltage applied
to the VTGT pin, usually the accurate reference of 1.25 V
provided at the VREF pin.

The difference in the outputs of these squaring cells is
integrated in a high gain error amplifier, generating a voltage at
the VOUT pin with rail-to-rail capabilities. In a controller
mode, this low noise output can be used to vary the gain of a
host system’s RF amplifier, thus balancing the set point against

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

60 dB TruPwr™ Detector

AD8362

FUNCTIONAL BLOCK DIAGRAM

CHPF

DECL

INHI

INLO

AD8362

REF

the input power. Optionally, the voltage at VSET may be a
replica of the RF signal’s amplitude modulation, in which case
the overall effect is to remove the modulation component prior
to detection and low-pass filtering. The corner frequency of the
averaging filter may be lowered without limit by adding an
external capacitor at the CLPF pin. The AD8362 can be used to
determine the true power of a high frequency signal having a
complex low frequency modulation envelope (or simply as a
low frequency rms voltmeter). The high-pass corner generated
by its offset-nulling loop can be lowered by a capacitor added
on the CHPF pin.

Used as a power measurement device, VOUT is strapped to
VSET, and the output is then proportional to the logarithm of
the rms value of the input; that is, the reading is presented
directly in decibels and is conveniently scaled 1 V per decade,
that is, 50 mV/dB; other slopes are easily arranged. In controller
modes, the voltage applied to VSET determines the power level
required at the input to null the deviation from the setpoint.
The output buffer can provide high load currents.

The AD8362 is powered down by a logic high applied to the
PWDN pin, i.e., the consumption is reduced to about 1.3 mW. It
powers up within about 20 µs to its nominal operating current
of 20 mA at 25°C. The AD8362 is supplied in a 16-lead TSSOP
package for operation over the industrial temperature range of

−40°C to +85°C. An evaluation board is available.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

2

x

2

x

Figure 1.

BIAS

PWDNCOMM

CLPF

VOUT

ACOM

VSET

VPOS

02923-B-001

AD8362

TABLE OF CONTENTS

Specifications ...................................................................................3

Uncertainties in R

and Power Calibration............................ 24

IN

Absolute Maximum Ratings ..........................................................6

ESD Caution.................................................................................. 6

Pin Configuration and Function Description .............................7

Equivalent Circuits..........................................................................8

Typical Performance Characteristics............................................ 9

Characterization Setup .................................................................14

Equipment................................................................................... 14

Analysis........................................................................................ 14

Circuit Description........................................................................15

Square-Law Detection ...............................................................15

Effect of Input Coupling on the Intercept Value.................... 16

Offset Elimination...................................................................... 16

Voltage vs. Power Calibration ................................................... 17

Effect of Signal Waveform......................................................... 17

Operation at Low Frequencies.................................................. 17

Choosing the Right Value for CHPF and CLPF..................... 24

Use of Nonstandard Target Voltages........................................ 24

Adjusting the Intercept ..............................................................25

Altering the Slope....................................................................... 25

Envelope Elimination Mode..................................................... 26

Operator in Controller Modes ....................................................27

Use of an Input Balun................................................................ 27

General Applications ....................................................................29

RMS Voltmeter with >100 dB Dynamic Range...................... 29

RF Power Meter with 80 dB Range.......................................... 30

High Slope Detectors Centered on a Narrow Window......... 31

AD8362 Evaluation Board........................................................ 32

Outline Dimensions...................................................................... 34

Ordering Guide .......................................................................... 34

REVISION HISTORY

Time-Domain Response of the Closed Loop .........................17

Alteration of the Internal Target Voltage................................. 18

Effects at Each End of Dynamic Range................................... 18

Input Protection.......................................................................... 19

Power-Enable Response Time .................................................. 19

Using the AD8362......................................................................... 20

Basic Connections...................................................................... 20

Main Modes of Operation............................................................ 21

Operation in Measurement Modes.............................................22

Law Conformance Error............................................................ 22

Alternative Input Coupling Means ..........................................23

Using a Narrow-Band Input Match .........................................23

3/04—Data Sheet Changed from Rev. A to Rev. B.

Updated Format.................................................................Universal

Changes to Specifications............................................................... 3

Changes to the Offset Elimination Section................................16

Changes to the Operation at Low Frequencies Section............17

Changes to the Time-Domain Response of the Closed Loop

Section............................................................................................. 17

Changes to Equation 13................................................................ 24

Changes to Table 5......................................................................... 31

6/03—Data Sheet Changed from Rev. 0 to Rev. A.

Updated Ordering Guide................................................................ 5

Change to Analysis Section.......................................................... 12

Updated AD8362 Evaluation Board Section .............................26

2/03—Revision 0: Initial Version

Rev. B | Page 2 of 36

AD8362

SPECIFICATIONS

VS = 5 V, T = 25°C, ZO = 50 Ω, differential input drive via Balun1, VTGT connec ted to VREF, VOUT tied to VSET, unl ess other wise note d.

Table 1.

Parameter Conditions Min Typ Max Unit

OVERALL FUNCTION

Maximum Input Frequency 2.7 GHz
Input Power Range (Differential)

Nominal Low End of Range −52 dBm
Nominal High End of Range +8 dBm

Input Voltage Range (Differential)

Nominal Low End of Range 1.12 mV rms
Nominal High End of Range 1.12 V rms

Input Power Range (S-Sided)

Nominal Low End of Range −40 dBm
Nominal High End of Range 0 dBm

Input Voltage Range (S-Sided) RMS Voltage at Input Terminals, f ≤ 2.7 GHz

Nominal Low End of Range 2.23 mV rms
Nominal High End of Range 223 V rms

Output Voltage Range RL ≥ 200 Ω to Ground

Nominal Low End of Range +100 mV

Nominal High End of Range In General, VS – 0.1 V +4.9 V
Output Scaling (Log Slope) 50 mV/dB
Law Conformance Error Over Central 60 dB Range, f ≤ 2.7 GHz ±0.5 dB

RF INPUT INTERFACE Pins INHI, INLO, AC-Coupled

Input Resistance Single-Ended Drive, wrt DECL 100 Ω

Differential Drive 200 Ω
OUTPUT INTERFACE Pin VOUT

Available Output Range RL ≥ 200 Ω to Ground 0.1 4.9 V
Absolute Voltage Range

Nominal Low End of Range Measurement Mode, f = 900 MHz, PIN = −52 dBm 0.32 0.48 V

Nominal High End of Range Measurement Mode, f = 900 MHz, PIN = +8 dBm 3.44 3.52 V
Source/Sink Current VOUT Held at VS/2, to 1% Change 48 mA
Slew Rate Rising CL = Open 60 V/µs
Slew Rate Falling CL = Open 5 V/µs
Rise Time, 10% to 90% 0.2 V to 1.8 V, CLPF = 0 45 ns
Fall Time, 90% to 10% 1.8 V to 0.2 V, CLPF = 0 0.4 µs
Wideband Noise CLPF = 1000 pF, f

VSET INTERFACE Pin VSET

Nominal Input Voltage Range To ±1 dB Error 0.5 3.75 V
Input Resistance 68 kΩ
Scaling (Log Slope) f = 900 MHz 46 50 54 mV/dB
Scaling (Log Intercept) f = 900 MHz, into 1:4 Balun −64 −60 −56 dBm

−77 −73 −69 dBV
VOLTAGE REFERENCE Pin VREF

Output Voltage 25°C 1.225 1.25 1.275 V
Temperature Sensitivity3 −40°C ≤ TA ≤ +85°C 0.08 mV/°C
Output Resistance 8 Ω

dB Referred to 50 Ω Impedance Level,
f ≤ 2.7 GHz, into 1:4 Balun

RMS Voltage at Input Terminals,
f ≤ 2.7 GHz, into Input of the Device

Single-Ended Drive, CW Input, f ≤ 2.7 GHz,
into Input Resistive Network

SPOT

1

2

≤ 100 kHz 70 nV/√Hz

Rev. B | Page 3 of 36

AD8362

Parameter Conditions Min Typ Max Unit

RMS TARGET INTERFACE Pin VTGT

Nominal Input Voltage Range Measurement Range = 60 dB, to ±1 dB Error 0.625 2.5 V
Input Bias Current VTGT = 1.25 V −28 µA
VTGT = 0 V −52 µA
Incremental Input Resistance 52 kΩ

POWER-DOWN INTERFACE Pin PWDN

Logic Level to Enable Logic Low Enables
Logic Level to Disable Logic High Disables 3
Input Current Logic High

Logic Low

Enable Time

Disable Time

POWER SUPPLY INTERFACE Pin VPOS

Supply Voltage
Quiescent Current
Supply Current When Disabled 0.2 mA

900 MHz

Dynamic Range Error Referred to Best Fit Line (Linear Regression)

±1 dB Linearity, CW Input 65 dB
±0.5 dB Linearity, CW Input 62 dB

Deviation vs. Temperature Deviation from Output at 25°C

−40°C < TA < +85°C; PIN = −45 dBm −1.7 dB

−40°C < TA < +85°C; PIN = −20 dBm −1.4 dB

−40°C < TA < +85°C; PIN = +5 dBm −1 dB

Logarithmic Slope 46 50 54 mV/dB
Logarithmic Intercept −64 −60 −56 dBm
Deviation from CW Response 5.5 dB Peak-to-RMS Ratio (IS95 Reverse Link) 0.2 dB

12 dB Peak-to-RMS Ratio (WCDMA 4 Channels) 0.2 dB

18 dB Peak-to-RMS Ratio (WCDMA 15 Channels) 0.5 dB

1.9 GHz
Dynamic Range Error Referred to Best Fit Line (Linear Regression)

±1 dB Linearity, CW Input 65 dB
±0.5 dB Linearity, CW Input 62 dB

Deviation vs. Temperature Deviation from Output at 25°C

−40°C < TA < +85°C; PIN = −45 dBm −0.6 dB

−40°C < TA < +85°C; PIN = −20 dBm −0.5 dB

−40°C < TA < +85°C; PIN= +5 dBm −0.3 dB

Logarithmic Slope 51 mV/dB
Logarithmic Intercept −59 dBm
Deviation from CW Response 5.5 dB Peak-to-RMS Ratio (IS95 Reverse Link) 0.2 dB

12 dB Peak-to-RMS Ratio (WCDMA 4 Channels) 0.2 dB
18 dB Peak-to-RMS Ratio (WCDMA 15 Channels) 0.5 dB

From PWDN Low to VOUT within
10% of Final Value, CLPF = 1000 pF

From PWDN High to VOUT within
10% of Final Value, CLPF = 1000 pF

4.5 5 5.5 V

20 22 mA

230
5

14.5

2.5

1 V

V
µA
µA
ns

µs

Rev. B | Page 4 of 36

AD8362

Parameter Conditions Min Typ Max Unit

2.2 GHz
Dynamic Range Error Referred to Best Fit Line (Linear Regression)

±1 dB Linearity, CW Input 65 dB
±0.5 dB Linearity, CW Input 65 dB

Deviation vs. Temperature Deviation from Output at 25°C

−40°C < TA < +85°C; PIN = −45 dBm −1.8 dB

−40°C < TA < +85°C; PIN = −20 dBm −1.6 dB

−40°C < TA < +85°C; PIN= +5 dBm −1.3 dB

Logarithmic Slope 50.5 mV/dB
Logarithmic Intercept −61 dBm
Deviation from CW Response 5.5 dB Peak-to-RMS Ratio (IS95 Reverse Link) 0.2 dB

12 dB Peak-to-RMS Ratio (WCDMA 4 Channels) 0.2 dB
18 dB Peak-to-RMS Ratio (WCDMA 15 Channels) 0.5 dB

2.7 GHz
Dynamic Range Error Referred to Best Fit Line (Linear Regression)
±1 dB Linearity, CW Input 63 dB
±0.5 dB Linearity, CW Input 62 dB
Deviation vs. Temperature Deviation from Output at 25°C

−40°C < TA < +85°C; PIN = −40 dBm −5.3 dB

−40°C < TA < +85°C; PIN = −15 dBm −5.5 dB

−40°C < TA < +85°C; PIN = +15 dBm −4.8 dB
Logarithmic Slope 50.5 mV/dB
Logarithmic Intercept −58 dBm
Deviation from CW Response 5.5 dB Peak-to-RMS Ratio (IS95 Reverse Link) 0.2 dB

12 dB Peak-to-RMS Ratio (WCDMA 4 Channels) 0.2 dB
18 dB Peak-to-RMS Ratio (WCDMA 15 Channels) 0.4 dB

1

1:4 balun transformer, M/A-COM ETC 1.6-4-2-3.

2

Resistive network consists of 33 Ω shunt and 25 Ω series.

3

See Figure 36.

Rev. B | Page 5 of 36

AD8362

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameters Ratings

Supply Voltage VPOS 5.5 V
Input Power (into Input of Device) 13 dBm
Equivalent Voltage 2 V rms
Internal Power Dissipation 500 mW
θJA 125°C/W
Maximum Junction Temperature 125°C/W
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range (Soldering 60 sec) 300°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. B | Page 6 of 36

AD8362

PIN CONFIGURATION AND FUNCTION DESCRIPTION

COMM

CHPF
DECL

INHI

INLO

DECL

PWDN

COMM

1

2

3

AD8362

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

15

14

13

12

11

10

9

ACOM
VREF
VTGT
VPOS
VOUT
VSET
ACOM
CLPF

02923-B-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin
No.

Mnemonic Description

Equivalent
Circuit

1, 8 COMM Common Connection. Connect via low impedance to system common.
2 CHPF Input HPF. Connect to common via a capacitor to determine 3 dB point of input signal high-pass filter.
3, 6 DECL

Decoupling Terminals for INHI and INLO. Connect to common via a large capacitance to complete

input circuit.
4 INHI High Signal Input Terminal. Part of a differential input port with INLO. Circuit A
5 INLO Low Signal Input Terminal. Part of a differential input port with INHI. Circuit A
7 PWDN Disable/Enable Control Input. Apply logic high voltage to shut down the AD8362.
9 CLPF

Connection for loop filter integration (averaging) capacitor, the other pin of which is usually

grounded via a resistor to improve loop stability and response time.
10, 16 ACOM Analog Common Connection for Output Amplifier.
11 VSET

The voltage applied to this pin sets the decibel value of the required RF input voltage that results in

Circuit B

zero current out of CLPF and thus the loop integrating capacitor.
12 VOUT Output of Error Amplifier. In measurement mode, normally connected directly to VSET. Circuit C
13 VPOS Connect to 5 V Power Supply.
14 VTGT

The logarithmic intercept voltage is proportional to the voltage applied to this pin. The use of a lower

Circuit D

target voltage increases the crest factor capacity.
15 VREF General-Purpose Reference Voltage Output of 1.25 V (usually connected only to VTGT). Circuit E

Rev. B | Page 7 of 36

AD8362

EQUIVALENT CIRCUITS

DECL

INHI

INLO

DECL

COMM

100Ω

VGA

100Ω

VPOS

Figure 3. Circuit A

VPOS

COMM

VPOS

VSET

ACOM

COMM

~35kΩ

~35kΩ

VSET

INTERFACE

RAIL-TO-RAIL

0.7V

CLPF

02923-B-004

OUTPUT

2kΩ

500Ω

Figure 6. Circuit D

VPOS

VOUT

ACOM

COMM

02923-B-006

Figure 4. Circuit B

SOURCE ONLY

VPOS

02923-B-003

VTGT

ACOM

COMM

50kΩ

50kΩ

VTGT

INTERFACE

GAIN = 0.12

02923-B-005

~0.35V

REF BUF

13kΩ

5kΩ

Figure 7. Circuit E

Figure 5. Circuit C

VPOS

VOUT

ACOM

COMM

02923-B-007

Rev. B | Page 8 of 36

AD8362

TYPICAL PERFORMANCE CHARACTERISTICS

4.5

4.0

3.5

3.0

2.5

2.0

VOUT (V)

1.5

1.0

0.5

0

–60

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

900MHz

1900MHz

INPUT AMPLITUDE (dBm)

2200MHz

2700MHz

–10

100MHz

15

02923-B-008

4.0

3.6

3.2

2.8

2.4

2.0

VOUT (V)

1.6
+25°C

1.2

–40°C

0.8

0.4

0
–60–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10 15–10

–40°C

+85°C

+25°C

+85°C

INPUT AMPLITUDE (dBm)

3.0

2.4

1.8

1.2

0.6
0
–0.6
–1.2

ERROR IN VOUT (dB)

–1.8

–2.4

–3.0

02923-B-011

Figure 8. Output Voltage (VOUT) vs. Input Amplitude (dBm),

Frequencies 100 MHz, 900 MHz, 1900 MHz, 2200 MHz, 2700 MHz,

Sine Wave, Differential Drive

3.0

2.5

2.0

1.5
100MHz

1.0

0.5

0
–0.5
–1.0

ERROR IN VOUT (dB)

–1.5
–2.0
–2.5
–3.0

–60

2200MHz

900MHz

2700MHz

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

INPUT AMPLITUDE (dBm)

1900MHz

–10

Figure 9. Logarithmic Law Conformance vs. Input Amplitude

Frequencies 100 MHz, 900 MHz, 1900 MHz, 2200 MHz, 2700 MHz,

Sine Wave, Differential Drive

4.0

3.6

3.2

2.8

2.4

2.0

VOUT (V)

1.6

1.2

0.8

0.4

–40°C

+25°C

+85°C

–40°C

+85°C

+25°C

0

–55

–50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

INPUT AMPLITUDE (dBm)

–10

15

3.0

2.4

1.8

1.2

0.6

0
–0.6
–1.2

–1.8

–2.4

–3.0

15

02923-B-009

ERROR IN VOUT (dB)

02923-B-010

Figure 11. VOUT and Law Conformance vs. Input Amplitude, Frequency

1900 MHz, Sine Wave, Temperature −40°C, +25°C, and +85°C

4.0

3.6

3.2

2.8

2.4

2.0

VOUT (V)

1.6

1.2
–40°C

0.8

0.4

0

–50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

–60

–55

–40°C

+25°C

+85°C

+25°C

INPUT AMPLITUDE (dBm)

+85°C

–10

3.0

2.4

1.8

1.2

0.6
0
–0.6
–1.2

–1.8

–2.4

–3.0

15

Figure 12. VOUT and Law Conformance vs. Input Amplitude, Frequency

2200 MHz, Sine Wave, Temperature −40°C, +25°C, and +85°C

4.0

3.5

3.0

2.5

2.0

VOUT (V)

1.5

1.0

0.5

0

IS95 REVERSE LINK

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

–60

INPUT AMPLITUDE (dBm)

CW

WCDMA 8-CHANNEL

WCDMA 15-CHANNEL

–10

15

ERROR IN VOUT (dB)

02923-B-012

02923-B-013

Figure 10. VOUT and Law Conformance vs. Input Amplitude, Frequency

900 MHz, Sine Wave, Temperature −40°C, +25°C, and +85°C

Figure 13. VOUT vs. Input Amplitude with Different Waveforms, CW, IS95

Reverse Link, WCDMA 8-Channel, WCDM 15- Channel, Frequency 900 MHz

Rev. B | Page 9 of 36

AD8362

3.0

2.5

2.0

1.5
WCDMA 8-CHANNEL

–10

WCDMA

8-CHANNEL

WCDMA 8-CHANNEL

WCDMA 15-CHANNEL

–10

–0.5
–1.0

ERROR IN VOUT (dB)

–1.5
–2.0
–2.5
–3.0

1.0

0.5

0

–60

IS95 REVERSE LINK

CW

WCDMA 15-CHANNEL

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

INPUT AMPLITUDE (dBm)

Figure 14. Output Error from CW Linear Reference vs. Input Amplitude
with Different Waveforms, CW, IS95 Reverse Link, WCDMA 8-Channel,

WCDMA 15-Channel, Frequency 900 MHz

3.0

2.5

2.0

1.5

1.0

0.5
0

–0.5
–1.0

ERROR IN VOUT (dB)

–1.5
–2.0
–2.5
–3.0

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10–10

WCDMA

4-CHANNEL

C

W

WCDMA 15-CHANNEL

INPUT AMPLITUDE (dBm)

Figure 15. Output Error from CW Linear Reference vs. Input Amplitude

with Different WCDMA Channel Loading, 4-Channel, 8-Channel,

15-Channel, Frequency 2200 MHz

3.0

2.5

2.0

1.5

1.0

0.5
0

–0.5
–1.0

ERROR IN VOUT (dB)

–1.5
–2.0
–2.5

–3.0

–60

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

INPUT AMPLITUDE (dBm)

Figure 16. Output Error from CW Linear Reference vs. Input Amplitude,

3 Sigma to Either Side of Mean, with WCDMA 8-Channel,

WCDMA 15-Channel, Frequency 1900 MHz

3.0

2.5

2.0

1.5

1.0

0.5

–0.5
–1.0

ERROR IN VOUT (dB)

–1.5
–2.0
–2.5

15

02923-B-014

–3.0

WCDMA

8-CHANNEL

0

WCDMA

15-CHANNEL

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

–60

INPUT AMPLITUDE (dBm)

–10

15

02923-B-017

Figure 17. Output Error from CW Linear Reference vs. Input Amplitude,

3 Sigma to Either Side of Mean, with WCDMA 8-Channel,

15-Channel, Frequency 1900 MHz

3.0

2.5

2.0

WCDMA

8-CHANNEL

1.5

1.0

0.5
0

–0.5
–1.0

ERROR IN VOUT (dB)

–1.5
–2.0
–2.5
–3.0

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

02923-B-015

–60

WCDMA

15-CHANNEL

INPUT AMPLITUDE (dBm)

–10

15

02923-B-018

Figure 18. Output Error from CW Linear Reference vs. Input Amplitude,

3 Sigma to Either Side of Mean, with WCDMA 8-Channel,

WCDMA 15-Channel, Frequency 2200 MHz

4.0

3.5

3.0

2.5

2.0

VOUT (V)

1.5

1.0

0.5

0

15

02923-B-016

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

INPUT AMPLITUDE (dBm)

–10

02923-B-019

Figure 19. VOUT vs. Input Amplitude, 3 Sigma to Either Side of Mean,

Sine Wave, Frequency 900 MHz, Part-to-Part Variation

Rev. B | Page 10 of 36

AD8362

4.0

3.5

3.0

2.5

2.0

VOUT (V)

1.5

1.0

0.5

0

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5

INPUT AMPLITUDE (dBm)

–10

10

Figure 20. VOUT vs. Input Amplitude, 3 Sigma to Either Side of Mean,

Sine Wave, Frequency 1900 MHz, Part-to-Part Variation

3.0

2.5

2.0

1.5

1.0

0.5
0

–0.5
–1.0

ERROR IN VOUT (dB)

–1.5
–2.0
–2.5
–3.0

–55

–50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

–40°C

+25°C

INPUT AMPLITUDE (dBm)

+85°C

–10

Figure 21. Logarithmic Law Conformance vs. Input Amplitude,

3 Sigma to Either Side of Mean, Sine Wave, Frequency 900 MHz,

Temperature −40°C, +25°C, and +85°C

3.0

2.5

2.0

1.5

1.0

0.5
0

–0.5
–1.0

ERROR IN VOUT (dB)

–1.5
–2.0
–2.5
–3.0

–55

–50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

–45°C

+85°C

INPUT AMPLITUDE (dBm)

+25°C

–10

02923-B-022

Figure 22. Logarithmic Law Conformance vs. Input Amplitude,

3 Sigma to Either Side of Mean, Sine Wave, Frequency 1900 MHz,

Temperature −40°C, +25°C, and +85°C

02923-B-020

02923-B-021

3.0

2.5

2.0

1.5

1.0

0.5
0

–0.5
–1.0

ERROR IN VOUT (dB)

–1.5
–2.0
–2.5
–3.0

–55

–50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

–40°C

+85°C

+25°C

INPUT AMPLITUDE (dBm)

–10

Figure 23. Logarithmic Law Conformance vs. Input Amplitude,

3 Sigma to Either Side of Mean, Sine Wave, Frequency 2200 MHz,

Temperature −40°C, +25°C, and +85°C

52.0

SLOPE (mV)

51.5

51.0

50.5

50.0

49.5

49.0

900

1000

1100

1200

1300

1400

1500

1600

1700

FREQUENCY (MHz)

1800

1900

2000

2100

2200

+85°C

+25°C

–40°C

2300

2400

2500

2600

Figure 24. Logarithmic Slope vs. Frequency,

Temperature −40°C, +25°C, and +85°C

–53

–54

–55

–56

–57

–58

–59

INTERCEPT (dBm)

–60

–61

–62

–63

900

1000

1100

1200

1300

1400

1500

1600

1700

1800

FREQUENCY (MHz)

1900

2000

2100

2200

2300

+85°C

+25°C

–40°C

2400

2500

2600

Figure 25. Logarithmic Intercept vs. Frequency,

Temperature −40°C, +25°C, and +85°C

2700

2700

02923-B-023

02923-B-024

02923-B-025

Rev. B | Page 11 of 36