ANALOG DEVICES AD8362 Service Manual

50 Hz to 3.8 GHz

V

V

FEATURES

Complete fully calibrated measurement/control system
Accurate rms-to-dc conversion from 50 Hz to 3.8 GHz
Input dynamic range of >65 dB: −52 dBm to +8 dBm in 50 Ω
Waveform and modulation independent, such as

GSM/CDMA/TDMA
Linear-in-decibels output, scaled 50 mV/dB
Law conformance error of 0.5 dB
All functions temperature and supply stable
Operates from 4.5 V to 5.5 V at 24 mA
Power-down capability to 1.3 mW

APPLICATIONS

Power amplifier linearization/control loops
Transmitter power controls
Transmitter signal strength indication (TSSI)
RF instrumentation

GENERAL DESCRIPTION

The AD8362 is a true rms-responding power detector that has
a 65 dB measurement range. It is intended for use in a variety of
high frequency communication systems and in instrumentation
requiring an accurate response to signal power. It is easy to use,
requiring only a single supply of 5 V and a few capacitors. It can
operate from arbitrarily low frequencies to over 3.8 GHz and
can accept inputs that have rms values from 1 mV to at least
1 V rms, with large crest factors, exceeding the requirements
for accurate measurement of CDMA signals.

The input signal is applied to a resistive ladder attenuator that
comprises the input stage of a variable gain amplifier (VGA).
The 12 tap points are smoothly interpolated using a proprietary
technique to provide a continuously variable attenuator, which
is controlled by a voltage applied to the VSET pin. The resulting
signal is applied to a high performance broadband amplifier. Its
output is measured by an accurate square-law detector cell. The
fluctuating output is then filtered and compared with the output
of an identical squarer, whose input is a fixed dc voltage applied
to the VTGT pin, usually the accurate reference of 1.25 V pro­vided at the VREF pin.

The difference in the outputs of these squaring cells is integrated
in a high gain error amplifier, generating a voltage at the VOUT
pin with rail-to-rail capabilities. In a controller mode, this low
noise output can be used to vary the gain of a host system’s RF

65 dB TruPwr™ Detector

AD8362

FUNCTIONAL BLOCK DIAGRAM

CHPF

DECL

INHI

INLO

TGT

AD8362

REF

amplifier, thus balancing the setpoint against the input power.
Optionally, the voltage at VSET can be a replica of the RF signal’s
amplitude modulation, in which case the overall effect is to
remove the modulation component prior to detection and low­pass filtering. The corner frequency of the averaging filter can
be lowered without limit by adding an external capacitor at the
CLPF pin. The AD8362 can be used to determine the true power
of a high frequency signal having a complex low frequency
modulation envelope, or simply as a low frequency rms volt­meter. The high-pass corner generated by its offset-nulling
loop can be lowered by a capacitor added on the CHPF pin.

Used as a power measurement device, VOUT is strapped to
VSET. The output is then proportional to the logarithm of the
rms value of the input. In other words, the reading is presented
directly in decibels and is conveniently scaled 1 V per decade,
or 50 mV/dB; other slopes are easily arranged. In controller
modes, the voltage applied to VSET determines the power level
required at the input to null the deviation from the setpoint.
The output buffer can provide high load currents.

The AD8362 has 1.3 mW power consumption when powered
down by a logic high applied to the PWDN pin. It powers up
within about 20 µs to its nominal operating current of 20 mA at
25°C. The AD8362 is supplied in a 16-lead TSSOP for operation
over the temperature range of −40°C to +85°C.

2

x

2

x

Figure 1.

BIAS

PWDNCOMM

CLPF

VOUT

ACOM

VSET

VPOS

02923-001

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2003–2007 Analog Devices, Inc. All rights reserved.

AD8362

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Equivalent Circuits........................................................................... 8

Typical Performance Characteristics ............................................. 9

Characterization Setup .................................................................. 15

Equipment................................................................................... 15

Analysis........................................................................................ 15

Circuit Description......................................................................... 16

Square Law Detection................................................................ 16

Voltage vs. Power Calibration................................................... 17

Offset Elimination...................................................................... 18

Time-Domain Response of the Closed Loop .........................18

REVISION HISTORY

6/07—Rev. C to Rev. D

Changes to Features, General Description.................................... 1

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 6

Added Figure 21 to Figure 25........................................................ 11

Changes to Equipment Section..................................................... 15

Changes to Circuit Description Section...................................... 16

Changes to Single-Ended Input Drive Section ........................... 19

Changes to Choosing a Value for CHPF section........................ 21

Changes to Choosing a Value for CLPF section......................... 21

Changes to Figure 57...................................................................... 23

Changes to Figure 58...................................................................... 24

Added Temperature Compensation at Various WiMAX

Frequencies up to 3.8 GHz Section.............................................. 24

Changes to Ordering Guide.......................................................... 31

9/05—Rev. B to Rev. C

Changes to Specifications................................................................ 3

Changes to Table 3 ........................................................................... 7

Deleted Figure 16 to Figure 18; Renumbered Sequentially ......10

Changes to Figure 32 and Figure 33 ............................................ 13

Operation in RF Measurement Mode.......................................... 19

Basic Connections...................................................................... 19

Device Disable ............................................................................ 19

Recommended Input Coupling................................................ 19

Operation at Low Frequencies.................................................. 20

Choosing a Value for CHPF...................................................... 21

Choosing a Value for CLPF....................................................... 21

Adjusting VTGT to Accommodate Signals with Very High

Crest Factors ............................................................................... 22

Altering the Slope....................................................................... 22

Temperature Compensation and Reduction of Transfer

Function Ripple.......................................................................... 23

Temperature Compensation at Various WiMAX Frequencies up

to 3.8 GHz........................................................................................ 24

Operation in Controller Mode................................................. 26

RMS Voltmeter with 90 dB Dynamic Range.......................... 27

AD8362 Evaluation Board ............................................................ 28

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

Replaced Circuit Description Section ......................................... 15

Changes to Operation in RF Measurement Mode Section ...... 18

Deleted Using the AD8362 Section ............................................. 20

Deleted Main Modes of Operation Section ................................ 22

Changes to Operation in Controller Mode Section .................. 23

Changes to AD8362 Evaluation Board Section.......................... 25

Deleted General Applications Section......................................... 29

3/04—Rev. A to Rev. B

Updated Format .................................................................Universal

Changes to Specifications.................................................................3

Changes to the Offset Elimination Section................................. 16

Changes to the Operation at Low Frequencies Section ............ 17

Changes to the Time-Domain Response of the Closed

Loop Section.................................................................................... 17

Changes to Equation 13................................................................. 24

Changes to Table 5......................................................................... 31

6/03—Rev. 0 to Rev. A

Updated Ordering Guide .................................................................5

Change to Analysis Section........................................................... 12

Updated AD8362 Evaluation Board Section .............................. 26

2/03—Revision 0: Initial Version

Rev. D | Page 2 of 32

AD8362

SPECIFICATIONS

VS = 5 V, T = 25°C, ZO = 50 Ω, differential input drive via balun1, VTGT connected to VREF, VOUT tied to VSET, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

OVERALL FUNCTION

Maximum Input Frequency 3.8 GHz
Input Power Range (Differential)

Nominal Low End of Range −52 dBm
Nominal High End of Range 8 dBm

Input Voltage Range (Differential) RMS voltage at input terminals, f ≤ 2.7 GHz, into input of the device

Nominal Low End of Range 1.12 mV rms
Nominal High End of Range 1.12 V rms

Input Power Range (S-Sided) Single-ended drive, CW input, f ≤ 2.7 GHz, into input resistive network2

Nominal Low End of Range −40 dBm
Nominal High End of Range 0 dBm

Input Voltage Range (S-Sided) RMS voltage at input terminals, f ≤ 2.7 GHz

Nominal Low End of Range 2.23 mV rms
Nominal High End of Range 2.23 V rms

Input Power Range (S-Sided) Single-ended drive, CW input, f ≥ 2.7 GHz, into matched input network3

Nominal Low End of Range −35 dBm
Nominal High End of Range 12

Output Voltage Range RL ≥ 200 Ω to ground

Nominal Low End of Range 100 mV

Nominal High End of Range In general, VS − 0.1 V 4.9 V
Output Scaling (Log Slope) 50 mV/dB
Law Conformance Error Over central 60 dB range, f ≤ 2.7 GHz ±0.5 dB

RF INPUT INTERFACE Pin INHI, Pin INLO, ac-coupled, at low frequencies

Input Resistance Single-ended drive, with respect to DECL 100 Ω

Differential drive 200 Ω
OUTPUT INTERFACE Pin VOUT

Available Output Range RL ≥ 200 Ω to ground 0.1 4.9 V
Absolute Voltage Range

Nominal Low End of Range Measurement mode, f = 900 MHz, PIN = −52 dBm 0.32 0.48 V

Nominal High End of Range Measurement mode, f = 900 MHz, PIN = +8 dBm 3.44 3.52 V
Source/Sink Current VOUT held at VS/2, to 1% change 48 mA
Slew Rate Rising CL = open 60 V/μs
Slew Rate Falling CL = open 5 V/μs
Rise Time, 10% to 90% 0.2 V to 1.8 V, CLPF = Open 45 ns
Fall Time, 90% to 10% 1.8 V to 0.2 V, CLPF = Open 0.4 μs
Wideband Noise CLPF = 1000 pF, f

VSET INTERFACE Pin VSET

Nominal Input Voltage Range To ±1 dB error 0.5 3.75 V
Input Resistance 68 kΩ
Scaling (Log Slope) f = 900 MHz 46 50 54 mV/dB
Scaling (Log Intercept) f = 900 MHz, into 1:4 balun −64 −60 −56 dBm

−77 −73 −69 dBV
VOLTAGE REFERENCE Pin VREF

Output Voltage 25°C 1.225 1.25 1.275 V
Temperature Sensitivity −40°C ≤ TA ≤ +85°C 0.08 mV/°C
Output Resistance 8 Ω

dB referred to 50 Ω impedance level, f ≤ 2.7 GHz, into 1:4 balun

≤ 100 kHz 70 nV/√Hz

SPOT

1

4

dBm

Rev. D | Page 3 of 32

AD8362

Parameter Conditions Min Typ Max Unit

RMS TARGET INTERFACE Pin VTGT

Nominal Input Voltage Range Measurement range = 60 dB, to ±1 dB error 0.625 2.5 V
Input Bias Current VTGT = 1.25 V −28 μA
VTGT = 0 V −52 μA
Incremental Input Resistance 52 kΩ

POWER-DOWN INTERFACE Pin PWDN

Logic Level to Enable Logic low enables 1 V
Logic Level to Disable Logic high disables 3 V
Input Current Logic high 230 μA
Logic low 5 μA
Enable Time From PWDN low to VOUT within 10% of final value, CLPF = 1000 pF 14.5 ns
Disable Time From PWDN high to VOUT within 10% of final value, CLPF = 1000 pF 2.5 μs

POWER SUPPLY INTERFACE Pin VPOS

Supply Voltage 4.5 5 5.5 V
Quiescent Current 20 22 mA
Supply Current When disabled 0.2 mA

900 MHz

Dynamic Range Error referred to best-fit line (linear regression)
±1.0 dB linearity, CW input 65 dB
±0.5 dB linearity, CW input 62 dB
Deviation vs. Temperature Deviation from output at 25°C

−40°C < TA < +85°C, PIN = −45 dBm −1.7 dB

−40°C < TA < +85°C, PIN = −20 dBm −1.4 dB

−40°C < TA < +85°C, PIN = +5 dBm −1.0 dB
Logarithmic Slope 46 50 54 mV/dB
Logarithmic Intercept −64 −60 −56 dBm
Deviation from CW Response 5.5 dB peak-to-rms ratio (IS95 reverse link) 0.2 dB

12.0 dB peak-to-rms ratio (W-CDMA 4 channels) 0.2 dB

18.0 dB peak-to-rms ratio (W-CDMA 15 channels) 0.5 dB

1.9 GHz
Dynamic Range Error referred to best-fit line (linear regression)
±1 dB linearity, CW input 65 dB
±0.5 dB linearity, CW input 62 dB
Deviation vs. Temperature Deviation from output at 25°C

−40°C < TA < +85°C, PIN = −45 dBm −0.6 dB

−40°C < TA < +85°C, PIN = −20 dBm −0.5 dB

−40°C < TA < +85°C, PIN = +5 dBm −0.3 dB
Logarithmic Slope 51 mV/dB
Logarithmic Intercept −59 dBm
Deviation from CW Response 5.5 dB peak-to-rms ratio (IS95 reverse link) 0.2 dB

12.0 dB peak-to-rms ratio (W-CDMA 4 channels) 0.2 dB

18.0 dB peak-to-rms ratio (W-CDMA 15 channels) 0.5 dB

2.2 GHz
Dynamic Range Error referred to best-fit line (linear regression)
±1.0 dB linearity, CW input 65 dB
±0.5 dB linearity, CW input 65 dB
Deviation vs. Temperature Deviation from output at 25°C

−40°C < TA < +85°C, PIN = −45 dBm −1.8 dB

−40°C < TA < +85°C, PIN = −20 dBm −1.6 dB

−40°C < TA < +85°C, PIN = +5 dBm −1.3 dB
Logarithmic Slope 50.5 mV/dB
Logarithmic Intercept −61 dBm
Deviation from CW Response 5.5 dB peak-to-rms ratio (IS95 reverse link) 0.2 dB

12.0 dB peak-to-rms ratio (W-CDMA 4 channels) 0.2 dB

18.0 dB peak-to-rms ratio (W-CDMA 15 channels) 0.5 dB

Rev. D | Page 4 of 32

AD8362

Parameter Conditions Min Typ Max Unit

2.7 GHz
Dynamic Range Error referred to best-fit line (linear regression)
±1.0 dB linearity, CW input 63 dB
±0.5 dB linearity, CW input 62 dB
Deviation vs. Temperature Deviation from output at 25°C

−40°C < TA < +85°C, PIN = −40 dBm −5.3 dB

−40°C < TA < +85°C, PIN = −15 dBm −5.5 dB

−40°C < TA < +85°C, PIN = +5 dBm −4.8 dB
Logarithmic Slope 50.5 mV/dB
Logarithmic Intercept −58 dBm
Deviation from CW Response 5.5 dB peak-to-rms ratio (IS95 reverse link) 0.2 dB

12.0 dB peak-to-rms ratio (W-CDMA 4 channels) 0.2 dB

18.0 dB peak-to-rms ratio (W-CDMA 15 channels) 0.4 dB

3.65 GHz

Single-ended drive
Dynamic Range Error referred to best-fit line (linear regression)
±1.0 dB linearity, CW input 51 dB
±0.5 dB linearity, CW input 50 dB
Deviation vs. Temperature Deviation from output at 25°C

−40°C < TA < +85°C, PIN = −35 dBm −3 dB

−40°C < TA < +85°C, PIN = −15 dBm −3.5 dB

−40°C < TA < +85°C, PIN = +10 dBm −3.5 dB
Logarithmic Slope 51.7 mV/dB
Logarithmic Intercept −45 dBm

1

1:4 balun transformer, M/A-COM ETC 1.6-4-2-3.

2

See Figure 48.

3

See Figure 50.

4

The limitation of the high end of the power range is due to the test equipment not the device under test.

3

Rev. D | Page 5 of 32

AD8362

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage VPOS 5.5 V
Input Power (Into Input of Device) 15 dBm
Equivalent Voltage 2 V rms
Internal Power Dissipation 500 mW
θJA 125°C/W
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. D | Page 6 of 32

AD8362

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

COMM

2

CHPF

3

DECL

INHI

INLO

DECL

PWDN

COMM CLPF

AD8362

TOP VIEW

4

(Not to Scale)

5

6

7

8

16

ACOM

15

VREF

14

VTGT

13

VPOS

12

VOUT

11

VSET

10

ACOM

9

02923-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin
No.

Mnemonic Description

Equivalent
Circuit

1, 8 COMM Common Connection. Connect via low impedance to system common.
2 CHPF Input HPF. Connect to common via a capacitor to determine 3 dB point of input signal high-pass filter.
3, 6 DECL

Decoupling Terminals for INHI and INLO. Connect to common via a large capacitance to complete
input circuit.

4, 5 INHI , INLO

Differential Signal Input Terminals. Input Impedance = 200 Ω. Can also be driven single-ended, in

Circuit A

which case, the input impedance reduces to 100 Ω.
7 PWDN Disable/Enable Control Input. Apply logic high voltage to shut down the AD8362.
9 CLPF Connection for Ground Referenced Loop Filter Integration (Averaging) Capacitor.
10, 16 ACOM Analog Common Connection for Output Amplifier.
11 VSET

Setpoint Input. Connect directly to VOUT for measurement mode. Apply setpoint input to this pin for

Circuit B

controller mode.
12 VOUT RMS Output. In measurement mode, VOUT is normally connected directly to VSET. Circuit C
13 VPOS Connect to 5 V Power Supply.
14 VTGT

The logarithmic intercept voltage is proportional to the voltage applied to this pin. The use of a lower

Circuit D

target voltage increases the crest factor capacity. Normally connected to VREF.
15 VREF General-Purpose Reference Voltage Output of 1.25 V. Usually connected only to VTGT. Circuit E

Rev. D | Page 7 of 32

AD8362

EQUIVALENT CIRCUITS

DECL

INHI

INLO

DECL

COMM

100Ω

100Ω

VPOS

Figure 3. Circuit A

VGA

VPOS

COMM

VPOS

VSET

ACOM

COMM

~35kΩ

~35kΩ

VSET

INTERFACE

CLPF

02923-004

Figure 4. Circuit B

VPOS

50kΩ

VTGT

ACOM

02923-003

COMM

50kΩ

VTGT

INTERF ACE

GAIN = 0.12

02923-005

~0.35V

Figure 5. Circuit C

RAIL-TO-RAIL

0.7V

Figure 6. Circuit D

SOURCE ONLY

REF BUF

13kΩ

Figure 7. Circuit E

OUTPUT

2kΩ

500Ω

5kΩ

VPOS

VOUT

ACOM

COMM

VPOS

VOUT

ACOM

COMM

02923-006

02923-007

Rev. D | Page 8 of 32

AD8362

TYPICAL PERFORMANCE CHARACTERISTICS

4.5

2200MHz

2700MHz

–10

100MHz

15

02923-008

4.0

3.5

3.0

2.5

2.0

VOUT (V)

1.5

1.0

0.5

0

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

–60

900MHz

1900MHz

INPUT AMPLI TUDE (dBm)

Figure 8. Output Voltage (VOUT) vs. Input Amplitude (dBm),

Frequencies: 100 MHz, 900 MHz, 1900 MHz, 2200 MHz, and 2700 MHz;

Sine Wave, Differential Drive

3.0

2.5

2.0

1.5

100MHz

1.0

0.5

0

–0.5

–1.0

ERROR IN VOUT (dB)

–1.5

–2.0

–2.5

–3.0

–60

2200MHz

900MHz

2700MHz

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

INPUT AMPLI TUDE (dBm)

1900MHz

–10

15

02923-009

Figure 9. Logarithmic Law Conformance vs. Input Amplitude,

Frequencies: 100 MHz, 900 MHz, 1900 MHz, 2200 MHz, and 2700 MHz;

Sine Wave, Differential Drive

4.0

3.6

3.2

2.8

2.4

2.0

VOUT (V)

1.6

1.2

0.8

0.4

–40°C

+25°C

+85°C

–40°C

+85°C

+25°C

0

–50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

–55

INPUT AMPLI TUDE (dBm)

–10

3.0

2.4

1.8

1.2

0.6

0

–0.6

–1.2

–1.8

–2.4

–3.0

15

Figure 10. VOUT and Law Conformance vs. Input Amplitude,

Frequency 900 MHz, Sine Wave, Temperatures: −40°C, +25°C, and +85°C

ERROR IN VOUT (dB)

02923-010

4.0

3.6

3.2

2.8

2.4

2.0

VOUT (V)

1.6

+25°C

1.2
–40°C

0.8

0.4

0
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10 15–10

–40°C

+85°C

+25°C

+85°C

INPUT AMPLI TUDE (dBm)

3.0

2.4

1.8

1.2

0.6

0

–0.6

–1.2

–1.8

–2.4

–3.0

ERROR IN VOUT (dB)

02923-011

Figure 11. VOUT and Law Conformance vs. Input Amplitude,

Frequency 1900 MHz, Sine Wave, Temperatures: −40°C, +25°C, and +85°C

VOUT (V)

4.0

3.6

3.2

2.8

2.4

2.0

1.6

1.2

–40°C

0.8

0.4

0

–50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

–60

–55

–40°C

+25°C

+85°C

+25°C

INPUT AMPLITUDE (dBm)

+85°C

–10

3.0

2.4

1.8

1.2

0.6

0

–0.6

–1.2

ERROR IN VOUT (dB)

–1.8

–2.4

–3.0

15

02923-012

Figure 12. VOUT and Law Conformance vs. Input Amplitude,

Frequency 2200 MHz, Sine Wave, Temperatures: −40°C, +25°C, and +85°C

4.0

3.5

3.0

2.5

2.0

VOUT (V)

1.5

1.0

0.5

0

–60

IS95 REVERSE LINK

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

INPUT AMPLI TUDE (dBm)

CW

W-CDMA 8-CHANNEL

W-CDMA 15-CHANNEL

–10

15

02923-013

Figure 13. VOUT vs. Input Amplitude with Different Waveforms, CW, IS95

Reve rse Link, W-C DMA 8-Chann el, W-CDMA 1 5-Channel, Frequency 900 MHz

Rev. D | Page 9 of 32

AD8362

3.0

2.5

2.0

1.5

W-CDMA 8-CHANNEL

–10

ERROR IN VOUT (d B)

1.0

0.5

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

0

–60

IS95 REVERSE LINK

CW

W-CDMA 15-CHANNEL

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

INPUT AMPLITUDE (dBm)

Figure 14. Output Error from CW Linear Reference vs. Input Amplitude

with Different Waveforms, CW, IS95 Reverse Link, W-CDMA 8-Channel,

W-CDMA 15-Channel, Frequency 900 MHz, V

3.0

2.5

2.0

1.5

1.0

0.5

0

–0.5

–1.0

ERROR IN VOUT ( dB)

–1.5

–2.0

–2.5

–3.0

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10–10

W-CDMA

4-CHANNEL

CW

W-CDMA 15-CHANNEL

INPUT AMPLITUDE (dBm)

8-CHANNEL

W-CDMA

= 1.25 V

TGT

4.0

3.5

3.0

2.5

2.0

VOUT (V)

1.5

1.0

0.5

0

15

02923-014

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5

INPUT AMPLI TUDE (dBm)

–10

10

02923-017

Figure 17. VOUT vs. Input Amplitude, 3 Sigma to Either Side of Mean,

Sine Wave, Frequency 1900 MHz, Part-to-Part Variation

3.0

2.5

2.0

1.5

1.0

0.5

0

–0.5

–1.0

ERROR IN VOUT (dB)

–1.5

–2.0

–2.5

–3.0

–50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

–55

02923-015

–40°C

+25°C

INPUT AMPLITUDE (dBm)

+85°C

–10

02923-018

Figure 15. Output Error from CW Linear Reference vs. Input Amplitude

with Different W-CDMA Channel Loading, 4-Channel, 8-Channel,

15-Channel, Frequency 2200 MHz, V

4.0

3.5

3.0

2.5

2.0

VOUT (V)

1.5

1.0

0.5

0

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

INPUT AMPLI TUDE (dBm)

–10

= 1.25 V

TGT

Figure 16. VOUT vs. Input Amplitude, 3 Sigma to Either Side of Mean,

Sine Wave, Frequency 900 MHz, Part-to-Part Variation

02923-016

Rev. D | Page 10 of 32

Figure 18. Logarithmic Law Conformance vs. Input Amplitude,

3 Sigma to Either Side of Mean, Sine Wave, Frequency 900 MHz,

Temperatures: −40°C, +25°C, and +85°C

3.0

2.5

2.0

1.5

1.0

0.5

0

–0.5

–1.0

ERROR IN VOUT (dB)

–1.5

–2.0

–2.5

–3.0

–50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

–55

–45°C

+85°C

INPUT AMPLITUDE (dBm)

+25°C

–10

Figure 19. Logarithmic Law Conformance vs. Input Amplitude,

3 Sigma to Either Side of Mean, Sine Wave, Frequency 1900 MHz,

Temperatures: −40°C, +25°C, and +85°C

02923-019