Analog Devices AD8362 Service Manual

50 Hz to 2.7 GHz

V

V

FEATURES

Complete fully calibrated measurement/control system
Accurate rms-to-dc conversion from 50 Hz to 2.7 GHz
Input dynamic range of >60 dB: −52 dBm to +8 dBm in 50 Ω
Waveform and modulation independent, such as

GSM/CDMA/TDMA
Linear-in-decibels output, scaled 50 mV/dB
Law conformance error of 0.5 dB
All functions temperature and supply stable
Operates from 4.5 V to 5.5 V at 24 mA from −40°C to +85°C
Power-down capability to 1.3 mW

APPLICATIONS

Power amplifier linearization/control loops
Transmitter power control
Transmitter signal strength indication (TSSI)
RF instrumentation

GENERAL DESCRIPTION

INHI

INLO

TGT

REF

60 dB TruPwr™ Detector

AD8362

FUNCTIONAL BLOCK DIAGRAM

DECL

CHPF

2

AD8362

x

2

x

Figure 1.

BIAS

PWDNCOMM

CLPF

VOUT

ACOM

VSET

VPOS

02923-001

The AD8362 is a true rms-responding power detector that has a
60 dB measurement range. It is intended for use in a variety of
high frequency communication systems and in instrumentation
requiring an accurate response to signal power. It is easy to use,
requiring only a single supply of 5 V and a few capacitors. It can
operate from arbitrarily low frequencies to over 2.7 GHz and
can accept inputs that have rms values from 1 mV to at least
1 Vrms, with large crest factors, exceeding the requirements for
accurate measurement of CDMA signals.

The input signal is applied to a resistive ladder attenuator that
comprises the input stage of a variable gain amplifier. The
12 tap points are smoothly interpolated using a proprietary
technique to provide a continuously variable attenuator, which
is controlled by a voltage applied to the VSET pin. The resulting
signal is applied to a high performance broadband amplifier. Its
output is measured by an accurate square-law detector cell. The
fluctuating output is then filtered and compared with the output
of an identical squarer, whose input is a fixed dc voltage applied
to the VTGT pin, usually the accurate reference of 1.25 V
provided at the VREF pin.

The difference in the outputs of these squaring cells is
integrated in a high gain error amplifier, generating a voltage at
the VOUT pin with rail-to-rail capabilities. In a controller
mode, this low noise output can be used to vary the gain of a
host system’s RF amplifier, thus balancing the set point against

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registered trademarks are the property of their respective owners.

the input power. Optionally, the voltage at VSET may be a
replica of the RF signal’s amplitude modulation, in which case
the overall effect is to remove the modulation component prior
to detection and low-pass filtering. The corner frequency of the
averaging filter may be lowered without limit by adding an
external capacitor at the CLPF pin. The AD8362 can be used to
determine the true power of a high frequency signal having a
complex low frequency modulation envelope, or simply as a low
frequency rms voltmeter. The high-pass corner generated by its
offset-nulling loop can be lowered by a capacitor added on the
CHPF pin.

Used as a power measurement device, VOUT is strapped to
VSET. The output is then proportional to the logarithm of the
rms value of the input. In other words, the reading is presented
directly in decibels and is conveniently scaled 1 V per decade,
or 50 mV/dB; other slopes are easily arranged. In controller
modes, the voltage applied to VSET determines the power level
required at the input to null the deviation from the setpoint.
The output buffer can provide high load currents.

The AD8362 has a 1.3 mW power consumption when powered
down by a logic high applied to the PWDN pin. It powers up
within about 20 µs to its nominal operating current of 20 mA at
25°C. The AD8362 is supplied in a 16-lead TSSOP package for
operation over the industrial temperature range of −40°C to
+85°C. An evaluation board is available.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD8362

TABLE OF CONTENTS

Features .............................................................................................. 1

Operation in RF Measurement Mode.......................................... 18

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Equivalent Circuits........................................................................... 8

Typical Performance Characteristics ............................................. 9

Characterization Setup .................................................................. 14

Equipment................................................................................... 14

Analysis........................................................................................ 14

Circuit Description......................................................................... 15

Square Law Detection................................................................ 15

Volt a ge v s . Powe r Ca lib r ati o n ................................................... 16

Offset Elimination...................................................................... 17

Time-Domain Response of the Closed Loop ......................... 17

Basic Connections...................................................................... 18

Device Disable ............................................................................ 18

Recommended Input Coupling................................................ 18

Operation at Low Frequencies.................................................. 19

Choosing a Value for CHPF...................................................... 19

Choosing a Value for CLPF....................................................... 19

Adjusting VTGT to Accommodate Signals with

Ver y Hi g h Cr e st F a ct o r s ............................................................ 20

Altering the Slope....................................................................... 21

Temperature Compensation and Reduction of

Transf e r Funct i on Rippl e ........................................................... 21

Operation in Controller Mode ..................................................... 23

RMS Voltmeter with 90 dB Dynamic Range.......................... 23

AD8362 Evaluation Board ............................................................ 25

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 27

REVISION HISTORY

9/05—Rev. B to Rev. C

Changes to Specifications................................................................ 3

Changes to Table 3............................................................................ 7

Deleted Figure 16 to Figure 18; Renumbered Sequentially ...... 10

Changes to Figure 32 and Figure 33 ............................................ 13

Replaced Circuit Description Section.......................................... 15

Changes to Operation in RF Measurement Mode Section ....... 18

Deleted Using the AD8362 Section.............................................. 20

Deleted Main Modes of Operation Section ................................ 22

Changes to Operation in Controller Mode Section................... 23

Changes to AD8362 Evaluation Board Section .......................... 25

Deleted General Applications Section......................................... 29

Rev. C | Page 2 of 28

3/04—Data Sheet Changed from Rev. A to Rev. B

Updated Format.................................................................Universal

Changes to Specifications............................................................... 3

Changes to the Offset Elimination Section................................ 16

Changes to the Operation at Low Frequencies Section............17

Changes to the Time-Domain Response of the Closed Loop

Section............................................................................................. 17

Changes to Equation 13................................................................ 24

Changes to Table 5.........................................................................31

6/03—Data Sheet Changed from Rev. 0 to Rev. A

Updated Ordering Guide ...............................................................5

Change to Analysis Section.......................................................... 12

Updated AD8362 Evaluation Board Section ............................. 26

2/03—Revision 0: Initial Version

AD8362

SPECIFICATIONS

VS = 5 V, T = 25°C, ZO = 50 Ω, differential input drive via balun1, VTGT connected to VREF, VOUT tied to VSET, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

OVERALL FUNCTION

Maximum Input Frequency 2.7 GHz
Input Power Range (Differential)

Nominal Low End of Range −52 dBm
Nominal High End of Range +8 dBm

Input Voltage Range (Differential)

Nominal Low End of Range 1.12 mV rms
Nominal High End of Range 1.12 V rms

Input Power Range (S-Sided)

Nominal Low End of Range −40 dBm
Nominal High End of Range 0 dBm

Input Voltage Range (S-Sided) RMS voltage at input terminals, f ≤ 2.7 GHz

Nominal Low End of Range 2.23 mV rms
Nominal High End of Range 223 V rms

Output Voltage Range RL ≥ 200 Ω to ground

Nominal Low End of Range +100 mV

Nominal High End of Range In general, VS − 0.1 V +4.9 V
Output Scaling (Log Slope) 50 mV/dB
Law Conformance Error Over central 60 dB range, f ≤ 2.7 GHz ±0.5 dB

RF INPUT INTERFACE Pins INHI, INLO, ac-coupled

Input Resistance Single-ended drive, with respect to DECL 100 Ω

Differential drive 200 Ω
OUTPUT INTERFACE Pin VOUT

Available Output Range RL ≥ 200 Ω to ground 0.1 4.9 V
Absolute Voltage Range

Nominal Low End of Range Measurement mode, f = 900 MHz, PIN = −52 dBm 0.32 0.48 V

Nominal High End of Range Measurement mode, f = 900 MHz, PIN = +8 dBm 3.44 3.52 V
Source/Sink Current VOUT held at VS/2, to 1% change 48 mA
Slew Rate Rising CL = open 60 V/μs
Slew Rate Falling CL = open 5 V/μs
Rise Time, 10% to 90% 0.2 V to 1.8 V, CLPF = 0 45 ns
Fall Time, 90% to 10% 1.8 V to 0.2 V, CLPF = 0 0.4 μs
Wideband Noise CLPF = 1000 pF, f

VSET INTERFACE Pin VSET

Nominal Input Voltage Range To ±1 dB error 0.5 3.75 V
Input Resistance 68 kΩ
Scaling (Log Slope) f = 900 MHz 46 50 54 mV/dB
Scaling (Log Intercept) f = 900 MHz, into 1:4 balun −64 −60 −56 dBm

−77 −73 −69 dBV
VOLTAGE REFERENCE Pin VREF

Output Voltage 25°C 1.225 1.25 1.275 V
Temperature Sensitivity −40°C ≤ TA ≤ +85°C 0.08 mV/°C
Output Resistance 8 Ω

dB referred to 50 Ω impedance level,
f ≤ 2.7 GHz, into 1:4 balun

RMS voltage at input terminals,
f ≤ 2.7 GHz, into input of the device

Single-ended drive, CW input, f ≤ 2.7 GHz,
into input resistive network

SPOT

1

2

≤ 100 kHz 70 nV/√Hz

Rev. C | Page 3 of 28

AD8362

Parameter Conditions Min Typ Max Unit

RMS TARGET INTERFACE Pin VTGT

Nominal Input Voltage Range Measurement range = 60 dB, to ±1 dB error 0.625 2.5 V
Input Bias Current VTGT = 1.25 V −28 μA
VTGT = 0 V −52 μA
Incremental Input Resistance 52 kΩ

POWER-DOWN INTERFACE Pin PWDN

Logic Level to Enable Logic low enables
Logic Level to Disable Logic high disables 3
Input Current Logic high
Logic low
Enable Time

Disable Time

POWER SUPPLY INTERFACE Pin VPOS

Supply Voltage
Quiescent Current
Supply Current When disabled 0.2 mA

900 MHz

Dynamic Range Error referred to best fit line (linear regression)
±1.0 dB linearity, CW input 65 dB
±0.5 dB linearity, CW input 62 dB
Deviation vs. Temperature Deviation from output at 25°C

−40°C < TA < +85°C; PIN = −45 dBm −1.7 dB

−40°C < TA < +85°C; PIN = −20 dBm −1.4 dB

−40°C < TA < +85°C; PIN = +5 dBm −1 dB
Logarithmic Slope 46 50 54 mV/dB
Logarithmic Intercept −64 −60 −56 dBm
Deviation from CW Response 5.5 dB peak-to-rms ratio (IS95 reverse link) 0.2 dB

12.0 dB peak-to-rms ratio (WCDMA 4 channels) 0.2 dB

18.0 dB peak-to-rms ratio (WCDMA 15 channels) 0.5 dB

1.9 GHz
Dynamic Range Error referred to best fit line (linear regression)
±1 dB linearity, CW input 65 dB
±0.5 dB linearity, CW input 62 dB
Deviation vs. Temperature Deviation from output at 25°C

−40°C < TA < +85°C; PIN = −45 dBm −0.6 dB

−40°C < TA < +85°C; PIN = −20 dBm −0.5 dB

−40°C < TA < +85°C; PIN = +5 dBm −0.3 dB
Logarithmic Slope 51 mV/dB
Logarithmic Intercept −59 dBm
Deviation from CW Response 5.5 dB peak-to-rms ratio (IS95 reverse link) 0.2 dB

12.0 dB peak-to-rms ratio (WCDMA 4 channels) 0.2 dB

18.0 dB peak-to-rms ratio (WCDMA 15 channels) 0.5 dB

From PWDN low to VOUT within 10% of final value,
CLPF = 1000 pF

From PWDN high to VOUT within 10% of final value,
CLPF = 1000 pF

4.5 5 5.5 V
20 22 mA

230
5

14.5

2.5

1 V

V
μA
μA
ns

μs

Rev. C | Page 4 of 28

AD8362

Parameter Conditions Min Typ Max Unit

2.2 GHz
Dynamic Range Error referred to best fit line (linear regression)
±1.0 dB linearity, CW input 65 dB
±0.5 dB linearity, CW input 65 dB
Deviation vs. Temperature Deviation from output at 25°C

−40°C < TA < +85°C; PIN = −45 dBm −1.8 dB

−40°C < TA < +85°C; PIN = −20 dBm −1.6 dB

−40°C < TA < +85°C; PIN = +5 dBm −1.3 dB
Logarithmic Slope 50.5 mV/dB
Logarithmic Intercept −61 dBm
Deviation from CW Response 5.5 dB peak-to-rms ratio (IS95 reverse link) 0.2 dB

12.0 dB peak-to-rms ratio (WCDMA 4 channels) 0.2 dB

18.0 dB peak-to-rms ratio (WCDMA 15 channels) 0.5 dB

2.7 GHz
Dynamic Range Error referred to best fit line (linear regression)
±1.0 dB linearity, CW input 63 dB
±0.5 dB linearity, CW input 62 dB
Deviation vs. Temperature Deviation from output at 25°C

−40°C < TA < +85°C; PIN = −40 dBm −5.3 dB

−40°C < TA < +85°C; PIN = −15 dBm −5.5 dB

−40°C < TA < +85°C; PIN = +15 dBm −4.8 dB
Logarithmic Slope 50.5 mV/dB
Logarithmic Intercept −58 dBm
Deviation from CW Response 5.5 dB peak-to-rms ratio (IS95 reverse link) 0.2 dB

12.0 dB peak-to-rms ratio (WCDMA 4 channels) 0.2 dB

18.0 dB peak-to-rms ratio (WCDMA 15 channels) 0.4 dB

1

1:4 balun transformer, M/A-COM ETC 1.6-4-2-3.

2

See Figure 43.

Rev. C | Page 5 of 28

AD8362

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameters Ratings

Supply Voltage VPOS 5.5 V
Input Power (Into Input of Device) 13 dBm
Equivalent Voltage 2 V rms
Internal Power Dissipation 500 mW
θ

JA

Maximum Junction Temperature 125°C/W
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range (Soldering 60 sec) 300°C

125°C/W

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. C | Page 6 of 28

AD8362

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

COMM

2

CHPF

3

DECL

INHI

INLO

DECL

PWDN

COMM CLPF

AD8362

TOP VIEW

4

(Not to Scale)

5

6

7

8

16

15

14

13

12

11

10

9

ACOM
VREF
VTGT
VPOS
VOUT
VSET
ACOM

02923-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin
No.

Mnemonic Description

Equivalent
Circuit

1, 8 COMM Common Connection. Connect via low impedance to system common.
2 CHPF

Input HPF. Connect to common via a capacitor to determine 3 dB point of input signal high-pass
filter.

3, 6 DECL

Decoupling Terminals for INHI and INLO. Connect to common via a large capacitance to complete
input circuit.

4, 5 INHI , INLO

Differential Signal Input Terminals. Input Impedance = 200 Ω. Can also be driven single-ended, in

Circuit A

which case the input impedance reduces to 100 Ω.
7 PWDN Disable/Enable Control Input. Apply logic high voltage to shut down the AD8362.
9 CLPF Connection for Ground Referenced Loop Filter Integration (Averaging) Capacitor.
10, 16 ACOM Analog Common Connection for Output Amplifier.
11 VSET

Setpoint Input. Connect directly to VOUT for measurement mode. Apply setpoint

Circuit B

input to this pin for controller mode.
12 VOUT RMS Output. In measurement mode, VOUT is normally connected directly to VSET. Circuit C
13 VPOS Connect to 5 V Power Supply.
14 VTGT

The Logarithmic Intercept Voltage is Proportional to the Voltage Applied to this Pin.

Circuit D
The use of a lower target voltage increases the crest factor capacity. Normally
connected to VREF.

15 VREF General Purpose Reference Voltage Output of 1.25 V. Usually connected only to VTGT. Circuit E

Rev. C | Page 7 of 28

AD8362

EQUIVALENT CIRCUITS

DECL

COMM

INHI

100Ω

100Ω

INLO

VPOS

DECL

Figure 3. Circuit A

VGA

VPOS

COMM

VPOS

VSET

ACOM

COMM

~35kΩ

~35kΩ

VSET

INTERFACE

CLPF

02923-004

Figure 4. Circuit B

VPOS

50kΩ

VTGT

ACOM

02923-003

COMM

50kΩ

VTGT

INTERFACE

GAIN = 0.12

02923-005

~0.35V

Figure 5. Circuit C

RAIL-TO-RAIL

0.7V

Figure 6. Circuit D

SOURCE ONLY

REF BUF

13kΩ

5kΩ

Figure 7. Circuit E

OUTPUT

2kΩ

500Ω

VPOS

VOUT

ACOM

COMM

VPOS

VOUT

ACOM

COMM

02923-006

02923-007

Rev. C | Page 8 of 28

AD8362

TYPICAL PERFORMANCE CHARACTERISTICS

4.5

2200MHz

2700MHz

–10

100MHz

15

4.0

3.5

3.0

2.5

2.0

VOUT (V)

1.5

1.0

0.5

0

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

–60

900MHz

1900MHz

INPUT AMPLITUDE (dBm)

Figure 8. Output Voltage (VOUT) vs. Input Amplitude (dBm),

Frequencies 100 MHz, 900 MHz, 1900 MHz, 2200 MHz, 2700 MHz,

Sine Wave, Differential Drive

02923-008

4.0

3.6

3.2

2.8

2.4

2.0

VOUT (V)

1.6
+25°C

1.2

–40°C

0.8

0.4

0
–60–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10 15–10

–40°C

+85°C

+25°C

+85°C

INPUT AMPLITUDE (dBm)

3.0

2.4

1.8

1.2

0.6
0
–0.6
–1.2

ERROR IN VOUT (dB)

–1.8

–2.4

–3.0

Figure 11. VOUT and Law Conformance vs. Input Amplitude,

Frequency 1900 MHz, Sine Wave, Temperature −40°C, +25°C, and +85°C

02923-011

3.0

2.5

2.0

1.5
100MHz

1.0

0.5

0
–0.5
–1.0

ERROR IN VOUT (dB)

–1.5
–2.0
–2.5
–3.0

–60

2200MHz

900MHz

2700MHz

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

INPUT AMPLITUDE (dBm)

1900MHz

–10

02923-009

15

Figure 9. Logarithmic Law Conformance vs. Input Amplitude

Frequencies 100 MHz, 900 MHz, 1900 MHz, 2200 MHz, 2700 MHz,

Sine Wave, Differential Drive

4.0

3.6

3.2

2.8

2.4

2.0

VOUT (V)

1.6

1.2

0.8

0.4

–40°C

+25°C

+85°C

–40°C

+85°C

+25°C

0

–55

–50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

INPUT AMPLITUDE (dBm)

–10

3.0

2.4

1.8

1.2

0.6

0
–0.6

–1.2

–1.8
–2.4

–3.0

15

Figure 10. VOUT and Law Conformance vs. Input Amplitude,

Frequency 900 MHz, Sine Wave, Temperature −40°C, +25°C, and +85°C

ERROR IN VOUT (dB)

02923-010

4.0

3.6

3.2

2.8

2.4

2.0

VOUT (V)

1.6

1.2
–40°C

0.8

0.4

0

–60

–50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

–55

–40°C

+25°C

+85°C

+25°C

INPUT AMPLITUDE (dBm)

+85°C

–10

3.0

2.4

1.8

1.2

0.6
0
–0.6
–1.2

–1.8

–2.4

–3.0

15

ERROR IN VOUT (dB)

Figure 12. VOUT and Law Conformance vs. Input Amplitude,

Frequency 2200 MHz, Sine Wave, Temperature −40°C, +25°C, and +85°C

4.0

3.5

3.0

2.5

2.0

VOUT (V)

1.5

1.0

0.5

0

–60

IS95 REVERSE LINK

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

INPUT AMPLITUDE (dBm)

CW

WCDMA 8-CHANNEL

WCDMA 15-CHANNEL

–10

02923-013

15

Figure 13. VOUT vs. Input Amplitude with Different Waveforms, CW, IS95

Reverse Link, WCDMA 8-Channel, WCDM 15-Channel, Frequency 900 MHz

02923-012

Rev. C | Page 9 of 28

AD8362

3.0

2.5

2.0

1.5

1.0

0.5
0

–0.5
–1.0

ERROR IN VOUT (dB)

–1.5
–2.0
–2.5
–3.0

–60

IS95 REVERSE LINK

CW

WCDMA 15-CHANNEL

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

INPUT AMPLITUDE (dBm)

Figure 14. Output Error from CW Linear Reference vs. Input Amplitude
with Different Waveforms, CW, IS95 Reverse Link, WCDMA 8-Channel,

WCDMA 15-Channel, Frequency 900 MHz, V

WCDMA 8-CHANNEL

–10

= 1.25 V

TGT

4.0

3.5

3.0

2.5

2.0

VOUT (V)

1.5

1.0

0.5

02923-014

15

0

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5

INPUT AMPLITUDE (dBm)

–10

02923-020

10

Figure 17. VOUT vs. Input Amplitude, 3 Sigma to Either Side of Mean,

Sine Wave, Frequency 1900 MHz, Part-to-Part Variation

3.0

2.5

2.0

1.5

1.0

0.5
0

–0.5
–1.0

ERROR IN VOUT (dB)

–1.5
–2.0
–2.5
–3.0

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10–10

WCDMA

4-CHANNEL

C

W

WCDMA 15-CHANNEL

INPUT AMPLITUDE (dBm)

WCDMA

8-CHANNEL

02923-015

Figure 15. Output Error from CW Linear Reference vs. Input Amplitude

with Different WCDMA Channel Loading, 4-Channel, 8-Channel,

15-Channel, Frequency 2200 MHz, V

4.0

3.5

3.0

2.5

2.0

VOUT (V)

1.5

1.0

0.5

0

–55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

INPUT AMPLITUDE (dBm)

–10

= 1.25 V

TGT

02923-019

Figure 16. VOUT vs. Input Amplitude, 3 Sigma to Either Side of Mean,

Sine Wave, Frequency 900 MHz, Part-to-Part Variation

3.0

2.5

2.0

1.5

1.0

0.5
0

–0.5
–1.0

ERROR IN VOUT (dB)

–1.5
–2.0
–2.5
–3.0

–55

–50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

–40°C

+25°C

INPUT AMPLITUDE (dBm)

+85°C

–10

02923-021

Figure 18. Logarithmic Law Conformance vs. Input Amplitude,

3 Sigma to Either Side of Mean, Sine Wave, Frequency 900 MHz,

Temperature −40°C, +25°C, and +85°C

3.0

2.5

2.0

1.5

1.0

0.5
0

–0.5
–1.0

ERROR IN VOUT (dB)

–1.5
–2.0
–2.5
–3.0

–55

–50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

–45°C

+85°C

INPUT AMPLITUDE (dBm)

–10

+25°C

02923-022

Figure 19. Logarithmic Law Conformance vs. Input Amplitude,

3 Sigma to Either Side of Mean, Sine Wave, Frequency 1900 MHz,

Temperature −40°C, +25°C, and +85°C

Rev. C | Page 10 of 28

AD8362

3.0

2.5

2.0

1.5

1.0

0.5
0

–0.5
–1.0

ERROR IN VOUT (dB)

–1.5
–2.0
–2.5
–3.0

–55

–50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10

–40°C

+85°C

+25°C

INPUT AMPLITUDE (dBm)

–10

Figure 20. Logarithmic Law Conformance vs. Input Amplitude,

3 Sigma to Either Side of Mean, Sine Wave, Frequency 2200 MHz,

Temperature −40°C, +25°C, and +85°C

02923-023

3.0

2.5

2.0

CHANGE IN SLOPE (mV)

–0.5
–1.0
–1.5
–2.0
–2.5
–3.0

1.5

1.0

0.5
0

–40

1900MHz

2200MHz

–30 –20 –10 0 10 20 30 40 50 70 80 90

TEMPERATURE (°C)

900MHz

60

02923-026

Figure 23. Change in Logarithmic Slope vs. Temperature, 3 Sigma to Either

Side of Mean, Frequencies 900 MHz, 1900 MHz, 2200 MHz

52.0

51.5

51.0

50.5

SLOPE (mV)

50.0

49.5

49.0

900

1000

1100

1200

1300

1400

1500

1600

1700

FREQUENCY (MHz)

1800

Figure 21. Logarithmic Slope vs. Frequency,

Temperature −40°C, +25°C, and +85°C

–53

–54

–55

–56

–57

–58

–59

INTERCEPT (dBm)

–60

–61

–62

–63

900

1000

1100

1200

1300

1400

1500

1600

1700

FREQUENCY (MHz)

1800

Figure 22. Logarithmic Intercept vs. Frequency,

Temperature −40°C, +25°C, and +85°C

1900

1900

2000

2000

2100

2100

2200

2200

+85°C

+25°C

–40°C

2300

2300

2400

+85°C

+25°C

–40°C

2400

2500

2500

2600

2600

2700

2700

02923-024

02923-025

2.0

1.5

1.0

0.5

–0.5

–1.0

CHANGE IN INTERCEPT (dB)

–1.5

–2.0

1900MHz

0

2200MHz

–40

900MHz

–30 –20 –10 0 10 20 30 40 50 70 80 90

TEMPERATURE (°C)

60

02923-027

Figure 24. Change in Logarithmic Intercept vs. Temperature, 3 Sigma to

Either Side of Mean, Frequencies 900 MHz, 1900 MHz, 2200 MHz

100

80

60

HITS

40

20

0

48 5349 50 51 52

SLOPE (mV/dB)

02923-028

Figure 25. Slope Distribution, Frequency 900 MHz

Rev. C | Page 11 of 28

AD8362

80

70

60

50

40

HITS

30

20

10

0

–61.0 –58.0–60.5 –60.0 –59.5 –59.0 –58.5

Figure 26. Logarithmic Intercept Distribution, Frequency 900 MHz

INTERCEPT (dBm)

02923-029

5.0

4.5

O

W

ER-

P

DO

W

4.0

3.5

3.0

2.5

VOUT (V)

2.0

1.5

1.0

0.5

0

N

PIN

2dBm

O

UT

V

0.5V/DIV

0

210142

46

+

–10dBm
–20dBm

–30dBm

812 1816

TIME (μs)

6

4

2V/DIV

2

0

–2

–4

–6

–8

POWER-DOWN PIN (V)

–10

–12

–14

0

Figure 29. Output Response Using Power-Down Mode for Various RF Input

Levels, Carrier Frequency 900 MHz, CLPF = 0

02923-032

5.0

4.5

4.0

3.5

3.0

2.5

VOUT (V)

2.0

1.5

1.0

0.5

RF BURST

ENABLE

+2dBm

VO

UT

.5V/DIV

0

0

0

210142

46

–10dBm

–20dBm

–30dBm

812 1816

TIME (μs)

2V/DIV

6

4

2

0

–2

–4

–6

–8

RF BURST ENABLE (V)

–10

–12

–14

0

Figure 27. Output Response to RF Burst Input for Various

RF Input Levels, Carrier Frequency 900 MHz, CLPF = Open

5.0

4.5

RF BURST

4.0

3.5

3.0

2.5

VOUT (V)

2.0

1.5

1.0

0.5

ENABLE

+2dBm

–10dBm

VO

UT

0.5V/DIV

0

0

210142

46

–20dBm

–30dBm

812 1816

TIME (ms)

2V/DIV

6

4

2

0

–2

–4

–6

–8

RF BURST ENABLE (V)

–10

–12

–14

0

Figure 28. Output Response to RF Burst Input for Various RF Input Levels,

Carrier Frequency 900 MHz, CLPF = 0.1 μF

02923-030

02923-031

VOUT (V)

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

0.5V/DIV

1.0

0.5

0

0

210142

46

+2dBm

–10dBm
–20dBm

–30dBm

812 1816

TIME (ms)

6

4

V/DIV

2

2

0

–2

–4

–6

–8

POWER-DOWN PIN (V)

–10

–12

–14

0

02923-033

Figure 30. Output Response Using Power-Down Mode for Various RF Input

Levels, Carrier Frequency 900 MHz, CLPF = 0.1 μF

5.5

5.0

4.5

4.0

3.5

3.0

VOUT (V)

2.5

2.0

1.5

1.0

1V/DIV

0

0

210142

46

VPOS

812 1816

TIME (ms)

2V/DIV

+2dBm

–10dBm
–20dBm
–30dBm

6

4

2

0

–2

–4

–6

–8

POWER-DOWN PIN (V)

–10

–12

–14

0

02923-034

Figure 31. Output Response to Gating on Power Supply for Various RF Input

Levels, Carrier Frequency 900 MHz, CLPF = 0

Rev. C | Page 12 of 28

AD8362

300

250

200

100MHz

3GHz

02923-082

Figure 32. INHI, INLO Differential Input Impedance, 100 MHz to 3 GHz

5

0

–5

–10

–15

CHANGE IN VREF (mV)

–20

–25

–30

–30 –20 –10 0 10 20 30 40 50 70 80 90

–40

TEMPERATURE (°C)

60

02923-036

Figure 33. Change in VREF vs. Temperature, 3 Sigma to Either Side of Mean

HITS

150

100

50

0

1.230 1.2701.235 1.240 1.245 1.250 1.2601.255 1.265
VREF (V)

02923-037

Figure 34. VREF Distribution

Rev. C | Page 13 of 28

AD8362

(

)

CHARACTERIZATION SETUP

EQUIPMENT

The general hardware configuration used for most of the AD8362
characterization is shown in
Rohde & Schwarz SMIQ03B. A 1:4 balun transformer is used to
transform the single-ended RF signal to differential form. For
the response measurements in
configuration shown in
Figure 30, the configuration shown in Figure 37 is used. For
Figure 31, the configuration shown in Figure 38 is used.

SMIQ03B

RF SOURCE

3dB

Figure 35. The signal source is a

Figure 27 and Figure 28, the

Figure 36 is used. For Figure 29 and

AD8362

CHARACTERIZATION

RFIN

BOARD

VOUT

MULTIMETER

HP34401A

TEK TDS5104

SCOPE

SMT03

SIGNAL

GENERATOR

RF 50Ω

TEK P5050
VOLTAGE PROBE

BALUN

3dB

C2

AD8362

COMM

CHPF

C1

DECL

INHI

INLO

DECL

C3

PWDN

COMM

Figure 36. Response Measurement Setup for Modulated Pulse

ACOM

VREF

VTGT

VPOS

VOUT

VSET

ACOM

CLPF

HPE3631A

POWER

SUPPLY

C4

02923-039

PC

CONTROLLER

Figure 35. Primary Characterization Setup

ANALYSIS

The slope and intercept are derived using the coefficients of a
linear regression performed on data collected in its central
operating range. Error is stated in two forms: error from linear
response to CW waveform, and output delta from 25°C
performance.

The error from linear response to CW waveform is the decibel
difference in output from the ideal output defined by the
conversion gain and output reference. This is a measure of the
linearity of the device response to both CW and modulated
waveforms. The error in dB is calculated by

PPSlopeVOUT

−×−

IN

()

Error

where P

Z

=dB

Slope

is the x intercept, expressed in dBm.

Error from the linear response to CW waveform is not a
measure of absolute accuracy since it is calculated using the
slope and intercept of each device. However, it verifies the
linearity and the effect of modulation on the device response.
Error from 25°C performance uses the performance of a given
device and waveform type as the reference; it is predominantly a
measurement of output variation with temperature.

Z

TEK TDS5104

SCOPE

02923-038

SMT03

SIGNAL

GENERATOR

RF 50Ω

HP8112A

PULSE

GENERATOR

TEK P5050
VOLTAGE PROBE

BALUN

3dB

C2

AD8362

COMM

ACOM

CHPF

DECL

INHI

INLO

DECL

PWDN

COMM

VREF

VTGT

VPOS

VOUT

VSET

ACOM

CLPF

HPE3631A

POWER

SUPPLY

C4

02923-040

C1

C3

Figure 37. Response Measurement Setup for Power-Down Step

50Ω

C4

HP8112A

PULSE

GENERATOR

TEK TDS5104

SCOPE

TEK P5050
VOLTAGE
PROBE

02923-041

BALUN

3dB

SMT03

SIGNAL

GENERATOR

RF 50Ω

AD811

732Ω

AD8362

COMM

ACOM

CHPF

DECL

INHI

INLO

DECL

PWDN

COMM

VREF

VTGT

VPOS

0.01μF 100pF

VOUT

VSET

ACOM

CLPF

C1

C2

C3

Figure 38. Response Measurement Setup for Gated Supply

Rev. C | Page 14 of 28

AD8362

CIRCUIT DESCRIPTION

The AD8362 is a fully calibrated, high accuracy, rms-to-dc
converter providing a measurement range of over 60 dB. It is
capable of operating from signals as low in frequency as a few
hertz to at least 2.7 GHz. Unlike earlier rms-to-dc converters,
the response bandwidth is completely independent of the signal
magnitude. The −3 dB point occurs at about 3.5 GHz. The
capacity of this part to accurately measure waveforms having a
high peak-to-rms ratio (crest factor) is independent of either
the signal frequency or its absolute magnitude, over a wide
range of conditions.

This unique combination allows the AD8362 to be used as a
calibrated RF wattmeter covering a power ratio of >1,000,000:1,
a power controller in closed-loop systems, a general-purpose
rms-responding voltmeter, and in many other low frequency
applications.

The part comprises the core elements of a high performance
AGC loop (

Figure 39), laser-trimmed during manufacture to
close tolerances while fully operational at a test frequency of
100 MHz. Its linear, wideband, variable gain amplifier (VGA)
provides a general voltage gain, G

; this may be controlled in a

SET

precisely exponential (linear-in-dB) manner over the full 68 dB
range from −25 dB to +43 dB by a voltage V

. However, to

SET

provide adequate guard-banding, only the central 60 dB of this
range, from −21 dB to +39 dB, is normally used. The
VTGT to Accommodate Signals with Very High Crest Factors

Adjusting

section shows how this basic range may be shifted up or down.

AMPLITUDE TARGET

–25dB TO +43dB

INHI

INLO

CHPF

OFFSET

NULLING

VSET

VREF

1.25V

MATCH WIDE-

BAND SQUARERS

V

SIG

I

G

SET

CLPF

EXTERNAL

2

X

X

SQUITGT

C

LPF

VGA

SETPOINT
INTERFACE

BAND GAP

REFERENCE

Figure 39. Basic Structure of the AD8362

FORV

SIG

2

× 0.06

V

ATG

C

F

OUTPUT

FILTER

INTERNAL RESISTORS
SET BUFFER GAIN TO 5

VTGT

ACOM

VOUT

ACOM

02923-042

The VGA gain has the form

G

where G

= GO exp(−VSET/V

SET

is a basic fixed gain and V

O

) (1)

GNS

is a scaling voltage that

GNS

defines the gain slope (the dB change per volt). Note that the
gain decreases with V

SET

.

The VGA output is

V

where V

= G

SIG

is the ac voltage applied to the input terminals

IN

= GOVIN exp(VSET/V

SETVIN

) (2)

GNS

of the AD8362.

As is explained more fully in the

Recommended Input Coupling
section, the input drive may either be single-sided or differen­tial, although dynamic range is maximized with a differential
input drive. The effect of high frequency imbalances when
using a single-sided drive is less apparent at low frequencies
(from 50 Hz to 500 MHz), but the peak input voltage capacity is
always halved relative to differential operation.

SQUARE LAW DETECTION

The output of the variable-gain amplifier (V
a wideband square law detector, which provides a true rms
response to this alternating signal that is essentially inde­pendent of waveform. Its output is a fluctuating current (I
that has a positive mean value. This current is integrated by an
on-chip capacitance (C

), which is usually augmented by an

F

external capacitance (CLPF) to extend the averaging time. The
resulting voltage is buffered by a gain-of-5, dc-coupled amplifier
whose rail-to-rail output (VOUT) may be used for either
measurement or control purposes.

In most applications, the AGC loop is closed via the setpoint
interface pin, VSET, to which the VGA gain-control voltage on
VOUT is applied. In measurement modes, the closure is direct
and local by a simple connection from the output of the VOUT
pin to the VSET pin. In controller modes, the feedback path is
around some larger system, but the operation is the same.

The fluctuating current (I
setpoint target current (I

) is balanced against a fixed

SQU

) using current mode subtraction.

TGT

With the exact integration provided by the capacitor(s), the
AGC loop equilibrates when

) = I

MEAN(I

The current I

SQU

TGT

(3)

TGT

is provided by a second-reference squaring
cell whose input is the amplitude-target voltage V
fraction of the voltage VTGT applied to a special interface that
accepts this input at the VTGT pin. Since the two squaring cells
are electrically identical and are carefully implemented in the
IC, process and temperature-dependent variations in the
detailed behavior of the two square-law functions cancel.

) is applied to

SIG

. This is a

ATG

SQU

)

Rev. C | Page 15 of 28

AD8362

Accordingly, VTGT (and its fractional part V
the output that must be provided by the VGA for the AGC loop
to settle. Since the scaling parameters of the two squarers are
accurately matched, it follows that Equation 3 is satisfied only
when

MEAN(V

SIG

2

) = V

2

(4)

ATG

In a formal solution, extract the square root of both sides to
provide an explicit value for the root-mean-square (rms) value.
However, it is apparent that by forcing this identity through
varying the VGA gain and extracting the mean value by the
filter provided by the capacitor(s), the system inherently
establishes the relationship

rms(V

Substituting the value of V

rms[G

As a measurement device, V

) = V

SIG

ATG

exp(−VSET/V

OVIN

from Equation 2,

SIG

)] = V

GNS

is the unknown quantity and all

IN

ATG

other parameters can be fixed by design. To solve Equation 6,

rms[G

OVIN/VATG

] = exp(VSET/V

) (7)

GNS

so

VSET = V

The quantity V
because VSET must be 0 when rms (V

log[rms(VIN)/VZ] (8)

GNS

= V

Z

is defined as the intercept voltage

ATG/GO

) = VZ.

IN

When connected as a measurement device, the output of the
buffer is tied directly to VSET, which closes the AGC loop.
Making the substitution VOUT = VSET and changing the log
base to 10, as needed in a decibel conversion,

VOUT = V

where V

SLP

log10[rms(VIN)/VZ] (9)

SLP

is the slope voltage, that is, the change in output
voltage for each decade of change in the input amplitude.
Note that V

In the AD8362, V

SLP

= V

log (10) = 2.303 V

GNS

is laser trimmed to 1 V using a 100 MHz

SLP

GNS

test signal. Because a decade corresponds to 20 dB, this slope
may also be stated as 50 mV/dB. It is shown in the
Slope

section how the effective value of V

the user. The intercept V

is also laser trimmed to 224 µV (−60

Z

dBm relative to 50). In an ideal system, VOUT would cross
zero for an rms input of that value. In a single-supply realization
of the function, VOUT cannot run fully down to ground; here,
V

is the extrapolated value.

Z

VOLTAGE VS. POWER CALIBRATION

The AD8362 can be used as an accurate rms voltmeter from
arbitrarily low frequencies to microwave frequencies. For low
frequency operation, the input is usually specified either in volts
rms or in dBV (decibels relative to 1 V rms).

) determines

ATG

(5)

(6)

.

Altering the

may be altered by

SLP

At high frequencies, signal levels are commonly specified in
power terms. In these circumstances, the source and
termination impedances are an essential part of the overall
scaling. For this condition, the output voltage can be expressed as

VOUT = SLOPE × (P

where P

and the intercept PZ are expressed in dBm.

IN

− PZ) (10)

IN

In practice, the response deviates slightly from the ideal straight
line suggested by Equation 10. This deviation is called the law
conformance error. In defining the performance of high
accuracy measurement devices, it is customary to provide plots of
this error. In general terms, it is computed by extracting the best
straight line to the measured data using linear regression over a
substantial region of the dynamic range and under clearly specified
conditions.

3.8

3.5

3.2

2.9

2.6

2.3

2.0

1.7

VOUT (V)

1.4

1.1

–40°C

0.8

0.5

0.2
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –5 0 5 10 15–10

Figure 40. Output Voltage and Law Conformance Error

+25°C

–40°C

+85°C

+25°C

+85°C

INPUT AMPLITUDE (dBm)

= −40°C, +25°C, and +85°C

@ T

A

3.0

2.5

2.0

1.5

1.0

0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0

ERROR IN VOUT (dB)

02923-051

Figure 40 shows the output of the circuit of Figure 42 over the
full input range. The agreement with the ideal function (law
conformance) is also shown. This was determined by linear
regression on the data points over the central portion of the
transfer function for the +25°C data.

The error at −40°C, +25°C, and +85°C was then calculated by
subtracting the ideal output voltage at each input signal level
from the actual output, and dividing this quantity by the mean
slope of the regression equation to provide a measurement of
the error in decibels (scaled on the right-hand axis of

Figure 40).

The error curves generated in this way reveal not only the
deviations from the ideal transfer function at a nominal
temperature, but also all of the additional errors caused by
temperature changes. Notice that there is a small temperature
dependence in the intercept (the vertical position of the error
plots).

Rev. C | Page 16 of 28

AD8362

Figure 40 further reveals a periodic ripple in the conformance
curves. This is due to the interpolation technique used to select
the signals from the attenuator, not only at discrete tap points,
but anywhere in between; thus providing continuous
attenuation values. The selected signal is then applied to the 3.5
GHz, 40 dB fixed gain amplifier in the remaining stages of the
VGA of the AD8362.

An approximate schematic of the signal input section of the
AD8362 is shown in

Figure 41. The ladder attenuator is
composed of 11 sections (12 taps), each of which progressively
attenuates the input signal by 6.33 dB. Each tap is connected to
a variable transconductance cell whose bias current determines
the signal weighting given to that tap. The interpolator
determines which stages are active by generating a discrete set
of bias currents, each having a Gaussian profile. These are
arranged to move from left to right, thereby determining the
attenuation applied to the input signal as the gain is
progressively lowered over the 69.3 dB range under control of
the VSET input. The detailed manner in which the
transconductance of adjacent stages varies as the virtual tap
point slides along the attenuator accounts for the ripple
observed in the conformance curves. Its magnitude is slightly
temperature dependent and also varies with frequency (see
Figure 10, Figure 11 and Figure 12). Notice that the system’s
responses to signal inputs at INHI and INLO are not completely
independent; these pins do not constitute a fully floating
differential input.

GUASSIAN INTERPOLATOR

gm gm gm gm

ATTENUATION
CONTROL

TO FIXED
GAIN STAGE

OFFSET ELIMINATION

To address the small dc offsets that arise in the variable gain
amplifier, an offset-nulling loop is used. The high-pass corner
frequency of this loop is internally preset to 1 MHz, sufficiently
low for most high frequency applications. When using the
AD8362 in low frequency applications, the corner frequency
can be reduced as needed by the addition of a capacitor from
the CHPF pin to ground having a nominal value of 200 µF/Hz.
For example, to lower the high-pass corner frequency to
150 Hz, a capacitance of 1.33 µF is required. The offset
voltage varies depending on the actual gain at which the
VGA is operating, and thus on the input signal amplitude.

Baseline variations of this sort are a common aspect of all
VGAs, but they are more evident in the AD8362 because of the
method of its implementation, which causes the offsets to ripple
along the gain axis with a period of 6.33 dB. When an
excessively large value of CHPF is used, the offset correction
process may lag the more rapid changes in the VGA’s gain,
which may increase the time required for the loop to fully settle
for a given steady input amplitude.

TIME-DOMAIN RESPONSE OF THE CLOSED LOOP

The external low-pass averaging capacitance (CLPF) added at
the output of the squaring cell is chosen to provide adequate
filtering of the fluctuating detected signal. The optimum value
depends on the application; as a guideline, a value of roughly
900 µF/Hz should be used. For example, a capacitance of 5 µF
provides adequate filtering down to 180 Hz. Note that the
fluctuation in the quasi-dc output of a squaring cell operating
on a sine wave input is a raised cosine at twice the signal
frequency, easing this filtering function.

INHI

DECL

INLO

STAGE 1

6.33dB

Figure 41. Simplified Input Circuit

STAGE 2

6.33dB

STAGE 11

6.33dB

In the standard connections for the measurement mode, the
VSET pin is tied to VOUT. For small changes in input
amplitude (a few decibels), the time-domain response of this
loop is essentially linear, with a 3 dB low-pass corner frequency
of nominally f
around this local loop set the minimum recommended value of
this capacitor to about 300 pF, giving f

02923-B-052

When large and abrupt changes of input amplitude occur, the
loop response becomes nonlinear and exhibits slew rate
limitations.

Rev. C | Page 17 of 28

= 1/(CLPF × 1.1 kΩ). Internal time delays

LP

= 3 MHz.

LP

AD8362

OPERATION IN RF MEASUREMENT MODE

BASIC CONNECTIONS

Basic connections for operating the AD8362 in measurement
mode are shown in
single supply of nominally 5 V, its performance is essentially
unaffected by variations of up to ±10%.

The supply is connected to the VPOS pin using the decoupling
network also displayed in
network must provide a low impedance over the full frequency
range of the input, and should be placed as close as possible to
the VPOS pin. Two different capacitors are used in parallel to
reduce the overall impedance since these have different resonant
frequencies. The measurement accuracy is not critically depend­ent on supply decoupling, however, because the high frequency
signal path is confined to the relevant input pins. Lead lengths
from both DECL pins to ground and from INHI/INLO to the
input coupling capacitors should be as short as possible. All
COMM pins should also connect directly to the ground plane.

To place the device in measurement mode, connect VOUT to
VSET, and connect VTGT directly to VREF.

DEVICE DISABLE

The AD8362 is disabled by a logic high on the PWDN pin,
which may be directly grounded for continuous operation.
When enabled, the supply current is nominally 20 mA and
essentially independent of supply voltage and input signal
strength. When powered down by a logic low on PWDN, the
supply current is reduced to 230 µA.

RECOMMENDED INPUT COUPLING

The full dynamic range of the AD8362, particularly at very high
frequencies (above 500 MHz), is realized only when the input is
presented to it in differential (balanced) form. In
transmission line balun is used at the input. Having a 1:4
impedance ratio (1:2 turns ratio), the 200 Ω differential input
resistance of the AD8362 becomes 50 Ω at the input to the balun.

Figure 42. While the AD8362 requires a

Figure 42. The capacitors used in this

Figure 42, a

The balun outputs must be ac-coupled to the input of the
AD8362. The balun used in this example (M/A-COM ETC 1.6­4-2-3) is also used in the AD8362 evaluation board and is specified
for operation from 0.5 GHz to 2.5 GHz.

If a center-tapped flux-coupled transformer is used, connect the
center tap to the DECL pins, which are biased to the same
potential as the inputs (~3.6 V).

At lower frequencies where impedance matching is not
necessary, the AD8362 can be driven from a low impedance
differential source, remembering the inputs must be ac-coupled.

Choosing Input Coupling Capacitors

As noted, the inputs must be ac-coupled. The input coupling
capacitors combine with the 200  input impedance to create
an input high pass corner frequency equal to

= 1/(200 × π × CC)

F

HP

Ty pi ca ll y, F

should be set to at least one tenth the lowest input

HP

frequency of interest.

Single-Ended Input Drive

As already noted, the input stages of the AD8362 are optimally
driven from a fully balanced source, which should be provided
wherever possible. In many cases, unbalanced sources can be
applied directly to one or the other of the two input pins. The
chief disadvantage of this driving method is a 10 dB to 15 dB
reduction in dynamic range at frequencies above 500 MHz.

Figure 43 illustrates one of many ways of coupling the signal
source to the AD8362. Because the input pins are biased to
about 3.6 V (for V

= 5 V), dc-blocking capacitors are required

S

when driving from a grounded source. For signal frequencies
>5 MHz, a value of 1 nF is adequate. While either INHI or
INLO may be used, INHI is chosen here.

AD8362

SIGNAL

INPUT

Z = 50Ω

C10

1000pF

1:4 Z-RATIO

T1

ETC1.6-4-2-3

C6

100pF

C5

100pF

1 16

2 15

NC

C4

1nF

3 14

4 13

5 12

C7

1nF

6 11

7 10

8 9

COMM
CHPF
DECL
INHI
INLO
DECL
PWDN
COMM

Figure 42. Basic Connections for RF Power Measurement

ACOM

VREF

VTGT
VPOS
VOUT

VSET

ACOM

CLPF

V

5V @ 24mA

C3

0.1μF

S

0.1μF

C1

C2

1nF

V

OUT

02923-072

Rev. C | Page 18 of 28

AD8362

1 16

COMM

0.01μF

RF INPUT

100Ω

2 15

1nF

3 14

1nF

4 13

1nF

5 12

6 11

1nF

7 10

8 9

Figure 43. Input Coupling from a Single-Ended 50 Ω Source

CHPF
DECL
INHI
INLO
DECL
PWDN
COMM

ACOM

VREF
VTGT
VPOS
VOUT

VSET

ACOM

CLPF

02923-073

AD8362

An external 100 Ω shunt resistor combines with the internal
100 Ω single-ended input impedance to provide a broadband
50  match. The unused input (in this case, INLO) is ac­coupled to ground.

Figure 44 shows the transfer function of the
AD8362 at various frequencies when driven single-ended. The
results show that transfer function linearity at the top end of the
range is degraded by the single-ended drive.

4.0 2.0

3.5 1.5

3.0 1.0

2.5 0.5

2.0 0

VOUT (V)

1.5 –0.5

1.0 –1.0

450MHz
1900MHz
2500MHz
900MHz
2140MHz

ERROR (dB)

More information on operation of the AD8362 and other RF
power detectors at low frequency is available in Application Note
AN-691: Operation of RF Detector Products at Low Frequency.

CHOOSING A VALUE FOR CHPF

The 3.5 GHz variable gain amplifier of the AD8362 includes an
offset cancellation loop, which introduces a high-pass filter
effect in its transfer function. To properly measure the
amplitude of the input signal, the corner frequency (f
filter must be well below that of the lowest input signal in the
desired measurement bandwidth frequency. The required value
of the external capacitor is given by

CHPF = 200 F/f

(fHP in Hz) (12)

HP

For operation at frequencies as low as 100 kHz, set f
approximately 25 kHz (CHPF = 8 nF). For frequencies above
approximately 2 MHz, no external capacitance is required
because there is adequate internal capacitance on this node.

HP

to

HP

) of this

0.5 –1.5

0 –2.0

–50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5

–55 10

Figure 44. Transfer Function at Various Frequencies when

PIN (dBm)

RF Input is Driven Single-Ended.

OPERATION AT LOW FREQUENCIES

In conventional rms-to-dc converters based on junction
techniques, the effective signal bandwidth is proportional to the
signal amplitude. In contrast, the 3.5 GHz VGA bandwidth in
the AD8362 is independent of its gain. Because this amplifier is
internally dc-coupled, the system is also used as a high accuracy
rms voltmeter at low frequencies, retaining its temperature­stable decibel-scaled output; for example, in seismic, audio, and
sonar instrumentation.

While the AD8362 can be operated at arbitrarily low frequen­cies, an ac-coupled input interface must be maintained. In such
cases, the input coupling capacitors should be large enough so
that the lowest frequency components of the signal to be included
in the measurement are minimally attenuated. For example, for a
3 dB reduction at 1.5 kHz, capacitances of 1 µF are needed
because the input resistance is 100 Ω at each input pin (200 Ω
differentially), and the calculation is 1/(2π × 1.5 kΩ × 100) = 1 µF.
In addition, to lower the high-pass corner frequency of the VGA,
a large capacitor must be connected between the CHPF pin and
ground (see the

Choosing a Value for CHPF section).

02923-074

CHOOSING A VALUE FOR CLPF

In the standard connections for the measurement mode, the
VSET pin is tied to VOUT. For small changes in input
amplitude such as a few decibels, the time-domain response of
this loop is essentially linear with a 3 dB low-pass corner
frequency of nominally f
delays around this local loop set the minimum recommended
value of this capacitor to about 300 pF, making f

For operation at lower signal frequencies, or whenever the
averaging time needs to be longer, use

CLPF = 900 F/f

When the input signal exhibits large crest factors, such as a
CDMA or WCDMA signal, CLPF must be much larger than
might seem necessary. This is due to the presence of significant
low frequency components in the complex, pseudo-random
modulation, which generates fluctuations in the AD8362’s
output. Increasing CLPF will also increase the step response of
the AD8362 to a change at its input.

Tabl e 4 shows recommended values of CLPF for popular
modulation schemes. In each case, CLPF is increased until
residual output noise falls below 50 mV. A 10% to 90% step
response to an input step is also listed. Where the increased
response time is unacceptably high, CLPF must be reduced. If
the output of the AD8362 is sampled by an ADC, averaging in
the digital domain can further reduce the residual noise.

= 1/(CLPF × 1.1 kΩ). Internal time

LP

= 3 MHz.

LP

(fLP in Hz) (13)

LP

Table 4. Recommended CLPF Values for Various Modulation Schemes

Response Time (Rise/Fall)

Modulation Scheme/Standard Crest Factor CLPF Residual Ripple

10% to 90%

WCDMA, Single-Carrier, Test Model 1-64 12.0 dB 0.1 μF 28 mVpp 171 μs/1.57 ms
WCDMA 4-Carrier, Test Model 1-64 11.0 dB 0.1 μF 20 mVpp 162 μs/1.55 ms
CDMA2000, Single-Carrier, 9CH Test Model 9.1 dB 0.1 μF 38 mVpp 179 μs /1.55 ms
CDMA2000, 3-Carrier, 9CH Test Model 11.0 dB 0.1 μF 29 mVpp 171 μs/1.55 ms
WiMax 802.16 (64QAM, 256 Subcarriers, 10 MHz Bandwidth) 14.0 dB 0.1 μF 30 mVpp 157 μs/1.47 ms

Rev. C | Page 19 of 28

AD8362

Figure 45 shows how residual ripple and rise/fall times vary
with filter capacitance when the AD8362 is driven by a single
carrier WCDMA signal (Test Model 1-64) at 2140 MHz.

180 18
170 17
160 16
150 15

RESIDUAL RIPPLE (mV p-p)

140 14
130 13
120 12
110 11
100 10

90 9
80 8
70 7
60 6
50 5

RESIDUAL RIPPLE (mV p-p)

40 4
30 3
20 2
10 1

00

0.10 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
FILTER CAPACITANCE (μF)

FALL TIME (ms)

RISE TIME (ms)

RISE/FALL TIME (ms)

02923-083

Figure 45. Residual Ripple, Rise and Fall Times vs. Filter Capacitance,

Single Carrier WCDMA Input Signal, Test Model 1-64

ADJUSTING VTGT TO ACCOMMODATE SIGNALS WITH VERY HIGH CREST FACTORS

An external direct connection between VREF (1.25 V) and VTGT
sets up the internal target voltage, which is the rms voltage that
must be provided by the VGA to balance the AGC feedback loop.

In the default scheme, the VREF of 1.25 V positions this target
to 0.06 × 1.25 V = 75 mV. In principle, however, VTGT may be
driven by voltages that are larger or smaller than this. This
technique can be used to move the intercept, which increases or
decreases the input sensitivity of the device, or to improve the
accuracy when measuring signals with large crest factors.

For example, if this pin is supplied from VREF via a simple
resistive attenuator of 1 kΩ:1 kΩ, the output required from the
VGA is halved to 37.5 mV rms. Under these conditions, the
effective headroom in the signal path that drives the squaring
cell is doubled. In principle, this doubles the peak crest factor
that may be handled by the system.

Figure 46 and Figure 47 show the effect of varying VTGT on
measurement accuracy when the AD8362 is swept with a series
of signals with different crest factors, varying from CW with a
crest factor of 3 dB, to a WCDMA carrier (Test Model 1-64)
with a crest factor of 10.6 dB. The crest factors of each signal are
listed in the plots. In
of 1.25 V, while in

Figure 46, VTGT is set to its nominal value

Figure 47, it is reduced to 0.625 V.

4.0
VOUT CW

VOUT 64QAM

3.5

VOUT WCDMA TM1-64
VOUT QPSK
VOUT 256QAM

3.0

2.5

2.0

VOUT (V)

1.5

1.0

0.5 –1.5

0

–65 10

–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5

Figure 46. Transfer Function and Law Conformance for Signals with

Varying Crest Factors, VTGT = 1.25

4.0
VOUT CW

VOUT 64QAM

3.5

VOUT WCDMA TM1-64
VOUT QPSK
VOUT 256QAM

3.0

2.5

2.0

VOUT (V)

1.5

1.0

0.5 –1.5

0

–65 10

–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5

Figure 47. Transfer Function and Law Conformance for Signals with

Varying Crest Factors, VTGT = 0.625 V, CLPF = 0.1

Reducing VTGT also reduces the intercept. More significant in
this case, however, is the behavior of the error curves. Note that
in

Figure 47 all of the error curves sit on one another, while in
Figure 46 there is some vertical spreading. This suggests that
VTGT should be reduced in those applications where a wide
range of input crest factors are expected. As noted, VTGT can
also be increased above its nominal level of 1.25 V. While this
can be used to increase the intercept, it would have the
undesirable effect of degrading measurement accuracy in
situations where the crest factor of the signal being measured
varies significantly.

ERROR QPSK 4dB CF
ERROR 256QAM 8.2dB CF
ERROR CW
ERROR 64QAM 7.7dB CF
ERROR WCDMA TM1-64 10.6dB CF

PIN (dBm)

ERROR QPSK 4dB CF
ERROR 256QAM 8.2dB CF
ERROR CW
ERROR 64QAM 7.7dB CF
ERROR WCDMA TM1-64 10.6dB CF

PIN (dBm)

2.0

1.5

1.0

0.5

0

ERROR (dB)

–0.5

–1.0

–2.0

02923-075

2.0

1.5

1.0

0.5

0

ERROR (dB)

–0.5

–1.0

–2.0

02923-076

μ

F

Rev. C | Page 20 of 28

AD8362

ALTERING THE SLOPE

None of the changes in operating conditions discussed so far
affect the logarithmic slope (V
readily be altered by controlling the fraction of VOUT that is
fed back to the setpoint interface at the VSET pin. When the full
signal from VOUT is applied to VSET, the slope assumes its
nominal value of 50 mV/dB. It can be increased by including a
voltage divider between these pins, as shown in

AD8362

1

2

3

4

5

6

7

8

Figure 48. External Network to Raise Slope

COMM
CHPF
DECL
INHI
INLO
DECL
PWDN
COMM

ACOM

VREF

VTGT
VPOS
VOUT

VSET

ACOM

CLPF

) in Equation 9. This can

SLP

Figure 48.

16

15

14

13

12

11

10

9

V

R1

R2

OUT

02923-056

TEMPERATURE COMPENSATION AND REDUCTION OF TRANSFER FUNCTION RIPPLE

The transfer function ripple and intercept drift of the AD8362
can be reduced using two techniques detailed in
CLPF is reduced from its nominal value. For broadband­modulated input signals, this results in increased noise at the
output that is fed back to the VSET pin.

The noise contained in this signal causes the gain of the VGA to
fluctuate around a central point, moving the wiper of the
Gaussian Interpolator back and forth on the R-2R ladder.

Because the gain-control voltage is constantly moving across at
least one of taps of the Gaussian Interpolator, the relationship
between the rms signal strength of the VGA output and the
VGA control voltage becomes independent of the VGA gain
control ripple (

Figure 49). The signal being applied to the
squaring cell is now lightly AM modulated. However, this does
not change the peak-to-average ratio of the signal.

Figure 50.

Moderately low resistance values should be used to minimize
scaling errors due to the 70 kΩ input resistance at the VSET pin.
This resistor string also loads the output, and it eventually
reduces the load-driving capabilities if very low values are used.
To calculate the resistor values, use

R1 = R2' (S

/50 − 1) (15)

D

where:

is the desired slope, expressed in mV/dB.

S

D

R2' is the value of R2 in parallel with 70 kΩ.

For example, using R1 = 1.65 kΩ and R2 = 1.69 kΩ
(R2' = 1.649 kΩ), the nominal slope is increased to
100 mV/dB. Note however, that doubling the slope in
this manner will reduce the maximum input signal to
approximately −10 dBm because of the limited swing of
VOUT (4.9 V with a 5 V power supply).

5V

1nF

COMM

0.1μF

VPOS

1

AD8362

ACOM

1

ADDITIONAL PINS
OMITTED FOR CLARITY

VOUT

VSET
VREF

VTGT
CLPF

1kΩ

1μF

440pF

3

AD8031

2

1

4

Figure 50. Temperature Compensation and Reduction of Transfer Function Ripple

4.0

3.5

3.0

2.5

2.0

VOUT (V)

1.5

1.0

0.5

0

–60 –40–50 –30 –20 –10 0 10

ERROR (dB –40°C)

V

(+25°C)

OUT

V

(–40°C)

OUT

(+85°C)

V

OUT

PIN (dBm)

ERROR (dB +25°C)

ERROR (dB +85°C)

2.0

1.0

0

–1.0

–2.0

ERROR (dB)

02923-078

Figure 49. Transfer Function and Linearity with Combined Ripple Reduction

and Temperature Compensation Circuits, Frequency = 2.14 GHz,

Single-Carrier WCDMA, Test Model 1-64

5V

0.1μF

7

6

5

R1

R2

5V

0.1μF

1

2

TMP36F

V

TMP

3

V

OUT_COMP

FREQUENCY (MHz) R1 (kΩ) R2 (kΩ)
900 1.02 25.5
1900 1 82.5
2200 1 19.1

02923-077

Rev. C | Page 21 of 28

AD8362

Because of the reduced filter capacitor, the rms voltage appearing
at the output of the error amplifier now contains significant peak­to-peak noise. While it is critical to feed this signal back to the
VGA gain control input with the noise intact, the rms voltage
going to the external measurement node can be filtered using a
simple filter to yield a largely noise-free rms voltage.

These compensation techniques are discussed in more detail in
Application Note AN-653, Improving Temperature, Stability,
and Linearity of High Dynamic Range RMS RF Power Detectors.

The circuit shown in
sensor that compensates temperature drift of the intercept.
Because the temperature drift varies with frequency, the amount
of compensation required must also be varied using R1 and R2.

Figure 50 also incorporates a temperature

Rev. C | Page 22 of 28

AD8362

OPERATION IN CONTROLLER MODE

The AD8362 provides a controller mode feature at the VOUT
pin. Using VSET for the setpoint voltage, it is possible for the
AD8362 to control subsystems such as power amplifiers (PAs),
variable gain amplifiers (VGAs), or variable voltage attenuators
(VVAs), which have output power that decreases monotonically
with respect to their (increasing) gain control signal.

CONTROLLED SYSTEM

(OUTPUT POWER

DECREASES AS

P

OUT

OUTPUT CONTROL VOLTAGE

ATTN

1:4 Z-RATIO

C10

1000pF

T1

ETC1.6-4-2-3

C6

100pF

C5

100pF

1nF

C4

1nF

C7

VAPC INCREASES)

VACP

0.1V TO 4.9V

AD8362

1 16

COMM

ACOM

2 15

CHPF

VREF

3 14

DECL

VTGT

4 13

INHI

VPOS

5 12

INLO

VOUT

6 11

DECL

VSET

7 10

PWDN

ACOM

8 9

COMM

CLPF

(SEE TEXT)

C3

INPUTOUTPUT

V

S

0.1μF

SET-POINT
VOLTAGE
INPUT
0V TO 3.5V

C1

C2

1nF

P

IN

Figure 51. Basic Connections for Controller Mode Operation

To operate in controller mode, the link between VSET and
VOUT is broken. A setpoint voltage is applied to the VSET input,
while VOUT is connected to the gain control terminal of the
variable gain amplifier (VGA), and the AD8362 RF input is
connected to the output of the VGA (generally using a directional
coupler or power splitter and some additional attenuation). Based
on the defined relationship between VOUT and the RF input
signal when the device is in measurement mode, the AD8362 will
adjust the voltage on VOUT (VOUT is now an error amplifier
output), until the level at the RF input corresponds to the applied
VSET. For example, in a closed loop system, if VSET is set to 3 V,
VOUT will increase or decrease until the input signal is equal to
0 dBm. This relationship follows directly from the measurement
mode transfer function (see

Figure 10, Figure 11, and Figure 12).

02923-079

Therefore, when the AD8362 operates in controller mode, there
is no defined relationship between VSET and VOUT. VOUT will
settle to a value that results in balance between input signal level
appearing at INHI/INLO and VSET.

In order for this output power control loop to be stable, a
ground-referenced capacitor must be connected to the CLPF
pin. This capacitor integrates the internal error current that is
present when the loop is not balanced.

Increasing VSET, which corresponds to demanding a higher
signal from the VGA, will tend to decrease VOUT. The VGA or
VVA therefore must have a negative sense. In other words,
increasing the gain control voltage decreases gain. If this is not
the case, an op-amp, configured as an inverter with suitable level
shifting, can be used to correct the sense of the VOUT signal.

RMS VOLTMETER WITH 90 dB DYNAMIC RANGE

The 60 dB range of the AD8362 can be extended by adding a
stand alone VGA as a preamplifier whose gain control input is
derived directly from VOUT. This extends the dynamic range
by the gain control range of this second amplifier. When this
VGA also provides a linear-in-dB (exponential) gain control
function, the overall measurement remains linearly scaled in
decibels. The VGA gain must decrease with an increase in its
gain bias in the same way as the AD8362. Alternatively, an
inverting op-amp with suitable level shifting can be used. It is
convenient to select a VGA needing only a single 5 V supply
and capable of generating a fully balanced differential output.
All of these conditions are met by the AD8330.
the schematic. Also note that the AD8131 is used to convert a
single-ended input into the differential-ended input needed by
the AD8330. The AD8131’s gain of 2 does create a dc offset on
the output of the AD8362, but this is removed by connecting

0.5 V to the VMAG on AD8330.

Figure 52 shows

Rev. C | Page 23 of 28

AD8362

μ

F

0.1

OFSTENBL CNTRVPOS

VPS1 VPSO

INHI OPHI

AD8330

INLO OPLO

MODE CMOP

INPUT

49.9Ω

GAIN OF 2

0.1μF

AD8131

29.9Ω

0.1μF

–5V

0.01μF

0.1μF

3

8

4
2
1

5

6

0.1μF

0.01μF

Figure 52. RMS Voltmeter with 90 dB Dynamic Range

Using the inverse gain mode (MODE pin low) of the AD8330,
its gain decreases on a slope of 30 mV/dB to a minimum value
of 3 dB for a gain voltage (VDBS) of 1.5 V. VDBS is 40% of the
output of the AD8362. Over the 3 V range from 0.5 V to 3.5 V,
the gain of the AD8330 varies by (0.4 × 3 V)/(30 mV/dB), or
40 dB. Combined with the 60 dB gain span of the AD8362, this
results in a 100 dB variation for a 3 V change in VOUT. Due to
the noise generated from the AD8330, the dynamic range is
limited to approximately 90 dB. This can only be achieved when
a band-pass filter is used at the operating frequency between
the AD8330 and AD8362.

Figure 53 shows data results of the extended dynamic range at
70 MHz with error in VOUT.

0.1μF

0.1μF

VMAGCOMMCMGNVDBS

+0.5V

+5V

AD8362

1

COMM

10μF

2

CHPF

3

BANDPASS

@ 70MHz

0.1μF

DECL

4

INHI

5

INLO

6

DECL

7

PWDN

8

COMM

–93

–103

3.0 6

–83

ACOM

VREF

VTGT

VPOS

VOUT

VSET

ACOM

CLPF

–73

16

15

14

13

12

11

10

9

–63

0.1μF

10μF

2kΩ

2kΩ

INPUT (dBV)

–53

–43

V

OUT

–33

02923-080

–230–1310–3

7

2.5 4

2.0 2

1.5 0

OUTPUT (V)

1.0 –2

ERROR IN VOUT (dB)

0.5 –4

0–

–80

–70

–60

–50

–40

–30

–20

–90

INPUT (dBm)

–10

6

20

02923-081

Figure 53. Output and Conformance for the AD8330/AD8362

Extended Dynamic Range Circuit

Rev. C | Page 24 of 28

AD8362

AD8362 EVALUATION BOARD

The AD8362 evaluation board provides for a number of
different operating modes and configurations, including many
described in this data sheet. The measurement mode is set up
by positioning SW2 as shown in

Figure 54. The AD8362 can be
operated in controller mode by applying the setpoint voltage to
the VSET connector, and flipping SW2 to its alternate position.

The internal voltage reference is used for the target voltage when
SW1 is in the position shown in

Figure 54. This voltage may
optionally be reduced via a voltage divider implemented with R4
and R5, with LK1 in place and SW1 switched to its alternate
position. Alternatively, an external target voltage may be used
with SW1 switched to its alternate position, LK1 removed, and
the external target voltage applied to the VTGT connector.

RFIN

PDWN

C10

1000pF

AGND

R14

OPEN

1000pF

T1

SW3

R13
10kΩ

C8

C6

100pF

C5

100pF

R15

0Ω

1000pF

R16

OPEN

1000pF

VPOS

1

C7

2

3

4

5

C4

6

7

8

Figure 54. Evaluation Board Schematic

0.1μF

COMM

CHPF
DECL
INHI

INLO

DECL
PWDN

COMM

C1

AD8362

In measurement mode, the slope of the response at VOUT
may be increased by using a voltage divider implemented with
resistors in Positions R17 and R9, and with SW2 switched to its
alternate position.

The AD8362 is powered up with SW3 in the position shown in
Figure 54 and connector PWDN open. The part can be powered
down by either connecting a logic high voltage to connector
PWDN with SW3 in the position, or by switching SW3 to its
alternate position.

R1

0Ω

C2
100pF

ACOM

VREF
VTGT

VPOS

VOUT

VSET

ACOM

CLPF

16

15

14

13

12

11

10

9

R17
OPEN

R10

0Ω

R6
0Ω

R9
10kΩ

R8
0Ω

0.1μF

OPEN

R4

0Ω

R5
10kΩ

SW1

R7
0Ω

SW2

C3

C9

LK1

VREF

VTGT

VOUT

VSET

02923-069

Figure 55. Component Side Metal of Evaluation Board

02923-070

Rev. C | Page 25 of 28

Figure 56. Component Side Silkscreen of Evaluation Board

02923-071

AD8362

Table 5. Evaluation Board Configuration Options

Component Function Part Number Default Value

T1

C1 Supply filtering/decoupling capacitor 0.1 μF
C2 Supply filtering/decoupling capacitor 100 pF
C3 Output low-pass filter capacitor 0.1 μF
C9 Output low-pass filter capacitor Open
C4, C7, C10 Input bias-point decoupling capacitors 1000 pF
C5, C6 Input signal coupling capacitors 100 pF
C8 Input high-pass filter capacitor 1000 pF
DUT AD8362 AD8362ARU
SW1, LK1, R4, R5

R1, R6, R7, R8, R10,
R15

R16 Not installed Open
R9, R17

SW2 Measurement mode/controller mode selector SW2 connects VSET to VOUT
SW3, R13

Use to reduce VTGT or to externally apply a voltage
to VTGT

Jumpers 0 Ω

Slope adjustment resistors. See the
Slope

section.

Power-down/power-up or external power-down
selector

Altering the

ETC 1.6-4-2-3
(M/A-COM)

R13 = 10 kΩ, SW3 connects PWDN to R13

LK1 = Open, R4 = 0 Ω, R5 = 10k Ω,
SW1 connects VREF to VTGT

R9 = 10 kΩ, R17 = Open

Rev. C | Page 26 of 28

AD8362

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AB

0.10

0.30

0.19

9

81

1.20
MAX

6.40

BSC

SEATING
PLANE

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 57. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8362ARU −40°C to +85°C 16-Lead TSSOP, Tube RU-16
AD8362ARU-REEL7 −40°C to +85°C 16-Lead TSSOP, 7" Tape and Reel RU-16
AD8362ARUZ
AD8362ARUZ-REEL7
AD8362-EVAL Evaluation Board

1

Z = Pb-free part.

1

1

−40°C to +85°C 16-Lead TSSOP, Tube RU-16

−40°C to +85°C 16-Lead TSSOP, 7" Tape and Reel RU-16

Rev. C | Page 27 of 28

AD8362

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02923-0-9/05(C)

Rev. C | Page 28 of 28