Calibrated rms response
Excellent temperature stability
Up to 30 dB input range at 2.5 GHz
700 mV rms, 10 dBm, re 50 Ω maximum input
±0.25 dB linear response up to 2.5 GHz
Single-supply operation: 2.7 V to 5.5 V
Low power: 3.3 mW at 3 V supply
Rapid power-down to less than 1 µA
APPLICATIONS
Measurement of CDMA, W-CDMA, QAM, other complex
modulation waveforms
RF transmitter or receiver power measurement
GENERAL DESCRIPTION
The AD8361 is a mean-responding power detector for use in
high frequency receiver and transmitter signal chains, up to
2.5 GHz. It is very easy to apply. It requires a single supply only
between 2.7 V and 5.5 V, a power supply decoupling capacitor,
and an input coupling capacitor in most applications. The
output is a linear-responding dc voltage with a conversion gain
of 7.5 V/V rms. An external filter capacitor can be added to
increase the averaging time constant.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
V rms (Volts)
1.0
0.8
0.6
0.4
0.2
0.0
0
Figure 1. Output in the Three Reference Modes, Supply 3 V, Frequency 1.9 GHz
The AD8361 is intended for true power measurement of simple
and complex waveforms. The device is particularly useful for
measuring high crest-factor (high peak-to-rms ratio) signals,
such as CDMA and W-CDMA.
The AD8361 has three operating modes to accommodate a
variety of analog-to-digital converter requirements:
1. Ground reference mode, in which the origin is zero.
2. Internal reference mode, which offsets the output 350 mV
above ground.
3. Supply reference mode, which offsets the output to V
The AD8361 is specified for operation from −40°C to +85°C
and is available in 8-lead MSOP and 6-lead SOT-23 packages. It
is fabricated on a proprietary high f
silicon bipolar process.
T
01088-C-002
01088-C-003
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
TA = 25°C, VS = 3 V, fRF = 900 MHz, ground reference output mode, unless otherwise noted.
Table 1.
Parameter Condition Min Typ Max Unit
SIGNAL INPUT INTERFACE (Input RFIN)
Frequency Range
Linear Response Upper Limit VS = 3 V 390 mV rms
Equivalent dBm, re 50 Ω 4.9 dBm
V
Equivalent dBm, re 50 Ω 9.4 dBm
Input Impedance
RMS CONVERSION (Input RFIN to Output V rms)
Conversion Gain 7.5 V/V rms
f
Dynamic Range Error Referred to Best Fit Line
±0.25 dB Error
±1 dB Error CW Input, −40°C < TA < +85°C 23 dB
±2 dB Error CW Input, −40°C < TA < +85°C 26 dB
CW Input, VS = 5 V, −40°C < TA < +85°C 30 dB
Intercept-Induced Dynamic Internal Reference Mode 1 dB
Range Reduction
Supply Reference Mode, VS = 5.0 V 1.5 dB
Deviation from CW Response 5.5 dB Peak-to-Average Ratio (IS95 Reverse Link) 0.2 dB
12 dB Peak-to-Average Ratio (W-CDMA 4 Channels) 1.0 dB
18 dB Peak-to-Average Ratio (W-CDMA 15 Channels) 1.2 dB
OUTPUT INTERCEPT5 Inferred from Best Fit Line3
Ground Reference Mode (GRM) 0 V at SREF, VS at IREF 0 V
f
Internal Reference Mode (IRM) 0 V at SREF, IREF Open 350 mV
f
Supply Reference Mode (SRM) 3 V at IREF, 3 V at SREF 400 mV
V
f
POWER-DOWN INTERFACE
PWDN HI Threshold 2.7 ≤ VS ≤ 5.5 V, −40°C < TA < +85°C VS − 0.5 V
PWDN LO Threshold 2.7 ≤ VS ≤ 5.5 V, −40°C < TA < +85°C 0.1 V
Power-Up Response Time 2 pF at FLTR Pin, 224 mV rms at RFIN 5 µs
100 nF at FLTR Pin, 224 mV rms at RFIN 320 µs
PWDN Bias Current <1 µA
POWER SUPPLIES
Operating Range −40°C < TA < +85°C 2.7 5.5 V
Quiescent Current 0 mV rms at RFIN, PWDN Input LO
Power-Down Current GRM or IRM, 0 mV rms at RFIN, PWDN Input HI <1 µA
SRM, 0 mV rms at RFIN, PWDN Input HI 10 × VS µA
1
Operation at arbitrarily low frequencies is possible; see Ap section. plications
2
Figure 17 and Figure 47 show impedance versus frequency for the MSOP and SOT-23, respectively.
3
Calculated using linear regression.
4
Compensated for output reference temperature drift; see section.
5
SOT-23-6L operates in ground reference mode only.
6
The available output swing, and hence the dynamic range, is altered by both supply voltage and reference mode; see Figure 39 and Figure 40.
7
Supply current is input level dependant; see Figure 16.
1
2
4
5, 6
2.5 GHz
= 5 V 660 mV rms
S
225||1 Ω||pF
= 100 MHz, VS = 5 V 6.5 8.5 V/V rms
RF
3
CW Input, −40°C < TA < +85°C 14 dB
Supply Reference Mode, VS = 3.0 V 1 dB
= 100 MHz, VS = 5 V −50 +150 mV
RF
= 100 MHz, VS = 5 V 300 500 mV
RF
at IREF, VS at SREF VS/7.5 V
S
= 100 MHz, VS = 5 V 590 750 mV
RF
7
Applications
1.1 mA
Rev. C | Page 3 of 24
AD8361
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage V
S
SREF, PWDN 0 V, V
IREF VS − 0.3 V, V
RFIN 1 V rms
Equivalent Power, re 50 Ω 13 dBm
Internal Power Dissipation
1
6-Lead SOT-23 170 mW
8-Lead MSOP 200 mW
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range
(Soldering 60 sec)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
5.5 V
S
S
200 mW
300°C
1
Specification is for the device in free air.
6-Lead SOT-23: θ
8-Lead MSOP: θ
= 230°C/W; θJC = 92°C/W.
JA
= 200°C/W; θJC = 44°C/W.
JA
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 4 of 24
AD8361
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VPOS
1
IREF
RFIN
PWDN
AD8361
2
TOP VIEW
3
(Not to Scale)
4
Figure 4. 8-Lead MSOP
Table 3. Pin Function Descriptions
Pin No.
MSOP
Pin No.
SOT-23 Mnemonic Description
1 6 VPOS Supply Voltage Pin. Operational range 2.7 V to 5.5 V.
2 N/A IREF
3 5 RFIN
4 4 PWDN
5 2 COMM Device Ground Pin.
6 3 FLTR
7 1 VRMS
8 N/A SREF
SREF
8
VRMS
7
6
FLTR
COMM
5
01088-C-004
VRMS
1
AD8361
2
COMM
FLTR
TOP VIEW
(Not to Scale)
3
Figure 5. 6-Lead SOT-23
6
5
4
VPOS
RFIN
PWDN
01088-C-005
Output Reference Control Pin. Internal reference mode enabled when pin is left open; otherwise, this
pin should be tied to VPOS. Do not ground this pin.
Signal Input Pin. Must be driven from an ac-coupled source. The low frequency real input impedance
is 225 Ω.
Power-Down Pin. For the device to operate as a detector, it needs a logical low input (less than
100 mV). When a logic high (greater than V
current goes to nearly zero (ground and internal reference mode less than 1 µA, supply reference
mode V
divided by 100 kΩ).
S
By placing a capacitor between this pin and VPOS, the corner frequency of the modulation filter is
lowered. The on-chip filter is formed with 27 pF||2 kΩ for small input signals.
Output Pin. Near rail-to-rail voltage output with limited current drive capabilities. Expected load
>10 kΩ to ground.
Supply Reference Control Pin. To enable supply reference mode, this pin must be connected to VPOS;
otherwise, it should be connected to COMM (ground).
− 0.5 V) is applied, the device is turned off and the supply