Fixed gain of 20 dB
Operational frequency of 1 MHz to 2.7 GHz
Linear output power up to 4 dBm
Input/output internally matched to 50 Ω
Temperature and power supply stable
Noise figure: 4.2 dB
Power supply: 3 V or 5 V
APPLICATIONS
VCO buffers
General Tx/Rx amplification
Power amplifier predrivers
Low power antenna drivers
GENERAL DESCRIPTION
The AD8354 is a broadband, fixed-gain, linear amplifier that
operates at frequencies from 1 MHz up to 2.7 GHz. It is
intended for use in a wide variety of wireless devices, including
cellular, broadband, CATV, and LMDS/MMDS applications.
By taking advantage of ADI’s high performance, complementary Si
bipolar process, these gain blocks provide excellent stability
over process, temperature, and power supply. This amplifier is
single-ended and internally matched to 50 Ω with a return loss
of greater than 10 dB over the full operating frequency range.
RF Gain Block
AD8354
FUNCTIONAL BLOCK DIAGRAM
BIAS AND VREF
INPT
AD8354
Figure 1.
The noise figure is 4.2 dB at 900 MHz. The reverse isolation
(S
) is −33 dB at 900 MHz.
12
The AD8354 can also operate with a 5 V power supply; in
which case, no external inductor is required. Under these
conditions, the AD8354 delivers 4.88 dBm with 20 dB of gain
at 900 MHz. The dc supply current is 26 mA. At 900 MHz, the
OIP3 is greater than 19 dBm; at 2.7 GHz, the OIP3 is 15 dBm.
The noise figure is 4.4 dB at 900 MHz. The reverse isolation
(S
) is −33 dB.
12
VPOS
VOUT
COM2COM1
02722-001
The AD8354 provides linear output power of nearly 4.3 dBm
with 20 dB of gain at 900 MHz when biased at 3 V and an
external RF choke is connected between the power supply and
the output pin. The dc supply current is 24 mA. At 900 MHz,
the output third-order intercept (OIP3) is greater than 18 dBm;
at 2.7 GHz, the OIP3 is 14 dBm.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The AD8354 is fabricated on ADI’s proprietary, high performance,
25 GHz, Si complementary, bipolar IC process. The AD8354 is
available in a chip scale package that uses an exposed paddle for
excellent thermal impedance and low impedance electrical
connection to ground. It operates over a −40°C to +85°C
temperature range, and an evaluation board is also available.
VS = 3 V, TA = 25°C, 100 nH external inductor between VOUT and VPOS, ZO = 50 Ω, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
OVERALL FUNCTION
Frequency Range 1 2700 MHz
Gain f = 900 MHz 19.5 dB
f = 1.9 GHz 18.6 dB
f = 2.7 GHz 17.1 dB
Delta Gain f = 900 MHz, −40°C ≤ TA ≤ +85°C −0.97 dB
f = 1.9 GHz, −40°C ≤ TA ≤ +85°C −1.05 dB
f = 2.7 GHz, −40°C ≤ TA ≤ +85°C −1.33 dB
Gain Supply Sensitivity VPOS ± 10%, f = 900 MHz 0.54 dB/V
f = 1.9 GHz 0.37 dB/V
f = 2.7 GHz 0.2 dB/V
Reverse Isolation (S12) f = 900 MHz −33.5 dB
f = 1.9 GHz −38 dB
f = 2.7 GHz −32.9 dB
RF INPUT INTERFACE Pin INPT
Input Return Loss f = 900 MHz 24.4 dB
f = 1.9 GHz 23 dB
f = 2.7 GHz 12.7 dB
RF OUTPUT INTERFACE Pin VOUT
Output Compression Point f = 900 MHz, 1 dB compression 4.6 dBm
f = 1.9 GHz 3.7 dBm
f = 2.7 GHz 2.7 dBm
Delta Compression Point f = 900 MHz, −40°C ≤ TA ≤ +85°C 0.7 dB
f = 1.9 GHz, −40°C ≤ TA ≤ +85°C 0.7 dB
f = 2.7 GHz, −40°C ≤ TA ≤ +85°C 0.8 dB
Output Return Loss f = 900 MHz 23.6 dB
f = 1.9 GHz 16.5 dB
f = 2.7 GHz 14.6 dB
f = 1.9 GHz 4.8 dB
f = 2.7 GHz 5.4 dB
POWER INTERFACE Pin VPOS
Supply Voltage 2.7 3 3.3 V
Total Supply Current 16 23 31 mA
Supply Voltage Sensitivity 6.2 mA/V
Temperature Sensitivity −40°C ≤ TA ≤ +85°C 33 μA/°C
Rev. C | Page 3 of 16
AD8354
VS = 5 V, TA = 25°C, no external inductor between VOUT and VPOS, ZO = 50 Ω, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
OVERALL FUNCTION
Frequency Range 1 2700 MHz
Gain f = 900 MHz 19.5 dB
f = 1.9 GHz 18.7 dB
f = 2.7 GHz 17.3 dB
Delta Gain f = 900 MHz, −40°C ≤ TA ≤ +85°C −0.93 dB
f = 1.9 GHz, −40°C ≤ TA ≤ +85°C −0.99 dB
f = 2.7 GHz, −40°C ≤ TA ≤ +85°C −1.21 dB
Gain Supply Sensitivity VPOS ± 10%, f = 900 MHz 0.32 dB/V
f = 1.9 GHz 0.21 dB/V
f = 2.7 GHz 0.08 dB/V
Reverse Isolation (S12) f = 900 MHz −33.5 dB
f = 1.9 GHz −37.6 dB
f = 2.7 GHz −32.9 dB
RF INPUT INTERFACE Pin INPT
Input Return Loss f = 900 MHz 24.4 dB
f = 1.9 GHz 23.9 dB
f = 2.7 GHz 13.5 dB
RF OUTPUT INTERFACE Pin VOUT
Output Compression Point f = 900 MHz 4.8 dBm
f = 1.9 GHz 4.6 dBm
f = 2.7 GHz 3.6 dBm
Delta Compression Point f = 900 MHz, −40°C ≤ TA ≤ +85°C 0.37 dB
f = 1.9 GHz, −40°C ≤ TA ≤ +85°C −0.14 dB
f = 2.7 GHz, −40°C ≤ TA ≤ +85°C −0.05 dB
Output Return Loss f = 900 MHz 23.7 dB
f = 1.9 GHz 22.5 dB
f = 2.7 GHz 17.6 dB
DISTORTION/NOISE
Output Third-Order Intercept f = 900 MHz, ∆f = 50 MHz, PIN = −30 dBm 19.3 dBm
f = 1.9 GHz, ∆f = 50 MHz, PIN = −30 dBm 17.3 dBm
f = 2.7 GHz, ∆f = 50 MHz, PIN = −30 dBm 15.3 dBm
Output Second-Order Intercept f = 900 MHz, ∆f = 1 MHz, PIN = −28 dBm 28.7 dBm
Noise Figure f = 900 MHz 4.4 dB
f = 1.9 GHz 5 dB
f = 2.7 GHz 5.6 dB
POWER INTERFACE Pin VPOS
Supply Voltage 4.5 5 5.5 V
Total Supply Current TA = 27°C 17 25 34 mA
Supply Voltage Sensitivity 4 mA/V
Temperature Sensitivity −40°C ≤ TA ≤ +85°C 28 μA/°C
Rev. C | Page 4 of 16
AD8354
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage, VPOS 5.5 V
Input Power (re: 50 Ω) 10 dBm
Equivalent Voltage 700 mV rms
Internal Power Dissipation
Paddle Not Soldered 325 mW
Paddle Soldered 812 mW
θ
(Paddle Soldered) 80°C/W
JA
θ
(Paddle Not Soldered) 200°C/W
JA
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec) 240°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. C | Page 5 of 16
AD8354
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
COM1
NC
INPT
COM2
1
AD8354
2
TOP VIEW
3
(Not to Scale)
4
8
7
6
5
COM1
VOUT
VPOS
COM2
NC = NO CONNECT
Figure 2. Pin Configuration
02722-041
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 8 COM1 Device Common. Connect to low impedance ground.
2 NC No Connection.
3 INPT RF Input Connection. Must be ac-coupled.
4, 5 COM2 Device Common. Connect to low impedance ground.
6 VPOS Positive Supply Voltage.
7 VOUT RF Output Connection. Must be ac-coupled.
Rev. C | Page 6 of 16
AD8354
TYPICAL PERFORMANCE CHARACTERISTICS
90
60
120
90
60
120
150
180
210
Figure 3. S
25
20
15
GAIN (dB)
10
240
270
vs. Frequency, VS = 3 V, TA = 25°C, 100 MHz ≤ f ≤ 3 GHz
11
GAIN AT 3.3V
GAIN AT 3.0V
GAIN AT 2.7V
300
330
30
0
02722-002
150
180
210
Figure 6. S
25
20
15
GAIN (dB)
10
330
240
270
vs. Frequency, VS = 3 V, TA = 25°C, 100 MHz ≤ f ≤ 3 GHz
Figure 35. Output Power and Gain vs. Input Power, V
15
10
5
(dBm)
0
OUT
P
–5
–10
–15
–30–25–20–15–10–50
Figure 36. Output Power and Gain vs. Input Power, V
–20–15–10–50
PIN(dBm)
= 3 V, TA = 25°C, f = 900 MHz
S
PIN (dBm)
= 5 V, TA = 25°C, f = 900 MHz
S
19
18
17
16
15
14
20
19
18
17
16
15
14
GAIN (dB)
02722-034
GAIN (dB)
02722-035
Rev. C | Page 12 of 16
AD8354
THEORY OF OPERATION
The AD8354 is a 2-stage, feedback amplifier employing both
shunt-series and shunt-shunt feedback. The first stage is
degenerated and resistively loaded and provides approximately
10 dB of gain. The second stage is a PNP-NPN Darlington
output stage, which provides another 10 dB of gain. Seriesshunt feedback from the emitter of the output transistor sets the
input impedance to 50 Ω over a broad frequency range. Shuntshunt feedback from the amplifier output to the input of the
Darlington stage helps to set the output impedance to 50 Ω. The
amplifier can be operated from a 3 V supply by adding a choke
inductor from the amplifier output to VPOS. Without this
choke inductor, operation from a 5 V supply is also possible.
BASIC CONNECTIONS
The AD8354 RF gain block is a fixed gain amplifier with singleended input and output ports whose impedances are nominally
equal to 50 Ω over the frequency range 1 MHz to 2.7 GHz.
Consequently, it can be directly inserted into a 50 Ω system
with no impedance matching circuitry required. The input and
output impedances are sufficiently stable vs. variations in
temperature and supply voltage that no impedance matching
compensation is required. A complete set of scattering
parameters is available at
The input pin (INPT) is connected directly to the base of the
first amplifier stage, which is internally biased to approximately 1 V;
therefore, a dc blocking capacitor should be connected between the
source that drives the AD8354 and the input pin, INPT.
www.analog.com.
It is critical to supply very low inductance ground connections
to the ground pins (Pin 1, Pin 4, Pin 5, and Pin 8) as well as to
the backside exposed paddle. This ensures stable operation.
The AD8354 is designed to operate over a wide supply voltage
range, from 2.7 V to 5.5 V. The output of the part, VOUT, is
taken directly from the collector of the output amplifier stage.
This node is internally biased to approximately 3.2 V when the
supply voltage is 5 V. Consequently, a dc blocking capacitor
should be connected between the output pin, VOUT, and the
load that it drives. The value of this capacitor is not critical, but
it should be 100 pF or larger.
When the supply voltage is 3 V, it is recommended that an
external RF choke be connected between the supply voltage
and the output pin, VOUT. This increases the dc voltage applied
to the collector of the output amplifier stage, which improves
performance of the AD8354 to be very similar to the performance
produced when 5 V is used for the supply voltage. The inductance
of the RF choke should be approximately 100 nH, and care
should be taken to ensure that the lowest series self-resonant
frequency of this choke is well above the maximum frequency
of operation for the AD8354.
Bypass the supply voltage input, VPOS, using a large value
capacitance (approximately 0.47 μF or larger) and a smaller,
high frequency bypass capacitor (approximately 100 pF)
physically located close to the VPOS pin.
The recommended connections and components are shown in
Figure 40.
Rev. C | Page 13 of 16
AD8354
2
2
2
2
APPLICATIONS
The AD8354 RF gain block can be used as a general-purpose,
fixed gain amplifier in a wide variety of applications, such as a
driver for a transmitter power amplifier (see
Figure 37). Its
excellent reverse isolation also makes this amplifier suitable for
use as a local oscillator buffer amplifier that would drive the
local oscillator port of an upconverter or downconverter mixer
(see
Figure 38).
AD8354
HIGH POWER
AMPLIFIER
02722-036
Figure 37. AD8354 as a Driver Amplifier
MIXER
AD8354
LOCAL OSCILLATOR
02722-037
Figure 38. AD8354 as a LO Driver Amplifier
LOW FREQUENCY APPLICATIONS BELOW 100 MHz
The AD8354 RF gain block can be used below 100 MHz. To
accomplish this, the series dc blocking capacitors, C1 and C2,
need to be changed to a higher value that is appropriate for the
desired frequency. C1 and C2 were changed to 0.1 μF to accomplish
the sweeps in
19.5
19.0
18.5
18.0
17.5
17.0
16.5
Figure 39.
1.5
dB-S21
1.0
0.5
0.0
CH 1: START 300.000kHzSTOP 100.000MHz
Figure 39. Low Frequency Application from
300 kHz to 100 MHz at 5 V VPOS, −12 dBm Input Power
Mkr 1:19.40dB97.638034MHz
1
02722-042
Rev. C | Page 14 of 16
AD8354
T
EVALUATION BOARD
Figure 40 shows the schematic of the AD8354 evaluation board.
Note that L1 is shown as an optional component that is used to
obtain maximum gain only when V
by a single supply in the 2.7 V to 5.5 V range. The power supply
is decoupled by a 0.47 μF and a 100 pF capacitor.
AD8354
COM1
1
NC
2
C1
1000pF
INPU
INPT
3
4
NC = NO CONNECT
Figure 40. Evaluation Board Schematic
Table 5. Evaluation Board Configuration Options
Component Function
C1, C2 AC coupling capacitors.
C3 High frequency bypass capacitor.
C4 Low frequency bypass capacitor.
L1
Optional RF choke, used to increase
current through output stage when
= 3 V. Not recommended for use
V
P
when V
= 5 V.
P
= 3 V. The board is powered
P
COM1
8
VOUT
VPOS
COM2COM2
7
6
5
1000pF
L1
C3
100pFC40.47μF
C2
OUTPUT
Default
Value
1000 pF,
0603
100 pF,
0603
0.47 μF,
0603
100 nH,
0603
02722-039
Figure 41. Silkscreen Top
02722-038
02722-040
Figure 42. Component Side
Rev. C | Page 15 of 16
AD8354
R
OUTLINE DIMENSIONS
1.89
1.74
1.59
58
BOTTOM VIEW
EXPOSED PAD
41
*
0.55
0.40
0.30
0.15
0.10
0.05
0.25
0.20
0.15
PIN 1
INDICATO
1.00
0.85
0.80
SEATING
1.95
1.75
1.55
PLANE
3.25
3.00
2.75
0.60
0.45
0.30
0.50 BSC
0.05 MAX
0.02 NOM
12° MAX
TOP VIEW
2.95
2.75
2.55
0.30
0.23
0.18
2.25
2.00
1.75
0.80 MAX
0.65 TYP
0.20 REF
Figure 43. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
2 mm × 3 mm Body, Very Thin, Dual Lead
CP-8-1
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8354ACP-R2 −40°C to +85°C 8-Lead LFCSP_VD, 7" Tape and Reel CP-8-1 JC
AD8354ACP-REEL7 −40°C to +85°C 8-Lead LFCSP_VD, 7" Tape and Reel CP-8-1 JC
AD8354ACPZ-REEL71 −40°C to +85°C 8-Lead LFCSP_VD, 7" Tape and Reel CP-8-1 0G
AD8354-EVAL Evaluation Board