Analog Devices AD8351 Service Manual

Low Distortion

Differential RF/IF Amplifier

AD8351

FEATURES
–3 dB Bandwidth of 2.2 GHz for A

= 12 dB

V

Single Resistor Programmable Gain

0 dB ≤ A

≤ 26 dB

V

Differential Interface
Low Noise Input Stage 2.7 nV/√Hz @ A

= 10 dB

V

Low Harmonic Distortion
–79 dBc Second @ 70 MHz
–81 dBc Third @ 70 MHz
OIP3 of 31 dBm @ 70 MHz
Single-Supply Operation: 3 V to 5.5 V
Low Power Dissipation: 28 mA @ 5 V
Adjustable Output Common-Mode Voltage
Fast Settling and Overdrive Recovery
Slew Rate of 13,000 V/␮s
Power-Down Capability
10-Lead MSOP Package

APPLICATIONS
Differential ADC Drivers
Single-Ended-to-Differential Conversion
IF Sampling Receivers
RF/IF Gain Blocks
SAW Filter Interfacing

FUNCTIONAL BLOCK DIAGRAM

AD8351

PWUP

RGP1

INHI

INLO

RGP2

0

AD8351 WITH 10 dB OF

–10

GAIN DRIVING THE
AD6645 (RL = 1k⍀)

–20

ANALOG INPUT: 70MHz
ENCODE : 80MHz

–30

SNR : 69.1dB
FUND : –1.1dBFS

–40

HD2 : –78.5dBc
HD3 : –80.7dBc

–50

THD : –75.9dBc
SFDR : 78.2dBc

–60

–70

–80

–90

–100

–110

–120

–130

051015 20 25 30 35

+

BIAS CELL

INHI

RG

200⍀

INLO

AD8351

AD8351

100nF

100nF

VOCM

VPOS

OPHI

OPLO

COMM

25⍀

25⍀

2

AD6645

14-BIT ADC

3

GENERAL DESCRIPTION

The AD8351 is a low cost differential amplifier useful in RF and
IF applications up to 2.2 GHz. The voltage gain can be set from
unity to 26 dB using a single external gain resistor. The AD8351
provides a nominal 150 Ω differential output impedance. The
excellent distortion performance and low noise characteristics of
this device allow for a wide range of applications.

The AD8351 is designed to satisfy the demanding performance
requirements of communications transceiver applications. The
device can be used as a general-purpose gain block, an ADC driver,

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

and a high speed data interface driver, among other functions. The
AD8351 can also be used as a single-ended-to-differential
amplifier with similar distortion products as in the differential
configuration. The exceptionally good distortion performance
makes the AD8351 an ideal solution for 12-bit and 14-bit IF
sampling receiver designs.

Fabricated in ADI’s high speed XFCB process, the AD8351
has high bandwidth that provides high frequency performance
and low distortion. The quiescent current of the AD8351 is 28 mA
typically. The AD8351 amplifier comes in a compact 10-lead
MSOP package and will operate over the temperature range
of –40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

(VS = 5 V, RL = 150 , RG = 110  (AV = 10 dB), f = 70 MHz, T = 25C, parameters

AD8351–SPECIFICATIONS

specified differentially, unless otherwise noted .)

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth GAIN = 6 dB, V

GAIN = 12 dB, V
GAIN = 18 dB, V

Bandwidth for 0.1 dB Flatness 0 dB ≤ GAIN ≤ 20 dB, V
Bandwidth for 0.2 dB Flatness 0 dB ≤ GAIN ≤ 20 dB, V
Gain Accuracy Using 1% Resistor for R
Gain Supply Sensitivity V

± 5% 0.08 dB/V

S

≤ 1.0 V p-p 3,000 MHz

OUT

≤ 1.0 V p-p 2,200 MHz

OUT

≤ 1.0 V p-p 600 MHz

OUT

≤ 1.0 V p-p 200 MHz

OUT

≤ 1.0 V p-p 400 MHz

OUT

, 0 dB ≤ AV ≤ 20 dB ± 1dB

G

Gain Temperature Sensitivity –40°C to +85°C 3.9 mdB/°C
Slew Rate R

= 1 kΩ, V

L

R

= 150 Ω, VS = 2 V Step 7,500 V/␮s

L

= 2 V Step 13,000 V/␮s

OUT

Settling Time 1 V Step to 1% <3 ns
Overdrive Recovery Time V

= 4 V to 0 V Step, V

IN

≤ ± 10 mV <2 ns

OUT

Reverse Isolation (S12) –67 dB

INPUT/OUTPUT CHARACTERISTICS

Input Common-Mode

Voltage Adjustment Range 1.2 to 3.8 V

Max Output Voltage Swing 1 dB Compressed 4.75 V p-p
Output Common-Mode Offset 40 mV

Output Common-Mode Drift –40°C to +85°C 0.24 mV/°C
Output Differential Offset Voltage

20 mV

Output Differential Offset Drift –40°C to +85°C 0.13 mV/°C
Input Bias Current ±15 ␮A
Input Resistance
Input Capacitance

1

1

5kΩ

0.8 pF
CMRR 43 dB
Output Resistance
Output Capacitance

1

1

150 Ω

0.8 pF

POWER INTERFACE

Supply Voltage 3 5.5 V
PWUP Threshold 1.3 V
PWUP Input Bias Current PWUP at 5 V 100 ␮A

PWUP at 0 V 25 ␮A

Quiescent Current 28 32 mA

REV. B–2–

AD8351

Parameter Conditions Min Typ Max Unit

NOISE/DISTORTION

10 MHz

Second/Third Harmonic

Distortion

Third-Order IMD R

Output Third-Order Intercept f1 = 9.5 MHz, f2 = 10.5 MHz 33 dBm
Noise Spectral Density (RTI) 2.65 nV/√Hz
1 dB Compression Point 13.5 dBm

70 MHz

Second/Third Harmonic

Distortion

Third-Order IMD R

Output Third-Order Intercept f1 = 69.5 MHz, f2 = 70.5 MHz 31 dBm
Noise Spectral Density (RTI) 2.70 nV/√Hz
1 dB Compression Point 13.3 dBm

140 MHz

Second/Third Harmonic

Distortion

Third-Order IMD R

Output Third-Order Intercept f1 = 139.5 MHz, f2 = 140.5 MHz 29 dBm
Noise Spectral Density (RTI) 2.75 nV/√Hz
1 dB Compression Point 13 dBm

240 MHz

Second/Third Harmonic

Distortion

Third-Order IMD R

Output Third-Order Intercept f1 = 239.5 MHz, f2 = 240.5 MHz 27 dBm
Noise Spectral Density (RTI) 2.90 nV/√Hz
1 dB Compression Point 13 dBm

NOTES

1

Values are specified differentially.

2

See Applications section for single-ended-to-differential performance.

Specifications subject to change without notice.

2

2

2

2

RL = 1 kΩ, V
R

= 150 Ω, V

L

= 1 kΩ, f1 = 9.5 MHz, f2 = 10.5 MHz,

L

V

= 2 V p-p Composite –90 dBc

OUT

R

= 150 Ω, f1 = 9.5 MHz, f2 = 10.5 MHz,

L

V

= 2 V p-p Composite –70 dBc

OUT

RL = 1 kΩ, V
R

= 150 Ω, V

L

= 1 kΩ, f1 = 69.5 MHz, f2 = 70.5 MHz,

L

V

= 2 V p-p Composite –85 dBc

OUT

R

= 150 Ω, f1 = 69.5 MHz, f2 = 70.5 MHz,

L

V

= 2 V p-p Composite –69 dBc

OUT

RL = 1 kΩ, V
R

= 150 Ω, V

L

= 1 kΩ, f1 = 139.5 MHz, f2 = 140.5 MHz,

L

= 2 V p-p Composite –79 dBc

V

OUT

R

= 150 Ω, f1 = 139.5 MHz, f2 = 140.5 MHz,

L

= 2 V p-p Composite –67 dBc

V

OUT

RL = 1 kΩ, V
R

= 150 Ω, V

L

= 1 kΩ, f1 = 239.5 MHz, f2 = 240.5 MHz,

L

= 2 V p-p Composite –76 dBc

V

OUT

= 2 V p-p –95/–93 dBc

OUT

= 2 V p-p –86/–71 dBc

OUT

= 2 V p-p –79/–81 dBc

OUT

= 2 V p-p –65/–66 dBc

OUT

= 2 V p-p –69/–69 dBc

OUT

= 2 V p-p –54/–53 dBc

OUT

= 2 V p-p –60/–66 dBc

OUT

= 2 V p-p –46/–50 dBc

OUT

RL = 150 Ω, f1 = 239.5 MHz, f2 = 240.5 MHz,
V

= 2 V p-p Composite –62 dBc

OUT

REV. B

–3–

AD8351

ABSOLUTE MAXIMUM RATINGS*

PIN CONFIGURATION

Supply Voltage VPOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 V

PWUP Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VPOS

Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 320 mW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C/W

␪

JA

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125°C

Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

PWUP

RGP1

INHI

INLO

RGP2

1

2

AD8351

3

TOP VIEW

(Not to Scale)

4

5

10

9

8

7

6

VOCM

VPOS

OPHI

OPLO

COMM

Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model Temp. Range Package Description Package Option Branding

AD8351ARM –40°C to +85°C 10-Lead MSOP, 7" Tape and Reel RM-10 JDA
AD8351ARM-R2 –40°C to +85°C 10-Lead MSOP, 7" Tape and Reel RM-10 JDA
AD8351ARM-REEL7 –40°C to +85°C 10-Lead MSOP, 7" Tape and Reel RM-10 JDA
AD8351-EVAL Evaluation Board

PIN FUNCTION DESCRIPTIONS

Pin No. Name Function

1PWUP Apply a positive voltage (1.3 V ≤ V

≤ VPOS ) to activate device.

PWUP

2 RGP1 Gain Resistor Input 1.
3 INHI Balanced Differential Input. Biased to midsupply, typically ac-coupled
4 INLO Balanced Differential Input. Biased to midsupply, typically ac-coupled.
5 RGP2 Gain Resistor Input 2.
6 COMM Device Common. Connect to low impedance ground.
7 OPLO Balanced Differential Output. Biased to VOCM, typically ac-coupled.
8 OPHI Balanced Differential Output. Biased to VOCM, typically ac-coupled.
9 VPOS Positive Supply Voltage. 3 V to 5.5 V.
10 VOCM Voltage applied to this pin sets the common-mode voltage at both the input and output.

Typically decoupled to ground with a 0.1 µF capacitor.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8351 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

–4–

REV. B

(VS = 5 V, T = 25ⴗC, unless otherwise noted.)

FREQUENCY (MHz)

30

1 10000

GAIN (dB)

5

10 100 1000

25

20

15

10

0

RG = 10⍀

RG = 50⍀

RG = 200⍀

20

15

10

RG = 20⍀

RG = 80⍀

Typical Performance Characteristics–

AD8351

GAIN (dB)

5

0

–5

1 10000

TPC 1. Gain vs. Frequency for a 150 Ω Differential Load

= 6 dB, 12 dB, and 18 dB)

(A

V

35

30

25

20

15

10

GAIN (dB)

5

0

–5

–10

10 10k

TPC 2. Gain vs. Gain Resistor, RG (f = 100 MHz,

= 150 Ω, 1 kΩ, and Open)

R

L

10.75

10.50

10.25

10.00

= 1k⍀) (dB)

L

9.75

GAIN (R

9.50

9.25

TPC 3. Gain vs. Temperature at 100 MHz (AV = 10 dB)

–30 50

–50 110

RG = 200⍀

10 100 1000

FREQUENCY (MHz)

RL = OPEN

R

= 150⍀

L

= 1k⍀

R

L

100 1k

RG (⍀)

–10 10 30 70 90

TEMPERATURE (ⴗC)

10.50

10.25

10.00

9.75

9.50

9.25

9.00

GAIN (RL = 150⍀) (dB)

TPC 4. Gain vs. Frequency for a 1 kΩ Differential Load

= 10 dB, 18 dB, and 26 dB)

(A

V

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

–0.1
–0.2
–0.3

GAIN FLATNESS (dB)

–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0

RL = 150⍀

0

RL = 1k⍀

1 1000

10 100

FREQUENCY (MHz)

RL = 1k⍀

RL = 150⍀

TPC 5. Gain Flatness vs. Frequency
(R

= 150 Ω and 1 kΩ, AV =10 dB)

L

0

–10

–20

–30

–40

–50

ISOLATION (dB)

–60

–70

–80

–90

0 1000

100 200 300 400 500 600 700 800 900

FREQUENCY (MHz)

TPC 6. Isolation vs. Frequency (AV = 10 dB)

REV. B

–5–

AD8351

–30

–40

–50

–60

–70

–80

–90

HARMONIC DISTORTION (VPOS = 5V) (dBc)

–100

0 250

HD3

HD2

HD2

DIFFERENTIAL INPUT

25 50 75 100 125 150 175 200 225

FREQUENCY (MHz)

HD3

–45

–55

–65

–75

–85

–95

–105

HARMONIC DISTORTION (VPOS = 3V) (dBc)

–115

TPC 7. Harmonic Distortion vs. Frequency for 2 V p-p

= 1 kΩ (AV = 10 dB, at 3 V and 5 V Supplies)

into R

L

0

–10

–20

–30

–40

–50

–60

–70

–80

HARMONIC DISTORTION (VPOS = 5V) (dBc)

–90

HD3

25 50 75 100 125 150 175 200 225

0 250

HD3

HD2

DIFFERENTIAL INPUT

HD2

FREQUENCY (MHz)

–20

–30

–40

–50

–60

–70

–80

–90

–100

HARMONIC DISTORTION (VPOS = 3V) (dBc)

–110

TPC 8. Harmonic Distortion vs. Frequency for 2 V p-p into
RL = 150 Ω (AV = 10 dB, at 3 V and 5 V Supplies)

–50

–55

SINGLE-ENDED INPUT

–60

–65

–70

–75

–80

–85

HARMONIC DISTORTION (dBc)

–90

–95

–100

HD3

20 30 50 70 90

10 40 60 80

0 100

HD2

FREQUENCY (MHz)

HD3

TPC 10. Harmonic Distortion vs. Frequency for 2 V p-p

= 1 kΩ Using Single-Ended Input (AV = 10 dB)

into R

L

–50

–55

–60

–65

–70

–75

–80

–85

HARMONIC DISTORTION (dBc)

–90

–95

–100

SINGLE-ENDED INPUT

HD3

HD2

0 100

20 30 50 70 90

10 40 60 80

FREQUENCY (MHz)

TPC 11. Harmonic Distortion vs. Frequency for 2 V p-p

= 150 Ω Using Single-Ended Input (AV = 10 dB)

into R

L

3.00

2.95

2.90

2.85

2.80

2.75

2.70

2.65

2.60

NOISE SPECTRAL DENSITY (nV/ Hz)

2.55

2.50
0 250

50 100 150 200

FREQUENCY (MHz)

TPC 9. Noise Spectral Density (RTI) vs. Frequency

= 150 Ω, 5 V Supply, AV = 10 dB)

(R

L

–6–

3.00

2.95

2.90

2.85

2.80

2.75

2.70

2.65

2.60

NOISE SPECTRAL DENSITY (nV/ Hz)

2.55

2.50
0 250

50 100 150 200

FREQUENCY (MHz)

TPC 12. Noise Spectral Density (RTI) vs. Frequency
(RL = 150 Ω, 3 V Supply, AV = 10 dB)

REV. B

AD8351

16

14

12

10

8

6

4

OUTPUT 1dB COMPRESSION (dBm)

2

0

0 250

RL = 150
VPOS = 5V

R

= 1k

L

R

= 150

L

VPOS = 3V

R

= 1k

L

25 50 75 100 125 150 175 200 225

FREQUENCY (MHz)

TPC 13. Output Compression Point, P1 dB, vs. Frequency
(R

= 150 Ω and 1 kΩ, AV = 10 dB, at 3 V and 5 V Supplies)

L

16

14

12

10

8

6

VPOS = 5V

VPOS = 3V

–70

–75

–80

–85

THIRD-ORDER IMD (dBc)

–90

–95

0 250

25 50 75 100 125 150 175 200 225

FREQUENCY (MHz)

TPC 16. Third-Order Intermodulation Distortion vs.
Frequency for a 2 V p-p Composite Signal into R

= 1 k

L

(AV = 10 dB, at 5 V Supplies)

–50

–55

–60

–65

Ω

4

OUTPUT 1dB COMPRESSION (dBm)

2

0

0 1000100

GAIN RESISTOR ()

TPC 14. Output Compression Point, P1 dB, vs. RG (f =
100 MHz, RL = 150 Ω, AV = 10 dB, at 3 V and 5 V Supplies)

13.29

13.31

13.33

13.32

13.34

13.35

13.36

13.37

13.38

13.39

13.40

13.41

13.30

OUTPUT 1dB COMPRESSION (dB)

THIRD-ORDER IMD (dBc)

–70

–75

0 250

25 50 75 100 125 150 175 200 225

FREQUENCY (MHz)

TPC 17. Third-Order Intermodulation Distortion
vs. Frequency for a 2 V p-p Composite Signal into

= 150 Ω (AV = 10 dB, at 5 V Supplies)

R

L

–68.0 –68.2 –68.4 –68.6

THIRD-ORDER INTERMODULATION DISTORTION (dBc)

–68.6 –68.8 –69.0 –69.2 –69.4 –69.6 –69.8

TPC 15. Output Compression Point Distribution
(f = 70 MHz, RL = 150 Ω, AV = 10 dB)

REV. B

TPC 18. Third-Order Intermodulation Distortion
Distribution (f = 70 MHz, RL = 150 Ω, AV = 10 dB)

–7–

AD8351

4000

3500

3000

2500

2000

1500

1000

IMPEDANCE MAGNITUDE ()

500

0

10 1000100

FREQUENCY (MHz)

TPC 19. Input Impedance vs. Frequency

160

150

140

130

120

IMPEDANCE MAGNITUDE ()

110

0

–25

–50

PHASE (deg)

–75

–100

30

25

20

15

10

IMPEDANCE PHASE (deg)

5

WITH

50

10MHz

500MHz

3GHz

3GHz

10MHz

500MHz

TERMINATIONS

WITHOUT

TERMINATIONS

TPC 22. Input Reflection Coefficient vs. Frequency
(RS = RL = 100 Ω with and without 50 Ω Terminations)

500MHz

10MHz

3GHz

100

0 1000100

FREQUENCY (MHz)

0

TPC 20. Output Impedance vs. Frequency

0

–2

–4

–6

–8

–10

PHASE (deg)

–12

–14

–16

–18

0 250

25 50 75 100 125 150 175 200 225

FREQUENCY (MHz)

20
19
18
17
16
15
14
13
12
11
10
9
8
7

GROUP DELAY (ps)

6
5
4
3
2
1
0

TPC 21. Phase and Group Delay (AV = 10 dB, at 5 V Supplies)

TPC 23. Output Reflection Coefficient vs.
Frequency (R

80

70

60

RL = 1k

50

CMRR (dB)

40

30

20

0 1000

= RL = 100 Ω)

S

= 150

R

L

FREQUENCY (MHz)

10010

TPC 24. Common-Mode Rejection Ratio,
CMRR (RS = 100 Ω)

–8–

REV. B

0.6

TIME (ns)

0

VO LTAGE (V )

0.75

0.25

–0.50

–1.00

1.00

0.50

0

–0.25

–0.75

4.03.53.02.52.01.51.00.5

0.4

0.2

0

VOLTA G E ( V )

–0.2

–0.4

–0.6

16 17 18 19 20 21 22 23 24

15 25

0pF

2pF

5pF

10pF

TIME (ns)

TPC 25. Transient Response under Capacitive
Loading (RL = 150 Ω, CL = 0 pF, 2 pF, 5 pF, 10 pF)

AD8351

TPC 28. Large Signal Transient Response for a
1 V p-p Output Step (A

= 10 dB, RIP = 25 Ω)

V

5.0

4.5

4.0

3.5

3.0

2.5

2.0

OUTPUT (V)

1.5

1.0

0.5

0

0

510152025303540

TIME (ns)

TPC 26. 2⫻ Output Overdrive Recovery (RL = 150 Ω, AV = 10 dB)

3

2

1

V

0

VO LTAGE (V )

–1

V

OUT

IN

5

4

3

2

1

0

–1

SETTLING (%)

–2

–3

–4

–5

015

36912

TIME (ns)

TPC 29. 1% Settling Time for a 2 V p-p Step
(AV = 10 dB, RL = 150 Ω)

–2

–3

050

51015202530354045

TIME (ns)

TPC 27. Overdrive Recovery Using Sinusoidal Input
Waveform R

REV. B

= 150 Ω (AV = 10 dB, at 5 V Supplies)

L

–9–

AD8351

BASIC CONCEPTS

Differential signaling is used in high performance signal chains,
where distortion performance, signal-to-noise ratio, and low power
consumption is critical. Differential circuits inherently provide
improved common-mode rejection and harmonic distortion perfor­mance as well as better immunity to interference and ground noise.

VOCM

VPOS

OPHI

OPLO

COMM

10

9

8

7

6

A

R

L

2A

A

BALANCED

SOURCE

1

PWUP

RGP1

2

INHI

3

R

G

INLO

4

RGP2

5

Figure 1. Differential Circuit Representation

Figure 1 illustrates the expected input and output waveforms for
a typical application. Usually the applied input waveform will be
a balanced differential drive, where the signal applied to the INHI
and INLO pins are equal in amplitude and differ in phase by 180°.
In some applications, baluns may be used to transform a single­ended drive signal to a differential signal. The AD8351 may also be
used to transform a single-ended signal to a differential signal.

GAIN ADJUSTMENT

The differential gain of the AD8351 is set using a single external
resistor, R

, which is connected between Pins 2 and 5. The gain

G

can be set to any value between 0 dB and 26 dB using the resistor
values specified in TPC 2, with common gain values provided in
Table I. The board traces used to connect the external gain resis­tor should be balanced and as short as possible to help prevent
noise pickup and to ensure balanced gain and stability. The low
frequency voltage gain of the AD8351 can be modeled as

RR R R

×

A

=

V

×× + ×+ +

RR R RR R

GL G LF G

LG F L

46 19539

..

+××

56 92

..

()

()

V

OUT

=

×+

()

V

IN

where: RF is 350 Ω (internal).

R

is the single-ended load resistance.

L

R

is the gain setting resistor.

G

Table I. Gain Resistor Selection for Common Gain Values
(Load Resistance Is Specified as Single-Ended)

Gain, A

V

RG (RL = 75 )R

(RL = 500 )

G

0 dB 680 Ω 2 kΩ
6 dB 200 Ω 470 Ω
10 dB 100 Ω 200 Ω
20 dB 22 Ω 43 Ω

COMMON-MODE ADJUSTMENT

The output common-mode voltage level is the dc offset voltage
present at each of the differential outputs. The ac signals are of
equal amplitude with a 180° phase difference but are centered
at the same common-mode voltage level. The common-mode
output voltage level can be adjusted from 1.2 V to 3.8 V by
driving the desired voltage level into the VOCM pin, as illus­trated in Figure 2.

V

S

0.1F

BALANCED

SOURCE

1

PWUP

RGP1

2

INHI

3

R

G

INLO

4

RGP2

5

VOCM

VPOS

OPHI

OPLO

COMM

10

9

8

R

7

6

L

C

DECL

0.1F

V

OCM

1.2V
TO

3.8V

Figure 2. Common-Mode Adjustment

INPUT AND OUTPUT MATCHING

The AD8351 provides a moderately high differential input
impedance of 5 kΩ. In practical applications, the input of the
AD8351 will be terminated to a lower impedance to provide an
impedance match to the driving source, as depicted in Figure 3.
The terminating resistor, R

, should be as close as possible to

T

the input pins in order to minimize reflections due to imped­ance mismatch. The 150 Ω output impedance may need to be
transformed to provide the desired output match to a given
load. Matching components can be calculated using a Smith
Chart or by using a resonant approach to determine the match­ing network that results in a complex conjugate match. The
input and output impedances and reflection coefficients are
provided in TPCs 19, 20, 22, and 23. For additional informa­tion on reactive matching to differential sources and loads, refer
to the Applications section of the AD8350 data sheet.

Figure 3 illustrates a SAW (surface acoustic wave) filter inter­face. Many SAW filters are inherently differential, allowing for a
low loss output match. In this example, the SAW filter requires
a 50 Ω source impedance in order to provide the desired center
frequency and Q. The series L shunt C output network provides
a 150 Ω to 50 Ω impedance transformation at the desired frequency
of operation. The impedance transformation is illustrated on a Smith
Chart in Figure 4.

It is possible to drive a single-ended SAW filter simply by con­necting the unused output to ground using the appropriate
terminating resistance. The overall gain of the system will be
reduced by 6 dB due to the fact that only half of the signal will
be available to the input of the SAW filter.

BALANCED

SOURCE

VPOS

R

T

RS = R

R

T

0.1F

R

AD8351

0.1F

G

T

R

S

R

S

0.1F

150

0.1F

C
8pF

L

S

27nF

P

L

S

27nF

190MHz SAW

50

Figure 3. Example of Differential SAW Filter Interface (fC = 190 MHz)

–10–

REV. B

AD8351

50

25

10

50 150

SERIES L

25

10

100

SHUNT C

100

50

200

500

200

500

0

7

6

5

4

(k)

F

R

3

2

1

0

0 1000

RL = 150

RL = 1000

RL = 500

100

RG ()

Figure 6b. Feedback Resistor Selection

Figure 4. Smith Chart Representation of SAW
Filter Output Matching Network

50

50

0.1F

0.1F

25

R

G

AD8351

0.1F

R

0.1F

R

F

L

Figure 5. Single-Ended Application

SINGLE-ENDED-TO-DIFFERENTIAL OPERATION

The AD8351 can easily be configured as a single-ended-to­differential gain block, as illustrated in Figure 5. The input signal
is ac-coupled and applied to the INHI input. The unused input is
ac-coupled to ground. The values of C1 through C4 should be
selected such that their reactances are negligible at the desired
frequency of operation. To balance the outputs, an external feed­back resistor, R

, is required. To select the gain resistor and the

F

feedback resistor, refer to Figures 6a and 6b. From Figure 6a,
select an R
from Figure 6b an R

for the required dB gain at a given load. Next, select

G

resistor for the selected RG and load.

F

Even though the differential balance is not perfect under these
conditions, the distortion performance is still impressive. TPCs 10
and 11 show the second and third harmonic distortion perfor­mance when driving the input of the AD8351 using a single-ended
50 Ω source.

35

30

R

= 1000

= 150

R

L

L

RL = 500

100

RG ()

25

20

15

GAIN (dB)

10

5

0

0 1000

ADC DRIVING

The circuit in Figure 7 represents a simplified front end of the
AD8351 driving the AD6645, which is a 14-bit, 105 MSPS A/D
converter. For optimum performance, the AD6645 and the
AD8351 are driven differentially. The resistors R1 and R2 present
a 50 Ω differential input impedance to the source with R3 and R4
providing isolation from the A/D input. The gain setting resistor
for the AD8351 is R

. The AD6645 presents a 1 kΩ differential

G

load to the AD8351 and requires a 2.2 V p-p differential signal
between AIN and AIN for a full-scale output. This AD8351
circuit then provides the gain, isolation, and source matching for
the AD6645. The AD8351 also provides a balanced input, not
provided by the balun, to the AD6645, which is essential for
second-order cancellation. The signal generator is bipolar,
centered around ground. Connecting the VOCM pin (10) of the
AD8351 to the VREF pin of the AD6645 sets the common-mode
output voltage of the AD8351 at 2.4 V. This voltage is bypassed
with a 0.1 µF capacitor. Increasing the gain of the AD8351 will
increase the system noise and thus decrease the SNR but will
not significantly affect the distortion. The circuit in Figure 7 can
provide SFDR performance of better than –90 dBc with a 10 MHz
input and –80 dBc with a 70 MHz input at a gain of 10 dB.

100nF

BALANCE

50

SOURCE

25

25

100nF

R

INLO

INHI

G

OPHI

AD8351

VOCM

OPLO

25

25

AIN

AD6645

AIN

VREF

DIGITAL

OUT

Figure 7. ADC Driving Application Using Differential Input

The circuit of Figure 8 represents a single-ended input to differ­ential output configuration of the AD8351 driving the AD6645.
In this case, R1 provides the input impedance. R
setting resistor. The resistor R

is required to balance the output

F

is the gain

G

voltages required for second-order cancellation by the AD6645
and can be selected using a chart. (See the Single-Ended-to­Differential Operation section.) The circuit depicted in Figure 8
can provide SFDR performance of better than –90 dBc with a
10 MHz input and –77 dBc with a 70 MHz input.

REV. B

Figure 6a. Gain Selection

–11–

AD8351

R

F

SINGLE-

ENDED

50

SOURCE

R1
50

25

100nF

100nF

R

INLO

INHI

G

OPHI

AD8351

VOCM

Figure 8. ADC Driving Application Using Single-Ended Input

ANALOG MULTIPLEXING

The AD8351 can be used as an analog multiplexer in applications
where it is desirable to select multiple high speed signals. The
isolation of each device when in a disabled state (PWUP pin pulled
low) is about 60 dBc for the maximum input level of 0.5 V p-p out
to 100 MHz. The low output noise spectral density allows for a
simple implementation as depicted in Figure 9. The PWUP inter­face can be easily driven using most standard logic interfaces. By
using an N-bit digital interface, up to N devices can be controlled.
Output loading effects and noise need to be considered when using
a large number of input signal paths. Each disabled AD8351 pre­sents approximately a 700 Ω load in parallel with the 150 Ω output
source impedance of the enabled device. As the load increases due
to the addition of N devices, the distortion performance will degrade
due to the heavier loading. Distortion better than –70 dBc can be
achieved with four devices muxed into a 1 kΩ load for signal fre­quencies up to 70 MHz.

BIT 1

PWUP

SIGNAL

INPUT 1

INHI

RGP1

R

G

RGP2

INLO

OPHI

AD8351

OPLO

OPLO

25

25

100nF

AIN

AD6645

AIN

N-BIT
DIGITAL
INTERFACE

VREF

DIGITAL

OUT

I/O CAPACITIVE LOADING

Input or output direct capacitive loading greater than a few pico­farads can result in excessive peaking and/or oscillation outside
the pass band. This results from the package and bond wire induc­tance resonating in parallel with the input/output capacitance of
the device and the associated coupling that results internally
through the ground inductance. For low resistive load or source
resistance, the effective Q is lower, and higher relative capaci­tance termination(s) can be allowed before oscillation or excessive
peaking occurs. These effects can be eliminated by adding series
input resistors (R
resistors (R

) for high source capacitance, or series output

IP

) for high load capacitance. Generally less than

OP

25 Ω is all that is required for I/O capacitive loading greater than
~2 pF. The higher the C, the smaller the R parasitic suppression
resistor required. In addition, R

also helps to reduce low gain

IP

in-band peaking, especially for light resistive loads.

C

STRAY

R

IP

R

AD8351

G

R

OP

C

L

R

L

1k

C

STRAY

R

IP

R

OP

C

L

Figure 10. Input and Output Parasitic Suppression
Resistors, R

and ROP, Used to Suppress

IP

Capacitive Loading Effects

Due to package parasitic capacitance on the RG ports, high R

G

values (low gain) cause high ac-peaking inside the pass band,
resulting in poor settling in the time domain. As an example,
when driving a 1 kΩ load, using 25 Ω for R
by ~7 dB for R

equal to 200 Ω (AV = 10 dB) (see Figure 11).

G

reduces the peaking

IP

BIT 2

PWUP

SIGNAL

INPUT 2

SIGNAL

INPUT N

INHI

RGP1

R

G

RGP2

INLO

INHI

RGP1

R

G

RGP2

INLO

OPHI

AD8351

OPLO

BIT N

PWUP

OPHI

AD8351

OPLO

MUX
OUTPUT
LOAD

Figure 9. Using Several AD8351s to Form an
N-Channel Analog MUX

Figure 11. Reducing Gain Peaking with Parasitic
Suppressing Resistors (R

= 25 Ω, RL = 1 kΩ)

IP

–12–

REV. B

AD8351

It is important to ensure that all I/O, ground, and RG port traces
be kept as short as possible. In addition, it is required that the
ground plane be removed from under the package. Due to the
inverse relationship between the gain of the device and the value
of the R

resistor, any parasitic capacitance on the RG ports can

G

result in gain-peaking at high frequencies. Following the precau­tions outlined in Figure 12 will help to reduce parasitic board
capacitance, thus extending the device’s bandwidth and reducing
potential peaking or oscillation.

COPLANAR

WAVEGUIDE

OR STRIP

AGND

1

R

T

R

T

2

R

IP

3

4

R

IP

5

R

G

10

9

R

OP

8

7

6

R

OP

AGND

Hi-Z

Figure 12. General Description of Recommended
Board Layout for High-Z Load Conditions

TRANSMISSION LINE EFFECTS

As noted, stray transmission line capacitance, in combination with
package parasitics, can potentially form a resonant circuit at high
frequencies, resulting in excessive gain peaking. R

transmission

F

lines connecting the input and output networks should be designed
such that stray capacitance is minimized. The output single-ended
source impedance of the AD8351 is dynamically set to a nominal
value of 75 Ω. Therefore, for a matched load termination, the
characteristic impedance of the output transmission lines should be
designed to be 75 Ω. In many situations, the final load impedance
may be relatively high, greater than 1 kΩ. It is suggested that the
board be designed as shown in Figure 12 for high impedance load
conditions. In most practical board designs, this requires that
the printed-circuit board traces be dimensioned to a small width
(~5 mils) and that the underlying and adjacent ground planes are
far enough away to minimize capacitance.

Typically the driving source impedance into the device will be
low and terminating resistors will be used to prevent input reflec­tions. The transmission line should be designed to have the
appropriate characteristic impedance in the low-Z region. The
high impedance environment between the terminating resistors
and device input pins should not have ground planes under­neath or near the signal traces. Small parasitic suppressing
resistors may be necessary at the device input pins to help desensitize

(“de-Q”) the resonant effects of the device bond wires and
surrounding parasitic board capacitance. Typically, 25 Ω series
resistors (size 0402) adequately de-Q the input system without a
significant decrease in ac performance.

Figure 13 illustrates the value of adding input and output series
resistors to help desensitize the resonant effects of board parasitics.
Overshoot and undershoot can be significantly reduced with the
simple addition of R

1.5
NO R

1.0

0.5

0

VOLTA G E ( V )

–0.5

–1.0

–1.5

04

and ROP.

IP

OR R

IP

OP

R

= 25

OP

RIP = R

= 25

OP

13

2

TIME (ns)

Figure 13. Step Response Characteristics with and
without Input and Output Parasitic Suppression Resistors

CHARACTERIZATION SETUP

The test circuit used for 150 Ω and 1 kΩ load testing is provided
in Figure 14. The evaluation board uses balun transformers to
simplify interfacing to single-ended test equipment. Balun effects
need to be removed from the measurements in order to accu­rately characterize the performance of the device at frequencies
exceeding 1 GHz.

The output L-pad matching networks provide a broadband
impedance match with minimum insertion loss. The input
lines are terminated with 50 Ω resistors for input impedance
matching. The power loss associated with these networks needs
to be accounted for when attempting to measure the gain of the
device. The required resistor values and the appropriate inser­tion loss and correction factors used to assess the voltage gain
are provided in Table II.

Table II. Load Conditions Specified Differentially

Conversion

Total Factor
Load Insertion 20 log (S21)
Condition R1 R2 Loss to 20 log (AV)

150 Ω 43.2 Ω 86.6 Ω 5.8 dB 7.6 dB
1 kΩ 475 Ω 52.3 Ω 15.9 dB 25.9 dB

REV. B

BALANCED

SOURCE

R

50

R

50

S

S

50 CABLE

50 CABLE

R

T

50

50

0.1nF

0.1nF

R

T

AD8351

DUT

100nF

100nF

Figure 14. Test Circuit

–13–

R

LOAD

R1

R1

R2

R2

50 CABLE

50 CABLE

50

50 TEST
EQUIPMENT

50

AD8351

EVALUATION BOARD

An evaluation board is available for experimentation. Various
parameters such as gain, common-mode level, and input and
output network configurations can be modified through minor
resistor changes. The schematic and evaluation board artwork
are presented in Figures 15, 16, and 17.

P1

RF_IN+

RF_IN–

ENBL

W1

R18

0

R7
0

T1

1:1

(MACOM)

R2

24.9

R4

24.9

TEST IN2

100nF

100nF

J5

C4

R5
0

R1

100

R8

C5

0

R3

J1

J2

OPEN

ETC1-1-13

R12
0

AD8351

1

PWUP VOCM

2

RGP1 VPOS

3

INHI OPHI

4

INLO OPLO

RGP2 COMM

5

10 PIN mSOIC

T3

1:1

ETC1-1-13

(MACOM)

0.1F

C10

100nF

C9

100nF

OPEN

C3

VCOM

R17

R6

10

9

8

7

6

T4

1:1

ETC1-1-13

(MACOM)

0

R15

0

R16

0

VPOS

ACOM

C6

100nF

C7

100nF

C2

100nF

61.9

61.9

AGND

VPOS

R11

R9

R10

61.9

J6
TEST OUT2

T2

1:1

ETC1-1-13

(MACOM)

R13
OPEN

R14
0

J3
RF_OUT+

J4
RF_OUT–

Figure 15. Evaluation Board Schematic

Figure 16. Component Side Layout

–14–

Figure 17. Component Side Silkscreen

REV. B

AD8351

Table III. Evaluation Board Configuration Options

Component Function Default Condition

P1-1, P1-2, Supply and Ground Pins. Not Applicable
VPOS, AGND

P1-3 Common-Mode Offset Pin. Allows for monitoring or adjustment of the Not Applicable

output common-mode voltage.

W1, R7, P1-4, R17, R18 Device Enable. Configured such that switch W1 disables the device when W1 = Installed

Pin 1 is set to ground. Device can be disabled remotely using Pin 4 of R7 = 0 Ω (Size 0603)
header P1.

R2, R3, R4, R5, R8, R12, Input Interface. R3 and R12 are used to ground one side of the differential
T1, C4, C5 drive interface for single-ended applications. T1 is a 1-to-1 impedance ratio R3 = Open (Size 0603)

balun used to transform a single-ended input into a balanced differential R5 = R8 = R12 = 0 Ω
signal. R2 and R4 are used to provide a differential 50 Ω input termination. (Size 0603)
R5 and R8 can be increased to reduce gain peaking when driving from a high
source impedance. The 50 Ω termination provides an insertion loss of 6 dB. T1 = MacomTM ETC1-1-13
C4 and C5 are used to provide ac coupling.

R9, R10, R11, R13, R14, Output Interface. R13 and R14 are used to ground one side of the differential
R15, R16, T2, C4, C5, output interface for single-ended applications. T2 is a 1-to-1 impedance ratio R11 = 61.9 Ω (Size 0603)
C6, C7 balun used to transform a balanced differential signal into a single-ended R13 = Open (Size 0603)

signal. R9, R10, and R11 are provided for generic placement of matching R14 = 0 Ω (Size 0603)
components. R15 and R16 allow additional output series resistance when
driving capacitive loads. The evaluation board is configured to provide a
150 Ω to 50 Ω impedance transformation with an insertion loss of 9.9 dB.
C4 through C7 are used to provide ac coupling. T2 = Macom ETC1-1-13

R1 Gain Setting Resistor. Resistor R1 is used to set the gain of the device. R1 = 100 Ω (Size 0603)

Refer to TPC 2 when selecting gain resistor. When R1 is 100 Ω, the
overall system gain of the evaluation board will be approximately –6 dB.

C2 Power Supply Decoupling. The supply decoupling consists of a 100 nF C2 = 100 nF (Size 0805)

capacitor to ground.

R6, C3, P1-3 Common-Mode Offset Adjustment. Used to trim common-mode output R6 = 0 Ω (Size 0603)

level. By applying a voltage to Pin 3 of header P1, the output common- C3 = 0.1 µF (Size 0805)
mode voltage can be directly adjusted. Typically decoupled to ground
using a 0.1 µF capacitor.

T3, T4, C9, C10 Calibration Networks. Calibration path provided to allow for compensation T3 = T4 = Macom

of the insertion loss of the baluns and the reactance of the coupling capacitors. ETC1-1-13

R17 = R18 = 0 Ω (Size 0603)
R2 = R4 = 24.9 Ω (Size 0805)

C4 = C5 = 10 0 nF (Size 0603)

R9 = R10 = 61.9 Ω (Size 0603)

R15 = R16 = 0 Ω (Size 0402)
C4 = C5 = 100 nF (Size 0603)
C6 = C7 = 100 nF (Size 0603)

C9 = C10 = 100 nF
(Size 0603)

REV. B

–15–

AD8351

OUTLINE DIMENSIONS

10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

3.00 BSC

6

10

3.00 BSC

PIN 1

0.95

0.85

0.75

0.15

0.00

COPLANARITY

0.50 BSC

0.27

0.17

0.10

COMPLIANT TO JEDEC STANDARDS MO-187BA

4.90 BSC

1

5

1.10 MAX

SEATING
PLANE

0.23

0.08

8
0

C03145–0–2/04(B)

0.80

0.60

0.40

Revision History

Location Page

2/04—Data Sheet changed from REV. A to REV. B.

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to TPC 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3/03—Data Sheet changed from REV. 0 to REV. A.

Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Change to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

–16–

REV. B