250 MHz, Voltage Output
Y1
Y2
Z INPUT
Y = Y1
– Y2
X = X1 – X2
XY +
Z
X1
X2
W OUTPUT
XY
AD835
∑
+1
4-Quadrant Multiplier
AD835
FEATURES
Simple: Basic Function is W = XY + Z
Complete: Minimal External Components Required
Very Fast: Settles to 0.1% of FS in 20 ns
DC-Coupled Voltage Output Simplies Use
High Differential Input Impedance X, Y, and Z Inputs
Low Multiplier Noise: 50 nV/Hz
APPLICATIONS
Very Fast Multiplication, Division, Squaring
Wideband Modulation and Demodulation
Phase Detection and Measurement
Sinusoidal Frequency Doubling
Video Gain Control and Keying
Voltage Controlled Ampliers and Filters
PRODUCT DESCRIPTION
The AD835 is a complete four-quadrant voltage output analog
multiplier, fabricated on an advanced dielectrically isolated complementary bipolar process. It generates the linear product of its
X and Y voltage inputs with a –3 dB output bandwidth of 250 MHz
(a small signal rise time of 1 ns). Full scale (–1 V to +1 V) rise
to fall times are 2.5 ns (with the standard RL of 150 ), and the
settling time to 0.1% under the same conditions is typically 20 ns.
Its differential multiplication inputs (X, Y) and its summing input
(Z) are at high impedance. The low impedance output voltage (W)
can provide up to ±2.5 V and drive loads as low as 25 . Normal
operation is from ±5 V supplies.
Though providing state-of-the-art speed, the AD835 is simple to
use and versatile. For example, as well as permitting the addition
of a signal at the output, the Z input provides the means to operate
the AD835 with voltage gains up to about 10. In this capacity,
the very low product noise of this multiplier (50 nV/Hz) makes it
much more useful than earlier products.
The AD835 is available in an 8-lead PDIP package (N) and an
8-lead SOIC package (R) and is specied to operate over the
–40°C to +85°C industrial temperature range.
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1. The AD835 is the rst monolithic 250 MHz four quadrant
voltage output multiplier.
2. Minimal external components are required to apply the
AD835 to a variety of signal processing applications.
3. High input impedances (100 k2 pF) make signal source
loading negligible.
4. High output current capability allows low impedance loads to
be driven.
5. State of the art noise levels achieved through careful device
optimization and the use of a special low noise band gap voltage reference.
6. Designed to be easy to use and cost effective in applications
which formerly required the use of hybrid or board level
solutions.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks
and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
AD835–SPECIFICATIONS
W
X X Y Y
U
Z=
−
( )−( )
+
1 2 1 2
(TA = 25C, VS = 5 V, RL = 150 , CL 5 pF, unless otherwise noted.)
Model AD835AN/AR835
TRANSFER FUNCTION
Parameter Conditions Min Typ Max Unit
INPUT CHARACTERISTICS (X, Y)
Differential Voltage Range VCM = 0 ±1 V
Differential Clipping Level 1.2 ±1.4 V
Low Frequency Nonlinearity X = ±1 V, Y = 1 V 0.3 0.5 % FS
Y = ±1 V, X = 1 V 0.1 0.3 % FS
vs. Temperature T
MIN
to T
MAX
1
X = ±1 V, Y = 1 V 0.7 % FS
Y = ±1 V, X = 1 V 0.5 % FS
Common-Mode Voltage Range –2.5 +3 V
Offset Voltage ±3 20 mV
vs. Temperature T
MIN
to T
1
±25 mV
MAX
CMRR f 100 kHz; ±1 V p-p 70 dB
Bias Current 10 20 µA
vs. Temperature T
MIN
to T
1
27 µA
MAX
Offset Bias Current 2 µA
Differential Resistance 100 k
Single-Sided Capacitance 2 pF
Feedthrough, X X = ±1 V, Y = 0 V –46 dB
Feedthrough, Y Y = ±1 V, X = 0 V –60 dB
DYNAMIC CHARACTERISTICS
–3 dB Small-Signal Bandwidth 150 250 MHz
–0.1 dB Gain Flatness Frequency 15 MHz
Slew Rate W = –2.5 V to +2.5 V 1000 V/µs
Differential Gain Error, X f = 3.58 MHz 0.3 %
Differential Phase Error, X f = 3.58 MHz 0.2 Degrees
Differential Gain Error, Y f = 3.58 MHz 0.1 %
Differential Phase Error, Y f = 3.58 MHz 0.1 Degrees
Harmonic Distortion X or Y = 10 dBm, Second and Third Harmonic
Fund = 10 MHz –70 dB
Fund = 50 MHz –40 dB
Settling Time, X or Y To 0.1%, W = 2 V p-p 20 ns
SUMMING INPUT (Z)
Gain From Z to W, f 10 MHz 0.990 0.995
–3 dB Small-Signal Bandwidth 250 MHz
Differential Input Resistance 60 k
Single Sided Capacitance 2 pF
Maximum Gain X, Y to W, Z Shorted to W, f = 1 kHz 50 dB
Bias Current 50 µA
OUTPUT CHARACTERISTICS
Voltage Swing ±2.2 ±2.5 V
vs. Temperature T
MIN
to T
1
±2.0 V
MAX
Voltage Noise Spectral Density X = Y = 0, f < 10 MHz 50 nV/Hz
Offset Voltage ±25 75 mV
vs. Temperature2 T
MIN
to T
1
±10 mV
MAX
Short Circuit Current 75 mA
Scale Factor Error ±5 8 % FS
vs. Temperature T
Linearity (Relative Error)
vs. Temperature T
3
MIN
MIN
to T
to T
1
±9 % FS
MAX
1
±1.25 % FS
MAX
±0.5
1.0 % FS
–2–
REV. B REV. B
AD835
Y1
Y2
VN
Z
X1
X2
V
P
W
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
AD835
Parameter Conditions Min Typ Max Unit
POWER SUPPLIES
Supply Voltage
For Specied Performance ±4.5 ±5 ±5.5 V
Quiescent Supply Current 16 25 mA
vs. Temperature T
MIN
PSRR at Output vs. VP +4.5 V to +5.5 V
PSRR at Output vs. VN –4.5 V to –5.5 V 0.5 %/V
NOTES
1
T
= –40°C, T
MIN
2
Normalized to zero at 25°C.
3
Linearity is dened as residual error after compensating for input offset, output voltage offset, and scale factor errors.
All min and max specications are guaranteed. Specications in boldface are tested on all production units at nal electrical test.
Specications subject to change without notice.
MAX
= 85°C.
to T
1
26 mA
MAX
0.5 %/V
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 300 mW
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
1
PIN CONNECTIONS
8-Lead PDIP (N)
8-Lead SOIC (R)
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 sec . . . . . . . . . . . . . . . . 300°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational sections of
this specication is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.
2
Thermal Characteristics:
8-Lead PDIP (N): JC = 35°C/W; JA = 90°C/W
8-Lead SOIC (R): JC = 45°C/W; JA = 115°C/W.
Temperature Package
ORDERING GUIDE
Model Range Options
AD835AN –40°C to +85°C N-8
AD835AR –40°C to +85°C R-8
AD835AR-REEL –40°C to +85°C R-8
AD835AR-REEL7 –40°C to +85°C R-8
AD835ARZ2 –40°C to +85°C R-8
1
N = PDIP; R = Small Outline IC Plastic Package (SOIC).
2
The Z stands for a lead-free product.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the AD835 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
1
–3–
AD835–Typical Performance Characteristics AD835
1M 10M 1G100M
–2
–4
–6
–8
–10
0
2
MAGNITUDE (dB)
FREQUENCY (Hz)
PHASE (Degrees)
0
–90
–180
90
180
PHASE
X, Y, Z CH = 0dBm
RL = 150
CL ≤ 5pF
GAIN
FREQUENCY (Hz)
1G
–0.
2
–0.
3
–0.4
–0.
5
–0.
6
–0.
1
0
MAGNITUDE (dB)
X, Y CH = 0dBm
RL = 150
CL ≤ 5pF
1M 10M 100M300k
–30
–40
–50
–60
–20
–10
MAGNITUDE (dB)
FREQUENCY (Hz)
1M 10M 1G100M
X FEEDTHROUGH
Y FEEDTHROUGH
X FEEDTHROUGH
Y FEEDTHROUGH
X, Y
CH
= 5dBm
RL = 150
CL < 5pF
100mV
0.200V
GND
–0.200V
10ns
0.4
–0.
4
–0.
2
0.
2
0.
0
0.020.00 0.060.030.030.02
0.060.00 0.200.190.160.11
DIFFERENTIAL
PHASE (Degrees)
DIFFERENTIAL
GAIN
(%)
2ND1ST 6TH5TH4TH3RD
2ND1ST 6TH5TH4TH3RD
–0.3
0.
0
–0.2
–0.
1
0.
2
0.
3
0.
1
MIN = 0.00
MAX = 0.20
p-p/MAX = 0.20
MIN = 0.00
MAX = 0.06
p-p = 0.06
DG DP (NTSC) FIELD = 1 LINE = 18 Wfm FCC COMPOSITE
0.20
–0.20
–0.10
0.10
0.00
0.030.00 0.160.100.070.04
0.010.00 –0.20–0.010.00–0.00
DIFFERENTIAL
PHASE (Degrees
)
DIFFERENTIAL
GAIN
(%)
2ND1ST 6TH5TH4TH3RD
2ND1ST 6TH5TH4TH3RD
–0.
3
0.
0
–0.
2
–0.
1
0.
2
0.
3
0.
1
MIN = –0.02
MAX = 0.01
p-p/MAX = 0.03
MIN = 0.00
MAX = 0.16
p-p = 0.16
DG DP (NTSC) FIELD = 1 LINE = 18 Wfm FCC COMPOSITE
TPC 1. Typical Composite Output Differential Gain and
Phase, NTSC for X Channel; f = 3.58 MHz, RL = 150
TPC 2. Typical Composite Output Differential Gain and
Phase, NTSC for Y Channel; f = 3.58 MHz, RL = 150
TPC 4. Gain Flatness to 0.1 dB
TPC 5. X and Y Feedthrough vs. Frequency
TPC 3. Gain and Phase vs. Frequency of X, Y, Z Inputs
TPC 6. Small Signal Pulse Response at W Output, RL =
150 , CL 5 pF, X Channel = ±0.2 V, Y Channel = ±1.0 V
–4–
REV. B REV. B
500mV
1V
GND
–1V
10ns
TPC 7. Large Signal Pulse Response at W Output, RL =
60
80
0
40
20
CMRR (dB)
FREQUENCY (Hz)
1M 10M 1G100M
–40
–50
–60
–20
–10
–30
PSRR (dB)
FREQUENCY (Hz)
1M 10M 1G100M300k
PSRR ON V+
PSRR ON V–
0dBm ON SUPPLY
X, Y = 1V
10MHz
20MHz
30MHz
10dB/DIV
50MHz
100MHz
150MHz
10dB/DIV
100MHz
200MHz
300MHz
10dB/DIV
150 , CL 5 pF, X Channel = ±1.0 V, Y Channel = ±1.0 V
TPC 10. Harmonic Distortion at 10 MHz; 10 dBm
Input to X or Y Channels, RL = 150 , CL = 5 pF
TPC 8. CMRR vs. Frequency for X or Y Channel,
RL = 150 , CL 5 pF
TPC 9. PSRR vs. Frequency for V+ and V– Supply
TPC 11. Harmonic Distortion at 50 MHz, 10 dBm
Input to X or Y Channel, RL = 150 , CL 5 pF
TPC 12. Harmonic Distortion at 100 MHz, 10 dBm
Input to X or Y Channel, RL = 150 , CL 5 pF
–5–
AD835
AD835
–7–
1V
10ns
+2.5V
GN
D
–2.5V
15
–15
–10
0
5
10
–5
125–35–55 45255–15 1058565
TEMPERATURE (C)
V
OS
OUTPUT DRIFT (mV)
OUTPUT VOS DRIFT, NORMALIZED TO 0 AT 25C
OUTPUT OFFSET DRIFT WILL
TYPICALLY BE WITHIN SHADED AREA
35
0
15
5
10
20
25
30
200200 180160806040 140120100
RF FREQUENCY INPUT TO X CHANNEL (MHz)
THIRD ORDER INTERCEPT (dBm)
X CH = 6dBm
Y CH = 10dBm
RL = 100
35
0
15
5
10
20
25
30
200200 180160806040 140120100
LO FREQUENCY ON Y CHANNEL (MHz)
THIRD ORDER INTERCEPT (dBm)
X CH = 6dBm
Y CH = 10dBm
RL = 100
REV. B
TPC 13. Maximum Output Voltage Swing,
RL = 50 , CL 5 pF
TPC 14. VOS Output Drift vs. Temperature
TPC 15. Fixed LO on Y Channel vs. RF Frequency
Input to X Channel
TPC 16. Fixed IF vs. LO Frequency on Y Channel
–6–
REV. B
AD835
W
X X Y Y
U
Z=
−
( )−( )
+
1 2 1 2
W XY=
Y1
Y2
Z INPUT
Y = Y1
– Y2
X = X1 – X2
XY +
Z
X1
X2
W OUTPUT
XY
AD835
∑
+1
W
XY
U
kW k Z= + + −
( )
1 '
W
XY
k U
Z=
−
( )
+1'
U' k= −
( )
1 U
R1 = (1–k) R
2k
W
R2 = kR
200
+5V+5V
X1
X2 VP W
ZVNY2Y1
X1
AD835
FB
+5V
X
Y
–5V
Z
1
FB
3
42
1
5
7
0.01F CERAMIC
4.7F TANTALUM
8
0.01F CERAMIC
4.
7F TANTALUM
6
PRODUCT DESCRIPTION
The AD835 is a four-quadrant voltage output analog multiplier,
fabricated on an advanced dielectrically isolated complementary
bipolar process. In its basic mode, it provides the linear product
of its X and Y voltage inputs. In this mode, the –3 dB output voltage bandwidth is 250 MHz (a small signal rise time of 1 ns). Full
scale (–1 V to +1 V) rise to fall times are 2.5 ns (with the standard
RL of 150 ) and the settling time to 0.1% under the same conditions is typically 20 ns.
As in earlier multipliers from Analog Devices, a unique summing
feature is provided at the Z input. As well as providing independent ground references for input and output and enhanced
versatility, this feature allows the AD835 to operate with voltage
gain
. Its X-, Y-, and Z-input voltages are all nominally ±1 V FS,
with an overrange of at least 20%. The inputs are fully differential
at high impedance (100 k2 pF) and provide a 70 dB CMRR
(f 1 MHz).
The low impedance output is capable of driving loads as small
as 25 . The peak output can be as large as ±2.2 V minimum
for RL = 150 , or ±2.0 V minimum into RL = 50 . The AD835
has much lower noise than the AD534 or AD734, making it
attractive in low level signal-processing applications, for example,
as a wideband gain-control element or modulator.
Basic Theory
The multiplier is based on a classic form, having a translinear
core, supported by three (X, Y, Z) linearized voltage-to-current
converters, and the load driving output amplier. The scaling
voltage (the denominator U in the equations below) is provided
by a band gap reference of novel design, optimized for ultralow
noise. Figure 1 shows the functional block diagram.
In general terms, the AD835 provides the function
(1)
where the variables W, U, X, Y, and Z are all voltages. Connected
as a simple multiplier, with X = X1 – X2, Y = Y1 – Y2, and
Z = 0 and with a scale factor adjustment (see Figure 1), which
sets U = 1 V, the output can be expressed as
(2)
will be found to facilitate the development of new functions using
the AD835. The explicit inclusion of the denominator, U, is also
less helpful, as in the case of the AD835, if it is not an electrical
input variable.
Scaling Adjustment
The basic value of U in Equation 1 is nominally 1.05 V. Figure 2,
which shows the basic multiplier connections, also shows how the
effective value of U can be adjusted to have any lower voltage (usually 1 V) through the use of a resistive-divider between W (Pin 5)
and Z (Pin 4). Using the general resistor values shown, we can
rewrite Equation 1 as
(3 )
where Z' is distinguished from the signal Z at Pin 4. It follows that
(4)
In this way, we can modify the effective value of U to
(5)
without altering the scaling of the Z' input. (This is to be
expected since the only “ground reference” for the output is
through the Z' input.)
Thus, to set U' to 1 V, remembering that the basic value of U is
1.05 V, we need to choose R1 to have a nominal value of 20 times
R2. The values shown here allow U to be adjusted through the
nominal range 0.95 V to 1.05 V. That is, R2 provides a 5% gain
adjustment.
Note that in many applications, the exact gain of the multiplier
may not be very important; in which case, this network may be
omitted entirely, or R2 xed at 100 .
Figure 1. Functional Block Diagram
Simplied representations of this sort, where all signals are presumed to be expressed in V, are used throughout this data sheet
to avoid the needless use of less-intuitive subscripted variables
(such as VX1). We can view all variables as being normalized to 1 V.
For example, the input X can either be stated as being in the
range –1 V to +1 V or simply –1 to +1. The latter representation
REV. B
Figure 2. Multiplier Connections
–7–
AD835
AD835
–9–
V
IN
(SIGNAL)
R2
301
VOLTAGE
OUTPU
T
X1
X2 VP W
ZVNY2Y1
X1
AD835
+5V
–5V
R1
97.6
3
42
1
5678
C1
33pF
V
G
(GAIN CONTROL)
100k
100M10M1M10k
12dB
(VG = 1V)
0dB
(VG = 0.25V)
6dB
(VG = 0.5V)
START 10 000.000Hz STOP 100 000 000.000Hz
MODULATED
CARRIER
OUTPU
T
MODULATION
INPUT
CARRIER
OUTPU
T
X1
X2 VP W
ZVNY2Y1
X1
AD835
+5V
–5V
3
4
2
1
5
6
7
8
E
U
E
U
sin
cosωωtt
( )
= −
( )
2
2
2
1 2
REV. B
APPLICATIONS
The AD835 is easy to use and versatile. The capability for
adding another signal to the output at the Z input is frequently
valuable. Three applications of this feature are presented here:
a wideband voltage controlled amplier, an amplitude modulator,
and a frequency doubler. Of course, the AD835 may also be used
as a square law detector (with its X- and Y-inputs connected in
parallel). In this mode, it is useful at input frequencies to well
over 250 MHz, since that is the bandwidth limitation of the
output amplier only.
Multiplier Connections
Figure 2 shows the basic connections for multiplication. The
inputs will often be single-sided, in which case the X2 and Y2
inputs will normally be grounded. Note that by assigning Pins 7
and 2, respectively, to these (inverting) inputs, an extra measure
of isolation between inputs and output is provided. The X and Y
inputs may, of course, be reversed to achieve some desired overall
sign with inputs of a particular polarity, or they may be driven
fully differentially.
Power supply decoupling and careful board layout are always
important in applying wideband circuits. The decoupling recommendations shown in Figure 2 should be followed closely. In
remaining gures in this data sheet, these power supply decoupling
components have been omitted for clarity but should be used
wherever optimal performance with high speed inputs is required.
However, they may be omitted if the full high frequency capabilities of the AD835 are not being exploited.
Wideband Voltage Controlled Amplier
Figure 3 shows the AD835 congured to provide a gain of nominally 0 dB to 12 dB. (In fact, the control range extends from well
under –12 dB to about +14 dB.) R1 and R2 set the gain to be
nominally 4. The attendant bandwidth reduction that comes
with this increased gain can be partially offset by the addition of
the peaking capacitor C1. Although this circuit shows the use of
dual supplies, the AD835 can operate from a single 9 V supply
with a slight revision.
Figure 4. AC Response of VCA
Amplitude Modulator
Figure 5 shows a simple modulator. The carrier is applied to the
Y input and the Z input, while the modulating signal is applied
to the X input. For zero modulation, there is no product term so
the carrier input is simply replicated at unity gain by the voltage
follower action from the Z input. At X = 1 V, the RF output is
doubled, while for X = –1 V, it is fully suppressed. That is, an X
input of approximately ±1 V (actually ±U or about 1.05 V) corresponds to a modulation index of 100%. Carrier and modulation
frequencies can be up to 300 MHz, somewhat beyond the nominal –3 dB bandwidth.
Of course, a suppressed carrier modulator can be implemented by
omitting the feedforward to the Z input, grounding that pin instead.
The ac response of this amplier for gains of 0 dB (VG = 0.25 V),
6 dB (VG = 0.5 V), and 12 dB (VG = 1 V) is shown in Figure 4.
In this application, the resistor values have been slightly adjusted
to reect the nominal value of U = 1.05 V. The overall sign of the
gain may be controlled by the sign of VG.
Figure 3. Voltage Controlled 50 MHz Amplier Using
the AD835
Figure 5. Simple Amplitude Modulator Using the AD835
Squaring and Frequency Doubling
Amplitude domain squaring of an input signal, E, is achieved
simply by connecting the X and Y inputs in parallel to produce
an output of E2/U. The input may have either polarity, but the
output in this case will always be positive. The output polarity
may be reversed by interchanging either the X or Y inputs.
When the input is a sine wave E sin t, a signal squarer behaves
as a frequency doubler, since
While useful, Equation 6 shows a dc term at the output, which
will vary strongly with the amplitude of the input, E.
–8–
(6)
REV. B
AD835
R1
R3
301
VOLTAGE
OUTPU
T
X1
X2 VP W
ZVNY2Y1
X1
AD835
+5V
–5V
R2
97.
6
3
42
1
5678
C1
V
G
cos sin sinθ θ θ=
1
2
2
W
U
E
t
E
t
E
U
t
= −
°
( )
+ °
( )
=
( )
1
2
45
2
45
2
2
2
sin sin
sin
ω ω
ω
Figure 6 shows a frequency doubler, which overcomes this limitation and provides a relatively constant output over a moderately
wide frequency range, determined by the time-constant C1 and
R1. The voltage applied to the X and Y inputs are exactly in
quadrature at a frequency f = 1/2 C1R1 and their amplitudes
are equal. At higher frequencies, the X input becomes smaller
while the Y input increases in amplitude; the opposite happens
at lower frequencies. The result is a double frequency output
centered on ground whose amplitude of 1 V for a 1 V input varies
by only 0.5% over a frequency range of ±10%. Because there is
no squared dc component at the output, sudden changes in the
input amplitude do not cause a bounce in the dc level.
Figure 6. Broadband "Zero-Bounce" Frequency Doubler
This circuit is based on the identity
(7)
At O = 1/C1R1, the X input leads the input signal by 45° (and
is attenuated by 2, while the Y input lags the input signal by 45°
and is also attenuated by 2. Since the X and Y inputs are 90° out
of phase, the response of the circuit will be
(8)
which has no dc component, R2 and R3 are included to restore
the output to 1 V for an input amplitude of 1 V (the same gain
adjustment as mentioned earlier). Because the voltage across
the capacitor (C1) decreases with frequency, while that across
the resistor (R1) increases, the amplitude of the output varies
only slightly with frequency. In fact, it is only 0.5% below its
full value (at its center frequency O = 1/C1R1) at 90% and
110% of this frequency.
REV. B
–9–
AD835
AD835
–11–
SEATING
PLANE
0.180
(4.57)
MAX
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
8
1
4
5
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
0.100 (2.54)
BSC
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AA
0.015
(0.38)
MIN
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
45
8
0
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
8 5
41
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
REV. B
OUTLINE DIMENSIONS
8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
8-Lead Standard Small Outline Package [SOIC]
(R-8)
Dimensions shown in millimeters and (inches)
–10–
REV. B
AD835
Revision History
Location Page
6/03—Data Sheet changed from REV. A to REV. B.
Updated Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
REV. B
–11–
C00883–0–6/03(B)
–12–
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