Output frequency range: 700 MHz to 2700 MHz
Modulation bandwidth: dc to 160 MHz (large signal BW)
1 dB output compression: 5.6 dBm @ 2140 MHz
Output disable function: output below –50 dBm in < 50 ns
Noise floor: –156 dBm/Hz
Phase quadrature error: 0.3 degrees @ 2140 MHz
Amplitude balance: 0.1 dB
Single supply: 4.75 V to 5.5 V
Pin compatible with AD8345/AD8346s
16-lead, exposed-paddle TSSOP package
APPLICATIONS
Cellular/PCS communication systems infrastructure
WCDMA/CDMA2000/PCS/GSM/EDGE
Wireless LAN/wireless local loop
LMDS/broadband wireless access systems
Quadrature Modulator
AD8349
FUNCTIONAL BLOCK DIAGRAM
IBBP
IBBN
OM1
OM1
LOIN
LOIP
VPS1
ENOP
1
2
3
4
5
6
7
8
AD8349
PHASE
SPLITTER
Σ
BIAS
Figure 1.
16
QBBP
15
QBBN
14
COM3
13
COM3
12
VPS2
11
VOUT
10
COM3
9
COM2
03570-0-001
PRODUCT DESCRIPTION
The AD8349 is a silicon, monolithic, RF quadrature modulator
that is designed for use from 700 MHz to 2700 MHz. Its
excellent phase accuracy and amplitude balance enable high
performance direct RF modulation for communication systems.
The differential LO input signal is buffered, and then split into
an in-phase (I) signal and a quadrature-phase (Q) signal using a
polyphase phase splitter. These two LO signals are further
buffered and then mixed with the corresponding I channel and
Q channel baseband signals in two Gilbert cell mixers. The
mixers’ outputs are then summed together in the output
amplifier. The output amplifier is designed to drive 50 Ω loads.
The RF output can be switched on and off within 50 ns by
applying a control pulse to the ENOP pin.
The AD8349 can be used as a direct-to-RF modulator in digital
communication systems such as GSM, CDMA, and WCDMA
base stations, and QPSK or QAM broadband wireless access
transmitters. Its high dynamic range and high modulation
accuracy also make it a perfect IF modulator in local multipoint
distribution systems (LMDS) using complex modulation
formats.
The AD8349 is fabricated using Analog Devices’ advanced
complementary silicon bipolar process, and is available in a 16lead, exposed-paddle TSSOP package. Its performance is
specified over a –40°C to +85°C temperature range.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Changes to Figure 25 through Figure 30 ................................11
Changes to Figure 37 through Figure 39 ................................13
Change to WCDMA MultiCarrier Application section .......21
Change to Figure 60 and Figure 61 .........................................21
11/03—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD8349
SPECIFICATIONS
VS = 5 V; ambient temperature (TA) = 25°C; LO = –6 dBm; I/Q inputs = 1.2 V p-p differential sine waves in quadrature on a 400 mV dc
bias; baseband frequency = 1 MHz; LO source and RF output load impedances are 50 Ω, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
Operating Frequency 700 2700 MHz
LO = 900 MHz
Output Power 1.5 4 6 dBm
Output P1 dB 7.6 dBm
Carrier Feedthrough –45 –30 dBm
Sideband Suppression –35 –31 dBc
Third Harmonic
Output IP3 F1BB = 3 MHz, F2BB = 4 MHz, P
Quadrature Error 1.9 degree
I/Q Amplitude Balance 0.1 dB
Noise Floor 20 MHz offset from LO, all BB inputs 400 mV dc bias only –155 dBm/Hz
20 MHz offset from LO, BB inputs = 1.2 V p-p differential on 400 mV dc –150 dBm/Hz
GSM Sideband Noise LO = 884.8 MHz, 6 MHz offset from LO, P
LO = 1900 MHz
Output Power 0 3.8 6 dBm
Output P1dB 6.8 dBm
Carrier Feedthrough –38 dBm
Sideband Suppression –40 –36 dBc
Third Harmonic
Output IP3 F1BB = 3 MHz, F2BB = 4 MHz, P
Quadrature Error 0.7 degree
I/Q Amplitude Balance 0.1 dB
Noise Floor 20 MHz offset from LO, all BB inputs 400 mV dc bias only –156 dBm/Hz
20 MHz offset from LO, BB inputs = 1.2 V p-p differential on 400 mV dc –150 dBm/Hz
GSM Sideband Noise LO = 1960 MHz, 6 MHz offset from LO, P
LO = 2140 MHz
Output Power –2 2.4 5.1 dBm
Output P1dB 5.6 dBm
Carrier Feedthrough –42 –30 dBm
Sideband Suppression –43 –36 dBc
Third Harmonic
Output IP3 F1BB = 3 MHz, F2BB = 4 MHz, P
Quadrature Error 0.3 degree
I/Q Amplitude Balance 0.1 dB
Noise Floor 20 MHz offset from LO, all BB inputs 400 mV dc bias only –156 dBm/Hz
20 MHz offset from LO, BB inputs = 1.2 V p-p differential on 400 mV dc –151 dBm/Hz
WCDMA Noise Floor LO = 2140 MHz. 30 MHz offset from LO, P
LO INPUTS Pins LOIP and LOIN
LO Drive Level Characterization performed at typical level –10 –6 0 dBm
Nominal Impedance 50 Ω
Input Return Loss Drive via 1:1 balun, LO = 2140 MHz –8.6 dB
BASEBAND INPUTS Pins IBBP, IBBN, QBBP, QBBN
I and Q Input Bias Level 400 mV
Input Bias Current 11 µA
Input Offset Current 1.8 µA
Bandwidth (0.1 dB) LO = 1500 MHz, baseband input = 600 mV p-p sine wave on 400 mV dc 10 MHz
LO = 1500 MHz, baseband input = 60 mV p-p sine wave on 400 mV dc 24 MHz
1
1
1
P
– (FLO + (3 × FBB)), P
OUT
P
– (FLO + (3 × FBB)), P
OUT
P
– (FLO + (3 × FBB)), P
OUT
= 4 dBm –39 –36 dBc
OUT
= -4.2 dBm 21 dBm
OUT
= 2 dBm –152 dBc/Hz
OUT
= 3.8 dBm –37 –36 dBc
OUT
= –4.5 dBm 22 dBm
OUT
= 2 dBm –151 dBc/Hz
OUT
= 2.4 dBm –37 –36 dBc
OUT
= –6.5 dBm 19 dBm
OUT
= –17.3 dBm –156 dBm/Hz
CHAN
Rev. A | Page 3 of 28
AD8349
Parameter Conditions Min Typ Max Unit
Bandwidth (3 dB) LO = 1500 MHz, baseband input = 600 mV p-p sine wave on 400 mV dc 160 MHz
LO = 1500 MHz, baseband input = 60 mV p-p sine wave on 400 mV dc 340 MHz
OUTPUT ENABLE Pin ENOP
Off Isolation ENOP Low –78 –50 dBm
Turn-On Settling Time ENOP Low to High (90% of envelope) 20 ns
Turn-Off Settling Time ENOP High to Low (10% of envelope) 50 ns
ENOP High Level (Logic 1) 2.0 V
ENOP Low Level (Logic 0) 0.8 V
POWER SUPPLIES Pins VPS1 and VPS2
Voltage 4.75 5.5 V
Supply Current ENOP = High 135 150 mA
ENOP = Low 130 145 mA
1
The amplitude of the third harmonic relative to the single sideband power decreases with decreasing baseband drive level (see Figure 19, Figure 20, and Figure 21).
Rev. A | Page 4 of 28
AD8349
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage VPOS 5.5 V
IBBP, IBBN, QBBP, QBBN 0 V, 2.5 V
LOIP and LOIN 10 dBm
Internal Power Dissipation 800 mW
θJA (Exposed Paddle Soldered Down) 30°C/W
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 5 of 28
AD8349
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2,
15, 16
IBBP, IBBN,
QBBN, QBBP
Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs must be
dc-biased to approximately 400 mV dc, and must be driven from a low impedance source.
Nominal characterized ac signal swing is 600 mV p-p on each pin (100 mV to 700 mV). This
results in a differential drive of 1.2 V p-p with a 400 mV dc bias. These inputs are not self-biased
and must be externally biased.
3, 4 COM1
Common Pin for LO Phase Splitter and LO Buffers. COM1, COM2, and COM3 should all be
connected to a ground plane via a low impedance path.
5, 6 LOIN, LOIP
Differential Local Oscillator Inputs. Internally dc-biased to approximately 1.8 V when V
Pins must be ac-coupled. Single-ended drive is possible with degradation in performance.
7 VPS1
Positive Supply Voltage (4.75 V to 5.5 V) for the LO Bias-Cell and Buffer. VPS1 and VPS2 should
be connected to the same supply. To ensure adequate external bypassing, connect 0.1 µF and
100 pF capacitors between VPS1 and ground.
8 ENOP
Output Enable. This pin can be used to enable or disable the RF output. Connect to high logic
level for normal operation. Connect to low logic level to disable output.
9 COM2
Common Pin for the Output Amplifier. COM1, COM2, and COM3 should all be connected to a
ground plane via a low impedance path.
10, 13,
14
11 VOUT
COM3
Common Pin for Input V-to-I Converters and Mixer Cores. COM1, COM2, and COM3 should all
be connected to a ground plane via a low impedance path.
Device Output. Single-ended, 50 Ω internally biased RF output. Pin must be ac-coupled to the
load.
12 VPS2
Positive Supply Voltage (4.75 V to 5.5 V) for the Baseband Input V-to-I Converters, Mixer Core,
Band Gap Reference, and Output Amplifer. VPS1 and VPS2 should be connected to the same
supply. To ensure adequate external bypassing, connect 0.1 µF and 100 pF capacitors between
VPS2 and ground.