Analog Devices AD8349 Service Manual

700 MHz to 2700 MHz

C

C

FEATURES

Output frequency range: 700 MHz to 2700 MHz
Modulation bandwidth: dc to 160 MHz (large signal BW)
1 dB output compression: 5.6 dBm @ 2140 MHz
Output disable function: output below –50 dBm in < 50 ns
Noise floor: –156 dBm/Hz
Phase quadrature error: 0.3 degrees @ 2140 MHz
Amplitude balance: 0.1 dB
Single supply: 4.75 V to 5.5 V
Pin compatible with AD8345/AD8346s
16-lead, exposed-paddle TSSOP package

APPLICATIONS

Cellular/PCS communication systems infrastructure

WCDMA/CDMA2000/PCS/GSM/EDGE
Wireless LAN/wireless local loop
LMDS/broadband wireless access systems

Quadrature Modulator

AD8349

FUNCTIONAL BLOCK DIAGRAM

IBBP

IBBN

OM1

OM1

LOIN

LOIP

VPS1

ENOP

1

2

3

4

5

6

7

8

AD8349

PHASE

SPLITTER

Σ

BIAS

Figure 1.

16

QBBP

15

QBBN

14

COM3

13

COM3

12

VPS2

11

VOUT

10

COM3

9

COM2

03570-0-001

PRODUCT DESCRIPTION

The AD8349 is a silicon, monolithic, RF quadrature modulator
that is designed for use from 700 MHz to 2700 MHz. Its
excellent phase accuracy and amplitude balance enable high
performance direct RF modulation for communication systems.

The differential LO input signal is buffered, and then split into
an in-phase (I) signal and a quadrature-phase (Q) signal using a
polyphase phase splitter. These two LO signals are further
buffered and then mixed with the corresponding I channel and
Q channel baseband signals in two Gilbert cell mixers. The
mixers’ outputs are then summed together in the output
amplifier. The output amplifier is designed to drive 50 Ω loads.

The RF output can be switched on and off within 50 ns by
applying a control pulse to the ENOP pin.

The AD8349 can be used as a direct-to-RF modulator in digital
communication systems such as GSM, CDMA, and WCDMA
base stations, and QPSK or QAM broadband wireless access
transmitters. Its high dynamic range and high modulation
accuracy also make it a perfect IF modulator in local multipoint
distribution systems (LMDS) using complex modulation
formats.

The AD8349 is fabricated using Analog Devices’ advanced
complementary silicon bipolar process, and is available in a 16­lead, exposed-paddle TSSOP package. Its performance is
specified over a –40°C to +85°C temperature range.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD8349

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Functional Descriptions.......................... 6

Equivalent Circuits........................................................................... 7

Typical Performance Characteristics............................................. 8

Circuit Description......................................................................... 14

Overview...................................................................................... 14

LO Interface................................................................................. 14

V-to-I Converter......................................................................... 14

Mixers .......................................................................................... 14

D-to-S Amplifier......................................................................... 14

Bias Circuit ..................................................................................14

Output Enable............................................................................. 14

Basic Connections .......................................................................... 15

Baseband I and Q Inputs........................................................... 15

Single-Ended Baseband Drive .................................................. 15

LO Input Drive Level ................................................................. 16

Frequency Range ........................................................................ 16

LO Input Impedance Matching ................................................16

Single-Ended LO Drive.............................................................. 17

RF Output.................................................................................... 17

Output Enable............................................................................. 17

Baseband DAC Interface........................................................... 18

AD9777 Interface ....................................................................... 18

Biasing and Filtering.................................................................. 18

Reducing Undesired Sideband Leakage .................................. 19

Reduction of LO Feedthrough ................................................. 19

Sideband Suppression and LO Feedthrough vs. Temperature

....................................................................................................... 20

Applications..................................................................................... 21

3GPP WCDMA Single-Carrier Application........................... 21

WCDMA MultiCarrier Application ........................................ 21

GSM/EDGE Application........................................................... 22

Soldering Information ............................................................... 23

LO Generation Using PLLs....................................................... 23

Transm i t DAC O p tions ............................................................. 23

Evaluation Board ............................................................................ 24

Characterization Setups................................................................. 26

SSB Setup..................................................................................... 26

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 27

REVISION HISTORY

11/04—Data Sheet Changed from Rev. 0 to Rev. A

Changes to Figure 25 through Figure 30 ................................11

Changes to Figure 37 through Figure 39 ................................13

Change to WCDMA MultiCarrier Application section .......21

Change to Figure 60 and Figure 61 .........................................21

11/03—Revision 0: Initial Version

Rev. A | Page 2 of 28

AD8349

SPECIFICATIONS

VS = 5 V; ambient temperature (TA) = 25°C; LO = –6 dBm; I/Q inputs = 1.2 V p-p differential sine waves in quadrature on a 400 mV dc
bias; baseband frequency = 1 MHz; LO source and RF output load impedances are 50 Ω, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

Operating Frequency 700 2700 MHz
LO = 900 MHz

Output Power 1.5 4 6 dBm
Output P1 dB 7.6 dBm
Carrier Feedthrough –45 –30 dBm
Sideband Suppression –35 –31 dBc
Third Harmonic
Output IP3 F1BB = 3 MHz, F2BB = 4 MHz, P
Quadrature Error 1.9 degree
I/Q Amplitude Balance 0.1 dB
Noise Floor 20 MHz offset from LO, all BB inputs 400 mV dc bias only –155 dBm/Hz

20 MHz offset from LO, BB inputs = 1.2 V p-p differential on 400 mV dc –150 dBm/Hz

GSM Sideband Noise LO = 884.8 MHz, 6 MHz offset from LO, P

LO = 1900 MHz

Output Power 0 3.8 6 dBm
Output P1dB 6.8 dBm
Carrier Feedthrough –38 dBm
Sideband Suppression –40 –36 dBc
Third Harmonic
Output IP3 F1BB = 3 MHz, F2BB = 4 MHz, P
Quadrature Error 0.7 degree
I/Q Amplitude Balance 0.1 dB
Noise Floor 20 MHz offset from LO, all BB inputs 400 mV dc bias only –156 dBm/Hz

20 MHz offset from LO, BB inputs = 1.2 V p-p differential on 400 mV dc –150 dBm/Hz

GSM Sideband Noise LO = 1960 MHz, 6 MHz offset from LO, P

LO = 2140 MHz

Output Power –2 2.4 5.1 dBm
Output P1dB 5.6 dBm
Carrier Feedthrough –42 –30 dBm
Sideband Suppression –43 –36 dBc
Third Harmonic
Output IP3 F1BB = 3 MHz, F2BB = 4 MHz, P
Quadrature Error 0.3 degree
I/Q Amplitude Balance 0.1 dB
Noise Floor 20 MHz offset from LO, all BB inputs 400 mV dc bias only –156 dBm/Hz

20 MHz offset from LO, BB inputs = 1.2 V p-p differential on 400 mV dc –151 dBm/Hz

WCDMA Noise Floor LO = 2140 MHz. 30 MHz offset from LO, P

LO INPUTS Pins LOIP and LOIN

LO Drive Level Characterization performed at typical level –10 –6 0 dBm
Nominal Impedance 50 Ω
Input Return Loss Drive via 1:1 balun, LO = 2140 MHz –8.6 dB

BASEBAND INPUTS Pins IBBP, IBBN, QBBP, QBBN

I and Q Input Bias Level 400 mV
Input Bias Current 11 µA
Input Offset Current 1.8 µA
Bandwidth (0.1 dB) LO = 1500 MHz, baseband input = 600 mV p-p sine wave on 400 mV dc 10 MHz

LO = 1500 MHz, baseband input = 60 mV p-p sine wave on 400 mV dc 24 MHz

1

1

1

P

– (FLO + (3 × FBB)), P

OUT

P

– (FLO + (3 × FBB)), P

OUT

P

– (FLO + (3 × FBB)), P

OUT

= 4 dBm –39 –36 dBc

OUT

= -4.2 dBm 21 dBm

OUT

= 2 dBm –152 dBc/Hz

OUT

= 3.8 dBm –37 –36 dBc

OUT

= –4.5 dBm 22 dBm

OUT

= 2 dBm –151 dBc/Hz

OUT

= 2.4 dBm –37 –36 dBc

OUT

= –6.5 dBm 19 dBm

OUT

= –17.3 dBm –156 dBm/Hz

CHAN

Rev. A | Page 3 of 28

AD8349

Parameter Conditions Min Typ Max Unit

Bandwidth (3 dB) LO = 1500 MHz, baseband input = 600 mV p-p sine wave on 400 mV dc 160 MHz
LO = 1500 MHz, baseband input = 60 mV p-p sine wave on 400 mV dc 340 MHz
OUTPUT ENABLE Pin ENOP

Off Isolation ENOP Low –78 –50 dBm

Turn-On Settling Time ENOP Low to High (90% of envelope) 20 ns

Turn-Off Settling Time ENOP High to Low (10% of envelope) 50 ns

ENOP High Level (Logic 1) 2.0 V

ENOP Low Level (Logic 0) 0.8 V
POWER SUPPLIES Pins VPS1 and VPS2

Voltage 4.75 5.5 V

Supply Current ENOP = High 135 150 mA
ENOP = Low 130 145 mA

1

The amplitude of the third harmonic relative to the single sideband power decreases with decreasing baseband drive level (see Figure 19, Figure 20, and Figure 21).

Rev. A | Page 4 of 28

AD8349

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage VPOS 5.5 V
IBBP, IBBN, QBBP, QBBN 0 V, 2.5 V
LOIP and LOIN 10 dBm
Internal Power Dissipation 800 mW
θJA (Exposed Paddle Soldered Down) 30°C/W
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. A | Page 5 of 28

AD8349

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1, 2,
15, 16

IBBP, IBBN,
QBBN, QBBP

Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs must be
dc-biased to approximately 400 mV dc, and must be driven from a low impedance source.
Nominal characterized ac signal swing is 600 mV p-p on each pin (100 mV to 700 mV). This
results in a differential drive of 1.2 V p-p with a 400 mV dc bias. These inputs are not self-biased
and must be externally biased.

3, 4 COM1

Common Pin for LO Phase Splitter and LO Buffers. COM1, COM2, and COM3 should all be
connected to a ground plane via a low impedance path.

5, 6 LOIN, LOIP

Differential Local Oscillator Inputs. Internally dc-biased to approximately 1.8 V when V
Pins must be ac-coupled. Single-ended drive is possible with degradation in performance.

7 VPS1

Positive Supply Voltage (4.75 V to 5.5 V) for the LO Bias-Cell and Buffer. VPS1 and VPS2 should
be connected to the same supply. To ensure adequate external bypassing, connect 0.1 µF and
100 pF capacitors between VPS1 and ground.

8 ENOP

Output Enable. This pin can be used to enable or disable the RF output. Connect to high logic
level for normal operation. Connect to low logic level to disable output.

9 COM2

Common Pin for the Output Amplifier. COM1, COM2, and COM3 should all be connected to a
ground plane via a low impedance path.

10, 13,
14

11 VOUT

COM3

Common Pin for Input V-to-I Converters and Mixer Cores. COM1, COM2, and COM3 should all
be connected to a ground plane via a low impedance path.

Device Output. Single-ended, 50 Ω internally biased RF output. Pin must be ac-coupled to the
load.

12 VPS2

Positive Supply Voltage (4.75 V to 5.5 V) for the Baseband Input V-to-I Converters, Mixer Core,
Band Gap Reference, and Output Amplifer. VPS1 and VPS2 should be connected to the same
supply. To ensure adequate external bypassing, connect 0.1 µF and 100 pF capacitors between
VPS2 and ground.

IBBP

IBBN
COM1
COM1

LOIN

LOIP

VPS1

ENOP

1

AD8349

2
3

TOP VIEW

(Not to Scale)

4
5

6
7
8

Figure 2.

16

QBBP

15

QBBN

14

COM3
COM3

13
12

VPS2

VOUT

11

COM3

10

COM2

9

03570-0-002

Equivalent
Circuit

Circuit A

= 5.0 V.

S

Circuit B

Circuit C

Circuit D

Rev. A | Page 6 of 28

AD8349

C

EQUIVALENT CIRCUITS

VPS2

VPS2

VPS1

LOIN

LOIP

OM1

IBBP

COM3

Figure 3. Circuit A

03570-0-003

03570-0-004

ENOP

COM3

40Ω

40Ω

Figure 5. Circuit C

VPS2

VOUT

COM2

03570-0-006

04500-0-005

Figure 4. Circuit B

Figure 6. Circuit D

Rev. A | Page 7 of 28

AD8349

TYPICAL PERFORMANCE CHARACTERISTICS

8
7
6
5
4
3
2
1
0

–1

SSB OUTPUT POWER (dBm)

–2
–3
–4

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

Figure 7. Single Sideband (SSB) Output Power (P

(I and Q Inputs Driven in Quadrature at Baseband Frequency (F

I and Q Inputs at 1.2 V p-p Differential, T

VS = 5.25V

VS = 5V

VS = 4.75V

LO FREQUENCY (MHz)

) vs. LO Frequency (FLO)

OUT

= 25°C)

A

) = 1 MHz,

BB

03570-0-007

10

9
8
7
6
5
4
3
2
1
0

–1

1dB OUTPUT COMPRESSION (dBm)

–2
–3
–4

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

T = +85°C

°

C

T = +25

°

C

T = –40

LO FREQUENCY (MHz)

Figure 10. SSB Output 1 dB Compression Point (OP1dB) vs. F

I and Q Inputs Driven in Quadrature , T

= 25°C)

A

(FBB = 1 MHz,

LO

03570-0-010

1

0
–1
–2
–3
–4
–5
–6
–7
–8

OUTPUT POWER VARIATION (dB)

–9

–10

1 10 1000100

BASEBAND FREQUENCY (MHz)

600mV p-p

Figure 8. I and Q Input Bandwidth Normalized to Gain @ 1 MHz

= 1500 MHz, TA = 25°C)

(F

LO

4.0

3.5

3.0

2.5

2.0

1.5

1.0

SSB OUTPUT POWER (dBm)

0.5

Figure 9. SSB P

VS = 4.75V

0

–40–30–20–100 10203040

TEMPERATURE (°C)

vs. Temperature (FLO = 2140 MHz, FBB = 1 MHz, I and Q

OUT

VS = 5.25V

VS = 5V

Inputs Driven in Quadrature at 1.2 V p-p Differential)

60mV p-p

6050 70 80

03570-0-008

03570-0-009

–10

–15

–20

–25

–30

–35

VS = 5V

–40

–45

–50

CARRIER FEEDTHROUGH (dBm)

–55

–60

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

Figure 11. Carrier Feedthrough vs. F

VS = 5.25V

VS = 4.75V

LO FREQUENCY (MHz)

(FBB = 1 MHz, I and Q Inputs Driven in

LO

Quadrature at 1.2 V p-p Differential, TA = 25°C)

–20
–22
–24
–26
–28
–30
–32
–34
–36
–38
–40
–42
–44

CARRIER FEEDTHROUGH (dBm)

–46
–48

–50

–40–30–20–100 10203040

VS = 4.75V

Figure 12. Carrier Feedthrough vs. Temperature (F

VS = 5.25V

TEMPERATURE (

VS = 5V

6050 70 80

°

C)

= 2140 MHz, FBB = 1 MHz,

LO

I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential, T

= 25°C)

A

03570-0-011

03570-0-012

Rev. A | Page 8 of 28

AD8349

–10

–15

–20

–25

–30

–35

–40

–45

–50

SIDEBAND SUPPRESSION (dBc)

–55

–60

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

Figure 13. Sideband Suppression vs. F

VS = 5.25V

VS = 5V

LO FREQUENCY (MHz)

LO

VS = 4.75V

(FBB = 1 MHz, I and Q Inputs

Driven in Quadrature at 1.2 V p-p Differential, T

= 25°C)

A

03570-0013

–10

–15

–20

–25

–30

–35

–40

–45

–50

THIRD ORDER DISTORTION (dBc)

–55

–60

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

VS = 5V

Figure 16. Third Order Distortion vs. F

VS = 4.75V

VS = 5.25V

LO FREQUENCY (MHz)

(FBB = 1 MHz, I and Q Inputs

LO

Driven in Quadrature at 1.2 V p-p Differential, TA = 25°C)

03570-0016

–10

–15

–20

–25

–30

–35

–40

–45

–50

SIDEBAND SUPPRESSION (dBc)

–55

–60

1 10 100

VS = 5V

BASEBAND FREQUENCY (MHz)

Figure 14. Sideband Suppression vs. F

VS = 5.25V

(FLO = 2140 MHz, I and Q Inputs

BB

Driven in Quadrature at 1.2 V p-p Differential, T

–30

–35

–40

VS = 5V

VS = 4.75V

VS = 4.75V

= 25°C)

A

03570-0-014

–10

–15

–20

–25

VS = 5V

–30

–35

–40

–45

–50

THIRD ORDER DISTORTION (dBc)

–55

–60

1 10 100

BASEBAND FREQUENCY (MHz)

Figure 17. Third Order Distortion vs. F

VS = 5.25V

(FLO = 2140 MHz, I and Q Inputs

BB

VS = 4.75V

Driven in Quadrature at 1.2 V p-p Differential, T

–30

–35

–40

VS = 4.75V

VS = 5V

VS = 5.25V

= 25°C)

A

03570-0-017

–45

VS = 5.25V

–50

SIDEBAND SUPPRESSION (dBc)

–55

–60

–40–30–20–100 10203040

TEMPERATURE (

°

Figure 15. Sideband Suppression vs. Temperature (F

F

= 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential)

BB

6050 70 80

C)

= 2140 MHz,

LO

03570-0-015

F

Rev. A | Page 9 of 28

–45

–50

THIRD ORDER DISTORTION (dBc)

–55

–60

–40–30–20–100 10203040

TEMPERATURE (

°

Figure 18. Third Order Distortion vs. Temperature (F

= 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p -p Differential)

BB

6050 70 80

C)

= 2140 MHz,

LO

03570-0-018

AD8349

–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70

0.2 0.4 0.6 0.8 1.0 1.4 2.41.2 1.6 1.8 2.0 2.6 2.8 3.0

SSB, dBm

USB, dBC

LO, dBm

BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p)

3USB, dBc

2.2

Figure 19. Third Order Distortion (3USB), Carrier Feedthrough, Sideband

Suppression, and SSB P

(F

= 900 MHz, FBB = 1 MHz, I and Q Inputs Driven in Quadrature, TA = 25°C)

LO

–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70

0.2 0.4 0.6 0.8 1.0 1.4 2.41.2 1.6 1.8 2.0 2.6 2.8 3.0

SSB, dBm

3USB, dBc

BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p)

vs. Baseband Differential Input Level

OUT

LO, dBm

USB, dBc

2.2

10
8
6
4
2
0
–2
–4
–6
–8
–10
–12
–14

10
8
6
4
2
0
–2
–4
–6
–8
–10
–12
–14

03570-0-019

03570-0-020

160

155

150

145

140

135

130

125

SUPPLY CURRENT (mA)

120

115

110

–40–30–20–100 10203040

VS = 5.25V

VS = 4.75V

TEMPERATURE (

Figure 22. Power Supply Current vs. Temperature

200Ω

VS = 5V

°

C)

500Ω

NO TERMINATION

6050 70 80

03570-0-022

Figure 20. Third Order Distortion (3USB), Carrier Feedthrough, Sideband

Suppression, and SSB P

(F

= 1900 MHz, FBB = 1 MHz, I and Q Inputs Driven in Quadrature, TA = 25°C)

LO

–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70

0.2 0.4 0.6 0.8 1.0 1.4 2.41.2 1.6 1.8 2.0 2.6 2.8 3.0

BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p)

vs. Baseband Differential Input Level

OUT

3USB, dBc

SSB, dBm

LO, dBm

USB, dBc

2.2

10
8
6
4
2
0
–2
–4
–6
–8
–10
–12
–14

Figure 21. Third Order Distortion (3USB), Carrier Feedthrough, Sideband

Suppression, and SSB P

(F

= 2140 MHz, FBB = 1 MHz, I and Q Inputs Driven in Quadrature, TA = 25°C)

LO

vs. Baseband Differential Input Level

OUT

03570-0-021

Rev. A | Page 10 of 28

Figure 23. Smith Chart of LOIP Port S

(LOIN Pin AC-Coupled

11

to Ground). Curves with Balun and External Termination

Resistors Also Shown (T

0

–5

–10

–15

–20

–25

–30

RETURN LOSS (dB)

–35

–40

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

Figure 24. Return Loss

VS = 5V

FREQUENCY (MHz)

⏐

S

22

= 25°C)

A

⏐

of V

Output (TA = 25°C)

OUT

03570-0023

03570-0-024

AD8349

30
28
26
24
22
20
18
16
14
12

PERCENTAGE

10

8
6
4
2
0

–157.0

–156.5

–156.0

–155.5

–155.0

–154.5

–154.0

–153.5

–153.0

20

18

16

14

12

10

PERCENTAGE

8

6

4

2

0

–152.0

–151.5

–151.0

–150.5

–150.0

–149.5

–149.0

–148.5

–148.0

–147.5

–147.0

NOISE FLOOR (dBm/Hz)

Figure 25. 20 MHz Offset Noise Floor Distribution at F

(BB Inputs at a Bias of 400 mV with no AC signal, T

30
28
26
24
22
20
18
16
14
12

PERCENTAGE

10

8
6
4
2
0

–158.0

–157.5

–156.5

–157.0

NOISE FLOOR (dBm/Hz)

–156.0

–155.5

Figure 26. 20 MHz Offset Noise Floor Distribution at F

(BB Inputs at a Bias of 400 mV with no AC signal, T

30
28
26
24
22
20
18
16
14
12

PERCENTAGE

10

8
6
4
2
0

–159.0

–158.5

–158.0

–157.5

–157.0

–156.5

–155.0

–156.0

= 900 MHz

LO

= 25°C)

A

–154.5

–154.0

= 1900 MHz

LO

= 25°C)

A

–155.5

–155.0

03570-0-025

03570-0-026

NOISE FLOOR (dBm/Hz)

–149.0

–150.0

= 940 MHz

LO

–148.5

= 1960 MHz

LO

–149.5

Figure 28. 20 MHz Offset Noise Floor Distribution at F

(F

= 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p, TA = 25°C)

BB

28
26
24
22
20
18
16
14
12

PERCENTAGE

10

8
6
4
2
0

–152.5

–152.0

–151.5

–151.0

–150.5

NOISE FLOOR (dBm/Hz)

–150.0

–149.5

Figure 29. 20 MHz Offset Noise Floor Distribution at F

(F

= 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p, TA = 25°C)

BB

30
28
26
24
22
20
18
16
14
12

PERCENTAGE

10

8
6
4
2
0

–153.0

–152.5

–152.0

–151.5

–151.0

–150.5

03570-0-028

–148.0

03570-0-029

–149.0

NOISE FLOOR (dBm/Hz)

Figure 27. 20 MHz Offset Noise Floor Distribution at F

(BB Inputs at a Bias of 400 mV with no AC signal, T

= 2140 MHz

LO

= 25°C)

A

03570-0-027

(F

Rev. A | Page 11 of 28

NOISE FLOOR (dBm/Hz)

Figure 30. 20 MHz Offset Noise Floor Distribution at F

= 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p, TA = 25°C)

BB

= 2140 MHz

LO

03570-0-030

AD8349

–140

–142

–144

–146

–148

–150

–152

–154

NOISE FLOOR (dBm/Hz)

–156

–158

–160

–10 2

–8 –6 –4 –2 0

Figure 31. 20 MHz Offset Noise Floor vs. LO Input Power

= 2140 MHz, TA = 25°C)

(F

LO

WITH AC INPUT

WITHOUT AC INPUT

LO INPUT (dBm)

03570-0-031

35

30

25

20

15

PERCENTAGE

10

5

0

MAGNITUDE IMBALANCE (dB)

–0.100–0.125–0.175 –0.150–0.200 –0.075 –0.050 –0.025 0

Figure 34. I and Q Inputs Quadrature Phase Imbalance Distribution

= 2140 MHz, FBB = 1 MHz, I and Q Inputs Driven in

(F

LO

Quadrature at 1.2 V p-p Differential, T

= 25°C)

A

03570-0-034

–10

–15

–20

–25

–30

–35

–40

–45

–50

CARRIER FEEDTHROUGH (dBm)

–55

–60

Figure 32. Carrier Feedthrough vs. LO Input Power (F

FLO = 1900MHz

FLO = 2140MHz

FLO = 900MHz

–6 –4–10 –8 –2 0 2

LO INPUT (dBm)

= 1 MHz, I and Q

BB

Inputs Driven in Quadrature at 1.2 V p-p Differential, TA = 25°C)

–10

–15

–20

–25

–30

–35

–40

–45

–50

SIDEBAND SUPPRESSION (dBc)

–55

–60

FLO = 1900MHz

Figure 33. Sideband Suppression vs. LO Input Power (F

FLO = 900MHz

FLO = 2140MHz

–6 –4–10 –8 –2 0 2

LO INPUT (dBm)

= 1 MHz, I and Q

BB

Inputs Driven in Quadrature at 1.2 V p-p Differential, T

= 25°C)

A

03570-0032

03570-0033

35

30

25

20

15

PERCENTAGE

10

5

0

0.50 0.750 0.25 1.00 1.25 1.50

PHASE (I-Q) IMBALANCE (Degrees)

Figure 35. I and Q Inputs Amplitude Imbalance Distribution

= 2140 MHz, FBB = 1 MHz, I and Q Inputs Driven in

(F

LO

Quadrature at 1.2 V p-p Differential, T

35

30

25

20

15

PERCENTAGE

10

5

0

Figure 36. OP1dB Distribution. (F

5.04.5 5.5 6.0 6.5
OP1dB (dBm)

= 2140 MHz, FBB = 1 MHz, I and Q Inputs

Driven in Quadrature, T

LO

= 25°C)

A

= 25°C)

A

03570-0-035

03570-0-036

Rev. A | Page 12 of 28

AD8349

20

18

16

14

12

10

8

PERCENTAGE

6

4

2

0

–80 –70 –60 –50 –40 –30

CARRIER FEEDTHROUGH (dBm)

Figure 37. Carrier Feedthrough Distribution at F

= 900 MHZ (FBB = 1 MHz,

LO

I and Q Inputs Driven in Quadrature at 1.2 V p-p, T

= 25°C)

A

03570-0-039

35

30

25

20

15

PERCENTAGE

10

5

0

–70

T = +85°C
T = –40°C

–65 –60 –55 –50

CARRIER FEEDTHROUGH (dBm)

AFTER NULLING TO < –65dBm AT +25°C

–45

Figure 40. Carrier Feedthrough Distribution at Temperature Extremes, After

Carrier Feedthrough Nulled to < - 65 dBm at T

= 25°C. (FLO = 2140 MHz,

A

I and Q Inputs at a bias of 400 mV )

03570-0-037

40

35

30

25

20

15

PERCENTAGE

10

5

0

–60 –45 –40 –35 –30 –25

–55 –50

CARRIER FEEDTHROUGH (dBm)

Figure 38. Carrier Feedthrough Distribution at F

= 1900 MHz (FBB = 1 MHz,

LO

I and Q Inputs Driven in Quadrature at 1.2 Vp-p, T

24
22
20
18
16
14
12
10

PERCENTAGE

8
6
4
2
0

–70 –65 –60 –55 –50 –45 –40 –35 –30

CARRIER FEEDTHROUGH (dBm)

Figure 39. Carrier Feedthrough Distribution at F

= 2140 MHz (FBB = 1 MHz,

LO

I and Q Inputs Driven in Quadrature at 1.2 V p-p, T

= 25°C)

A

= 25°C)

A

03570-0-040

03570-0-041

30
28
26
24
22
20
18
16
14
12

PERCENTAGE

10

8
6
4
2
0

–75

T = +85°C
T = –40°C

–70

–65 –60 –55 –50

SIDEBAND SUPPRESSION (dBc)

AFTER NULLING TO < –50dBc AT +25°C

–45

–40

–35

Figure 41. Sideband Suppression Distribution at Temperature Extremes, After

Sideband Suppression Nulled to < -50 dBc at T

F

= 1 MHz, I and Q Inputs biased at 0.4 V)

BB

= 25°C. (FLO = 2140 MHz,

A

03570-0-038

Rev. A | Page 13 of 28

AD8349

CIRCUIT DESCRIPTION

OVERVIEW

The AD8349 can be divided into five sections: the local oscil­lator (LO) interface, the baseband voltage-to-current (V-to-I)
converter, the mixers, the differential-to-single-ended (D-to-S)
amplifier, and the bias circuit. A detailed block diagram of the
device is shown in Figure 42.

V-TO-I CONVERTER

The differential baseband input voltages that are applied to the
baseband input pins are fed to two op amps that perform a
differential voltage-to-current conversion. The differential
output currents of these op amps then feed each of their
respective mixers.

LOIP

LOIN

IBBP
IBBN

QBBP
QBBN

Figure 42. Block Diagram

PHASE

SPLITTER

Σ

OUT

03570-0-043

The LO interface generates two LO signals at 90 degrees of
phase difference to drive two mixers in quadrature. Baseband
signals are converted into currents by the V-to-I converters,
which feed into the two mixers. The outputs of the mixers
combine to feed the differential-to-single-ended amplifier,
which provides a 50 Ω output interface. Reference currents to
each section are generated by the bias circuit. Additionally, the
RF output is controlled by an output enable pin (ENOP), which
is capable of switching the output on and off within 50 ns. A
detailed description of each section follows.

LO INTERFACE

The LO interface consists of interleaved stages of buffer
amplifiers and polyphase phase splitters. An input buffer
provides a 50 Ω termination to the LO signal source driving
LOIP and LOIN. The buffer also increases the LO signal
amplitude to drive the phase splitter. The phase splitter is
formed by an R-C polyphase network that splits the buffered
LO signal into two parts in precise quadrature phase relation
with each other. Each LO signal then passes through a buffer
amplifier to compensate for the signal loss through the phase
splitter. The two signals pass through another polyphase
network to enhance the quadrature accuracy over the full
operating frequency range. The outputs of the second phase
splitter are fed into the driver amplifiers for the mixers’ LO
inputs.

MIXERS

The AD8349 has two double-balanced mixers, one for the in­phase channel (I channel) and one for the quadrature channel
(Q channel). Both mixers are based on the Gilbert cell design of
four cross-connected transistors. The output currents from the
two mixers sum together in a pair of resistor-inductor (R-L)
loads. The signals developed across the R-L loads are sent to the
D-to-S amplifier.

D-TO-S AMPLIFIER

The output D-to-S amplifier consists of two emitter followers
driving a totem pole output stage. Output impedance is estab­lished by the emitter resistors in the output transistors. The
output of this stage connects to the output (VOUT) pin.

BIAS CIRCUIT

A band gap reference circuit generates the proportional-to­absolute-temperature (PTAT) reference currents used by
different sections. The band gap reference circuit also generates
a temperature stable current in the V-to-I converters to produce
a temperature independent slew rate.

OUTPUT ENABLE

During normal operation (ENOP = high), the output current
from the V-to-I converters feeds into the mixers, where they
mix with the two phases of LO signals. When ENOP is pulled
low, the V-to-I output currents are steered away from the
mixers, thus turning off the RF output. Power to the final stage
of LO drivers is also removed to minimize LO feedthrough.
Even when the output is disabled, the differential-to-single­ended stage is still powered up to maintain constant output
impedance.

Rev. A | Page 14 of 28

AD8349

BASIC CONNECTIONS

The basic connections for operating the AD8349 are shown in
Figure 43. A single power supply of between 4.75 V and 5.5 V is
applied to pins VPS1 and VPS2. A pair of ESD protection diodes
connect internally between VPS1 and VPS2, so these must be
tied to the same potential. Both pins should be individually
decoupled using 100 pF and 0.1 μF capacitors to ground. These
capacitors should be located as close as possible to the device.
For normal operation, the output enable pin, ENOP, must be
pulled high. The turn-on threshold for ENOP is 2 V. Pins
COM1, COM2, and COM3 should all be tied to the same
ground plane through low impedance paths.

BASEBAND I AND Q INPUTS

The I and Q inputs should be driven differentially. The typical
differential drive level (as used for characterization measure­ments) for the I and Q baseband signals is 1.2 V p-p, which is
equivalent to 600 mV p-p on each baseband input. The base­band inputs have to be externally biased to a level between

mV and 500 mV. The optimum level for the best perfor-

400
mance is 400 mV. The recommended drive level of 1.2 V p-p
does not indicate a maximum drive level. If operation closer to
compression is desired, the 1.2 V p-p differential limit can be
exceeded.

For baseband signals with a high peak-to-average ratio (e.g.,
CDDA or WCDMA), the peak signal level will have to be below
the AD8349’s compression level in order to prevent clipping of
the signal peaks. Clipping of signal peaks increases distortion.
In the case of CDMA and WCDMA inputs, clipping results in
an increase of signal leakage into adjacent channels. In general,
the baseband drive should be at a level where the peak signal

power of the output signal is at least a crest factor below the
AD8349’s output compression point. Refer to the Applications
section for drive-level considerations in WCDMA and
GSM/EDGE systems.

Reducing the baseband drive level also has the benefit of
increasing the bandwidth of the baseband input. This would
allow the AD8349 to be used in applications requiring a high
modulation bandwidth, e.g., as the IF modulator in high data­rate microwave radios.

SINGLE-ENDED BASEBAND DRIVE

Where only single-ended I and Q signals are available, a
differential amplifier, such as the AD8132 or AD8138, can be
used to generate the required differential drive signal for the
AD8349.

Figure 44 shows an example of a circuit that converts a ground­referenced, single-ended signal to a differential signal, and adds
the required 400 mV bias voltage.

The baseband inputs can also be driven with a single-ended
signal biased to 400 mV, with the unused inputs biased to
400 mV dc. This mode of operation is not recommended,
however, because any dc level difference between the bias level
of the drive signal and the dc level on the unused input
(including the effect of temperature drift), can result in
increased LO feedthrough. Additionally, the maximum low
distortion output power will be reduced by 6 dB.

IP

IN

200Ω

5

ETC1-1-13

LO

+V

S

4

0.1µF

1

200Ω

2

3

100pF

100pF
100pF

T1

1

IBBP

2

IBBN

3

COM1

4

COM1

AD8349

5

LOIN

6

LOIP

7

VPS1

8

ENOP

QBBP

QBBN

COM3

COM3

VPS2

VOUT

COM3

COM2

16

15

14

13

12

11

10

9

100pF

0.1µF

100pF

QP

QN

+V

S

VOUT

03570-0-044

Figure 43. Basic Connections

Rev. A | Page 15 of 28

AD8349

+5V

10kΩ

+

0.1µF

0.1µF

10µF

+

+

10µF

10µF

+

10µF

0.1µF

100pF

IBBP

IBBN

QBBP

QBBN

VPS1

COM1

PHASE

SPLITTER

AD8349

COM2

VPS2

COM3

100pF

Σ

0.1µF

VOUT

LOIP

LOIN

03570-0-045

866Ω

49.9Ω

24.8Ω

49.9Ω

24.9Ω

499Ω

499Ω

499Ω

499Ω

0.1µF

0.1µF

I

IN

Q

IN

499Ω

499Ω

499Ω

499Ω

8

2

AD8132

1

8

2

AD8132

1

0.1µF

3

5

4

6

–5V

+5V

0.1µF

3

5

4

6

–5V

Figure 44. Single-Ended IQ Drive Circuit

LO INPUT DRIVE LEVEL

The local oscillator inputs are designed to be driven differen­tially. The device is specified with an LO drive level of –6 dBm.
This level was chosen to provide the best noise performance.
Increasing the LO drive level degrades sideband suppression
and increases carrier feedthrough, while improving noise
performance. Reducing the LO drive level creates the opposite
effect: improved sideband suppression and reduced carrier
feedthrough.

FREQUENCY RANGE

The LO frequency range is from 700 MHz to 2700 MHz. These
limits are defined by the nature of the LO phase splitter
circuitry. The phase splitter generates LO drive signals for the
internal mixers, which are 90 degrees out of phase from each
other. Outside of the specified frequency range (700 MHz to
2700 MHz), this quadrature accuracy degrades, resulting in
poor sideband rejection performance. Figure 45 and Figure 46
show the sideband suppression of a typical device operating
outside the specified LO frequency range. The level of sideband
suppression and degradation is also influenced by manufac­turing process variations.

Rev. A | Page 16 of 28

LO INPUT IMPEDANCE MATCHING

Single-ended LO sources are transformed into a differential
signal via a 1:1 balun (ETC1-1-13). A 200 Ω shunt resistor to
GND on each LO input on the device side of the balun reduces
the return loss for the LO input port. Because the LO input pins
are internally dc-biased, ac coupling capacitors must be used on
each LO input pin.

AD8349

4.0

3.5

3.0

2.5

2.0

SSB OUTPUT POWER (dBm)

1.5

1.0
300 350 400 450 500 550 600 650 700

LO FREQUENCY (MHz)

SSB

Figure 45. Sideband Suppression below 700 MHz

0

–1

–2

–3

–4

–5

–6

SSB OUTPUT POWER (dBm)

–7

USB

SSB

USB

0

–10

–20

–30

–40

SIDEBAND SUPPRESSION (dBc)

–50

–60

03570-0-046

–40

–41

RF OUTPUT

The RF output is designed to drive a 50 Ω load, but should be

–42

–43

ac-coupled, as shown in Figure 43, because of internal dc
biasing. The RF output impedance is close to 50 Ω and provides
fairly good return loss over the specified operating frequency

–44

–45

range (see Figure 24). As a result, no additional matching
circuitry is required if the output is driving a 50 Ω load. The
output power of the AD8349 under nominal conditions

–46

SIDEBAND SUPPRESSION (dBc)

–47

(1.2
bias, and a 5 V supply) is shown in Figure 7.

–10

–15

–20

–25

–30

–35

–40

–45

–50

CARRIER FEEDTHROUGH (dBm)

–55

–60

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

SINGLE-ENDED LO DRIVE

DIFFERENTIAL LO DRIVE

LO FREQUENCY (MHz)

Figure 48. LO Feedthrough vs. Frequency, Single-Ended vs. Differential LO

Drive (Single-Sideband Modulation)

V p-p differential baseband drive, 400 mV dc baseband

03570-0-049

–8

2700 2750 2800 2850 2900 2950 3000

LO FREQUENCY (MHz)

–48

Figure 46. Sideband Suppression above 2700 MHz

SINGLE-ENDED LO DRIVE

The LO input can be driven single-ended at the expense of
higher LO feedthrough at most frequencies (see Figure 48).
LOIN is ac-coupled to ground, and LOIP is driven through a
coupling capacitor from a single-ended 50 Ω source (see
Figure 47).

A 400 Ω shunt resistor on the signal-source side of the ac
coupling capacitor was used for the measurement.

100pF

5

LOIN

100pF

LO

400Ω

6

Figure 47. Schematic for Single-Ended LO Drive

LOIP

AD8349

03570-0-048

03570-0-047

OUTPUT ENABLE

The ENOP pin can be used to turn the RF output on and off.
This pin should be held high (greater than 2 V) for normal
operation. Taking ENOP low (less than 800 mV) disables the
output power and provides an off-isolation level of < –50 dBm
at the output.

Figure 49 and Figure 50 show the enable and disable time
domain responses of the ENOP function at 900 MHz. Typical
enable and disable times are approximately 20 ns and
50 ns, respectively.

8

6

4

2

(V)

0

ENOP

V

–2

–4

–6

–8

0 20 10040 60 80

TIME (ns)

Figure 49. ENOP Enable Time, 900 MHz

800

600

400

200

0

–200

–400

–600

–800

(mV)

VOUT

V

03570-0-050

Rev. A | Page 17 of 28

AD8349

8

6

4

2

(V)

0

ENOP

V

–2

–4

–6

–8

0 20 10040 60 80

TIME (ns)

Figure 50. ENOP Disable Time, 900 MHz

BASEBAND DAC INTERFACE

The recommended baseband input swing and bias levels of the
AD8349’s differential baseband inputs allow for direct
connection to most baseband DACs without the need for any
external active components. Typically these DACs have a
differential full-scale output current from 0 mA to 20 mA on
each differential output. These currents can be easily converted
to voltages using ground-referenced shunt resistors. Most
baseband DACs for transmit chains are designed with two
DACs in a single package.

AD9777 INTERFACE

The AD977x family of dual DACs is well suited to driving the
baseband inputs of the AD8349. The AD9777 is a dual 16-bit
DAC that can generate either a baseband output or a complex
IF using the device’s complex modulator.

The basic interface between the AD9777’s I
AD8349’s differential baseband inputs is shown in Figure 51.
The Resistors R1 and R2 set the dc bias level, and R3 sets the
amplitude of the baseband input voltage swing.

AD9777 AD8349

73

I

OUTA1

I

OUTB1

I

OUTA2

I

OUTB2

R1I

R2I

72

69

R1Q

R2Q

68

OPTIONAL

LOW-PASS

FILTER

OPTIONAL
LOW-PASS

FILTER

outputs and the

OUT

R3I

R3Q

800

600

400

200

(mV)

0

V

–200

–400

–600

–800

1

IBBP

2

IBBN

16

QBBP

15

QBBN

VOUT

03570-0-051

1.50

1.35

1.20

1.05

0.90

0.75

0.60

0.45

DIFFERENTIAL IQ SWING (V p-p)

0.30

0.15
10 100 1.10

R3 (Ω)

3

03570-0-053

Figure 52. Relationship Between R3 in Figure 51 and Peak

Baseband Input Voltage

BIASING AND FILTERING

A value of 40 Ω on R1 and R2 in Figure 51 will generate the
required 400 mV dc bias. Note that this is independent of the
value of R3. Figure 52 shows the relationship between the value
of R3 and the peak baseband input voltage with the 40 Ω
resistors in place. From Figure 52, it can be seen that a value of
240 Ω will provide a peak-to-peak swing of approximately

V p-p differential into the AD8349’s baseband inputs.

1.2

The closest available resistor values are 40.2 Ω and 240 Ω, and
these values were used in the characterization of the AD8349
when the DAC was used as a signal source.

When using a DAC, low-pass image reject filters are typically
used to eliminate images that are produced by the DAC. They
provide the added benefit of eliminating broadband noise that
might feed into the modulator from the DAC.

Figure 53 shows a single sideband spectrum at 2140 MHz. The
baseband sine and cosine signals come from the digital output
of a Rohde & Schwarz AMIQ arbitrary waveform generator.
These signals drive the AD9777 dual DAC, which in turn drives
the AD8349’s baseband inputs. Note that the AD9777’s complex
modulator is not being used.

Due to offset voltages, internal device mismatch, and imperfect
quadrature over the AD8349’s operating range, the SSB
spectrum has a number of undesirable components such as LO
feedthrough and undesired sideband leakage. When the
AD8349 is driven by a modulated baseband signal, (e.g. 8-PSK,
GMSK, QPSK, or QAM), t hese nonidealities will manifest
themselves as degraded error vector magnitude (EVM) and
degraded spectral purity.

Figure 51. Basic AD9777 to AD8349 Interface

03570-0-052

Rev. A | Page 18 of 28

AD8349

10

0

–10

–20

–30

–40

–50

AMPLITUDE (dBm)

–60

–70

–80

–90

E

C

E

T

N

2

R

.

14G

z

H

Figure 53. AD8349 Single Sideband Spectrum at 2140 MHz

THIRD HARMONIC = –36.8dBc

SSB = 1.7dBm

LO = –44.5dBm

USB = –52dBc

SPAN 10MHz

03570-0-054

REDUCING UNDESIRED SIDEBAND LEAKAGE

Undesired sideband leakage is the result of phase and amplitude
imbalances between the I and Q channel baseband signals.
Therefore, to reduce the undesired sideband leakage, the
amplitude and phase of the baseband signals have to be
matched at the mixer cores. Because of mismatches in the
baseband input paths leading to the mixers, perfectly matched
baseband signals at the pins of the device may not be perfectly
matched when they reach the mixers. Therefore, slight
adjustments have to be made to the phase and amplitudes of the
baseband signals to compensate for these mismatches.

Begin by making one of the inputs, say the I channel, the
reference signal. Then adjust the amplitude and phase of the
Q channel’s signal until the unwanted sideband power reaches a
trough. The AD9777 has built-in gain adjust registers that allow
this to be performed easily. If an iterative adjustment is
performed between the amplitude and the phase, the undesired
sideband leakage can be minimized significantly.

Note that the compensated sideband rejection performance
degrades as the operating baseband frequency is moved away
from the frequency at which the compensation was performed.
As a result, the frequency of the I and Q sine waves should be
approximately half the baseband bandwidth of the modulated
carrier. For example, if the modulator is being used to transmit
a single WCDMA carrier whose baseband spectrum spans from
dc to 3.84/2 MHz, the calibration could be effectively performed
with 1 MHz I and Q sine waves.

REDUCTION OF LO FEEDTHROUGH

Because the I and Q signals are being multiplied with the LO,
any internal offset voltages on these inputs will result in leakage
of the LO to the output. Additionally, any imbalance in the LO
to RF in the mixers will also cause the LO signal to leak through
the mixer to the RF output. The LO feedthrough is clearly
visible in the single sideband spectrum. The nominal LO
feedthrough of –42 dBm can be reduced further by applying
offset compensation voltages on the I and Q inputs. Note that

the LO feedthrough is reduced by varying the differential offset
voltages on the I and Q inputs (xBBP – xBBN), not by varying
the nominal bias level of 400 mV. This is easily accomplished by
programming and then storing the appropriate DAC offset code
required to minimize the LO feedthrough. This, however,
requires a dc-coupled path from the DAC to the I and Q inputs.

The procedure for reducing the LO feedthrough is simple. A
differential offset voltage is applied from the I DAC until the LO
feedthrough reaches a trough. With this offset level held, a
differential offset voltage is applied to the Q DAC until a lower
trough is reached (This is an iterative process).

Figure 54 shows a plot of LO feedthrough vs. I channel offset (in
mV) after the Q channel offset has been nulled. This suggests
that the compensating offset voltage should have a resolution of
at least 100 µV to reduce the LO feedthrough to be less than –
65 dBm. Figure 55 shows the single sideband spectrum at 2140
MHz after the nulling of the LO. The reduced LO feedthrough
can clearly be seen when compared with the performance
shown in Figure 53.

Compensated LO feedthrough degrades somewhat as the LO
frequency is moved away from the frequency at which the
compensation was performed. This variation is very small
across a 30 MHz or 60 MHz cellular band, however. This small
variation is due to the effects of LO-to-RF output leakage
around the package and on the board.

–52

–54

–56

–58

–60

–62

–64

–66

CARRIER FEEDTHROUGH (dBm)

–68

–70

3.0 4.0 4.5 5.0 5.53.5

IOPP-IOPN (mV)

Figure 54. Plot of LO Feedthrough vs. I Channel Baseband Offset

(Q Channel Offset Nulled)

03570-0-055

Rev. A | Page 19 of 28

AD8349

10

0

–10

–20

–30

–40

–50

AMPLITUDE (dBm)

–60

–70

–80

–90

C

N

E

TER

2

.

1

4

G

H

z

THIRD HARMONIC = –36.8dBc

Figure 55. AD8349 Single Sideband Spectrum at 2140 MHz after LO Nulling

SIDEBAND SUPPRESSION AND LO FEEDTHROUGH VS. TEMPERATURE

In practical applications, reduction of LO feedthrough and
undesired sideband suppression can be performed as a one time
calibration, with the required correction factors being stored in
nonvolatile RAM. These compensation schemes hold up well
over temperature. Figure 40 and Figure 41 show the variation in
LO feedthrough and sideband suppression over temperature
after compensation is performed at 25°C.

SINGLE SIDEBAND PERFORMANCE VS. BASEBAND
DRIVE LEVEL

Figure 56 shows the SSB output power and noise floor in
dBc/100 kHz versus baseband drive level at LO frequencies of
940 MHz, 1960 MHz, and 2140 MHz.

SSB = 1.7dBm

LO = –71.4dBm

USB = –52dBc

SPAN 10MHz

03570-0-077

IMPROVING THIRD HARMONIC DISTORTION

While sideband suppression can be improved by adjusting the
relative baseband amplitudes and phase, the only means
available to reduce the third harmonic is to reduce the output
power. (See Figure 19, Figure 20, and Figure 21). It is worth
noting, however, that as the output power is reduced, the noise
floor, in dBc, stays fairly constant at the higher end of the power
curve (Figure 56). This indicates that the output power can be
reduced to a level that yields an acceptable third harmonic
without incurring a signal-to-noise ratio penalty. The constant
SNR vs. output power relationship also indicates that baseband
voltage variations can be effectively used to control system
output power and/or regulate signal chain gain.

6

4

2

0

–2

–4

–6

–8

SSB OUTPUT POWER (dBm)

–10

–12

–14

0.2 0.3 0.4 0.5 0.80.6 0.9 1.0 1.21.1

Figure 56. SSB P

940 SSB
1960 SSB
2140 SSB

1960 20 MHz NOISE
940 20 MHz NOISE
2140 20 MHz NOISE

0.7

DIFFERENTIAL BASEBAND DRIVE (V p-p)

and 20 MHz Noise Floor vs. Baseband Drive Level

OUT

(F

= 940 MHz, 1960 MHz, and 2140 MHz)

LO

–84

–86

–88

–90

–92

–94

–96

–98

–100

–102

–104

20 MHz NOISE FLOOR (dBC/100kHz)

03570-0-056

Rev. A | Page 20 of 28

AD8349

APPLICATIONS

3GPP WCDMA SINGLE-CARRIER APPLICATION

The interpolation filter used for the measurement of WCDMA
performance is shown in Figure 57. This third order Bessel filter
has a 3 dB bandwidth of 12 MHz. While the 3GPP single
channel bandwidth is only 3.84 MHz, this wide 3 dB bandwidth
of 12 MHz was driven by the need for a flat group delay out to
at least half the bandwidth of the baseband signal. Figure 58
shows a plot of a WCDMA spectrum at 2140 MHz using the

GPP Test Model 1 (64 channels active). At an output power of

3
–17.3 dBm, an adjacent channel power ratio (ACPR) just shy of
–69 dBc was measured.

Figure 59 shows the variation in ACPR with output power at
1960 MHz and 2140 MHz. It also shows the noise floor
measured at an offset of 30 MHz from the center of the modu­lated WCDMA signal. From the graphs, it can be seen that there
is an optimal output power at which to operate that delivers the
best ACPR. If the output power is increased beyond that point,
the ACPR degrades as the result of increased distortion. Below
that optimum, the ACPR degrades due to a reduction in the
signal-to-noise ratio of the signal.

AD9777 AD8349

73

I

OUTA1

I

OUTB1

I

OUTA2

I

OUTB2

40.2Ω

40.2Ω

72

69

40.2Ω

40.2Ω

68

Figure 57. Single-Carrier WCDMA Application Circuit

(DAC-Modulator Interconnect)

–33
–40

–50

–60

–70

–80

–90

–100

AMPLITUDE (dBm)

–110

–120

–130

ALT

LO

C

N

E

T

E

ADJ

LO

R

2

.

1

4

G

H

z

Figure 58. Single-Carrier WCDMA Spectral Plot at 2140 MHz,

including Adjacent and Alternate Channel Power Ratio

100pF

100pF

680nH

270pF

680nH

680nH

270pF

680nH

CH

1

240Ω

2

16

QBBP

240Ω

15

QBBN

CH PWR = –17.3dBm
ADJ CPR = –68.7dB
ALT CPR = –72.7dB

ADJ

UP

ALT

UP

SPAN 24.6848MHz

IBBP

IBBN

03570-0-059

03570-0-058

–62
–63
–64
–65
–66
–67

2140 ADJ CPR

–68

ACPR (dB)

–69
–70
–71
–72

1960 NOISE

2140 NOISE

–26 –24 –22 –20

1960 ADJ CPR

–

1

–16 –14 –12 –10 –8

8

CHANNEL POWER (DBM)

Figure 59. Single-Carrier WCDMA ACPR and Noise Floor (dBm/Hz) at 30 MHz

Carrier Offset vs. Channel Power at 1960 MHz and 2140 MHz

(Test Model 1 with 64 Active Channels)

WCDMA MULTICARRIER APPLICATION

The high dynamic range of the AD8349 also permits use in
multicarrier WCDMA applications. Figure 60 shows a 4-carrier
WCDMA spectrum at 1960 MHz. At a per-carrier power of
–24.2 dBm, an ACPR of –60.4dB is achieved. Figure 61 shows
the variation in ACP and noise floor (dBc/Hz) with output
power.

–30

CH PWR = –24.2dBm
ADJ CPR = –60.4dB

–40

ALT CPR = –63.1dB

–50

–60

–70

–80

–90

AMPLITUDE (dBm)

–100

–110

–120

–130

C

N

E

E

T

R

1

.

9

6

G

H

z

4

H

M

/

z

Figure 60. 4-Carrier WCDMA Spectral Plot at 1960 MHz,

Including Adjacent and Alternate Channel Power Ratio

SPAN 40MHz

–147
–148
–149
–150
–151
–152
–153
–154
–155
–156
–157

NOISE FLOOR (dBm/Hz)

03570-0-062

03570-0-060

Rev. A | Page 21 of 28

AD8349

–54
–55
–56
–57
–58
–59
–60
–61
–62

ALT AND ADJ CPR (dB)

–63
–64
–65
–66

1960 NOISE

2140 NOISE

–29 –28 –27 –26 –25 –24 –23 –22 –21 –20 –19 –18 –17

CHANNEL POWER (dBm)

2140 ADJ CPR

1960 ADJ CPR

2140 ALT CPR

1960 ALT CPR

–144

–146

–148

–150

–152

–154

–156

Figure 61. 4-Carrier WCDMA Adjacent and Alternate Channel Power Ratio

and 50 MHz Noise Floor (dBm/Hz) vs. Per-Channel Power

at 1960 MHz and 2140 MHz

GSM/EDGE APPLICATION

Figure 62 and Figure 64 show plots of GMSK error vector
magnitude (EVM), spectral performance, and noise floor
(dBc/100 kHz at 6 MHz carrier offset) at 885 MHz and

MHz. Based on spectral performance, a maximum output

1960
power level of around 2 dBm is appropriate. Note, however, that
as the output power decreases below this level, there is only a
very slight increase in the dBc noise floor. This indicates that
baseband drive variation can be used to control or correct the
gain of the signal chain over a range of at least 5 dB, with little
or no SNR penalty.

Figure 63 and Figure 65 show plots of 8-PSK EVM, spectral
performance, and noise floor at 885 MHz and 1960 MHz.

An LO drive level of approximately –6 dBm is recommended
for GMSK and 8-PSK. A higher LO drive power will improve
the noise floor slightly; however, it also tends to degrade EVM.

–50
–55
–60
–65
–70
–75
–80
–85
–90

–95
–100
–105

6MHz OFFSET NOISE FLOOR (dBc/100kHz)

400kHz AND 600kHz SPECTRAL MASK (dBc/30kHz)

–110

EVM

PEAK NOISE FLOOR

AVERAGE NOISE FLOOR

–2–4–8 –6–10 0246

CHANNEL POWER (dBm)

Figure 62.GMSK EVM, Spectral Performance, and Noise Floor

vs. Channel Power (Frequency = 885 MHz)

400kHz

600kHz

4.0

3.5

3.0

2.5

2.0

1.5

1.0

50MHz NOISE FLOOR (dBm/Hz)

03570-0063

EVM%

03570-0065

–50
–55
–60
–65
–70
–75
–80
–85

PEAK NOISE FLOOR

–90

–95
–100
–105

6MHz OFFSET NOISE FLOOR (dBc/100kHz)

400kHz AND 600kHz SPECTRAL MASK (dBc/30kHz)

–110

600kHz

EVM

AVERAGE NOISE FLOOR

–6–8–12 –10–14 –4 –2 0 4

CHANNEL POWER (dBm)

400kHz

4.0

3.5

3.0

2.5

2.0

1.5

1.0

2

Figure 63. 8-PSK EVM, Spectral Performance, and Noise Floor

vs. Channel Power (Frequency = 885 MHz)

–50

–55

–60

–65

–70

–75

–80

–85

–90

–95
–100
–105

6MHz OFFSET NOISE FLOOR (dBc/100kHz)

400kHz AND 600kHz SPECTRAL MASK (dBc/30kHz)

–110

400kHz

600kHz

PEAK NOISE FLOOR

AVERAGE NOISE FLOOR

EVM

–5–7–11 –9–13 –3 –1 1 5

CHANNEL POWER (dBm)

4.0

3.5

3.0

2.5

2.0

1.5

1.0

3

Figure 64. GMSK EVM, Spectral Performance, and Noise Floor

vs. Channel Power (Frequency = 1960 MHz)

–50

–55

–60

–65

–70

–75

–80

–85

–90

–95
–100

6MHz OFFSET NOISE FLOOR (dBc/100kHz)

–105

400kHz AND 600kHz SPECTRAL MASK (dBc/30kHz)

–110

400kHz

600kHz

PEAK NOISE FLOOR

AVERAGE NOISE FLOOR

EVM

–6–8–12 –10–14 –4 –2 0 2

CHANNEL POWER (dBm)

4.0

3.5

3.0

2.5

2.0

1.5

1.0

Figure 65. 8-PSK EVM, Spectral Performance, and Noise Floor vs. Channel

Power (Frequency = 1960 MHz)

EVM%

03570-0066

EVM%

03570-0067

EVM%

03570-0068

Rev. A | Page 22 of 28

AD8349

SOLDERING INFORMATION

The AD8349 is available in a 16-lead TSSOP package with an
exposed paddle. The exposed paddle must be soldered to the
exposed metal of a ground plane for a lowered thermal
impedance and reduced inductance to ground. This results in a
junction-to-air thermal impedance (θ

) of 30°C/W. If multiple

JA

ground planes are present, the area under the exposed paddle
should be stitched together with vias.

LO GENERATION USING PLLS

Analog Devices has a line of PLLs that can be used for
generating the LO signal. Table 4 lists the PLLs together with
their maximum frequency and phase noise performance.

Table 4. ADI PLL Selection Table

Frequency F

ADI Model

ADF4111BRU 1200 –78
ADF4111BCP 1200 –78
ADF4112BRU 3000 –86
ADF4112BCP 3000 –86
ADF4117BRU 1200 –87
ADF4118BRU 3000 –90

(MHz)

Analog Devices also offers the ADF4360 fully integrated
synthesizer and VCO on a single chip that offers differential
outputs for driving the local oscillator input of the AD8349.
This means that the user can eliminate the use of the balun
necessary for the single-ended-to-differential conversion. The
ADF4360 comes as a family of chips with six operating
frequency ranges. One can be chosen depending on the local
oscillator frequency required. The user should be aware that
while the use of the integrated synthesizer might come at the
expense of slightly degraded noise performance from the
AD8349, it can be a much cheaper alternative to a separate PLL
and VCO solution. Figure 61 shows the options available.

At 1 kHz Phase Noise

IN

dBc/Hz, 200 kHz PFD

Table 5. ADF4360 Family Operating Frequencies

ADI Model Output Frequency Range (MHz)

ADF4360-1 2150/2450
ADF4360-2 1800/2150
ADF4360-3 1550/1950
ADF4360-4 1400/1800
ADF4360-5 1150/1400
ADF4360-6 1000/1250
ADF4360-7 Lower frequencies set by external L

TRANSMIT DAC OPTIONS

The AD9777 recommended in the previous sections of this data
sheet is by no means the only DAC that can be used to drive the
AD8349. There are other DACs that are appropriate, depending
on the level of performance required. Table 6 lists the dual
Tx-DACs that ADI offers.

Table 6. ADI Dual Tx – DAC Selection Table

Part Resolution (Bits) Update Rate (MSPS Min)

AD9709 8 125
AD9761 10 40
AD9763 10 125
AD9765 12 125
AD9767 14 125
AD9773 12 160
AD9775 14 160
AD9777 16 160

Rev. A | Page 23 of 28

AD8349

EVALUATION BOARD

A populated AD8349 evaluation board is available.

The AD8349 has an exposed paddle underneath the package,
which is soldered to the board. The evaluation board is

YuPing Toh
Mike Chowkwanyun

03570-0-074

Figure 66. Layout of Evaluation Board, Top Layer

Table 7. Evaluation Board Configuration Options

Component Function Default Condition

TP1, TP4, TP3 Power Supply and Ground Vector Pins. Not applicable
SW1, ENOP,

TP2

Output Enable: Place in the A position to connect the ENOP pin to +VS via pull-up resistor R10.
Place in the B position to disable the device by grounding the pin ENOP through a 49.9 Ω pull­down resistor. The device may be enabled via an external voltage applied to the SMA connector
ENOP or TP2.

R1, R2, R5, R9,
C8–C11

Baseband Input Filters: These components can be used to implement a low-pass filter for the
baseband signals.

designed without any components on the underside of the
board so that heat may be applied under the AD8349 for easy
removal and replacement of the DUT.

Figure 67. Evaluation Board Silkscreen

SW1 = A

R1, R2, R5, R9 = 0 Ω,
C8 – C11 = OPEN

03570-0-073

Rev. A | Page 24 of 28

AD8349

IP

IN

ENOP

LO

C8

OPEN

R1
0Ω

R9

0Ω

R3

200Ω

R6
OPEN

T1

ETC-1-1-13

+V

S

R10
10kΩ

0.1µF

C3

R4
200Ω

R7
0Ω

TP4

GND

C4
100pF

C1
100pF

C2
100pF

C11

OPEN

1

2

3

4

5

6

7

8

49.9Ω

R8

IBBP

IBBN

COM1

COM1

LOIN

LOIP

VPS1

ENOP

TP2
ENOP

AD8349

QBBP

QBBN

COM3

COM3

VPS2

VOUT

COM3

COM2

A

B

Figure 68. Evaluation Board Schematic

16

15

14

13

12

11

10

9

OPEN

C9

C10
OPEN

C5

100pF

100pF

TP1
GND

C7

R2

0Ω

R5

0Ω

VPOS

R11

0Ω

C6

0.1µF

TP3

QP

QN

+V

S

VOUT

03570-0-072

Rev. A | Page 25 of 28

AD8349

CHARACTERIZATION SETUPS

SSB SETUP

The primary setup used to characterize the AD8349 is shown in
Figure 69. This setup was used to evaluate the product as a
single-sideband modulator. The interface board has circuitry
that converts the single-ended I and Q inputs from the arbitrary
function generator to differential inputs with a dc bias of
400 mV. Additionally, the interface board provides connections
for power supply routing. The HP34970A and its associated
plug-in 34901 were used to monitor power supply currents and
voltages being supplied to the AD8349 characterization board.

IEEE

D1 D2 D3

34901 34907 34907

D1 D2 D3

VPS1

VN
GND

VP

IEEE

+15V MAX

COM
+25V MAX
–25V MAX

HP3631

Two HP34907 plug-ins were used to provide additional
miscellaneous dc and control signals to the interface board. The
LO input was driven directly by an RF signal generator and the
output was measured directly with a spectrum analyzer. With
the I channel driven by a sine wave and the Q channel by a
cosine wave, the lower sideband is the single sideband (SSB)
output. The typical SSB output spectrum is shown in Figure 53.

HP34970A

INTERFACE

BOARD

P1 IN IP QP QN

I_IN

Q_IN

TEKAFG2020

OUTPUT_1
OUTPUT_2

ARB FUNCTION GEN

IEEE

AGILENT

E4437B

RFOUTIEEE

IEEE

PC CONTROLLER

IP QP

IN

AD8349

CHARACTERIZATION

BOARD

LO
ENOP

QN

HP8561E

VOUT

P1

RF I/P

SPECTRUM
ANALYZER

IEEE

03570-0-076

Figure 69. Characterization Board SSB Test Setup

Rev. A | Page 26 of 28

AD8349

OUTLINE DIMENSIONS

5.10

5.00

4.90

BOTTOM

VIEW

0.15

0.00

16

TOP

VIEW

1.20 MAX

SEATING
PLANE

0.65
BSC

COMPLIANT TO JEDEC STANDARDS MO-153-ABT

0.30

0.19

9

4.50

6.40

4.40

BSC

4.30

81

1.05

1.00

0.80

0.20

0.09

8°
0°

EXPOSED

PAD

(Pins Up)

0.75

0.60

0.45

3.00
SQ

Figure 70. 16-Lead Thin Shrink Small Outline with Exposed Pad [TSSOP/EP]

(RE-16-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range (°C) Package Description Package Option

AD8349ARE –40 to +85 16-Lead TSSOP, Tube RE-16
AD8349ARE-REEL7 –40 to +85 16-Lead TSSOP, 7" Tape and Reel RE-16
AD8349AREZ
AD8349AREZ-REEL71 –40 to +85 16-Lead TSSOP, 7" Tape and Reel RE-16
AD8349-EVAL Evaluation Board

1

Z = Pb-free part.

1

–40 to +85 16-Lead TSSOP, Tube RE-16

Rev. A | Page 27 of 28

AD8349

NOTES

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C03570-0-11/04(A)

Rev. A | Page 28 of 28